radeon_fence.c 10 KB

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  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Dave Airlie
  30. */
  31. #include <linux/seq_file.h>
  32. #include <asm/atomic.h>
  33. #include <linux/wait.h>
  34. #include <linux/list.h>
  35. #include <linux/kref.h>
  36. #include "drmP.h"
  37. #include "drm.h"
  38. #include "radeon_reg.h"
  39. #include "radeon.h"
  40. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
  41. {
  42. unsigned long irq_flags;
  43. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  44. if (fence->emited) {
  45. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  46. return 0;
  47. }
  48. fence->seq = atomic_add_return(1, &rdev->fence_drv.seq);
  49. if (!rdev->cp.ready) {
  50. /* FIXME: cp is not running assume everythings is done right
  51. * away
  52. */
  53. WREG32(rdev->fence_drv.scratch_reg, fence->seq);
  54. } else {
  55. radeon_fence_ring_emit(rdev, fence);
  56. }
  57. fence->emited = true;
  58. fence->timeout = jiffies + ((2000 * HZ) / 1000);
  59. list_del(&fence->list);
  60. list_add_tail(&fence->list, &rdev->fence_drv.emited);
  61. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  62. return 0;
  63. }
  64. static bool radeon_fence_poll_locked(struct radeon_device *rdev)
  65. {
  66. struct radeon_fence *fence;
  67. struct list_head *i, *n;
  68. uint32_t seq;
  69. bool wake = false;
  70. if (rdev == NULL) {
  71. return true;
  72. }
  73. if (rdev->shutdown) {
  74. return true;
  75. }
  76. seq = RREG32(rdev->fence_drv.scratch_reg);
  77. rdev->fence_drv.last_seq = seq;
  78. n = NULL;
  79. list_for_each(i, &rdev->fence_drv.emited) {
  80. fence = list_entry(i, struct radeon_fence, list);
  81. if (fence->seq == seq) {
  82. n = i;
  83. break;
  84. }
  85. }
  86. /* all fence previous to this one are considered as signaled */
  87. if (n) {
  88. i = n;
  89. do {
  90. n = i->prev;
  91. list_del(i);
  92. list_add_tail(i, &rdev->fence_drv.signaled);
  93. fence = list_entry(i, struct radeon_fence, list);
  94. fence->signaled = true;
  95. i = n;
  96. } while (i != &rdev->fence_drv.emited);
  97. wake = true;
  98. }
  99. return wake;
  100. }
  101. static void radeon_fence_destroy(struct kref *kref)
  102. {
  103. unsigned long irq_flags;
  104. struct radeon_fence *fence;
  105. fence = container_of(kref, struct radeon_fence, kref);
  106. write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
  107. list_del(&fence->list);
  108. fence->emited = false;
  109. write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
  110. kfree(fence);
  111. }
  112. int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence)
  113. {
  114. unsigned long irq_flags;
  115. *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
  116. if ((*fence) == NULL) {
  117. return -ENOMEM;
  118. }
  119. kref_init(&((*fence)->kref));
  120. (*fence)->rdev = rdev;
  121. (*fence)->emited = false;
  122. (*fence)->signaled = false;
  123. (*fence)->seq = 0;
  124. INIT_LIST_HEAD(&(*fence)->list);
  125. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  126. list_add_tail(&(*fence)->list, &rdev->fence_drv.created);
  127. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  128. return 0;
  129. }
  130. bool radeon_fence_signaled(struct radeon_fence *fence)
  131. {
  132. struct radeon_device *rdev = fence->rdev;
  133. unsigned long irq_flags;
  134. bool signaled = false;
  135. if (rdev->gpu_lockup) {
  136. return true;
  137. }
  138. if (fence == NULL) {
  139. return true;
  140. }
  141. write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
  142. signaled = fence->signaled;
  143. /* if we are shuting down report all fence as signaled */
  144. if (fence->rdev->shutdown) {
  145. signaled = true;
  146. }
  147. if (!fence->emited) {
  148. WARN(1, "Querying an unemited fence : %p !\n", fence);
  149. signaled = true;
  150. }
  151. if (!signaled) {
  152. radeon_fence_poll_locked(fence->rdev);
  153. signaled = fence->signaled;
  154. }
  155. write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
  156. return signaled;
  157. }
  158. int radeon_fence_wait(struct radeon_fence *fence, bool interruptible)
  159. {
  160. struct radeon_device *rdev;
  161. unsigned long cur_jiffies;
  162. unsigned long timeout;
  163. bool expired = false;
  164. int r;
  165. if (fence == NULL) {
  166. WARN(1, "Querying an invalid fence : %p !\n", fence);
  167. return 0;
  168. }
  169. rdev = fence->rdev;
  170. if (radeon_fence_signaled(fence)) {
  171. return 0;
  172. }
  173. retry:
  174. cur_jiffies = jiffies;
  175. timeout = HZ / 100;
  176. if (time_after(fence->timeout, cur_jiffies)) {
  177. timeout = fence->timeout - cur_jiffies;
  178. }
  179. if (interruptible) {
  180. r = wait_event_interruptible_timeout(rdev->fence_drv.queue,
  181. radeon_fence_signaled(fence), timeout);
  182. if (unlikely(r == -ERESTARTSYS)) {
  183. return -ERESTART;
  184. }
  185. } else {
  186. r = wait_event_timeout(rdev->fence_drv.queue,
  187. radeon_fence_signaled(fence), timeout);
  188. }
  189. if (unlikely(!radeon_fence_signaled(fence))) {
  190. if (unlikely(r == 0)) {
  191. expired = true;
  192. }
  193. if (unlikely(expired)) {
  194. timeout = 1;
  195. if (time_after(cur_jiffies, fence->timeout)) {
  196. timeout = cur_jiffies - fence->timeout;
  197. }
  198. timeout = jiffies_to_msecs(timeout);
  199. if (timeout > 500) {
  200. DRM_ERROR("fence(%p:0x%08X) %lums timeout "
  201. "going to reset GPU\n",
  202. fence, fence->seq, timeout);
  203. radeon_gpu_reset(rdev);
  204. WREG32(rdev->fence_drv.scratch_reg, fence->seq);
  205. }
  206. }
  207. goto retry;
  208. }
  209. if (unlikely(expired)) {
  210. rdev->fence_drv.count_timeout++;
  211. cur_jiffies = jiffies;
  212. timeout = 1;
  213. if (time_after(cur_jiffies, fence->timeout)) {
  214. timeout = cur_jiffies - fence->timeout;
  215. }
  216. timeout = jiffies_to_msecs(timeout);
  217. DRM_ERROR("fence(%p:0x%08X) %lums timeout\n",
  218. fence, fence->seq, timeout);
  219. DRM_ERROR("last signaled fence(0x%08X)\n",
  220. rdev->fence_drv.last_seq);
  221. }
  222. return 0;
  223. }
  224. int radeon_fence_wait_next(struct radeon_device *rdev)
  225. {
  226. unsigned long irq_flags;
  227. struct radeon_fence *fence;
  228. int r;
  229. if (rdev->gpu_lockup) {
  230. return 0;
  231. }
  232. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  233. if (list_empty(&rdev->fence_drv.emited)) {
  234. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  235. return 0;
  236. }
  237. fence = list_entry(rdev->fence_drv.emited.next,
  238. struct radeon_fence, list);
  239. radeon_fence_ref(fence);
  240. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  241. r = radeon_fence_wait(fence, false);
  242. radeon_fence_unref(&fence);
  243. return r;
  244. }
  245. int radeon_fence_wait_last(struct radeon_device *rdev)
  246. {
  247. unsigned long irq_flags;
  248. struct radeon_fence *fence;
  249. int r;
  250. if (rdev->gpu_lockup) {
  251. return 0;
  252. }
  253. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  254. if (list_empty(&rdev->fence_drv.emited)) {
  255. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  256. return 0;
  257. }
  258. fence = list_entry(rdev->fence_drv.emited.prev,
  259. struct radeon_fence, list);
  260. radeon_fence_ref(fence);
  261. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  262. r = radeon_fence_wait(fence, false);
  263. radeon_fence_unref(&fence);
  264. return r;
  265. }
  266. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
  267. {
  268. kref_get(&fence->kref);
  269. return fence;
  270. }
  271. void radeon_fence_unref(struct radeon_fence **fence)
  272. {
  273. struct radeon_fence *tmp = *fence;
  274. *fence = NULL;
  275. if (tmp) {
  276. kref_put(&tmp->kref, &radeon_fence_destroy);
  277. }
  278. }
  279. void radeon_fence_process(struct radeon_device *rdev)
  280. {
  281. unsigned long irq_flags;
  282. bool wake;
  283. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  284. wake = radeon_fence_poll_locked(rdev);
  285. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  286. if (wake) {
  287. wake_up_all(&rdev->fence_drv.queue);
  288. }
  289. }
  290. int radeon_fence_driver_init(struct radeon_device *rdev)
  291. {
  292. unsigned long irq_flags;
  293. int r;
  294. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  295. r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg);
  296. if (r) {
  297. DRM_ERROR("Fence failed to get a scratch register.");
  298. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  299. return r;
  300. }
  301. WREG32(rdev->fence_drv.scratch_reg, 0);
  302. atomic_set(&rdev->fence_drv.seq, 0);
  303. INIT_LIST_HEAD(&rdev->fence_drv.created);
  304. INIT_LIST_HEAD(&rdev->fence_drv.emited);
  305. INIT_LIST_HEAD(&rdev->fence_drv.signaled);
  306. rdev->fence_drv.count_timeout = 0;
  307. init_waitqueue_head(&rdev->fence_drv.queue);
  308. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  309. if (radeon_debugfs_fence_init(rdev)) {
  310. DRM_ERROR("Failed to register debugfs file for fence !\n");
  311. }
  312. return 0;
  313. }
  314. void radeon_fence_driver_fini(struct radeon_device *rdev)
  315. {
  316. unsigned long irq_flags;
  317. wake_up_all(&rdev->fence_drv.queue);
  318. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  319. radeon_scratch_free(rdev, rdev->fence_drv.scratch_reg);
  320. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  321. DRM_INFO("radeon: fence finalized\n");
  322. }
  323. /*
  324. * Fence debugfs
  325. */
  326. #if defined(CONFIG_DEBUG_FS)
  327. static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
  328. {
  329. struct drm_info_node *node = (struct drm_info_node *)m->private;
  330. struct drm_device *dev = node->minor->dev;
  331. struct radeon_device *rdev = dev->dev_private;
  332. struct radeon_fence *fence;
  333. seq_printf(m, "Last signaled fence 0x%08X\n",
  334. RREG32(rdev->fence_drv.scratch_reg));
  335. if (!list_empty(&rdev->fence_drv.emited)) {
  336. fence = list_entry(rdev->fence_drv.emited.prev,
  337. struct radeon_fence, list);
  338. seq_printf(m, "Last emited fence %p with 0x%08X\n",
  339. fence, fence->seq);
  340. }
  341. return 0;
  342. }
  343. static struct drm_info_list radeon_debugfs_fence_list[] = {
  344. {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
  345. };
  346. #endif
  347. int radeon_debugfs_fence_init(struct radeon_device *rdev)
  348. {
  349. #if defined(CONFIG_DEBUG_FS)
  350. return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);
  351. #else
  352. return 0;
  353. #endif
  354. }