i810_dma.c 33 KB

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  1. /* i810_dma.c -- DMA support for the i810 -*- linux-c -*-
  2. * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
  3. *
  4. * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  5. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the "Software"),
  10. * to deal in the Software without restriction, including without limitation
  11. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12. * and/or sell copies of the Software, and to permit persons to whom the
  13. * Software is furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the next
  16. * paragraph) shall be included in all copies or substantial portions of the
  17. * Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25. * DEALINGS IN THE SOFTWARE.
  26. *
  27. * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
  28. * Jeff Hartmann <jhartmann@valinux.com>
  29. * Keith Whitwell <keith@tungstengraphics.com>
  30. *
  31. */
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "i810_drm.h"
  35. #include "i810_drv.h"
  36. #include <linux/interrupt.h> /* For task queue support */
  37. #include <linux/delay.h>
  38. #include <linux/pagemap.h>
  39. #define I810_BUF_FREE 2
  40. #define I810_BUF_CLIENT 1
  41. #define I810_BUF_HARDWARE 0
  42. #define I810_BUF_UNMAPPED 0
  43. #define I810_BUF_MAPPED 1
  44. static struct drm_buf *i810_freelist_get(struct drm_device * dev)
  45. {
  46. struct drm_device_dma *dma = dev->dma;
  47. int i;
  48. int used;
  49. /* Linear search might not be the best solution */
  50. for (i = 0; i < dma->buf_count; i++) {
  51. struct drm_buf *buf = dma->buflist[i];
  52. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  53. /* In use is already a pointer */
  54. used = cmpxchg(buf_priv->in_use, I810_BUF_FREE,
  55. I810_BUF_CLIENT);
  56. if (used == I810_BUF_FREE) {
  57. return buf;
  58. }
  59. }
  60. return NULL;
  61. }
  62. /* This should only be called if the buffer is not sent to the hardware
  63. * yet, the hardware updates in use for us once its on the ring buffer.
  64. */
  65. static int i810_freelist_put(struct drm_device * dev, struct drm_buf * buf)
  66. {
  67. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  68. int used;
  69. /* In use is already a pointer */
  70. used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE);
  71. if (used != I810_BUF_CLIENT) {
  72. DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
  73. return -EINVAL;
  74. }
  75. return 0;
  76. }
  77. static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
  78. {
  79. struct drm_file *priv = filp->private_data;
  80. struct drm_device *dev;
  81. drm_i810_private_t *dev_priv;
  82. struct drm_buf *buf;
  83. drm_i810_buf_priv_t *buf_priv;
  84. lock_kernel();
  85. dev = priv->minor->dev;
  86. dev_priv = dev->dev_private;
  87. buf = dev_priv->mmap_buffer;
  88. buf_priv = buf->dev_private;
  89. vma->vm_flags |= (VM_IO | VM_DONTCOPY);
  90. vma->vm_file = filp;
  91. buf_priv->currently_mapped = I810_BUF_MAPPED;
  92. unlock_kernel();
  93. if (io_remap_pfn_range(vma, vma->vm_start,
  94. vma->vm_pgoff,
  95. vma->vm_end - vma->vm_start, vma->vm_page_prot))
  96. return -EAGAIN;
  97. return 0;
  98. }
  99. static const struct file_operations i810_buffer_fops = {
  100. .open = drm_open,
  101. .release = drm_release,
  102. .ioctl = drm_ioctl,
  103. .mmap = i810_mmap_buffers,
  104. .fasync = drm_fasync,
  105. };
  106. static int i810_map_buffer(struct drm_buf * buf, struct drm_file *file_priv)
  107. {
  108. struct drm_device *dev = file_priv->minor->dev;
  109. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  110. drm_i810_private_t *dev_priv = dev->dev_private;
  111. const struct file_operations *old_fops;
  112. int retcode = 0;
  113. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  114. return -EINVAL;
  115. down_write(&current->mm->mmap_sem);
  116. old_fops = file_priv->filp->f_op;
  117. file_priv->filp->f_op = &i810_buffer_fops;
  118. dev_priv->mmap_buffer = buf;
  119. buf_priv->virtual = (void *)do_mmap(file_priv->filp, 0, buf->total,
  120. PROT_READ | PROT_WRITE,
  121. MAP_SHARED, buf->bus_address);
  122. dev_priv->mmap_buffer = NULL;
  123. file_priv->filp->f_op = old_fops;
  124. if (IS_ERR(buf_priv->virtual)) {
  125. /* Real error */
  126. DRM_ERROR("mmap error\n");
  127. retcode = PTR_ERR(buf_priv->virtual);
  128. buf_priv->virtual = NULL;
  129. }
  130. up_write(&current->mm->mmap_sem);
  131. return retcode;
  132. }
  133. static int i810_unmap_buffer(struct drm_buf * buf)
  134. {
  135. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  136. int retcode = 0;
  137. if (buf_priv->currently_mapped != I810_BUF_MAPPED)
  138. return -EINVAL;
  139. down_write(&current->mm->mmap_sem);
  140. retcode = do_munmap(current->mm,
  141. (unsigned long)buf_priv->virtual,
  142. (size_t) buf->total);
  143. up_write(&current->mm->mmap_sem);
  144. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  145. buf_priv->virtual = NULL;
  146. return retcode;
  147. }
  148. static int i810_dma_get_buffer(struct drm_device * dev, drm_i810_dma_t * d,
  149. struct drm_file *file_priv)
  150. {
  151. struct drm_buf *buf;
  152. drm_i810_buf_priv_t *buf_priv;
  153. int retcode = 0;
  154. buf = i810_freelist_get(dev);
  155. if (!buf) {
  156. retcode = -ENOMEM;
  157. DRM_DEBUG("retcode=%d\n", retcode);
  158. return retcode;
  159. }
  160. retcode = i810_map_buffer(buf, file_priv);
  161. if (retcode) {
  162. i810_freelist_put(dev, buf);
  163. DRM_ERROR("mapbuf failed, retcode %d\n", retcode);
  164. return retcode;
  165. }
  166. buf->file_priv = file_priv;
  167. buf_priv = buf->dev_private;
  168. d->granted = 1;
  169. d->request_idx = buf->idx;
  170. d->request_size = buf->total;
  171. d->virtual = buf_priv->virtual;
  172. return retcode;
  173. }
  174. static int i810_dma_cleanup(struct drm_device * dev)
  175. {
  176. struct drm_device_dma *dma = dev->dma;
  177. /* Make sure interrupts are disabled here because the uninstall ioctl
  178. * may not have been called from userspace and after dev_private
  179. * is freed, it's too late.
  180. */
  181. if (drm_core_check_feature(dev, DRIVER_HAVE_IRQ) && dev->irq_enabled)
  182. drm_irq_uninstall(dev);
  183. if (dev->dev_private) {
  184. int i;
  185. drm_i810_private_t *dev_priv =
  186. (drm_i810_private_t *) dev->dev_private;
  187. if (dev_priv->ring.virtual_start) {
  188. drm_core_ioremapfree(&dev_priv->ring.map, dev);
  189. }
  190. if (dev_priv->hw_status_page) {
  191. pci_free_consistent(dev->pdev, PAGE_SIZE,
  192. dev_priv->hw_status_page,
  193. dev_priv->dma_status_page);
  194. /* Need to rewrite hardware status page */
  195. I810_WRITE(0x02080, 0x1ffff000);
  196. }
  197. kfree(dev->dev_private);
  198. dev->dev_private = NULL;
  199. for (i = 0; i < dma->buf_count; i++) {
  200. struct drm_buf *buf = dma->buflist[i];
  201. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  202. if (buf_priv->kernel_virtual && buf->total)
  203. drm_core_ioremapfree(&buf_priv->map, dev);
  204. }
  205. }
  206. return 0;
  207. }
  208. static int i810_wait_ring(struct drm_device * dev, int n)
  209. {
  210. drm_i810_private_t *dev_priv = dev->dev_private;
  211. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  212. int iters = 0;
  213. unsigned long end;
  214. unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  215. end = jiffies + (HZ * 3);
  216. while (ring->space < n) {
  217. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  218. ring->space = ring->head - (ring->tail + 8);
  219. if (ring->space < 0)
  220. ring->space += ring->Size;
  221. if (ring->head != last_head) {
  222. end = jiffies + (HZ * 3);
  223. last_head = ring->head;
  224. }
  225. iters++;
  226. if (time_before(end, jiffies)) {
  227. DRM_ERROR("space: %d wanted %d\n", ring->space, n);
  228. DRM_ERROR("lockup\n");
  229. goto out_wait_ring;
  230. }
  231. udelay(1);
  232. }
  233. out_wait_ring:
  234. return iters;
  235. }
  236. static void i810_kernel_lost_context(struct drm_device * dev)
  237. {
  238. drm_i810_private_t *dev_priv = dev->dev_private;
  239. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  240. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  241. ring->tail = I810_READ(LP_RING + RING_TAIL);
  242. ring->space = ring->head - (ring->tail + 8);
  243. if (ring->space < 0)
  244. ring->space += ring->Size;
  245. }
  246. static int i810_freelist_init(struct drm_device * dev, drm_i810_private_t * dev_priv)
  247. {
  248. struct drm_device_dma *dma = dev->dma;
  249. int my_idx = 24;
  250. u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx);
  251. int i;
  252. if (dma->buf_count > 1019) {
  253. /* Not enough space in the status page for the freelist */
  254. return -EINVAL;
  255. }
  256. for (i = 0; i < dma->buf_count; i++) {
  257. struct drm_buf *buf = dma->buflist[i];
  258. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  259. buf_priv->in_use = hw_status++;
  260. buf_priv->my_use_idx = my_idx;
  261. my_idx += 4;
  262. *buf_priv->in_use = I810_BUF_FREE;
  263. buf_priv->map.offset = buf->bus_address;
  264. buf_priv->map.size = buf->total;
  265. buf_priv->map.type = _DRM_AGP;
  266. buf_priv->map.flags = 0;
  267. buf_priv->map.mtrr = 0;
  268. drm_core_ioremap(&buf_priv->map, dev);
  269. buf_priv->kernel_virtual = buf_priv->map.handle;
  270. }
  271. return 0;
  272. }
  273. static int i810_dma_initialize(struct drm_device * dev,
  274. drm_i810_private_t * dev_priv,
  275. drm_i810_init_t * init)
  276. {
  277. struct drm_map_list *r_list;
  278. memset(dev_priv, 0, sizeof(drm_i810_private_t));
  279. list_for_each_entry(r_list, &dev->maplist, head) {
  280. if (r_list->map &&
  281. r_list->map->type == _DRM_SHM &&
  282. r_list->map->flags & _DRM_CONTAINS_LOCK) {
  283. dev_priv->sarea_map = r_list->map;
  284. break;
  285. }
  286. }
  287. if (!dev_priv->sarea_map) {
  288. dev->dev_private = (void *)dev_priv;
  289. i810_dma_cleanup(dev);
  290. DRM_ERROR("can not find sarea!\n");
  291. return -EINVAL;
  292. }
  293. dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
  294. if (!dev_priv->mmio_map) {
  295. dev->dev_private = (void *)dev_priv;
  296. i810_dma_cleanup(dev);
  297. DRM_ERROR("can not find mmio map!\n");
  298. return -EINVAL;
  299. }
  300. dev->agp_buffer_token = init->buffers_offset;
  301. dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
  302. if (!dev->agp_buffer_map) {
  303. dev->dev_private = (void *)dev_priv;
  304. i810_dma_cleanup(dev);
  305. DRM_ERROR("can not find dma buffer map!\n");
  306. return -EINVAL;
  307. }
  308. dev_priv->sarea_priv = (drm_i810_sarea_t *)
  309. ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset);
  310. dev_priv->ring.Start = init->ring_start;
  311. dev_priv->ring.End = init->ring_end;
  312. dev_priv->ring.Size = init->ring_size;
  313. dev_priv->ring.map.offset = dev->agp->base + init->ring_start;
  314. dev_priv->ring.map.size = init->ring_size;
  315. dev_priv->ring.map.type = _DRM_AGP;
  316. dev_priv->ring.map.flags = 0;
  317. dev_priv->ring.map.mtrr = 0;
  318. drm_core_ioremap(&dev_priv->ring.map, dev);
  319. if (dev_priv->ring.map.handle == NULL) {
  320. dev->dev_private = (void *)dev_priv;
  321. i810_dma_cleanup(dev);
  322. DRM_ERROR("can not ioremap virtual address for"
  323. " ring buffer\n");
  324. return -ENOMEM;
  325. }
  326. dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
  327. dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
  328. dev_priv->w = init->w;
  329. dev_priv->h = init->h;
  330. dev_priv->pitch = init->pitch;
  331. dev_priv->back_offset = init->back_offset;
  332. dev_priv->depth_offset = init->depth_offset;
  333. dev_priv->front_offset = init->front_offset;
  334. dev_priv->overlay_offset = init->overlay_offset;
  335. dev_priv->overlay_physical = init->overlay_physical;
  336. dev_priv->front_di1 = init->front_offset | init->pitch_bits;
  337. dev_priv->back_di1 = init->back_offset | init->pitch_bits;
  338. dev_priv->zi1 = init->depth_offset | init->pitch_bits;
  339. /* Program Hardware Status Page */
  340. dev_priv->hw_status_page =
  341. pci_alloc_consistent(dev->pdev, PAGE_SIZE,
  342. &dev_priv->dma_status_page);
  343. if (!dev_priv->hw_status_page) {
  344. dev->dev_private = (void *)dev_priv;
  345. i810_dma_cleanup(dev);
  346. DRM_ERROR("Can not allocate hardware status page\n");
  347. return -ENOMEM;
  348. }
  349. memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  350. DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
  351. I810_WRITE(0x02080, dev_priv->dma_status_page);
  352. DRM_DEBUG("Enabled hardware status page\n");
  353. /* Now we need to init our freelist */
  354. if (i810_freelist_init(dev, dev_priv) != 0) {
  355. dev->dev_private = (void *)dev_priv;
  356. i810_dma_cleanup(dev);
  357. DRM_ERROR("Not enough space in the status page for"
  358. " the freelist\n");
  359. return -ENOMEM;
  360. }
  361. dev->dev_private = (void *)dev_priv;
  362. return 0;
  363. }
  364. static int i810_dma_init(struct drm_device *dev, void *data,
  365. struct drm_file *file_priv)
  366. {
  367. drm_i810_private_t *dev_priv;
  368. drm_i810_init_t *init = data;
  369. int retcode = 0;
  370. switch (init->func) {
  371. case I810_INIT_DMA_1_4:
  372. DRM_INFO("Using v1.4 init.\n");
  373. dev_priv = kmalloc(sizeof(drm_i810_private_t), GFP_KERNEL);
  374. if (dev_priv == NULL)
  375. return -ENOMEM;
  376. retcode = i810_dma_initialize(dev, dev_priv, init);
  377. break;
  378. case I810_CLEANUP_DMA:
  379. DRM_INFO("DMA Cleanup\n");
  380. retcode = i810_dma_cleanup(dev);
  381. break;
  382. default:
  383. return -EINVAL;
  384. }
  385. return retcode;
  386. }
  387. /* Most efficient way to verify state for the i810 is as it is
  388. * emitted. Non-conformant state is silently dropped.
  389. *
  390. * Use 'volatile' & local var tmp to force the emitted values to be
  391. * identical to the verified ones.
  392. */
  393. static void i810EmitContextVerified(struct drm_device * dev,
  394. volatile unsigned int *code)
  395. {
  396. drm_i810_private_t *dev_priv = dev->dev_private;
  397. int i, j = 0;
  398. unsigned int tmp;
  399. RING_LOCALS;
  400. BEGIN_LP_RING(I810_CTX_SETUP_SIZE);
  401. OUT_RING(GFX_OP_COLOR_FACTOR);
  402. OUT_RING(code[I810_CTXREG_CF1]);
  403. OUT_RING(GFX_OP_STIPPLE);
  404. OUT_RING(code[I810_CTXREG_ST1]);
  405. for (i = 4; i < I810_CTX_SETUP_SIZE; i++) {
  406. tmp = code[i];
  407. if ((tmp & (7 << 29)) == (3 << 29) &&
  408. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  409. OUT_RING(tmp);
  410. j++;
  411. } else
  412. printk("constext state dropped!!!\n");
  413. }
  414. if (j & 1)
  415. OUT_RING(0);
  416. ADVANCE_LP_RING();
  417. }
  418. static void i810EmitTexVerified(struct drm_device * dev, volatile unsigned int *code)
  419. {
  420. drm_i810_private_t *dev_priv = dev->dev_private;
  421. int i, j = 0;
  422. unsigned int tmp;
  423. RING_LOCALS;
  424. BEGIN_LP_RING(I810_TEX_SETUP_SIZE);
  425. OUT_RING(GFX_OP_MAP_INFO);
  426. OUT_RING(code[I810_TEXREG_MI1]);
  427. OUT_RING(code[I810_TEXREG_MI2]);
  428. OUT_RING(code[I810_TEXREG_MI3]);
  429. for (i = 4; i < I810_TEX_SETUP_SIZE; i++) {
  430. tmp = code[i];
  431. if ((tmp & (7 << 29)) == (3 << 29) &&
  432. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  433. OUT_RING(tmp);
  434. j++;
  435. } else
  436. printk("texture state dropped!!!\n");
  437. }
  438. if (j & 1)
  439. OUT_RING(0);
  440. ADVANCE_LP_RING();
  441. }
  442. /* Need to do some additional checking when setting the dest buffer.
  443. */
  444. static void i810EmitDestVerified(struct drm_device * dev,
  445. volatile unsigned int *code)
  446. {
  447. drm_i810_private_t *dev_priv = dev->dev_private;
  448. unsigned int tmp;
  449. RING_LOCALS;
  450. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  451. tmp = code[I810_DESTREG_DI1];
  452. if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
  453. OUT_RING(CMD_OP_DESTBUFFER_INFO);
  454. OUT_RING(tmp);
  455. } else
  456. DRM_DEBUG("bad di1 %x (allow %x or %x)\n",
  457. tmp, dev_priv->front_di1, dev_priv->back_di1);
  458. /* invarient:
  459. */
  460. OUT_RING(CMD_OP_Z_BUFFER_INFO);
  461. OUT_RING(dev_priv->zi1);
  462. OUT_RING(GFX_OP_DESTBUFFER_VARS);
  463. OUT_RING(code[I810_DESTREG_DV1]);
  464. OUT_RING(GFX_OP_DRAWRECT_INFO);
  465. OUT_RING(code[I810_DESTREG_DR1]);
  466. OUT_RING(code[I810_DESTREG_DR2]);
  467. OUT_RING(code[I810_DESTREG_DR3]);
  468. OUT_RING(code[I810_DESTREG_DR4]);
  469. OUT_RING(0);
  470. ADVANCE_LP_RING();
  471. }
  472. static void i810EmitState(struct drm_device * dev)
  473. {
  474. drm_i810_private_t *dev_priv = dev->dev_private;
  475. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  476. unsigned int dirty = sarea_priv->dirty;
  477. DRM_DEBUG("%x\n", dirty);
  478. if (dirty & I810_UPLOAD_BUFFERS) {
  479. i810EmitDestVerified(dev, sarea_priv->BufferState);
  480. sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS;
  481. }
  482. if (dirty & I810_UPLOAD_CTX) {
  483. i810EmitContextVerified(dev, sarea_priv->ContextState);
  484. sarea_priv->dirty &= ~I810_UPLOAD_CTX;
  485. }
  486. if (dirty & I810_UPLOAD_TEX0) {
  487. i810EmitTexVerified(dev, sarea_priv->TexState[0]);
  488. sarea_priv->dirty &= ~I810_UPLOAD_TEX0;
  489. }
  490. if (dirty & I810_UPLOAD_TEX1) {
  491. i810EmitTexVerified(dev, sarea_priv->TexState[1]);
  492. sarea_priv->dirty &= ~I810_UPLOAD_TEX1;
  493. }
  494. }
  495. /* need to verify
  496. */
  497. static void i810_dma_dispatch_clear(struct drm_device * dev, int flags,
  498. unsigned int clear_color,
  499. unsigned int clear_zval)
  500. {
  501. drm_i810_private_t *dev_priv = dev->dev_private;
  502. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  503. int nbox = sarea_priv->nbox;
  504. struct drm_clip_rect *pbox = sarea_priv->boxes;
  505. int pitch = dev_priv->pitch;
  506. int cpp = 2;
  507. int i;
  508. RING_LOCALS;
  509. if (dev_priv->current_page == 1) {
  510. unsigned int tmp = flags;
  511. flags &= ~(I810_FRONT | I810_BACK);
  512. if (tmp & I810_FRONT)
  513. flags |= I810_BACK;
  514. if (tmp & I810_BACK)
  515. flags |= I810_FRONT;
  516. }
  517. i810_kernel_lost_context(dev);
  518. if (nbox > I810_NR_SAREA_CLIPRECTS)
  519. nbox = I810_NR_SAREA_CLIPRECTS;
  520. for (i = 0; i < nbox; i++, pbox++) {
  521. unsigned int x = pbox->x1;
  522. unsigned int y = pbox->y1;
  523. unsigned int width = (pbox->x2 - x) * cpp;
  524. unsigned int height = pbox->y2 - y;
  525. unsigned int start = y * pitch + x * cpp;
  526. if (pbox->x1 > pbox->x2 ||
  527. pbox->y1 > pbox->y2 ||
  528. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  529. continue;
  530. if (flags & I810_FRONT) {
  531. BEGIN_LP_RING(6);
  532. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  533. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  534. OUT_RING((height << 16) | width);
  535. OUT_RING(start);
  536. OUT_RING(clear_color);
  537. OUT_RING(0);
  538. ADVANCE_LP_RING();
  539. }
  540. if (flags & I810_BACK) {
  541. BEGIN_LP_RING(6);
  542. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  543. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  544. OUT_RING((height << 16) | width);
  545. OUT_RING(dev_priv->back_offset + start);
  546. OUT_RING(clear_color);
  547. OUT_RING(0);
  548. ADVANCE_LP_RING();
  549. }
  550. if (flags & I810_DEPTH) {
  551. BEGIN_LP_RING(6);
  552. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  553. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  554. OUT_RING((height << 16) | width);
  555. OUT_RING(dev_priv->depth_offset + start);
  556. OUT_RING(clear_zval);
  557. OUT_RING(0);
  558. ADVANCE_LP_RING();
  559. }
  560. }
  561. }
  562. static void i810_dma_dispatch_swap(struct drm_device * dev)
  563. {
  564. drm_i810_private_t *dev_priv = dev->dev_private;
  565. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  566. int nbox = sarea_priv->nbox;
  567. struct drm_clip_rect *pbox = sarea_priv->boxes;
  568. int pitch = dev_priv->pitch;
  569. int cpp = 2;
  570. int i;
  571. RING_LOCALS;
  572. DRM_DEBUG("swapbuffers\n");
  573. i810_kernel_lost_context(dev);
  574. if (nbox > I810_NR_SAREA_CLIPRECTS)
  575. nbox = I810_NR_SAREA_CLIPRECTS;
  576. for (i = 0; i < nbox; i++, pbox++) {
  577. unsigned int w = pbox->x2 - pbox->x1;
  578. unsigned int h = pbox->y2 - pbox->y1;
  579. unsigned int dst = pbox->x1 * cpp + pbox->y1 * pitch;
  580. unsigned int start = dst;
  581. if (pbox->x1 > pbox->x2 ||
  582. pbox->y1 > pbox->y2 ||
  583. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  584. continue;
  585. BEGIN_LP_RING(6);
  586. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4);
  587. OUT_RING(pitch | (0xCC << 16));
  588. OUT_RING((h << 16) | (w * cpp));
  589. if (dev_priv->current_page == 0)
  590. OUT_RING(dev_priv->front_offset + start);
  591. else
  592. OUT_RING(dev_priv->back_offset + start);
  593. OUT_RING(pitch);
  594. if (dev_priv->current_page == 0)
  595. OUT_RING(dev_priv->back_offset + start);
  596. else
  597. OUT_RING(dev_priv->front_offset + start);
  598. ADVANCE_LP_RING();
  599. }
  600. }
  601. static void i810_dma_dispatch_vertex(struct drm_device * dev,
  602. struct drm_buf * buf, int discard, int used)
  603. {
  604. drm_i810_private_t *dev_priv = dev->dev_private;
  605. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  606. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  607. struct drm_clip_rect *box = sarea_priv->boxes;
  608. int nbox = sarea_priv->nbox;
  609. unsigned long address = (unsigned long)buf->bus_address;
  610. unsigned long start = address - dev->agp->base;
  611. int i = 0;
  612. RING_LOCALS;
  613. i810_kernel_lost_context(dev);
  614. if (nbox > I810_NR_SAREA_CLIPRECTS)
  615. nbox = I810_NR_SAREA_CLIPRECTS;
  616. if (used > 4 * 1024)
  617. used = 0;
  618. if (sarea_priv->dirty)
  619. i810EmitState(dev);
  620. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  621. unsigned int prim = (sarea_priv->vertex_prim & PR_MASK);
  622. *(u32 *) buf_priv->kernel_virtual =
  623. ((GFX_OP_PRIMITIVE | prim | ((used / 4) - 2)));
  624. if (used & 4) {
  625. *(u32 *) ((char *) buf_priv->kernel_virtual + used) = 0;
  626. used += 4;
  627. }
  628. i810_unmap_buffer(buf);
  629. }
  630. if (used) {
  631. do {
  632. if (i < nbox) {
  633. BEGIN_LP_RING(4);
  634. OUT_RING(GFX_OP_SCISSOR | SC_UPDATE_SCISSOR |
  635. SC_ENABLE);
  636. OUT_RING(GFX_OP_SCISSOR_INFO);
  637. OUT_RING(box[i].x1 | (box[i].y1 << 16));
  638. OUT_RING((box[i].x2 -
  639. 1) | ((box[i].y2 - 1) << 16));
  640. ADVANCE_LP_RING();
  641. }
  642. BEGIN_LP_RING(4);
  643. OUT_RING(CMD_OP_BATCH_BUFFER);
  644. OUT_RING(start | BB1_PROTECTED);
  645. OUT_RING(start + used - 4);
  646. OUT_RING(0);
  647. ADVANCE_LP_RING();
  648. } while (++i < nbox);
  649. }
  650. if (discard) {
  651. dev_priv->counter++;
  652. (void)cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  653. I810_BUF_HARDWARE);
  654. BEGIN_LP_RING(8);
  655. OUT_RING(CMD_STORE_DWORD_IDX);
  656. OUT_RING(20);
  657. OUT_RING(dev_priv->counter);
  658. OUT_RING(CMD_STORE_DWORD_IDX);
  659. OUT_RING(buf_priv->my_use_idx);
  660. OUT_RING(I810_BUF_FREE);
  661. OUT_RING(CMD_REPORT_HEAD);
  662. OUT_RING(0);
  663. ADVANCE_LP_RING();
  664. }
  665. }
  666. static void i810_dma_dispatch_flip(struct drm_device * dev)
  667. {
  668. drm_i810_private_t *dev_priv = dev->dev_private;
  669. int pitch = dev_priv->pitch;
  670. RING_LOCALS;
  671. DRM_DEBUG("page=%d pfCurrentPage=%d\n",
  672. dev_priv->current_page,
  673. dev_priv->sarea_priv->pf_current_page);
  674. i810_kernel_lost_context(dev);
  675. BEGIN_LP_RING(2);
  676. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  677. OUT_RING(0);
  678. ADVANCE_LP_RING();
  679. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  680. /* On i815 at least ASYNC is buggy */
  681. /* pitch<<5 is from 11.2.8 p158,
  682. its the pitch / 8 then left shifted 8,
  683. so (pitch >> 3) << 8 */
  684. OUT_RING(CMD_OP_FRONTBUFFER_INFO | (pitch << 5) /*| ASYNC_FLIP */ );
  685. if (dev_priv->current_page == 0) {
  686. OUT_RING(dev_priv->back_offset);
  687. dev_priv->current_page = 1;
  688. } else {
  689. OUT_RING(dev_priv->front_offset);
  690. dev_priv->current_page = 0;
  691. }
  692. OUT_RING(0);
  693. ADVANCE_LP_RING();
  694. BEGIN_LP_RING(2);
  695. OUT_RING(CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP);
  696. OUT_RING(0);
  697. ADVANCE_LP_RING();
  698. /* Increment the frame counter. The client-side 3D driver must
  699. * throttle the framerate by waiting for this value before
  700. * performing the swapbuffer ioctl.
  701. */
  702. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  703. }
  704. static void i810_dma_quiescent(struct drm_device * dev)
  705. {
  706. drm_i810_private_t *dev_priv = dev->dev_private;
  707. RING_LOCALS;
  708. i810_kernel_lost_context(dev);
  709. BEGIN_LP_RING(4);
  710. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  711. OUT_RING(CMD_REPORT_HEAD);
  712. OUT_RING(0);
  713. OUT_RING(0);
  714. ADVANCE_LP_RING();
  715. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  716. }
  717. static int i810_flush_queue(struct drm_device * dev)
  718. {
  719. drm_i810_private_t *dev_priv = dev->dev_private;
  720. struct drm_device_dma *dma = dev->dma;
  721. int i, ret = 0;
  722. RING_LOCALS;
  723. i810_kernel_lost_context(dev);
  724. BEGIN_LP_RING(2);
  725. OUT_RING(CMD_REPORT_HEAD);
  726. OUT_RING(0);
  727. ADVANCE_LP_RING();
  728. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  729. for (i = 0; i < dma->buf_count; i++) {
  730. struct drm_buf *buf = dma->buflist[i];
  731. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  732. int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE,
  733. I810_BUF_FREE);
  734. if (used == I810_BUF_HARDWARE)
  735. DRM_DEBUG("reclaimed from HARDWARE\n");
  736. if (used == I810_BUF_CLIENT)
  737. DRM_DEBUG("still on client\n");
  738. }
  739. return ret;
  740. }
  741. /* Must be called with the lock held */
  742. static void i810_reclaim_buffers(struct drm_device * dev,
  743. struct drm_file *file_priv)
  744. {
  745. struct drm_device_dma *dma = dev->dma;
  746. int i;
  747. if (!dma)
  748. return;
  749. if (!dev->dev_private)
  750. return;
  751. if (!dma->buflist)
  752. return;
  753. i810_flush_queue(dev);
  754. for (i = 0; i < dma->buf_count; i++) {
  755. struct drm_buf *buf = dma->buflist[i];
  756. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  757. if (buf->file_priv == file_priv && buf_priv) {
  758. int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  759. I810_BUF_FREE);
  760. if (used == I810_BUF_CLIENT)
  761. DRM_DEBUG("reclaimed from client\n");
  762. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  763. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  764. }
  765. }
  766. }
  767. static int i810_flush_ioctl(struct drm_device *dev, void *data,
  768. struct drm_file *file_priv)
  769. {
  770. LOCK_TEST_WITH_RETURN(dev, file_priv);
  771. i810_flush_queue(dev);
  772. return 0;
  773. }
  774. static int i810_dma_vertex(struct drm_device *dev, void *data,
  775. struct drm_file *file_priv)
  776. {
  777. struct drm_device_dma *dma = dev->dma;
  778. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  779. u32 *hw_status = dev_priv->hw_status_page;
  780. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  781. dev_priv->sarea_priv;
  782. drm_i810_vertex_t *vertex = data;
  783. LOCK_TEST_WITH_RETURN(dev, file_priv);
  784. DRM_DEBUG("idx %d used %d discard %d\n",
  785. vertex->idx, vertex->used, vertex->discard);
  786. if (vertex->idx < 0 || vertex->idx > dma->buf_count)
  787. return -EINVAL;
  788. i810_dma_dispatch_vertex(dev,
  789. dma->buflist[vertex->idx],
  790. vertex->discard, vertex->used);
  791. atomic_add(vertex->used, &dev->counts[_DRM_STAT_SECONDARY]);
  792. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  793. sarea_priv->last_enqueue = dev_priv->counter - 1;
  794. sarea_priv->last_dispatch = (int)hw_status[5];
  795. return 0;
  796. }
  797. static int i810_clear_bufs(struct drm_device *dev, void *data,
  798. struct drm_file *file_priv)
  799. {
  800. drm_i810_clear_t *clear = data;
  801. LOCK_TEST_WITH_RETURN(dev, file_priv);
  802. /* GH: Someone's doing nasty things... */
  803. if (!dev->dev_private) {
  804. return -EINVAL;
  805. }
  806. i810_dma_dispatch_clear(dev, clear->flags,
  807. clear->clear_color, clear->clear_depth);
  808. return 0;
  809. }
  810. static int i810_swap_bufs(struct drm_device *dev, void *data,
  811. struct drm_file *file_priv)
  812. {
  813. DRM_DEBUG("\n");
  814. LOCK_TEST_WITH_RETURN(dev, file_priv);
  815. i810_dma_dispatch_swap(dev);
  816. return 0;
  817. }
  818. static int i810_getage(struct drm_device *dev, void *data,
  819. struct drm_file *file_priv)
  820. {
  821. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  822. u32 *hw_status = dev_priv->hw_status_page;
  823. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  824. dev_priv->sarea_priv;
  825. sarea_priv->last_dispatch = (int)hw_status[5];
  826. return 0;
  827. }
  828. static int i810_getbuf(struct drm_device *dev, void *data,
  829. struct drm_file *file_priv)
  830. {
  831. int retcode = 0;
  832. drm_i810_dma_t *d = data;
  833. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  834. u32 *hw_status = dev_priv->hw_status_page;
  835. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  836. dev_priv->sarea_priv;
  837. LOCK_TEST_WITH_RETURN(dev, file_priv);
  838. d->granted = 0;
  839. retcode = i810_dma_get_buffer(dev, d, file_priv);
  840. DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n",
  841. task_pid_nr(current), retcode, d->granted);
  842. sarea_priv->last_dispatch = (int)hw_status[5];
  843. return retcode;
  844. }
  845. static int i810_copybuf(struct drm_device *dev, void *data,
  846. struct drm_file *file_priv)
  847. {
  848. /* Never copy - 2.4.x doesn't need it */
  849. return 0;
  850. }
  851. static int i810_docopy(struct drm_device *dev, void *data,
  852. struct drm_file *file_priv)
  853. {
  854. /* Never copy - 2.4.x doesn't need it */
  855. return 0;
  856. }
  857. static void i810_dma_dispatch_mc(struct drm_device * dev, struct drm_buf * buf, int used,
  858. unsigned int last_render)
  859. {
  860. drm_i810_private_t *dev_priv = dev->dev_private;
  861. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  862. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  863. unsigned long address = (unsigned long)buf->bus_address;
  864. unsigned long start = address - dev->agp->base;
  865. int u;
  866. RING_LOCALS;
  867. i810_kernel_lost_context(dev);
  868. u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_HARDWARE);
  869. if (u != I810_BUF_CLIENT) {
  870. DRM_DEBUG("MC found buffer that isn't mine!\n");
  871. }
  872. if (used > 4 * 1024)
  873. used = 0;
  874. sarea_priv->dirty = 0x7f;
  875. DRM_DEBUG("addr 0x%lx, used 0x%x\n", address, used);
  876. dev_priv->counter++;
  877. DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter);
  878. DRM_DEBUG("start : %lx\n", start);
  879. DRM_DEBUG("used : %d\n", used);
  880. DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4);
  881. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  882. if (used & 4) {
  883. *(u32 *) ((char *) buf_priv->virtual + used) = 0;
  884. used += 4;
  885. }
  886. i810_unmap_buffer(buf);
  887. }
  888. BEGIN_LP_RING(4);
  889. OUT_RING(CMD_OP_BATCH_BUFFER);
  890. OUT_RING(start | BB1_PROTECTED);
  891. OUT_RING(start + used - 4);
  892. OUT_RING(0);
  893. ADVANCE_LP_RING();
  894. BEGIN_LP_RING(8);
  895. OUT_RING(CMD_STORE_DWORD_IDX);
  896. OUT_RING(buf_priv->my_use_idx);
  897. OUT_RING(I810_BUF_FREE);
  898. OUT_RING(0);
  899. OUT_RING(CMD_STORE_DWORD_IDX);
  900. OUT_RING(16);
  901. OUT_RING(last_render);
  902. OUT_RING(0);
  903. ADVANCE_LP_RING();
  904. }
  905. static int i810_dma_mc(struct drm_device *dev, void *data,
  906. struct drm_file *file_priv)
  907. {
  908. struct drm_device_dma *dma = dev->dma;
  909. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  910. u32 *hw_status = dev_priv->hw_status_page;
  911. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  912. dev_priv->sarea_priv;
  913. drm_i810_mc_t *mc = data;
  914. LOCK_TEST_WITH_RETURN(dev, file_priv);
  915. if (mc->idx >= dma->buf_count || mc->idx < 0)
  916. return -EINVAL;
  917. i810_dma_dispatch_mc(dev, dma->buflist[mc->idx], mc->used,
  918. mc->last_render);
  919. atomic_add(mc->used, &dev->counts[_DRM_STAT_SECONDARY]);
  920. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  921. sarea_priv->last_enqueue = dev_priv->counter - 1;
  922. sarea_priv->last_dispatch = (int)hw_status[5];
  923. return 0;
  924. }
  925. static int i810_rstatus(struct drm_device *dev, void *data,
  926. struct drm_file *file_priv)
  927. {
  928. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  929. return (int)(((u32 *) (dev_priv->hw_status_page))[4]);
  930. }
  931. static int i810_ov0_info(struct drm_device *dev, void *data,
  932. struct drm_file *file_priv)
  933. {
  934. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  935. drm_i810_overlay_t *ov = data;
  936. ov->offset = dev_priv->overlay_offset;
  937. ov->physical = dev_priv->overlay_physical;
  938. return 0;
  939. }
  940. static int i810_fstatus(struct drm_device *dev, void *data,
  941. struct drm_file *file_priv)
  942. {
  943. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  944. LOCK_TEST_WITH_RETURN(dev, file_priv);
  945. return I810_READ(0x30008);
  946. }
  947. static int i810_ov0_flip(struct drm_device *dev, void *data,
  948. struct drm_file *file_priv)
  949. {
  950. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  951. LOCK_TEST_WITH_RETURN(dev, file_priv);
  952. //Tell the overlay to update
  953. I810_WRITE(0x30000, dev_priv->overlay_physical | 0x80000000);
  954. return 0;
  955. }
  956. /* Not sure why this isn't set all the time:
  957. */
  958. static void i810_do_init_pageflip(struct drm_device * dev)
  959. {
  960. drm_i810_private_t *dev_priv = dev->dev_private;
  961. DRM_DEBUG("\n");
  962. dev_priv->page_flipping = 1;
  963. dev_priv->current_page = 0;
  964. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  965. }
  966. static int i810_do_cleanup_pageflip(struct drm_device * dev)
  967. {
  968. drm_i810_private_t *dev_priv = dev->dev_private;
  969. DRM_DEBUG("\n");
  970. if (dev_priv->current_page != 0)
  971. i810_dma_dispatch_flip(dev);
  972. dev_priv->page_flipping = 0;
  973. return 0;
  974. }
  975. static int i810_flip_bufs(struct drm_device *dev, void *data,
  976. struct drm_file *file_priv)
  977. {
  978. drm_i810_private_t *dev_priv = dev->dev_private;
  979. DRM_DEBUG("\n");
  980. LOCK_TEST_WITH_RETURN(dev, file_priv);
  981. if (!dev_priv->page_flipping)
  982. i810_do_init_pageflip(dev);
  983. i810_dma_dispatch_flip(dev);
  984. return 0;
  985. }
  986. int i810_driver_load(struct drm_device *dev, unsigned long flags)
  987. {
  988. /* i810 has 4 more counters */
  989. dev->counters += 4;
  990. dev->types[6] = _DRM_STAT_IRQ;
  991. dev->types[7] = _DRM_STAT_PRIMARY;
  992. dev->types[8] = _DRM_STAT_SECONDARY;
  993. dev->types[9] = _DRM_STAT_DMA;
  994. return 0;
  995. }
  996. void i810_driver_lastclose(struct drm_device * dev)
  997. {
  998. i810_dma_cleanup(dev);
  999. }
  1000. void i810_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
  1001. {
  1002. if (dev->dev_private) {
  1003. drm_i810_private_t *dev_priv = dev->dev_private;
  1004. if (dev_priv->page_flipping) {
  1005. i810_do_cleanup_pageflip(dev);
  1006. }
  1007. }
  1008. }
  1009. void i810_driver_reclaim_buffers_locked(struct drm_device * dev,
  1010. struct drm_file *file_priv)
  1011. {
  1012. i810_reclaim_buffers(dev, file_priv);
  1013. }
  1014. int i810_driver_dma_quiescent(struct drm_device * dev)
  1015. {
  1016. i810_dma_quiescent(dev);
  1017. return 0;
  1018. }
  1019. struct drm_ioctl_desc i810_ioctls[] = {
  1020. DRM_IOCTL_DEF(DRM_I810_INIT, i810_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1021. DRM_IOCTL_DEF(DRM_I810_VERTEX, i810_dma_vertex, DRM_AUTH),
  1022. DRM_IOCTL_DEF(DRM_I810_CLEAR, i810_clear_bufs, DRM_AUTH),
  1023. DRM_IOCTL_DEF(DRM_I810_FLUSH, i810_flush_ioctl, DRM_AUTH),
  1024. DRM_IOCTL_DEF(DRM_I810_GETAGE, i810_getage, DRM_AUTH),
  1025. DRM_IOCTL_DEF(DRM_I810_GETBUF, i810_getbuf, DRM_AUTH),
  1026. DRM_IOCTL_DEF(DRM_I810_SWAP, i810_swap_bufs, DRM_AUTH),
  1027. DRM_IOCTL_DEF(DRM_I810_COPY, i810_copybuf, DRM_AUTH),
  1028. DRM_IOCTL_DEF(DRM_I810_DOCOPY, i810_docopy, DRM_AUTH),
  1029. DRM_IOCTL_DEF(DRM_I810_OV0INFO, i810_ov0_info, DRM_AUTH),
  1030. DRM_IOCTL_DEF(DRM_I810_FSTATUS, i810_fstatus, DRM_AUTH),
  1031. DRM_IOCTL_DEF(DRM_I810_OV0FLIP, i810_ov0_flip, DRM_AUTH),
  1032. DRM_IOCTL_DEF(DRM_I810_MC, i810_dma_mc, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1033. DRM_IOCTL_DEF(DRM_I810_RSTATUS, i810_rstatus, DRM_AUTH),
  1034. DRM_IOCTL_DEF(DRM_I810_FLIP, i810_flip_bufs, DRM_AUTH)
  1035. };
  1036. int i810_max_ioctl = DRM_ARRAY_SIZE(i810_ioctls);
  1037. /**
  1038. * Determine if the device really is AGP or not.
  1039. *
  1040. * All Intel graphics chipsets are treated as AGP, even if they are really
  1041. * PCI-e.
  1042. *
  1043. * \param dev The device to be tested.
  1044. *
  1045. * \returns
  1046. * A value of 1 is always retured to indictate every i810 is AGP.
  1047. */
  1048. int i810_driver_device_is_agp(struct drm_device * dev)
  1049. {
  1050. return 1;
  1051. }