mbcs.c 20 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (c) 2005 Silicon Graphics, Inc. All rights reserved.
  7. */
  8. /*
  9. * MOATB Core Services driver.
  10. */
  11. #include <linux/interrupt.h>
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/types.h>
  15. #include <linux/ioport.h>
  16. #include <linux/notifier.h>
  17. #include <linux/reboot.h>
  18. #include <linux/init.h>
  19. #include <linux/fs.h>
  20. #include <linux/delay.h>
  21. #include <linux/device.h>
  22. #include <linux/mm.h>
  23. #include <linux/uio.h>
  24. #include <linux/mutex.h>
  25. #include <linux/smp_lock.h>
  26. #include <asm/io.h>
  27. #include <asm/uaccess.h>
  28. #include <asm/system.h>
  29. #include <asm/pgtable.h>
  30. #include <asm/sn/addrs.h>
  31. #include <asm/sn/intr.h>
  32. #include <asm/sn/tiocx.h>
  33. #include "mbcs.h"
  34. #define MBCS_DEBUG 0
  35. #if MBCS_DEBUG
  36. #define DBG(fmt...) printk(KERN_ALERT fmt)
  37. #else
  38. #define DBG(fmt...)
  39. #endif
  40. static int mbcs_major;
  41. static LIST_HEAD(soft_list);
  42. /*
  43. * file operations
  44. */
  45. static const struct file_operations mbcs_ops = {
  46. .open = mbcs_open,
  47. .llseek = mbcs_sram_llseek,
  48. .read = mbcs_sram_read,
  49. .write = mbcs_sram_write,
  50. .mmap = mbcs_gscr_mmap,
  51. };
  52. struct mbcs_callback_arg {
  53. int minor;
  54. struct cx_dev *cx_dev;
  55. };
  56. static inline void mbcs_getdma_init(struct getdma *gdma)
  57. {
  58. memset(gdma, 0, sizeof(struct getdma));
  59. gdma->DoneIntEnable = 1;
  60. }
  61. static inline void mbcs_putdma_init(struct putdma *pdma)
  62. {
  63. memset(pdma, 0, sizeof(struct putdma));
  64. pdma->DoneIntEnable = 1;
  65. }
  66. static inline void mbcs_algo_init(struct algoblock *algo_soft)
  67. {
  68. memset(algo_soft, 0, sizeof(struct algoblock));
  69. }
  70. static inline void mbcs_getdma_set(void *mmr,
  71. uint64_t hostAddr,
  72. uint64_t localAddr,
  73. uint64_t localRamSel,
  74. uint64_t numPkts,
  75. uint64_t amoEnable,
  76. uint64_t intrEnable,
  77. uint64_t peerIO,
  78. uint64_t amoHostDest,
  79. uint64_t amoModType, uint64_t intrHostDest,
  80. uint64_t intrVector)
  81. {
  82. union dma_control rdma_control;
  83. union dma_amo_dest amo_dest;
  84. union intr_dest intr_dest;
  85. union dma_localaddr local_addr;
  86. union dma_hostaddr host_addr;
  87. rdma_control.dma_control_reg = 0;
  88. amo_dest.dma_amo_dest_reg = 0;
  89. intr_dest.intr_dest_reg = 0;
  90. local_addr.dma_localaddr_reg = 0;
  91. host_addr.dma_hostaddr_reg = 0;
  92. host_addr.dma_sys_addr = hostAddr;
  93. MBCS_MMR_SET(mmr, MBCS_RD_DMA_SYS_ADDR, host_addr.dma_hostaddr_reg);
  94. local_addr.dma_ram_addr = localAddr;
  95. local_addr.dma_ram_sel = localRamSel;
  96. MBCS_MMR_SET(mmr, MBCS_RD_DMA_LOC_ADDR, local_addr.dma_localaddr_reg);
  97. rdma_control.dma_op_length = numPkts;
  98. rdma_control.done_amo_en = amoEnable;
  99. rdma_control.done_int_en = intrEnable;
  100. rdma_control.pio_mem_n = peerIO;
  101. MBCS_MMR_SET(mmr, MBCS_RD_DMA_CTRL, rdma_control.dma_control_reg);
  102. amo_dest.dma_amo_sys_addr = amoHostDest;
  103. amo_dest.dma_amo_mod_type = amoModType;
  104. MBCS_MMR_SET(mmr, MBCS_RD_DMA_AMO_DEST, amo_dest.dma_amo_dest_reg);
  105. intr_dest.address = intrHostDest;
  106. intr_dest.int_vector = intrVector;
  107. MBCS_MMR_SET(mmr, MBCS_RD_DMA_INT_DEST, intr_dest.intr_dest_reg);
  108. }
  109. static inline void mbcs_putdma_set(void *mmr,
  110. uint64_t hostAddr,
  111. uint64_t localAddr,
  112. uint64_t localRamSel,
  113. uint64_t numPkts,
  114. uint64_t amoEnable,
  115. uint64_t intrEnable,
  116. uint64_t peerIO,
  117. uint64_t amoHostDest,
  118. uint64_t amoModType,
  119. uint64_t intrHostDest, uint64_t intrVector)
  120. {
  121. union dma_control wdma_control;
  122. union dma_amo_dest amo_dest;
  123. union intr_dest intr_dest;
  124. union dma_localaddr local_addr;
  125. union dma_hostaddr host_addr;
  126. wdma_control.dma_control_reg = 0;
  127. amo_dest.dma_amo_dest_reg = 0;
  128. intr_dest.intr_dest_reg = 0;
  129. local_addr.dma_localaddr_reg = 0;
  130. host_addr.dma_hostaddr_reg = 0;
  131. host_addr.dma_sys_addr = hostAddr;
  132. MBCS_MMR_SET(mmr, MBCS_WR_DMA_SYS_ADDR, host_addr.dma_hostaddr_reg);
  133. local_addr.dma_ram_addr = localAddr;
  134. local_addr.dma_ram_sel = localRamSel;
  135. MBCS_MMR_SET(mmr, MBCS_WR_DMA_LOC_ADDR, local_addr.dma_localaddr_reg);
  136. wdma_control.dma_op_length = numPkts;
  137. wdma_control.done_amo_en = amoEnable;
  138. wdma_control.done_int_en = intrEnable;
  139. wdma_control.pio_mem_n = peerIO;
  140. MBCS_MMR_SET(mmr, MBCS_WR_DMA_CTRL, wdma_control.dma_control_reg);
  141. amo_dest.dma_amo_sys_addr = amoHostDest;
  142. amo_dest.dma_amo_mod_type = amoModType;
  143. MBCS_MMR_SET(mmr, MBCS_WR_DMA_AMO_DEST, amo_dest.dma_amo_dest_reg);
  144. intr_dest.address = intrHostDest;
  145. intr_dest.int_vector = intrVector;
  146. MBCS_MMR_SET(mmr, MBCS_WR_DMA_INT_DEST, intr_dest.intr_dest_reg);
  147. }
  148. static inline void mbcs_algo_set(void *mmr,
  149. uint64_t amoHostDest,
  150. uint64_t amoModType,
  151. uint64_t intrHostDest,
  152. uint64_t intrVector, uint64_t algoStepCount)
  153. {
  154. union dma_amo_dest amo_dest;
  155. union intr_dest intr_dest;
  156. union algo_step step;
  157. step.algo_step_reg = 0;
  158. intr_dest.intr_dest_reg = 0;
  159. amo_dest.dma_amo_dest_reg = 0;
  160. amo_dest.dma_amo_sys_addr = amoHostDest;
  161. amo_dest.dma_amo_mod_type = amoModType;
  162. MBCS_MMR_SET(mmr, MBCS_ALG_AMO_DEST, amo_dest.dma_amo_dest_reg);
  163. intr_dest.address = intrHostDest;
  164. intr_dest.int_vector = intrVector;
  165. MBCS_MMR_SET(mmr, MBCS_ALG_INT_DEST, intr_dest.intr_dest_reg);
  166. step.alg_step_cnt = algoStepCount;
  167. MBCS_MMR_SET(mmr, MBCS_ALG_STEP, step.algo_step_reg);
  168. }
  169. static inline int mbcs_getdma_start(struct mbcs_soft *soft)
  170. {
  171. void *mmr_base;
  172. struct getdma *gdma;
  173. uint64_t numPkts;
  174. union cm_control cm_control;
  175. mmr_base = soft->mmr_base;
  176. gdma = &soft->getdma;
  177. /* check that host address got setup */
  178. if (!gdma->hostAddr)
  179. return -1;
  180. numPkts =
  181. (gdma->bytes + (MBCS_CACHELINE_SIZE - 1)) / MBCS_CACHELINE_SIZE;
  182. /* program engine */
  183. mbcs_getdma_set(mmr_base, tiocx_dma_addr(gdma->hostAddr),
  184. gdma->localAddr,
  185. (gdma->localAddr < MB2) ? 0 :
  186. (gdma->localAddr < MB4) ? 1 :
  187. (gdma->localAddr < MB6) ? 2 : 3,
  188. numPkts,
  189. gdma->DoneAmoEnable,
  190. gdma->DoneIntEnable,
  191. gdma->peerIO,
  192. gdma->amoHostDest,
  193. gdma->amoModType,
  194. gdma->intrHostDest, gdma->intrVector);
  195. /* start engine */
  196. cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
  197. cm_control.rd_dma_go = 1;
  198. MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg);
  199. return 0;
  200. }
  201. static inline int mbcs_putdma_start(struct mbcs_soft *soft)
  202. {
  203. void *mmr_base;
  204. struct putdma *pdma;
  205. uint64_t numPkts;
  206. union cm_control cm_control;
  207. mmr_base = soft->mmr_base;
  208. pdma = &soft->putdma;
  209. /* check that host address got setup */
  210. if (!pdma->hostAddr)
  211. return -1;
  212. numPkts =
  213. (pdma->bytes + (MBCS_CACHELINE_SIZE - 1)) / MBCS_CACHELINE_SIZE;
  214. /* program engine */
  215. mbcs_putdma_set(mmr_base, tiocx_dma_addr(pdma->hostAddr),
  216. pdma->localAddr,
  217. (pdma->localAddr < MB2) ? 0 :
  218. (pdma->localAddr < MB4) ? 1 :
  219. (pdma->localAddr < MB6) ? 2 : 3,
  220. numPkts,
  221. pdma->DoneAmoEnable,
  222. pdma->DoneIntEnable,
  223. pdma->peerIO,
  224. pdma->amoHostDest,
  225. pdma->amoModType,
  226. pdma->intrHostDest, pdma->intrVector);
  227. /* start engine */
  228. cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
  229. cm_control.wr_dma_go = 1;
  230. MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg);
  231. return 0;
  232. }
  233. static inline int mbcs_algo_start(struct mbcs_soft *soft)
  234. {
  235. struct algoblock *algo_soft = &soft->algo;
  236. void *mmr_base = soft->mmr_base;
  237. union cm_control cm_control;
  238. if (mutex_lock_interruptible(&soft->algolock))
  239. return -ERESTARTSYS;
  240. atomic_set(&soft->algo_done, 0);
  241. mbcs_algo_set(mmr_base,
  242. algo_soft->amoHostDest,
  243. algo_soft->amoModType,
  244. algo_soft->intrHostDest,
  245. algo_soft->intrVector, algo_soft->algoStepCount);
  246. /* start algorithm */
  247. cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
  248. cm_control.alg_done_int_en = 1;
  249. cm_control.alg_go = 1;
  250. MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg);
  251. mutex_unlock(&soft->algolock);
  252. return 0;
  253. }
  254. static inline ssize_t
  255. do_mbcs_sram_dmawrite(struct mbcs_soft *soft, uint64_t hostAddr,
  256. size_t len, loff_t * off)
  257. {
  258. int rv = 0;
  259. if (mutex_lock_interruptible(&soft->dmawritelock))
  260. return -ERESTARTSYS;
  261. atomic_set(&soft->dmawrite_done, 0);
  262. soft->putdma.hostAddr = hostAddr;
  263. soft->putdma.localAddr = *off;
  264. soft->putdma.bytes = len;
  265. if (mbcs_putdma_start(soft) < 0) {
  266. DBG(KERN_ALERT "do_mbcs_sram_dmawrite: "
  267. "mbcs_putdma_start failed\n");
  268. rv = -EAGAIN;
  269. goto dmawrite_exit;
  270. }
  271. if (wait_event_interruptible(soft->dmawrite_queue,
  272. atomic_read(&soft->dmawrite_done))) {
  273. rv = -ERESTARTSYS;
  274. goto dmawrite_exit;
  275. }
  276. rv = len;
  277. *off += len;
  278. dmawrite_exit:
  279. mutex_unlock(&soft->dmawritelock);
  280. return rv;
  281. }
  282. static inline ssize_t
  283. do_mbcs_sram_dmaread(struct mbcs_soft *soft, uint64_t hostAddr,
  284. size_t len, loff_t * off)
  285. {
  286. int rv = 0;
  287. if (mutex_lock_interruptible(&soft->dmareadlock))
  288. return -ERESTARTSYS;
  289. atomic_set(&soft->dmawrite_done, 0);
  290. soft->getdma.hostAddr = hostAddr;
  291. soft->getdma.localAddr = *off;
  292. soft->getdma.bytes = len;
  293. if (mbcs_getdma_start(soft) < 0) {
  294. DBG(KERN_ALERT "mbcs_strategy: mbcs_getdma_start failed\n");
  295. rv = -EAGAIN;
  296. goto dmaread_exit;
  297. }
  298. if (wait_event_interruptible(soft->dmaread_queue,
  299. atomic_read(&soft->dmaread_done))) {
  300. rv = -ERESTARTSYS;
  301. goto dmaread_exit;
  302. }
  303. rv = len;
  304. *off += len;
  305. dmaread_exit:
  306. mutex_unlock(&soft->dmareadlock);
  307. return rv;
  308. }
  309. static int mbcs_open(struct inode *ip, struct file *fp)
  310. {
  311. struct mbcs_soft *soft;
  312. int minor;
  313. lock_kernel();
  314. minor = iminor(ip);
  315. /* Nothing protects access to this list... */
  316. list_for_each_entry(soft, &soft_list, list) {
  317. if (soft->nasid == minor) {
  318. fp->private_data = soft->cxdev;
  319. unlock_kernel();
  320. return 0;
  321. }
  322. }
  323. unlock_kernel();
  324. return -ENODEV;
  325. }
  326. static ssize_t mbcs_sram_read(struct file * fp, char __user *buf, size_t len, loff_t * off)
  327. {
  328. struct cx_dev *cx_dev = fp->private_data;
  329. struct mbcs_soft *soft = cx_dev->soft;
  330. uint64_t hostAddr;
  331. int rv = 0;
  332. hostAddr = __get_dma_pages(GFP_KERNEL, get_order(len));
  333. if (hostAddr == 0)
  334. return -ENOMEM;
  335. rv = do_mbcs_sram_dmawrite(soft, hostAddr, len, off);
  336. if (rv < 0)
  337. goto exit;
  338. if (copy_to_user(buf, (void *)hostAddr, len))
  339. rv = -EFAULT;
  340. exit:
  341. free_pages(hostAddr, get_order(len));
  342. return rv;
  343. }
  344. static ssize_t
  345. mbcs_sram_write(struct file * fp, const char __user *buf, size_t len, loff_t * off)
  346. {
  347. struct cx_dev *cx_dev = fp->private_data;
  348. struct mbcs_soft *soft = cx_dev->soft;
  349. uint64_t hostAddr;
  350. int rv = 0;
  351. hostAddr = __get_dma_pages(GFP_KERNEL, get_order(len));
  352. if (hostAddr == 0)
  353. return -ENOMEM;
  354. if (copy_from_user((void *)hostAddr, buf, len)) {
  355. rv = -EFAULT;
  356. goto exit;
  357. }
  358. rv = do_mbcs_sram_dmaread(soft, hostAddr, len, off);
  359. exit:
  360. free_pages(hostAddr, get_order(len));
  361. return rv;
  362. }
  363. static loff_t mbcs_sram_llseek(struct file * filp, loff_t off, int whence)
  364. {
  365. loff_t newpos;
  366. switch (whence) {
  367. case SEEK_SET:
  368. newpos = off;
  369. break;
  370. case SEEK_CUR:
  371. newpos = filp->f_pos + off;
  372. break;
  373. case SEEK_END:
  374. newpos = MBCS_SRAM_SIZE + off;
  375. break;
  376. default: /* can't happen */
  377. return -EINVAL;
  378. }
  379. if (newpos < 0)
  380. return -EINVAL;
  381. filp->f_pos = newpos;
  382. return newpos;
  383. }
  384. static uint64_t mbcs_pioaddr(struct mbcs_soft *soft, uint64_t offset)
  385. {
  386. uint64_t mmr_base;
  387. mmr_base = (uint64_t) (soft->mmr_base + offset);
  388. return mmr_base;
  389. }
  390. static void mbcs_debug_pioaddr_set(struct mbcs_soft *soft)
  391. {
  392. soft->debug_addr = mbcs_pioaddr(soft, MBCS_DEBUG_START);
  393. }
  394. static void mbcs_gscr_pioaddr_set(struct mbcs_soft *soft)
  395. {
  396. soft->gscr_addr = mbcs_pioaddr(soft, MBCS_GSCR_START);
  397. }
  398. static int mbcs_gscr_mmap(struct file *fp, struct vm_area_struct *vma)
  399. {
  400. struct cx_dev *cx_dev = fp->private_data;
  401. struct mbcs_soft *soft = cx_dev->soft;
  402. if (vma->vm_pgoff != 0)
  403. return -EINVAL;
  404. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  405. /* Remap-pfn-range will mark the range VM_IO and VM_RESERVED */
  406. if (remap_pfn_range(vma,
  407. vma->vm_start,
  408. __pa(soft->gscr_addr) >> PAGE_SHIFT,
  409. PAGE_SIZE,
  410. vma->vm_page_prot))
  411. return -EAGAIN;
  412. return 0;
  413. }
  414. /**
  415. * mbcs_completion_intr_handler - Primary completion handler.
  416. * @irq: irq
  417. * @arg: soft struct for device
  418. *
  419. */
  420. static irqreturn_t
  421. mbcs_completion_intr_handler(int irq, void *arg)
  422. {
  423. struct mbcs_soft *soft = (struct mbcs_soft *)arg;
  424. void *mmr_base;
  425. union cm_status cm_status;
  426. union cm_control cm_control;
  427. mmr_base = soft->mmr_base;
  428. cm_status.cm_status_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_STATUS);
  429. if (cm_status.rd_dma_done) {
  430. /* stop dma-read engine, clear status */
  431. cm_control.cm_control_reg =
  432. MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
  433. cm_control.rd_dma_clr = 1;
  434. MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL,
  435. cm_control.cm_control_reg);
  436. atomic_set(&soft->dmaread_done, 1);
  437. wake_up(&soft->dmaread_queue);
  438. }
  439. if (cm_status.wr_dma_done) {
  440. /* stop dma-write engine, clear status */
  441. cm_control.cm_control_reg =
  442. MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
  443. cm_control.wr_dma_clr = 1;
  444. MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL,
  445. cm_control.cm_control_reg);
  446. atomic_set(&soft->dmawrite_done, 1);
  447. wake_up(&soft->dmawrite_queue);
  448. }
  449. if (cm_status.alg_done) {
  450. /* clear status */
  451. cm_control.cm_control_reg =
  452. MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
  453. cm_control.alg_done_clr = 1;
  454. MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL,
  455. cm_control.cm_control_reg);
  456. atomic_set(&soft->algo_done, 1);
  457. wake_up(&soft->algo_queue);
  458. }
  459. return IRQ_HANDLED;
  460. }
  461. /**
  462. * mbcs_intr_alloc - Allocate interrupts.
  463. * @dev: device pointer
  464. *
  465. */
  466. static int mbcs_intr_alloc(struct cx_dev *dev)
  467. {
  468. struct sn_irq_info *sn_irq;
  469. struct mbcs_soft *soft;
  470. struct getdma *getdma;
  471. struct putdma *putdma;
  472. struct algoblock *algo;
  473. soft = dev->soft;
  474. getdma = &soft->getdma;
  475. putdma = &soft->putdma;
  476. algo = &soft->algo;
  477. soft->get_sn_irq = NULL;
  478. soft->put_sn_irq = NULL;
  479. soft->algo_sn_irq = NULL;
  480. sn_irq = tiocx_irq_alloc(dev->cx_id.nasid, TIOCX_CORELET, -1, -1, -1);
  481. if (sn_irq == NULL)
  482. return -EAGAIN;
  483. soft->get_sn_irq = sn_irq;
  484. getdma->intrHostDest = sn_irq->irq_xtalkaddr;
  485. getdma->intrVector = sn_irq->irq_irq;
  486. if (request_irq(sn_irq->irq_irq,
  487. (void *)mbcs_completion_intr_handler, IRQF_SHARED,
  488. "MBCS get intr", (void *)soft)) {
  489. tiocx_irq_free(soft->get_sn_irq);
  490. return -EAGAIN;
  491. }
  492. sn_irq = tiocx_irq_alloc(dev->cx_id.nasid, TIOCX_CORELET, -1, -1, -1);
  493. if (sn_irq == NULL) {
  494. free_irq(soft->get_sn_irq->irq_irq, soft);
  495. tiocx_irq_free(soft->get_sn_irq);
  496. return -EAGAIN;
  497. }
  498. soft->put_sn_irq = sn_irq;
  499. putdma->intrHostDest = sn_irq->irq_xtalkaddr;
  500. putdma->intrVector = sn_irq->irq_irq;
  501. if (request_irq(sn_irq->irq_irq,
  502. (void *)mbcs_completion_intr_handler, IRQF_SHARED,
  503. "MBCS put intr", (void *)soft)) {
  504. tiocx_irq_free(soft->put_sn_irq);
  505. free_irq(soft->get_sn_irq->irq_irq, soft);
  506. tiocx_irq_free(soft->get_sn_irq);
  507. return -EAGAIN;
  508. }
  509. sn_irq = tiocx_irq_alloc(dev->cx_id.nasid, TIOCX_CORELET, -1, -1, -1);
  510. if (sn_irq == NULL) {
  511. free_irq(soft->put_sn_irq->irq_irq, soft);
  512. tiocx_irq_free(soft->put_sn_irq);
  513. free_irq(soft->get_sn_irq->irq_irq, soft);
  514. tiocx_irq_free(soft->get_sn_irq);
  515. return -EAGAIN;
  516. }
  517. soft->algo_sn_irq = sn_irq;
  518. algo->intrHostDest = sn_irq->irq_xtalkaddr;
  519. algo->intrVector = sn_irq->irq_irq;
  520. if (request_irq(sn_irq->irq_irq,
  521. (void *)mbcs_completion_intr_handler, IRQF_SHARED,
  522. "MBCS algo intr", (void *)soft)) {
  523. tiocx_irq_free(soft->algo_sn_irq);
  524. free_irq(soft->put_sn_irq->irq_irq, soft);
  525. tiocx_irq_free(soft->put_sn_irq);
  526. free_irq(soft->get_sn_irq->irq_irq, soft);
  527. tiocx_irq_free(soft->get_sn_irq);
  528. return -EAGAIN;
  529. }
  530. return 0;
  531. }
  532. /**
  533. * mbcs_intr_dealloc - Remove interrupts.
  534. * @dev: device pointer
  535. *
  536. */
  537. static void mbcs_intr_dealloc(struct cx_dev *dev)
  538. {
  539. struct mbcs_soft *soft;
  540. soft = dev->soft;
  541. free_irq(soft->get_sn_irq->irq_irq, soft);
  542. tiocx_irq_free(soft->get_sn_irq);
  543. free_irq(soft->put_sn_irq->irq_irq, soft);
  544. tiocx_irq_free(soft->put_sn_irq);
  545. free_irq(soft->algo_sn_irq->irq_irq, soft);
  546. tiocx_irq_free(soft->algo_sn_irq);
  547. }
  548. static inline int mbcs_hw_init(struct mbcs_soft *soft)
  549. {
  550. void *mmr_base = soft->mmr_base;
  551. union cm_control cm_control;
  552. union cm_req_timeout cm_req_timeout;
  553. uint64_t err_stat;
  554. cm_req_timeout.cm_req_timeout_reg =
  555. MBCS_MMR_GET(mmr_base, MBCS_CM_REQ_TOUT);
  556. cm_req_timeout.time_out = MBCS_CM_CONTROL_REQ_TOUT_MASK;
  557. MBCS_MMR_SET(mmr_base, MBCS_CM_REQ_TOUT,
  558. cm_req_timeout.cm_req_timeout_reg);
  559. mbcs_gscr_pioaddr_set(soft);
  560. mbcs_debug_pioaddr_set(soft);
  561. /* clear errors */
  562. err_stat = MBCS_MMR_GET(mmr_base, MBCS_CM_ERR_STAT);
  563. MBCS_MMR_SET(mmr_base, MBCS_CM_CLR_ERR_STAT, err_stat);
  564. MBCS_MMR_ZERO(mmr_base, MBCS_CM_ERROR_DETAIL1);
  565. /* enable interrupts */
  566. /* turn off 2^23 (INT_EN_PIO_REQ_ADDR_INV) */
  567. MBCS_MMR_SET(mmr_base, MBCS_CM_ERR_INT_EN, 0x3ffffff7e00ffUL);
  568. /* arm status regs and clear engines */
  569. cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
  570. cm_control.rearm_stat_regs = 1;
  571. cm_control.alg_clr = 1;
  572. cm_control.wr_dma_clr = 1;
  573. cm_control.rd_dma_clr = 1;
  574. MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg);
  575. return 0;
  576. }
  577. static ssize_t show_algo(struct device *dev, struct device_attribute *attr, char *buf)
  578. {
  579. struct cx_dev *cx_dev = to_cx_dev(dev);
  580. struct mbcs_soft *soft = cx_dev->soft;
  581. uint64_t debug0;
  582. /*
  583. * By convention, the first debug register contains the
  584. * algorithm number and revision.
  585. */
  586. debug0 = *(uint64_t *) soft->debug_addr;
  587. return sprintf(buf, "0x%lx 0x%lx\n",
  588. (debug0 >> 32), (debug0 & 0xffffffff));
  589. }
  590. static ssize_t store_algo(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
  591. {
  592. int n;
  593. struct cx_dev *cx_dev = to_cx_dev(dev);
  594. struct mbcs_soft *soft = cx_dev->soft;
  595. if (count <= 0)
  596. return 0;
  597. n = simple_strtoul(buf, NULL, 0);
  598. if (n == 1) {
  599. mbcs_algo_start(soft);
  600. if (wait_event_interruptible(soft->algo_queue,
  601. atomic_read(&soft->algo_done)))
  602. return -ERESTARTSYS;
  603. }
  604. return count;
  605. }
  606. DEVICE_ATTR(algo, 0644, show_algo, store_algo);
  607. /**
  608. * mbcs_probe - Initialize for device
  609. * @dev: device pointer
  610. * @device_id: id table pointer
  611. *
  612. */
  613. static int mbcs_probe(struct cx_dev *dev, const struct cx_device_id *id)
  614. {
  615. struct mbcs_soft *soft;
  616. dev->soft = NULL;
  617. soft = kzalloc(sizeof(struct mbcs_soft), GFP_KERNEL);
  618. if (soft == NULL)
  619. return -ENOMEM;
  620. soft->nasid = dev->cx_id.nasid;
  621. list_add(&soft->list, &soft_list);
  622. soft->mmr_base = (void *)tiocx_swin_base(dev->cx_id.nasid);
  623. dev->soft = soft;
  624. soft->cxdev = dev;
  625. init_waitqueue_head(&soft->dmawrite_queue);
  626. init_waitqueue_head(&soft->dmaread_queue);
  627. init_waitqueue_head(&soft->algo_queue);
  628. mutex_init(&soft->dmawritelock);
  629. mutex_init(&soft->dmareadlock);
  630. mutex_init(&soft->algolock);
  631. mbcs_getdma_init(&soft->getdma);
  632. mbcs_putdma_init(&soft->putdma);
  633. mbcs_algo_init(&soft->algo);
  634. mbcs_hw_init(soft);
  635. /* Allocate interrupts */
  636. mbcs_intr_alloc(dev);
  637. device_create_file(&dev->dev, &dev_attr_algo);
  638. return 0;
  639. }
  640. static int mbcs_remove(struct cx_dev *dev)
  641. {
  642. if (dev->soft) {
  643. mbcs_intr_dealloc(dev);
  644. kfree(dev->soft);
  645. }
  646. device_remove_file(&dev->dev, &dev_attr_algo);
  647. return 0;
  648. }
  649. static const struct cx_device_id __devinitdata mbcs_id_table[] = {
  650. {
  651. .part_num = MBCS_PART_NUM,
  652. .mfg_num = MBCS_MFG_NUM,
  653. },
  654. {
  655. .part_num = MBCS_PART_NUM_ALG0,
  656. .mfg_num = MBCS_MFG_NUM,
  657. },
  658. {0, 0}
  659. };
  660. MODULE_DEVICE_TABLE(cx, mbcs_id_table);
  661. static struct cx_drv mbcs_driver = {
  662. .name = DEVICE_NAME,
  663. .id_table = mbcs_id_table,
  664. .probe = mbcs_probe,
  665. .remove = mbcs_remove,
  666. };
  667. static void __exit mbcs_exit(void)
  668. {
  669. unregister_chrdev(mbcs_major, DEVICE_NAME);
  670. cx_driver_unregister(&mbcs_driver);
  671. }
  672. static int __init mbcs_init(void)
  673. {
  674. int rv;
  675. if (!ia64_platform_is("sn2"))
  676. return -ENODEV;
  677. // Put driver into chrdevs[]. Get major number.
  678. rv = register_chrdev(mbcs_major, DEVICE_NAME, &mbcs_ops);
  679. if (rv < 0) {
  680. DBG(KERN_ALERT "mbcs_init: can't get major number. %d\n", rv);
  681. return rv;
  682. }
  683. mbcs_major = rv;
  684. return cx_driver_register(&mbcs_driver);
  685. }
  686. module_init(mbcs_init);
  687. module_exit(mbcs_exit);
  688. MODULE_AUTHOR("Bruce Losure <blosure@sgi.com>");
  689. MODULE_DESCRIPTION("Driver for MOATB Core Services");
  690. MODULE_LICENSE("GPL");