solos-pci.c 32 KB

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  1. /*
  2. * Driver for the Solos PCI ADSL2+ card, designed to support Linux by
  3. * Traverse Technologies -- http://www.traverse.com.au/
  4. * Xrio Limited -- http://www.xrio.com/
  5. *
  6. *
  7. * Copyright © 2008 Traverse Technologies
  8. * Copyright © 2008 Intel Corporation
  9. *
  10. * Authors: Nathan Williams <nathan@traverse.com.au>
  11. * David Woodhouse <dwmw2@infradead.org>
  12. * Treker Chen <treker@xrio.com>
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License
  16. * version 2, as published by the Free Software Foundation.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. */
  23. #define DEBUG
  24. #define VERBOSE_DEBUG
  25. #include <linux/interrupt.h>
  26. #include <linux/module.h>
  27. #include <linux/kernel.h>
  28. #include <linux/errno.h>
  29. #include <linux/ioport.h>
  30. #include <linux/types.h>
  31. #include <linux/pci.h>
  32. #include <linux/atm.h>
  33. #include <linux/atmdev.h>
  34. #include <linux/skbuff.h>
  35. #include <linux/sysfs.h>
  36. #include <linux/device.h>
  37. #include <linux/kobject.h>
  38. #include <linux/firmware.h>
  39. #include <linux/ctype.h>
  40. #include <linux/swab.h>
  41. #define VERSION "0.07"
  42. #define PTAG "solos-pci"
  43. #define CONFIG_RAM_SIZE 128
  44. #define FLAGS_ADDR 0x7C
  45. #define IRQ_EN_ADDR 0x78
  46. #define FPGA_VER 0x74
  47. #define IRQ_CLEAR 0x70
  48. #define WRITE_FLASH 0x6C
  49. #define PORTS 0x68
  50. #define FLASH_BLOCK 0x64
  51. #define FLASH_BUSY 0x60
  52. #define FPGA_MODE 0x5C
  53. #define FLASH_MODE 0x58
  54. #define TX_DMA_ADDR(port) (0x40 + (4 * (port)))
  55. #define RX_DMA_ADDR(port) (0x30 + (4 * (port)))
  56. #define DATA_RAM_SIZE 32768
  57. #define BUF_SIZE 4096
  58. #define FPGA_PAGE 528 /* FPGA flash page size*/
  59. #define SOLOS_PAGE 512 /* Solos flash page size*/
  60. #define FPGA_BLOCK (FPGA_PAGE * 8) /* FPGA flash block size*/
  61. #define SOLOS_BLOCK (SOLOS_PAGE * 8) /* Solos flash block size*/
  62. #define RX_BUF(card, nr) ((card->buffers) + (nr)*BUF_SIZE*2)
  63. #define TX_BUF(card, nr) ((card->buffers) + (nr)*BUF_SIZE*2 + BUF_SIZE)
  64. #define RX_DMA_SIZE 2048
  65. static int reset = 0;
  66. static int atmdebug = 0;
  67. static int firmware_upgrade = 0;
  68. static int fpga_upgrade = 0;
  69. struct pkt_hdr {
  70. __le16 size;
  71. __le16 vpi;
  72. __le16 vci;
  73. __le16 type;
  74. };
  75. struct solos_skb_cb {
  76. struct atm_vcc *vcc;
  77. uint32_t dma_addr;
  78. };
  79. #define SKB_CB(skb) ((struct solos_skb_cb *)skb->cb)
  80. #define PKT_DATA 0
  81. #define PKT_COMMAND 1
  82. #define PKT_POPEN 3
  83. #define PKT_PCLOSE 4
  84. #define PKT_STATUS 5
  85. struct solos_card {
  86. void __iomem *config_regs;
  87. void __iomem *buffers;
  88. int nr_ports;
  89. int tx_mask;
  90. struct pci_dev *dev;
  91. struct atm_dev *atmdev[4];
  92. struct tasklet_struct tlet;
  93. spinlock_t tx_lock;
  94. spinlock_t tx_queue_lock;
  95. spinlock_t cli_queue_lock;
  96. spinlock_t param_queue_lock;
  97. struct list_head param_queue;
  98. struct sk_buff_head tx_queue[4];
  99. struct sk_buff_head cli_queue[4];
  100. struct sk_buff *tx_skb[4];
  101. struct sk_buff *rx_skb[4];
  102. wait_queue_head_t param_wq;
  103. wait_queue_head_t fw_wq;
  104. int using_dma;
  105. };
  106. struct solos_param {
  107. struct list_head list;
  108. pid_t pid;
  109. int port;
  110. struct sk_buff *response;
  111. };
  112. #define SOLOS_CHAN(atmdev) ((int)(unsigned long)(atmdev)->phy_data)
  113. MODULE_AUTHOR("Traverse Technologies <support@traverse.com.au>");
  114. MODULE_DESCRIPTION("Solos PCI driver");
  115. MODULE_VERSION(VERSION);
  116. MODULE_LICENSE("GPL");
  117. MODULE_PARM_DESC(reset, "Reset Solos chips on startup");
  118. MODULE_PARM_DESC(atmdebug, "Print ATM data");
  119. MODULE_PARM_DESC(firmware_upgrade, "Initiate Solos firmware upgrade");
  120. MODULE_PARM_DESC(fpga_upgrade, "Initiate FPGA upgrade");
  121. module_param(reset, int, 0444);
  122. module_param(atmdebug, int, 0644);
  123. module_param(firmware_upgrade, int, 0444);
  124. module_param(fpga_upgrade, int, 0444);
  125. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  126. struct atm_vcc *vcc);
  127. static uint32_t fpga_tx(struct solos_card *);
  128. static irqreturn_t solos_irq(int irq, void *dev_id);
  129. static struct atm_vcc* find_vcc(struct atm_dev *dev, short vpi, int vci);
  130. static int list_vccs(int vci);
  131. static void release_vccs(struct atm_dev *dev);
  132. static int atm_init(struct solos_card *);
  133. static void atm_remove(struct solos_card *);
  134. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size);
  135. static void solos_bh(unsigned long);
  136. static int print_buffer(struct sk_buff *buf);
  137. static inline void solos_pop(struct atm_vcc *vcc, struct sk_buff *skb)
  138. {
  139. if (vcc->pop)
  140. vcc->pop(vcc, skb);
  141. else
  142. dev_kfree_skb_any(skb);
  143. }
  144. static ssize_t solos_param_show(struct device *dev, struct device_attribute *attr,
  145. char *buf)
  146. {
  147. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  148. struct solos_card *card = atmdev->dev_data;
  149. struct solos_param prm;
  150. struct sk_buff *skb;
  151. struct pkt_hdr *header;
  152. int buflen;
  153. buflen = strlen(attr->attr.name) + 10;
  154. skb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);
  155. if (!skb) {
  156. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_show()\n");
  157. return -ENOMEM;
  158. }
  159. header = (void *)skb_put(skb, sizeof(*header));
  160. buflen = snprintf((void *)&header[1], buflen - 1,
  161. "L%05d\n%s\n", current->pid, attr->attr.name);
  162. skb_put(skb, buflen);
  163. header->size = cpu_to_le16(buflen);
  164. header->vpi = cpu_to_le16(0);
  165. header->vci = cpu_to_le16(0);
  166. header->type = cpu_to_le16(PKT_COMMAND);
  167. prm.pid = current->pid;
  168. prm.response = NULL;
  169. prm.port = SOLOS_CHAN(atmdev);
  170. spin_lock_irq(&card->param_queue_lock);
  171. list_add(&prm.list, &card->param_queue);
  172. spin_unlock_irq(&card->param_queue_lock);
  173. fpga_queue(card, prm.port, skb, NULL);
  174. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  175. spin_lock_irq(&card->param_queue_lock);
  176. list_del(&prm.list);
  177. spin_unlock_irq(&card->param_queue_lock);
  178. if (!prm.response)
  179. return -EIO;
  180. buflen = prm.response->len;
  181. memcpy(buf, prm.response->data, buflen);
  182. kfree_skb(prm.response);
  183. return buflen;
  184. }
  185. static ssize_t solos_param_store(struct device *dev, struct device_attribute *attr,
  186. const char *buf, size_t count)
  187. {
  188. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  189. struct solos_card *card = atmdev->dev_data;
  190. struct solos_param prm;
  191. struct sk_buff *skb;
  192. struct pkt_hdr *header;
  193. int buflen;
  194. ssize_t ret;
  195. buflen = strlen(attr->attr.name) + 11 + count;
  196. skb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);
  197. if (!skb) {
  198. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_store()\n");
  199. return -ENOMEM;
  200. }
  201. header = (void *)skb_put(skb, sizeof(*header));
  202. buflen = snprintf((void *)&header[1], buflen - 1,
  203. "L%05d\n%s\n%s\n", current->pid, attr->attr.name, buf);
  204. skb_put(skb, buflen);
  205. header->size = cpu_to_le16(buflen);
  206. header->vpi = cpu_to_le16(0);
  207. header->vci = cpu_to_le16(0);
  208. header->type = cpu_to_le16(PKT_COMMAND);
  209. prm.pid = current->pid;
  210. prm.response = NULL;
  211. prm.port = SOLOS_CHAN(atmdev);
  212. spin_lock_irq(&card->param_queue_lock);
  213. list_add(&prm.list, &card->param_queue);
  214. spin_unlock_irq(&card->param_queue_lock);
  215. fpga_queue(card, prm.port, skb, NULL);
  216. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  217. spin_lock_irq(&card->param_queue_lock);
  218. list_del(&prm.list);
  219. spin_unlock_irq(&card->param_queue_lock);
  220. skb = prm.response;
  221. if (!skb)
  222. return -EIO;
  223. buflen = skb->len;
  224. /* Sometimes it has a newline, sometimes it doesn't. */
  225. if (skb->data[buflen - 1] == '\n')
  226. buflen--;
  227. if (buflen == 2 && !strncmp(skb->data, "OK", 2))
  228. ret = count;
  229. else if (buflen == 5 && !strncmp(skb->data, "ERROR", 5))
  230. ret = -EIO;
  231. else {
  232. /* We know we have enough space allocated for this; we allocated
  233. it ourselves */
  234. skb->data[buflen] = 0;
  235. dev_warn(&card->dev->dev, "Unexpected parameter response: '%s'\n",
  236. skb->data);
  237. ret = -EIO;
  238. }
  239. kfree_skb(skb);
  240. return ret;
  241. }
  242. static char *next_string(struct sk_buff *skb)
  243. {
  244. int i = 0;
  245. char *this = skb->data;
  246. for (i = 0; i < skb->len; i++) {
  247. if (this[i] == '\n') {
  248. this[i] = 0;
  249. skb_pull(skb, i + 1);
  250. return this;
  251. }
  252. if (!isprint(this[i]))
  253. return NULL;
  254. }
  255. return NULL;
  256. }
  257. /*
  258. * Status packet has fields separated by \n, starting with a version number
  259. * for the information therein. Fields are....
  260. *
  261. * packet version
  262. * RxBitRate (version >= 1)
  263. * TxBitRate (version >= 1)
  264. * State (version >= 1)
  265. * LocalSNRMargin (version >= 1)
  266. * LocalLineAttn (version >= 1)
  267. */
  268. static int process_status(struct solos_card *card, int port, struct sk_buff *skb)
  269. {
  270. char *str, *end, *state_str, *snr, *attn;
  271. int ver, rate_up, rate_down;
  272. if (!card->atmdev[port])
  273. return -ENODEV;
  274. str = next_string(skb);
  275. if (!str)
  276. return -EIO;
  277. ver = simple_strtol(str, NULL, 10);
  278. if (ver < 1) {
  279. dev_warn(&card->dev->dev, "Unexpected status interrupt version %d\n",
  280. ver);
  281. return -EIO;
  282. }
  283. str = next_string(skb);
  284. if (!str)
  285. return -EIO;
  286. if (!strcmp(str, "ERROR")) {
  287. dev_dbg(&card->dev->dev, "Status packet indicated Solos error on port %d (starting up?)\n",
  288. port);
  289. return 0;
  290. }
  291. rate_down = simple_strtol(str, &end, 10);
  292. if (*end)
  293. return -EIO;
  294. str = next_string(skb);
  295. if (!str)
  296. return -EIO;
  297. rate_up = simple_strtol(str, &end, 10);
  298. if (*end)
  299. return -EIO;
  300. state_str = next_string(skb);
  301. if (!state_str)
  302. return -EIO;
  303. /* Anything but 'Showtime' is down */
  304. if (strcmp(state_str, "Showtime")) {
  305. card->atmdev[port]->signal = ATM_PHY_SIG_LOST;
  306. release_vccs(card->atmdev[port]);
  307. dev_info(&card->dev->dev, "Port %d: %s\n", port, state_str);
  308. return 0;
  309. }
  310. snr = next_string(skb);
  311. if (!str)
  312. return -EIO;
  313. attn = next_string(skb);
  314. if (!attn)
  315. return -EIO;
  316. dev_info(&card->dev->dev, "Port %d: %s @%d/%d kb/s%s%s%s%s\n",
  317. port, state_str, rate_down/1000, rate_up/1000,
  318. snr[0]?", SNR ":"", snr, attn[0]?", Attn ":"", attn);
  319. card->atmdev[port]->link_rate = rate_down / 424;
  320. card->atmdev[port]->signal = ATM_PHY_SIG_FOUND;
  321. return 0;
  322. }
  323. static int process_command(struct solos_card *card, int port, struct sk_buff *skb)
  324. {
  325. struct solos_param *prm;
  326. unsigned long flags;
  327. int cmdpid;
  328. int found = 0;
  329. if (skb->len < 7)
  330. return 0;
  331. if (skb->data[0] != 'L' || !isdigit(skb->data[1]) ||
  332. !isdigit(skb->data[2]) || !isdigit(skb->data[3]) ||
  333. !isdigit(skb->data[4]) || !isdigit(skb->data[5]) ||
  334. skb->data[6] != '\n')
  335. return 0;
  336. cmdpid = simple_strtol(&skb->data[1], NULL, 10);
  337. spin_lock_irqsave(&card->param_queue_lock, flags);
  338. list_for_each_entry(prm, &card->param_queue, list) {
  339. if (prm->port == port && prm->pid == cmdpid) {
  340. prm->response = skb;
  341. skb_pull(skb, 7);
  342. wake_up(&card->param_wq);
  343. found = 1;
  344. break;
  345. }
  346. }
  347. spin_unlock_irqrestore(&card->param_queue_lock, flags);
  348. return found;
  349. }
  350. static ssize_t console_show(struct device *dev, struct device_attribute *attr,
  351. char *buf)
  352. {
  353. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  354. struct solos_card *card = atmdev->dev_data;
  355. struct sk_buff *skb;
  356. spin_lock(&card->cli_queue_lock);
  357. skb = skb_dequeue(&card->cli_queue[SOLOS_CHAN(atmdev)]);
  358. spin_unlock(&card->cli_queue_lock);
  359. if(skb == NULL)
  360. return sprintf(buf, "No data.\n");
  361. memcpy(buf, skb->data, skb->len);
  362. dev_dbg(&card->dev->dev, "len: %d\n", skb->len);
  363. kfree_skb(skb);
  364. return skb->len;
  365. }
  366. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size)
  367. {
  368. struct sk_buff *skb;
  369. struct pkt_hdr *header;
  370. if (size > (BUF_SIZE - sizeof(*header))) {
  371. dev_dbg(&card->dev->dev, "Command is too big. Dropping request\n");
  372. return 0;
  373. }
  374. skb = alloc_skb(size + sizeof(*header), GFP_ATOMIC);
  375. if (!skb) {
  376. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in send_command()\n");
  377. return 0;
  378. }
  379. header = (void *)skb_put(skb, sizeof(*header));
  380. header->size = cpu_to_le16(size);
  381. header->vpi = cpu_to_le16(0);
  382. header->vci = cpu_to_le16(0);
  383. header->type = cpu_to_le16(PKT_COMMAND);
  384. memcpy(skb_put(skb, size), buf, size);
  385. fpga_queue(card, dev, skb, NULL);
  386. return 0;
  387. }
  388. static ssize_t console_store(struct device *dev, struct device_attribute *attr,
  389. const char *buf, size_t count)
  390. {
  391. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  392. struct solos_card *card = atmdev->dev_data;
  393. int err;
  394. err = send_command(card, SOLOS_CHAN(atmdev), buf, count);
  395. return err?:count;
  396. }
  397. static DEVICE_ATTR(console, 0644, console_show, console_store);
  398. #define SOLOS_ATTR_RO(x) static DEVICE_ATTR(x, 0444, solos_param_show, NULL);
  399. #define SOLOS_ATTR_RW(x) static DEVICE_ATTR(x, 0644, solos_param_show, solos_param_store);
  400. #include "solos-attrlist.c"
  401. #undef SOLOS_ATTR_RO
  402. #undef SOLOS_ATTR_RW
  403. #define SOLOS_ATTR_RO(x) &dev_attr_##x.attr,
  404. #define SOLOS_ATTR_RW(x) &dev_attr_##x.attr,
  405. static struct attribute *solos_attrs[] = {
  406. #include "solos-attrlist.c"
  407. NULL
  408. };
  409. static struct attribute_group solos_attr_group = {
  410. .attrs = solos_attrs,
  411. .name = "parameters",
  412. };
  413. static int flash_upgrade(struct solos_card *card, int chip)
  414. {
  415. const struct firmware *fw;
  416. const char *fw_name;
  417. uint32_t data32 = 0;
  418. int blocksize = 0;
  419. int numblocks = 0;
  420. int offset;
  421. if (chip == 0) {
  422. fw_name = "solos-FPGA.bin";
  423. blocksize = FPGA_BLOCK;
  424. } else {
  425. fw_name = "solos-Firmware.bin";
  426. blocksize = SOLOS_BLOCK;
  427. }
  428. if (request_firmware(&fw, fw_name, &card->dev->dev))
  429. return -ENOENT;
  430. dev_info(&card->dev->dev, "Flash upgrade starting\n");
  431. numblocks = fw->size / blocksize;
  432. dev_info(&card->dev->dev, "Firmware size: %zd\n", fw->size);
  433. dev_info(&card->dev->dev, "Number of blocks: %d\n", numblocks);
  434. dev_info(&card->dev->dev, "Changing FPGA to Update mode\n");
  435. iowrite32(1, card->config_regs + FPGA_MODE);
  436. data32 = ioread32(card->config_regs + FPGA_MODE);
  437. /* Set mode to Chip Erase */
  438. dev_info(&card->dev->dev, "Set FPGA Flash mode to %s Chip Erase\n",
  439. chip?"Solos":"FPGA");
  440. iowrite32((chip * 2), card->config_regs + FLASH_MODE);
  441. iowrite32(1, card->config_regs + WRITE_FLASH);
  442. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  443. for (offset = 0; offset < fw->size; offset += blocksize) {
  444. int i;
  445. /* Clear write flag */
  446. iowrite32(0, card->config_regs + WRITE_FLASH);
  447. /* Set mode to Block Write */
  448. /* dev_info(&card->dev->dev, "Set FPGA Flash mode to Block Write\n"); */
  449. iowrite32(((chip * 2) + 1), card->config_regs + FLASH_MODE);
  450. /* Copy block to buffer, swapping each 16 bits */
  451. for(i = 0; i < blocksize; i += 4) {
  452. uint32_t word = swahb32p((uint32_t *)(fw->data + offset + i));
  453. iowrite32(word, RX_BUF(card, 3) + i);
  454. }
  455. /* Specify block number and then trigger flash write */
  456. iowrite32(offset / blocksize, card->config_regs + FLASH_BLOCK);
  457. iowrite32(1, card->config_regs + WRITE_FLASH);
  458. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  459. }
  460. release_firmware(fw);
  461. iowrite32(0, card->config_regs + WRITE_FLASH);
  462. iowrite32(0, card->config_regs + FPGA_MODE);
  463. iowrite32(0, card->config_regs + FLASH_MODE);
  464. dev_info(&card->dev->dev, "Returning FPGA to Data mode\n");
  465. return 0;
  466. }
  467. static irqreturn_t solos_irq(int irq, void *dev_id)
  468. {
  469. struct solos_card *card = dev_id;
  470. int handled = 1;
  471. iowrite32(0, card->config_regs + IRQ_CLEAR);
  472. /* If we're up and running, just kick the tasklet to process TX/RX */
  473. if (card->atmdev[0])
  474. tasklet_schedule(&card->tlet);
  475. else
  476. wake_up(&card->fw_wq);
  477. return IRQ_RETVAL(handled);
  478. }
  479. void solos_bh(unsigned long card_arg)
  480. {
  481. struct solos_card *card = (void *)card_arg;
  482. uint32_t card_flags;
  483. uint32_t rx_done = 0;
  484. int port;
  485. /*
  486. * Since fpga_tx() is going to need to read the flags under its lock,
  487. * it can return them to us so that we don't have to hit PCI MMIO
  488. * again for the same information
  489. */
  490. card_flags = fpga_tx(card);
  491. for (port = 0; port < card->nr_ports; port++) {
  492. if (card_flags & (0x10 << port)) {
  493. struct pkt_hdr _hdr, *header;
  494. struct sk_buff *skb;
  495. struct atm_vcc *vcc;
  496. int size;
  497. if (card->using_dma) {
  498. skb = card->rx_skb[port];
  499. card->rx_skb[port] = NULL;
  500. pci_unmap_single(card->dev, SKB_CB(skb)->dma_addr,
  501. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  502. header = (void *)skb->data;
  503. size = le16_to_cpu(header->size);
  504. skb_put(skb, size + sizeof(*header));
  505. skb_pull(skb, sizeof(*header));
  506. } else {
  507. header = &_hdr;
  508. rx_done |= 0x10 << port;
  509. memcpy_fromio(header, RX_BUF(card, port), sizeof(*header));
  510. size = le16_to_cpu(header->size);
  511. skb = alloc_skb(size + 1, GFP_ATOMIC);
  512. if (!skb) {
  513. if (net_ratelimit())
  514. dev_warn(&card->dev->dev, "Failed to allocate sk_buff for RX\n");
  515. continue;
  516. }
  517. memcpy_fromio(skb_put(skb, size),
  518. RX_BUF(card, port) + sizeof(*header),
  519. size);
  520. }
  521. if (atmdebug) {
  522. dev_info(&card->dev->dev, "Received: device %d\n", port);
  523. dev_info(&card->dev->dev, "size: %d VPI: %d VCI: %d\n",
  524. size, le16_to_cpu(header->vpi),
  525. le16_to_cpu(header->vci));
  526. print_buffer(skb);
  527. }
  528. switch (le16_to_cpu(header->type)) {
  529. case PKT_DATA:
  530. vcc = find_vcc(card->atmdev[port], le16_to_cpu(header->vpi),
  531. le16_to_cpu(header->vci));
  532. if (!vcc) {
  533. if (net_ratelimit())
  534. dev_warn(&card->dev->dev, "Received packet for unknown VCI.VPI %d.%d on port %d\n",
  535. le16_to_cpu(header->vci), le16_to_cpu(header->vpi),
  536. port);
  537. continue;
  538. }
  539. atm_charge(vcc, skb->truesize);
  540. vcc->push(vcc, skb);
  541. atomic_inc(&vcc->stats->rx);
  542. break;
  543. case PKT_STATUS:
  544. if (process_status(card, port, skb) &&
  545. net_ratelimit()) {
  546. dev_warn(&card->dev->dev, "Bad status packet of %d bytes on port %d:\n", skb->len, port);
  547. print_buffer(skb);
  548. }
  549. dev_kfree_skb_any(skb);
  550. break;
  551. case PKT_COMMAND:
  552. default: /* FIXME: Not really, surely? */
  553. if (process_command(card, port, skb))
  554. break;
  555. spin_lock(&card->cli_queue_lock);
  556. if (skb_queue_len(&card->cli_queue[port]) > 10) {
  557. if (net_ratelimit())
  558. dev_warn(&card->dev->dev, "Dropping console response on port %d\n",
  559. port);
  560. dev_kfree_skb_any(skb);
  561. } else
  562. skb_queue_tail(&card->cli_queue[port], skb);
  563. spin_unlock(&card->cli_queue_lock);
  564. break;
  565. }
  566. }
  567. /* Allocate RX skbs for any ports which need them */
  568. if (card->using_dma && card->atmdev[port] &&
  569. !card->rx_skb[port]) {
  570. struct sk_buff *skb = alloc_skb(RX_DMA_SIZE, GFP_ATOMIC);
  571. if (skb) {
  572. SKB_CB(skb)->dma_addr =
  573. pci_map_single(card->dev, skb->data,
  574. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  575. iowrite32(SKB_CB(skb)->dma_addr,
  576. card->config_regs + RX_DMA_ADDR(port));
  577. card->rx_skb[port] = skb;
  578. } else {
  579. if (net_ratelimit())
  580. dev_warn(&card->dev->dev, "Failed to allocate RX skb");
  581. /* We'll have to try again later */
  582. tasklet_schedule(&card->tlet);
  583. }
  584. }
  585. }
  586. if (rx_done)
  587. iowrite32(rx_done, card->config_regs + FLAGS_ADDR);
  588. return;
  589. }
  590. static struct atm_vcc *find_vcc(struct atm_dev *dev, short vpi, int vci)
  591. {
  592. struct hlist_head *head;
  593. struct atm_vcc *vcc = NULL;
  594. struct hlist_node *node;
  595. struct sock *s;
  596. read_lock(&vcc_sklist_lock);
  597. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  598. sk_for_each(s, node, head) {
  599. vcc = atm_sk(s);
  600. if (vcc->dev == dev && vcc->vci == vci &&
  601. vcc->vpi == vpi && vcc->qos.rxtp.traffic_class != ATM_NONE)
  602. goto out;
  603. }
  604. vcc = NULL;
  605. out:
  606. read_unlock(&vcc_sklist_lock);
  607. return vcc;
  608. }
  609. static int list_vccs(int vci)
  610. {
  611. struct hlist_head *head;
  612. struct atm_vcc *vcc;
  613. struct hlist_node *node;
  614. struct sock *s;
  615. int num_found = 0;
  616. int i;
  617. read_lock(&vcc_sklist_lock);
  618. if (vci != 0){
  619. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  620. sk_for_each(s, node, head) {
  621. num_found ++;
  622. vcc = atm_sk(s);
  623. printk(KERN_DEBUG "Device: %d Vpi: %d Vci: %d\n",
  624. vcc->dev->number,
  625. vcc->vpi,
  626. vcc->vci);
  627. }
  628. } else {
  629. for(i = 0; i < VCC_HTABLE_SIZE; i++){
  630. head = &vcc_hash[i];
  631. sk_for_each(s, node, head) {
  632. num_found ++;
  633. vcc = atm_sk(s);
  634. printk(KERN_DEBUG "Device: %d Vpi: %d Vci: %d\n",
  635. vcc->dev->number,
  636. vcc->vpi,
  637. vcc->vci);
  638. }
  639. }
  640. }
  641. read_unlock(&vcc_sklist_lock);
  642. return num_found;
  643. }
  644. static void release_vccs(struct atm_dev *dev)
  645. {
  646. int i;
  647. write_lock_irq(&vcc_sklist_lock);
  648. for (i = 0; i < VCC_HTABLE_SIZE; i++) {
  649. struct hlist_head *head = &vcc_hash[i];
  650. struct hlist_node *node, *tmp;
  651. struct sock *s;
  652. struct atm_vcc *vcc;
  653. sk_for_each_safe(s, node, tmp, head) {
  654. vcc = atm_sk(s);
  655. if (vcc->dev == dev) {
  656. vcc_release_async(vcc, -EPIPE);
  657. sk_del_node_init(s);
  658. }
  659. }
  660. }
  661. write_unlock_irq(&vcc_sklist_lock);
  662. }
  663. static int popen(struct atm_vcc *vcc)
  664. {
  665. struct solos_card *card = vcc->dev->dev_data;
  666. struct sk_buff *skb;
  667. struct pkt_hdr *header;
  668. if (vcc->qos.aal != ATM_AAL5) {
  669. dev_warn(&card->dev->dev, "Unsupported ATM type %d\n",
  670. vcc->qos.aal);
  671. return -EINVAL;
  672. }
  673. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  674. if (!skb && net_ratelimit()) {
  675. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in popen()\n");
  676. return -ENOMEM;
  677. }
  678. header = (void *)skb_put(skb, sizeof(*header));
  679. header->size = cpu_to_le16(0);
  680. header->vpi = cpu_to_le16(vcc->vpi);
  681. header->vci = cpu_to_le16(vcc->vci);
  682. header->type = cpu_to_le16(PKT_POPEN);
  683. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);
  684. set_bit(ATM_VF_ADDR, &vcc->flags);
  685. set_bit(ATM_VF_READY, &vcc->flags);
  686. list_vccs(0);
  687. return 0;
  688. }
  689. static void pclose(struct atm_vcc *vcc)
  690. {
  691. struct solos_card *card = vcc->dev->dev_data;
  692. struct sk_buff *skb;
  693. struct pkt_hdr *header;
  694. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  695. if (!skb) {
  696. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in pclose()\n");
  697. return;
  698. }
  699. header = (void *)skb_put(skb, sizeof(*header));
  700. header->size = cpu_to_le16(0);
  701. header->vpi = cpu_to_le16(vcc->vpi);
  702. header->vci = cpu_to_le16(vcc->vci);
  703. header->type = cpu_to_le16(PKT_PCLOSE);
  704. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);
  705. clear_bit(ATM_VF_ADDR, &vcc->flags);
  706. clear_bit(ATM_VF_READY, &vcc->flags);
  707. return;
  708. }
  709. static int print_buffer(struct sk_buff *buf)
  710. {
  711. int len,i;
  712. char msg[500];
  713. char item[10];
  714. len = buf->len;
  715. for (i = 0; i < len; i++){
  716. if(i % 8 == 0)
  717. sprintf(msg, "%02X: ", i);
  718. sprintf(item,"%02X ",*(buf->data + i));
  719. strcat(msg, item);
  720. if(i % 8 == 7) {
  721. sprintf(item, "\n");
  722. strcat(msg, item);
  723. printk(KERN_DEBUG "%s", msg);
  724. }
  725. }
  726. if (i % 8 != 0) {
  727. sprintf(item, "\n");
  728. strcat(msg, item);
  729. printk(KERN_DEBUG "%s", msg);
  730. }
  731. printk(KERN_DEBUG "\n");
  732. return 0;
  733. }
  734. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  735. struct atm_vcc *vcc)
  736. {
  737. int old_len;
  738. unsigned long flags;
  739. SKB_CB(skb)->vcc = vcc;
  740. spin_lock_irqsave(&card->tx_queue_lock, flags);
  741. old_len = skb_queue_len(&card->tx_queue[port]);
  742. skb_queue_tail(&card->tx_queue[port], skb);
  743. if (!old_len)
  744. card->tx_mask |= (1 << port);
  745. spin_unlock_irqrestore(&card->tx_queue_lock, flags);
  746. /* Theoretically we could just schedule the tasklet here, but
  747. that introduces latency we don't want -- it's noticeable */
  748. if (!old_len)
  749. fpga_tx(card);
  750. }
  751. static uint32_t fpga_tx(struct solos_card *card)
  752. {
  753. uint32_t tx_pending, card_flags;
  754. uint32_t tx_started = 0;
  755. struct sk_buff *skb;
  756. struct atm_vcc *vcc;
  757. unsigned char port;
  758. unsigned long flags;
  759. spin_lock_irqsave(&card->tx_lock, flags);
  760. card_flags = ioread32(card->config_regs + FLAGS_ADDR);
  761. /*
  762. * The queue lock is required for _writing_ to tx_mask, but we're
  763. * OK to read it here without locking. The only potential update
  764. * that we could race with is in fpga_queue() where it sets a bit
  765. * for a new port... but it's going to call this function again if
  766. * it's doing that, anyway.
  767. */
  768. tx_pending = card->tx_mask & ~card_flags;
  769. for (port = 0; tx_pending; tx_pending >>= 1, port++) {
  770. if (tx_pending & 1) {
  771. struct sk_buff *oldskb = card->tx_skb[port];
  772. if (oldskb)
  773. pci_unmap_single(card->dev, SKB_CB(oldskb)->dma_addr,
  774. oldskb->len, PCI_DMA_TODEVICE);
  775. spin_lock(&card->tx_queue_lock);
  776. skb = skb_dequeue(&card->tx_queue[port]);
  777. if (!skb)
  778. card->tx_mask &= ~(1 << port);
  779. spin_unlock(&card->tx_queue_lock);
  780. if (skb && !card->using_dma) {
  781. memcpy_toio(TX_BUF(card, port), skb->data, skb->len);
  782. tx_started |= 1 << port;
  783. oldskb = skb; /* We're done with this skb already */
  784. } else if (skb && card->using_dma) {
  785. SKB_CB(skb)->dma_addr = pci_map_single(card->dev, skb->data,
  786. skb->len, PCI_DMA_TODEVICE);
  787. iowrite32(SKB_CB(skb)->dma_addr,
  788. card->config_regs + TX_DMA_ADDR(port));
  789. }
  790. if (!oldskb)
  791. continue;
  792. /* Clean up and free oldskb now it's gone */
  793. if (atmdebug) {
  794. dev_info(&card->dev->dev, "Transmitted: port %d\n",
  795. port);
  796. print_buffer(oldskb);
  797. }
  798. vcc = SKB_CB(oldskb)->vcc;
  799. if (vcc) {
  800. atomic_inc(&vcc->stats->tx);
  801. solos_pop(vcc, oldskb);
  802. } else
  803. dev_kfree_skb_irq(oldskb);
  804. }
  805. }
  806. /* For non-DMA TX, write the 'TX start' bit for all four ports simultaneously */
  807. if (tx_started)
  808. iowrite32(tx_started, card->config_regs + FLAGS_ADDR);
  809. spin_unlock_irqrestore(&card->tx_lock, flags);
  810. return card_flags;
  811. }
  812. static int psend(struct atm_vcc *vcc, struct sk_buff *skb)
  813. {
  814. struct solos_card *card = vcc->dev->dev_data;
  815. struct pkt_hdr *header;
  816. int pktlen;
  817. pktlen = skb->len;
  818. if (pktlen > (BUF_SIZE - sizeof(*header))) {
  819. dev_warn(&card->dev->dev, "Length of PDU is too large. Dropping PDU.\n");
  820. solos_pop(vcc, skb);
  821. return 0;
  822. }
  823. if (!skb_clone_writable(skb, sizeof(*header))) {
  824. int expand_by = 0;
  825. int ret;
  826. if (skb_headroom(skb) < sizeof(*header))
  827. expand_by = sizeof(*header) - skb_headroom(skb);
  828. ret = pskb_expand_head(skb, expand_by, 0, GFP_ATOMIC);
  829. if (ret) {
  830. dev_warn(&card->dev->dev, "pskb_expand_head failed.\n");
  831. solos_pop(vcc, skb);
  832. return ret;
  833. }
  834. }
  835. header = (void *)skb_push(skb, sizeof(*header));
  836. /* This does _not_ include the size of the header */
  837. header->size = cpu_to_le16(pktlen);
  838. header->vpi = cpu_to_le16(vcc->vpi);
  839. header->vci = cpu_to_le16(vcc->vci);
  840. header->type = cpu_to_le16(PKT_DATA);
  841. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, vcc);
  842. return 0;
  843. }
  844. static struct atmdev_ops fpga_ops = {
  845. .open = popen,
  846. .close = pclose,
  847. .ioctl = NULL,
  848. .getsockopt = NULL,
  849. .setsockopt = NULL,
  850. .send = psend,
  851. .send_oam = NULL,
  852. .phy_put = NULL,
  853. .phy_get = NULL,
  854. .change_qos = NULL,
  855. .proc_read = NULL,
  856. .owner = THIS_MODULE
  857. };
  858. static int fpga_probe(struct pci_dev *dev, const struct pci_device_id *id)
  859. {
  860. int err;
  861. uint16_t fpga_ver;
  862. uint8_t major_ver, minor_ver;
  863. uint32_t data32;
  864. struct solos_card *card;
  865. card = kzalloc(sizeof(*card), GFP_KERNEL);
  866. if (!card)
  867. return -ENOMEM;
  868. card->dev = dev;
  869. init_waitqueue_head(&card->fw_wq);
  870. init_waitqueue_head(&card->param_wq);
  871. err = pci_enable_device(dev);
  872. if (err) {
  873. dev_warn(&dev->dev, "Failed to enable PCI device\n");
  874. goto out;
  875. }
  876. err = pci_set_dma_mask(dev, DMA_BIT_MASK(32));
  877. if (err) {
  878. dev_warn(&dev->dev, "Failed to set 32-bit DMA mask\n");
  879. goto out;
  880. }
  881. err = pci_request_regions(dev, "solos");
  882. if (err) {
  883. dev_warn(&dev->dev, "Failed to request regions\n");
  884. goto out;
  885. }
  886. card->config_regs = pci_iomap(dev, 0, CONFIG_RAM_SIZE);
  887. if (!card->config_regs) {
  888. dev_warn(&dev->dev, "Failed to ioremap config registers\n");
  889. goto out_release_regions;
  890. }
  891. card->buffers = pci_iomap(dev, 1, DATA_RAM_SIZE);
  892. if (!card->buffers) {
  893. dev_warn(&dev->dev, "Failed to ioremap data buffers\n");
  894. goto out_unmap_config;
  895. }
  896. if (reset) {
  897. iowrite32(1, card->config_regs + FPGA_MODE);
  898. data32 = ioread32(card->config_regs + FPGA_MODE);
  899. iowrite32(0, card->config_regs + FPGA_MODE);
  900. data32 = ioread32(card->config_regs + FPGA_MODE);
  901. }
  902. data32 = ioread32(card->config_regs + FPGA_VER);
  903. fpga_ver = (data32 & 0x0000FFFF);
  904. major_ver = ((data32 & 0xFF000000) >> 24);
  905. minor_ver = ((data32 & 0x00FF0000) >> 16);
  906. dev_info(&dev->dev, "Solos FPGA Version %d.%02d svn-%d\n",
  907. major_ver, minor_ver, fpga_ver);
  908. if (0 && fpga_ver > 27)
  909. card->using_dma = 1;
  910. else {
  911. /* Set RX empty flag for all ports */
  912. iowrite32(0xF0, card->config_regs + FLAGS_ADDR);
  913. }
  914. data32 = ioread32(card->config_regs + PORTS);
  915. card->nr_ports = (data32 & 0x000000FF);
  916. pci_set_drvdata(dev, card);
  917. tasklet_init(&card->tlet, solos_bh, (unsigned long)card);
  918. spin_lock_init(&card->tx_lock);
  919. spin_lock_init(&card->tx_queue_lock);
  920. spin_lock_init(&card->cli_queue_lock);
  921. spin_lock_init(&card->param_queue_lock);
  922. INIT_LIST_HEAD(&card->param_queue);
  923. err = request_irq(dev->irq, solos_irq, IRQF_SHARED,
  924. "solos-pci", card);
  925. if (err) {
  926. dev_dbg(&card->dev->dev, "Failed to request interrupt IRQ: %d\n", dev->irq);
  927. goto out_unmap_both;
  928. }
  929. iowrite32(1, card->config_regs + IRQ_EN_ADDR);
  930. if (fpga_upgrade)
  931. flash_upgrade(card, 0);
  932. if (firmware_upgrade)
  933. flash_upgrade(card, 1);
  934. err = atm_init(card);
  935. if (err)
  936. goto out_free_irq;
  937. return 0;
  938. out_free_irq:
  939. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  940. free_irq(dev->irq, card);
  941. tasklet_kill(&card->tlet);
  942. out_unmap_both:
  943. pci_set_drvdata(dev, NULL);
  944. pci_iounmap(dev, card->config_regs);
  945. out_unmap_config:
  946. pci_iounmap(dev, card->buffers);
  947. out_release_regions:
  948. pci_release_regions(dev);
  949. out:
  950. kfree(card);
  951. return err;
  952. }
  953. static int atm_init(struct solos_card *card)
  954. {
  955. int i;
  956. for (i = 0; i < card->nr_ports; i++) {
  957. struct sk_buff *skb;
  958. struct pkt_hdr *header;
  959. skb_queue_head_init(&card->tx_queue[i]);
  960. skb_queue_head_init(&card->cli_queue[i]);
  961. card->atmdev[i] = atm_dev_register("solos-pci", &fpga_ops, -1, NULL);
  962. if (!card->atmdev[i]) {
  963. dev_err(&card->dev->dev, "Could not register ATM device %d\n", i);
  964. atm_remove(card);
  965. return -ENODEV;
  966. }
  967. if (device_create_file(&card->atmdev[i]->class_dev, &dev_attr_console))
  968. dev_err(&card->dev->dev, "Could not register console for ATM device %d\n", i);
  969. if (sysfs_create_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group))
  970. dev_err(&card->dev->dev, "Could not register parameter group for ATM device %d\n", i);
  971. dev_info(&card->dev->dev, "Registered ATM device %d\n", card->atmdev[i]->number);
  972. card->atmdev[i]->ci_range.vpi_bits = 8;
  973. card->atmdev[i]->ci_range.vci_bits = 16;
  974. card->atmdev[i]->dev_data = card;
  975. card->atmdev[i]->phy_data = (void *)(unsigned long)i;
  976. card->atmdev[i]->signal = ATM_PHY_SIG_UNKNOWN;
  977. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  978. if (!skb) {
  979. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in atm_init()\n");
  980. continue;
  981. }
  982. header = (void *)skb_put(skb, sizeof(*header));
  983. header->size = cpu_to_le16(0);
  984. header->vpi = cpu_to_le16(0);
  985. header->vci = cpu_to_le16(0);
  986. header->type = cpu_to_le16(PKT_STATUS);
  987. fpga_queue(card, i, skb, NULL);
  988. }
  989. return 0;
  990. }
  991. static void atm_remove(struct solos_card *card)
  992. {
  993. int i;
  994. for (i = 0; i < card->nr_ports; i++) {
  995. if (card->atmdev[i]) {
  996. struct sk_buff *skb;
  997. dev_info(&card->dev->dev, "Unregistering ATM device %d\n", card->atmdev[i]->number);
  998. sysfs_remove_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group);
  999. atm_dev_deregister(card->atmdev[i]);
  1000. skb = card->rx_skb[i];
  1001. if (skb) {
  1002. pci_unmap_single(card->dev, SKB_CB(skb)->dma_addr,
  1003. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  1004. dev_kfree_skb(skb);
  1005. }
  1006. skb = card->tx_skb[i];
  1007. if (skb) {
  1008. pci_unmap_single(card->dev, SKB_CB(skb)->dma_addr,
  1009. skb->len, PCI_DMA_TODEVICE);
  1010. dev_kfree_skb(skb);
  1011. }
  1012. while ((skb = skb_dequeue(&card->tx_queue[i])))
  1013. dev_kfree_skb(skb);
  1014. }
  1015. }
  1016. }
  1017. static void fpga_remove(struct pci_dev *dev)
  1018. {
  1019. struct solos_card *card = pci_get_drvdata(dev);
  1020. /* Disable IRQs */
  1021. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  1022. /* Reset FPGA */
  1023. iowrite32(1, card->config_regs + FPGA_MODE);
  1024. (void)ioread32(card->config_regs + FPGA_MODE);
  1025. atm_remove(card);
  1026. free_irq(dev->irq, card);
  1027. tasklet_kill(&card->tlet);
  1028. /* Release device from reset */
  1029. iowrite32(0, card->config_regs + FPGA_MODE);
  1030. (void)ioread32(card->config_regs + FPGA_MODE);
  1031. pci_iounmap(dev, card->buffers);
  1032. pci_iounmap(dev, card->config_regs);
  1033. pci_release_regions(dev);
  1034. pci_disable_device(dev);
  1035. pci_set_drvdata(dev, NULL);
  1036. kfree(card);
  1037. }
  1038. static struct pci_device_id fpga_pci_tbl[] __devinitdata = {
  1039. { 0x10ee, 0x0300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  1040. { 0, }
  1041. };
  1042. MODULE_DEVICE_TABLE(pci,fpga_pci_tbl);
  1043. static struct pci_driver fpga_driver = {
  1044. .name = "solos",
  1045. .id_table = fpga_pci_tbl,
  1046. .probe = fpga_probe,
  1047. .remove = fpga_remove,
  1048. };
  1049. static int __init solos_pci_init(void)
  1050. {
  1051. printk(KERN_INFO "Solos PCI Driver Version %s\n", VERSION);
  1052. return pci_register_driver(&fpga_driver);
  1053. }
  1054. static void __exit solos_pci_exit(void)
  1055. {
  1056. pci_unregister_driver(&fpga_driver);
  1057. printk(KERN_INFO "Solos PCI Driver %s Unloaded\n", VERSION);
  1058. }
  1059. module_init(solos_pci_init);
  1060. module_exit(solos_pci_exit);