perf_counter.c 45 KB

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  1. /*
  2. * Performance counter x86 architecture code
  3. *
  4. * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
  5. * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
  6. * Copyright (C) 2009 Jaswinder Singh Rajput
  7. * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
  8. * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
  9. *
  10. * For licencing details see kernel-base/COPYING
  11. */
  12. #include <linux/perf_counter.h>
  13. #include <linux/capability.h>
  14. #include <linux/notifier.h>
  15. #include <linux/hardirq.h>
  16. #include <linux/kprobes.h>
  17. #include <linux/module.h>
  18. #include <linux/kdebug.h>
  19. #include <linux/sched.h>
  20. #include <linux/uaccess.h>
  21. #include <linux/highmem.h>
  22. #include <asm/apic.h>
  23. #include <asm/stacktrace.h>
  24. #include <asm/nmi.h>
  25. static u64 perf_counter_mask __read_mostly;
  26. struct cpu_hw_counters {
  27. struct perf_counter *counters[X86_PMC_IDX_MAX];
  28. unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  29. unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  30. unsigned long interrupts;
  31. int enabled;
  32. };
  33. /*
  34. * struct x86_pmu - generic x86 pmu
  35. */
  36. struct x86_pmu {
  37. const char *name;
  38. int version;
  39. int (*handle_irq)(struct pt_regs *);
  40. void (*disable_all)(void);
  41. void (*enable_all)(void);
  42. void (*enable)(struct hw_perf_counter *, int);
  43. void (*disable)(struct hw_perf_counter *, int);
  44. unsigned eventsel;
  45. unsigned perfctr;
  46. u64 (*event_map)(int);
  47. u64 (*raw_event)(u64);
  48. int max_events;
  49. int num_counters;
  50. int num_counters_fixed;
  51. int counter_bits;
  52. u64 counter_mask;
  53. u64 max_period;
  54. u64 intel_ctrl;
  55. };
  56. static struct x86_pmu x86_pmu __read_mostly;
  57. static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = {
  58. .enabled = 1,
  59. };
  60. /*
  61. * Not sure about some of these
  62. */
  63. static const u64 p6_perfmon_event_map[] =
  64. {
  65. [PERF_COUNT_HW_CPU_CYCLES] = 0x0079,
  66. [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
  67. [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0000,
  68. [PERF_COUNT_HW_CACHE_MISSES] = 0x0000,
  69. [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
  70. [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
  71. [PERF_COUNT_HW_BUS_CYCLES] = 0x0062,
  72. };
  73. static u64 p6_pmu_event_map(int event)
  74. {
  75. return p6_perfmon_event_map[event];
  76. }
  77. /*
  78. * Counter setting that is specified not to count anything.
  79. * We use this to effectively disable a counter.
  80. *
  81. * L2_RQSTS with 0 MESI unit mask.
  82. */
  83. #define P6_NOP_COUNTER 0x0000002EULL
  84. static u64 p6_pmu_raw_event(u64 event)
  85. {
  86. #define P6_EVNTSEL_EVENT_MASK 0x000000FFULL
  87. #define P6_EVNTSEL_UNIT_MASK 0x0000FF00ULL
  88. #define P6_EVNTSEL_EDGE_MASK 0x00040000ULL
  89. #define P6_EVNTSEL_INV_MASK 0x00800000ULL
  90. #define P6_EVNTSEL_COUNTER_MASK 0xFF000000ULL
  91. #define P6_EVNTSEL_MASK \
  92. (P6_EVNTSEL_EVENT_MASK | \
  93. P6_EVNTSEL_UNIT_MASK | \
  94. P6_EVNTSEL_EDGE_MASK | \
  95. P6_EVNTSEL_INV_MASK | \
  96. P6_EVNTSEL_COUNTER_MASK)
  97. return event & P6_EVNTSEL_MASK;
  98. }
  99. /*
  100. * Intel PerfMon v3. Used on Core2 and later.
  101. */
  102. static const u64 intel_perfmon_event_map[] =
  103. {
  104. [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
  105. [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
  106. [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
  107. [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
  108. [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
  109. [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
  110. [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
  111. };
  112. static u64 intel_pmu_event_map(int event)
  113. {
  114. return intel_perfmon_event_map[event];
  115. }
  116. /*
  117. * Generalized hw caching related event table, filled
  118. * in on a per model basis. A value of 0 means
  119. * 'not supported', -1 means 'event makes no sense on
  120. * this CPU', any other value means the raw event
  121. * ID.
  122. */
  123. #define C(x) PERF_COUNT_HW_CACHE_##x
  124. static u64 __read_mostly hw_cache_event_ids
  125. [PERF_COUNT_HW_CACHE_MAX]
  126. [PERF_COUNT_HW_CACHE_OP_MAX]
  127. [PERF_COUNT_HW_CACHE_RESULT_MAX];
  128. static const u64 nehalem_hw_cache_event_ids
  129. [PERF_COUNT_HW_CACHE_MAX]
  130. [PERF_COUNT_HW_CACHE_OP_MAX]
  131. [PERF_COUNT_HW_CACHE_RESULT_MAX] =
  132. {
  133. [ C(L1D) ] = {
  134. [ C(OP_READ) ] = {
  135. [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
  136. [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
  137. },
  138. [ C(OP_WRITE) ] = {
  139. [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
  140. [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
  141. },
  142. [ C(OP_PREFETCH) ] = {
  143. [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
  144. [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
  145. },
  146. },
  147. [ C(L1I ) ] = {
  148. [ C(OP_READ) ] = {
  149. [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
  150. [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
  151. },
  152. [ C(OP_WRITE) ] = {
  153. [ C(RESULT_ACCESS) ] = -1,
  154. [ C(RESULT_MISS) ] = -1,
  155. },
  156. [ C(OP_PREFETCH) ] = {
  157. [ C(RESULT_ACCESS) ] = 0x0,
  158. [ C(RESULT_MISS) ] = 0x0,
  159. },
  160. },
  161. [ C(LL ) ] = {
  162. [ C(OP_READ) ] = {
  163. [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */
  164. [ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */
  165. },
  166. [ C(OP_WRITE) ] = {
  167. [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */
  168. [ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */
  169. },
  170. [ C(OP_PREFETCH) ] = {
  171. [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */
  172. [ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */
  173. },
  174. },
  175. [ C(DTLB) ] = {
  176. [ C(OP_READ) ] = {
  177. [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
  178. [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
  179. },
  180. [ C(OP_WRITE) ] = {
  181. [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
  182. [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
  183. },
  184. [ C(OP_PREFETCH) ] = {
  185. [ C(RESULT_ACCESS) ] = 0x0,
  186. [ C(RESULT_MISS) ] = 0x0,
  187. },
  188. },
  189. [ C(ITLB) ] = {
  190. [ C(OP_READ) ] = {
  191. [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
  192. [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
  193. },
  194. [ C(OP_WRITE) ] = {
  195. [ C(RESULT_ACCESS) ] = -1,
  196. [ C(RESULT_MISS) ] = -1,
  197. },
  198. [ C(OP_PREFETCH) ] = {
  199. [ C(RESULT_ACCESS) ] = -1,
  200. [ C(RESULT_MISS) ] = -1,
  201. },
  202. },
  203. [ C(BPU ) ] = {
  204. [ C(OP_READ) ] = {
  205. [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
  206. [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
  207. },
  208. [ C(OP_WRITE) ] = {
  209. [ C(RESULT_ACCESS) ] = -1,
  210. [ C(RESULT_MISS) ] = -1,
  211. },
  212. [ C(OP_PREFETCH) ] = {
  213. [ C(RESULT_ACCESS) ] = -1,
  214. [ C(RESULT_MISS) ] = -1,
  215. },
  216. },
  217. };
  218. static const u64 core2_hw_cache_event_ids
  219. [PERF_COUNT_HW_CACHE_MAX]
  220. [PERF_COUNT_HW_CACHE_OP_MAX]
  221. [PERF_COUNT_HW_CACHE_RESULT_MAX] =
  222. {
  223. [ C(L1D) ] = {
  224. [ C(OP_READ) ] = {
  225. [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
  226. [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
  227. },
  228. [ C(OP_WRITE) ] = {
  229. [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
  230. [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
  231. },
  232. [ C(OP_PREFETCH) ] = {
  233. [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
  234. [ C(RESULT_MISS) ] = 0,
  235. },
  236. },
  237. [ C(L1I ) ] = {
  238. [ C(OP_READ) ] = {
  239. [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
  240. [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
  241. },
  242. [ C(OP_WRITE) ] = {
  243. [ C(RESULT_ACCESS) ] = -1,
  244. [ C(RESULT_MISS) ] = -1,
  245. },
  246. [ C(OP_PREFETCH) ] = {
  247. [ C(RESULT_ACCESS) ] = 0,
  248. [ C(RESULT_MISS) ] = 0,
  249. },
  250. },
  251. [ C(LL ) ] = {
  252. [ C(OP_READ) ] = {
  253. [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
  254. [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
  255. },
  256. [ C(OP_WRITE) ] = {
  257. [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
  258. [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
  259. },
  260. [ C(OP_PREFETCH) ] = {
  261. [ C(RESULT_ACCESS) ] = 0,
  262. [ C(RESULT_MISS) ] = 0,
  263. },
  264. },
  265. [ C(DTLB) ] = {
  266. [ C(OP_READ) ] = {
  267. [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
  268. [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
  269. },
  270. [ C(OP_WRITE) ] = {
  271. [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
  272. [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
  273. },
  274. [ C(OP_PREFETCH) ] = {
  275. [ C(RESULT_ACCESS) ] = 0,
  276. [ C(RESULT_MISS) ] = 0,
  277. },
  278. },
  279. [ C(ITLB) ] = {
  280. [ C(OP_READ) ] = {
  281. [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
  282. [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
  283. },
  284. [ C(OP_WRITE) ] = {
  285. [ C(RESULT_ACCESS) ] = -1,
  286. [ C(RESULT_MISS) ] = -1,
  287. },
  288. [ C(OP_PREFETCH) ] = {
  289. [ C(RESULT_ACCESS) ] = -1,
  290. [ C(RESULT_MISS) ] = -1,
  291. },
  292. },
  293. [ C(BPU ) ] = {
  294. [ C(OP_READ) ] = {
  295. [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
  296. [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
  297. },
  298. [ C(OP_WRITE) ] = {
  299. [ C(RESULT_ACCESS) ] = -1,
  300. [ C(RESULT_MISS) ] = -1,
  301. },
  302. [ C(OP_PREFETCH) ] = {
  303. [ C(RESULT_ACCESS) ] = -1,
  304. [ C(RESULT_MISS) ] = -1,
  305. },
  306. },
  307. };
  308. static const u64 atom_hw_cache_event_ids
  309. [PERF_COUNT_HW_CACHE_MAX]
  310. [PERF_COUNT_HW_CACHE_OP_MAX]
  311. [PERF_COUNT_HW_CACHE_RESULT_MAX] =
  312. {
  313. [ C(L1D) ] = {
  314. [ C(OP_READ) ] = {
  315. [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
  316. [ C(RESULT_MISS) ] = 0,
  317. },
  318. [ C(OP_WRITE) ] = {
  319. [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
  320. [ C(RESULT_MISS) ] = 0,
  321. },
  322. [ C(OP_PREFETCH) ] = {
  323. [ C(RESULT_ACCESS) ] = 0x0,
  324. [ C(RESULT_MISS) ] = 0,
  325. },
  326. },
  327. [ C(L1I ) ] = {
  328. [ C(OP_READ) ] = {
  329. [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
  330. [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
  331. },
  332. [ C(OP_WRITE) ] = {
  333. [ C(RESULT_ACCESS) ] = -1,
  334. [ C(RESULT_MISS) ] = -1,
  335. },
  336. [ C(OP_PREFETCH) ] = {
  337. [ C(RESULT_ACCESS) ] = 0,
  338. [ C(RESULT_MISS) ] = 0,
  339. },
  340. },
  341. [ C(LL ) ] = {
  342. [ C(OP_READ) ] = {
  343. [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
  344. [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
  345. },
  346. [ C(OP_WRITE) ] = {
  347. [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
  348. [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
  349. },
  350. [ C(OP_PREFETCH) ] = {
  351. [ C(RESULT_ACCESS) ] = 0,
  352. [ C(RESULT_MISS) ] = 0,
  353. },
  354. },
  355. [ C(DTLB) ] = {
  356. [ C(OP_READ) ] = {
  357. [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
  358. [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
  359. },
  360. [ C(OP_WRITE) ] = {
  361. [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
  362. [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
  363. },
  364. [ C(OP_PREFETCH) ] = {
  365. [ C(RESULT_ACCESS) ] = 0,
  366. [ C(RESULT_MISS) ] = 0,
  367. },
  368. },
  369. [ C(ITLB) ] = {
  370. [ C(OP_READ) ] = {
  371. [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
  372. [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
  373. },
  374. [ C(OP_WRITE) ] = {
  375. [ C(RESULT_ACCESS) ] = -1,
  376. [ C(RESULT_MISS) ] = -1,
  377. },
  378. [ C(OP_PREFETCH) ] = {
  379. [ C(RESULT_ACCESS) ] = -1,
  380. [ C(RESULT_MISS) ] = -1,
  381. },
  382. },
  383. [ C(BPU ) ] = {
  384. [ C(OP_READ) ] = {
  385. [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
  386. [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
  387. },
  388. [ C(OP_WRITE) ] = {
  389. [ C(RESULT_ACCESS) ] = -1,
  390. [ C(RESULT_MISS) ] = -1,
  391. },
  392. [ C(OP_PREFETCH) ] = {
  393. [ C(RESULT_ACCESS) ] = -1,
  394. [ C(RESULT_MISS) ] = -1,
  395. },
  396. },
  397. };
  398. static u64 intel_pmu_raw_event(u64 event)
  399. {
  400. #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
  401. #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
  402. #define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL
  403. #define CORE_EVNTSEL_INV_MASK 0x00800000ULL
  404. #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL
  405. #define CORE_EVNTSEL_MASK \
  406. (CORE_EVNTSEL_EVENT_MASK | \
  407. CORE_EVNTSEL_UNIT_MASK | \
  408. CORE_EVNTSEL_EDGE_MASK | \
  409. CORE_EVNTSEL_INV_MASK | \
  410. CORE_EVNTSEL_COUNTER_MASK)
  411. return event & CORE_EVNTSEL_MASK;
  412. }
  413. static const u64 amd_hw_cache_event_ids
  414. [PERF_COUNT_HW_CACHE_MAX]
  415. [PERF_COUNT_HW_CACHE_OP_MAX]
  416. [PERF_COUNT_HW_CACHE_RESULT_MAX] =
  417. {
  418. [ C(L1D) ] = {
  419. [ C(OP_READ) ] = {
  420. [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
  421. [ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */
  422. },
  423. [ C(OP_WRITE) ] = {
  424. [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */
  425. [ C(RESULT_MISS) ] = 0,
  426. },
  427. [ C(OP_PREFETCH) ] = {
  428. [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */
  429. [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */
  430. },
  431. },
  432. [ C(L1I ) ] = {
  433. [ C(OP_READ) ] = {
  434. [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches */
  435. [ C(RESULT_MISS) ] = 0x0081, /* Instruction cache misses */
  436. },
  437. [ C(OP_WRITE) ] = {
  438. [ C(RESULT_ACCESS) ] = -1,
  439. [ C(RESULT_MISS) ] = -1,
  440. },
  441. [ C(OP_PREFETCH) ] = {
  442. [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */
  443. [ C(RESULT_MISS) ] = 0,
  444. },
  445. },
  446. [ C(LL ) ] = {
  447. [ C(OP_READ) ] = {
  448. [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
  449. [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */
  450. },
  451. [ C(OP_WRITE) ] = {
  452. [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */
  453. [ C(RESULT_MISS) ] = 0,
  454. },
  455. [ C(OP_PREFETCH) ] = {
  456. [ C(RESULT_ACCESS) ] = 0,
  457. [ C(RESULT_MISS) ] = 0,
  458. },
  459. },
  460. [ C(DTLB) ] = {
  461. [ C(OP_READ) ] = {
  462. [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
  463. [ C(RESULT_MISS) ] = 0x0046, /* L1 DTLB and L2 DLTB Miss */
  464. },
  465. [ C(OP_WRITE) ] = {
  466. [ C(RESULT_ACCESS) ] = 0,
  467. [ C(RESULT_MISS) ] = 0,
  468. },
  469. [ C(OP_PREFETCH) ] = {
  470. [ C(RESULT_ACCESS) ] = 0,
  471. [ C(RESULT_MISS) ] = 0,
  472. },
  473. },
  474. [ C(ITLB) ] = {
  475. [ C(OP_READ) ] = {
  476. [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */
  477. [ C(RESULT_MISS) ] = 0x0085, /* Instr. fetch ITLB misses */
  478. },
  479. [ C(OP_WRITE) ] = {
  480. [ C(RESULT_ACCESS) ] = -1,
  481. [ C(RESULT_MISS) ] = -1,
  482. },
  483. [ C(OP_PREFETCH) ] = {
  484. [ C(RESULT_ACCESS) ] = -1,
  485. [ C(RESULT_MISS) ] = -1,
  486. },
  487. },
  488. [ C(BPU ) ] = {
  489. [ C(OP_READ) ] = {
  490. [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr. */
  491. [ C(RESULT_MISS) ] = 0x00c3, /* Retired Mispredicted BI */
  492. },
  493. [ C(OP_WRITE) ] = {
  494. [ C(RESULT_ACCESS) ] = -1,
  495. [ C(RESULT_MISS) ] = -1,
  496. },
  497. [ C(OP_PREFETCH) ] = {
  498. [ C(RESULT_ACCESS) ] = -1,
  499. [ C(RESULT_MISS) ] = -1,
  500. },
  501. },
  502. };
  503. /*
  504. * AMD Performance Monitor K7 and later.
  505. */
  506. static const u64 amd_perfmon_event_map[] =
  507. {
  508. [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
  509. [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
  510. [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0080,
  511. [PERF_COUNT_HW_CACHE_MISSES] = 0x0081,
  512. [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
  513. [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
  514. };
  515. static u64 amd_pmu_event_map(int event)
  516. {
  517. return amd_perfmon_event_map[event];
  518. }
  519. static u64 amd_pmu_raw_event(u64 event)
  520. {
  521. #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
  522. #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
  523. #define K7_EVNTSEL_EDGE_MASK 0x000040000ULL
  524. #define K7_EVNTSEL_INV_MASK 0x000800000ULL
  525. #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL
  526. #define K7_EVNTSEL_MASK \
  527. (K7_EVNTSEL_EVENT_MASK | \
  528. K7_EVNTSEL_UNIT_MASK | \
  529. K7_EVNTSEL_EDGE_MASK | \
  530. K7_EVNTSEL_INV_MASK | \
  531. K7_EVNTSEL_COUNTER_MASK)
  532. return event & K7_EVNTSEL_MASK;
  533. }
  534. /*
  535. * Propagate counter elapsed time into the generic counter.
  536. * Can only be executed on the CPU where the counter is active.
  537. * Returns the delta events processed.
  538. */
  539. static u64
  540. x86_perf_counter_update(struct perf_counter *counter,
  541. struct hw_perf_counter *hwc, int idx)
  542. {
  543. int shift = 64 - x86_pmu.counter_bits;
  544. u64 prev_raw_count, new_raw_count;
  545. s64 delta;
  546. /*
  547. * Careful: an NMI might modify the previous counter value.
  548. *
  549. * Our tactic to handle this is to first atomically read and
  550. * exchange a new raw count - then add that new-prev delta
  551. * count to the generic counter atomically:
  552. */
  553. again:
  554. prev_raw_count = atomic64_read(&hwc->prev_count);
  555. rdmsrl(hwc->counter_base + idx, new_raw_count);
  556. if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
  557. new_raw_count) != prev_raw_count)
  558. goto again;
  559. /*
  560. * Now we have the new raw value and have updated the prev
  561. * timestamp already. We can now calculate the elapsed delta
  562. * (counter-)time and add that to the generic counter.
  563. *
  564. * Careful, not all hw sign-extends above the physical width
  565. * of the count.
  566. */
  567. delta = (new_raw_count << shift) - (prev_raw_count << shift);
  568. delta >>= shift;
  569. atomic64_add(delta, &counter->count);
  570. atomic64_sub(delta, &hwc->period_left);
  571. return new_raw_count;
  572. }
  573. static atomic_t active_counters;
  574. static DEFINE_MUTEX(pmc_reserve_mutex);
  575. static bool reserve_pmc_hardware(void)
  576. {
  577. int i;
  578. if (nmi_watchdog == NMI_LOCAL_APIC)
  579. disable_lapic_nmi_watchdog();
  580. for (i = 0; i < x86_pmu.num_counters; i++) {
  581. if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
  582. goto perfctr_fail;
  583. }
  584. for (i = 0; i < x86_pmu.num_counters; i++) {
  585. if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
  586. goto eventsel_fail;
  587. }
  588. return true;
  589. eventsel_fail:
  590. for (i--; i >= 0; i--)
  591. release_evntsel_nmi(x86_pmu.eventsel + i);
  592. i = x86_pmu.num_counters;
  593. perfctr_fail:
  594. for (i--; i >= 0; i--)
  595. release_perfctr_nmi(x86_pmu.perfctr + i);
  596. if (nmi_watchdog == NMI_LOCAL_APIC)
  597. enable_lapic_nmi_watchdog();
  598. return false;
  599. }
  600. static void release_pmc_hardware(void)
  601. {
  602. int i;
  603. for (i = 0; i < x86_pmu.num_counters; i++) {
  604. release_perfctr_nmi(x86_pmu.perfctr + i);
  605. release_evntsel_nmi(x86_pmu.eventsel + i);
  606. }
  607. if (nmi_watchdog == NMI_LOCAL_APIC)
  608. enable_lapic_nmi_watchdog();
  609. }
  610. static void hw_perf_counter_destroy(struct perf_counter *counter)
  611. {
  612. if (atomic_dec_and_mutex_lock(&active_counters, &pmc_reserve_mutex)) {
  613. release_pmc_hardware();
  614. mutex_unlock(&pmc_reserve_mutex);
  615. }
  616. }
  617. static inline int x86_pmu_initialized(void)
  618. {
  619. return x86_pmu.handle_irq != NULL;
  620. }
  621. static inline int
  622. set_ext_hw_attr(struct hw_perf_counter *hwc, struct perf_counter_attr *attr)
  623. {
  624. unsigned int cache_type, cache_op, cache_result;
  625. u64 config, val;
  626. config = attr->config;
  627. cache_type = (config >> 0) & 0xff;
  628. if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
  629. return -EINVAL;
  630. cache_op = (config >> 8) & 0xff;
  631. if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
  632. return -EINVAL;
  633. cache_result = (config >> 16) & 0xff;
  634. if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
  635. return -EINVAL;
  636. val = hw_cache_event_ids[cache_type][cache_op][cache_result];
  637. if (val == 0)
  638. return -ENOENT;
  639. if (val == -1)
  640. return -EINVAL;
  641. hwc->config |= val;
  642. return 0;
  643. }
  644. /*
  645. * Setup the hardware configuration for a given attr_type
  646. */
  647. static int __hw_perf_counter_init(struct perf_counter *counter)
  648. {
  649. struct perf_counter_attr *attr = &counter->attr;
  650. struct hw_perf_counter *hwc = &counter->hw;
  651. u64 config;
  652. int err;
  653. if (!x86_pmu_initialized())
  654. return -ENODEV;
  655. err = 0;
  656. if (!atomic_inc_not_zero(&active_counters)) {
  657. mutex_lock(&pmc_reserve_mutex);
  658. if (atomic_read(&active_counters) == 0 && !reserve_pmc_hardware())
  659. err = -EBUSY;
  660. else
  661. atomic_inc(&active_counters);
  662. mutex_unlock(&pmc_reserve_mutex);
  663. }
  664. if (err)
  665. return err;
  666. /*
  667. * Generate PMC IRQs:
  668. * (keep 'enabled' bit clear for now)
  669. */
  670. hwc->config = ARCH_PERFMON_EVENTSEL_INT;
  671. /*
  672. * Count user and OS events unless requested not to.
  673. */
  674. if (!attr->exclude_user)
  675. hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
  676. if (!attr->exclude_kernel)
  677. hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
  678. if (!hwc->sample_period) {
  679. hwc->sample_period = x86_pmu.max_period;
  680. hwc->last_period = hwc->sample_period;
  681. atomic64_set(&hwc->period_left, hwc->sample_period);
  682. }
  683. counter->destroy = hw_perf_counter_destroy;
  684. /*
  685. * Raw event type provide the config in the event structure
  686. */
  687. if (attr->type == PERF_TYPE_RAW) {
  688. hwc->config |= x86_pmu.raw_event(attr->config);
  689. return 0;
  690. }
  691. if (attr->type == PERF_TYPE_HW_CACHE)
  692. return set_ext_hw_attr(hwc, attr);
  693. if (attr->config >= x86_pmu.max_events)
  694. return -EINVAL;
  695. /*
  696. * The generic map:
  697. */
  698. config = x86_pmu.event_map(attr->config);
  699. if (config == 0)
  700. return -ENOENT;
  701. if (config == -1LL)
  702. return -EINVAL;
  703. hwc->config |= config;
  704. return 0;
  705. }
  706. static void p6_pmu_disable_all(void)
  707. {
  708. struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
  709. u64 val;
  710. if (!cpuc->enabled)
  711. return;
  712. cpuc->enabled = 0;
  713. barrier();
  714. /* p6 only has one enable register */
  715. rdmsrl(MSR_P6_EVNTSEL0, val);
  716. val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
  717. wrmsrl(MSR_P6_EVNTSEL0, val);
  718. }
  719. static void intel_pmu_disable_all(void)
  720. {
  721. wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
  722. }
  723. static void amd_pmu_disable_all(void)
  724. {
  725. struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
  726. int idx;
  727. if (!cpuc->enabled)
  728. return;
  729. cpuc->enabled = 0;
  730. /*
  731. * ensure we write the disable before we start disabling the
  732. * counters proper, so that amd_pmu_enable_counter() does the
  733. * right thing.
  734. */
  735. barrier();
  736. for (idx = 0; idx < x86_pmu.num_counters; idx++) {
  737. u64 val;
  738. if (!test_bit(idx, cpuc->active_mask))
  739. continue;
  740. rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
  741. if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE))
  742. continue;
  743. val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
  744. wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
  745. }
  746. }
  747. void hw_perf_disable(void)
  748. {
  749. if (!x86_pmu_initialized())
  750. return;
  751. return x86_pmu.disable_all();
  752. }
  753. static void p6_pmu_enable_all(void)
  754. {
  755. struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
  756. unsigned long val;
  757. if (cpuc->enabled)
  758. return;
  759. cpuc->enabled = 1;
  760. barrier();
  761. /* p6 only has one enable register */
  762. rdmsrl(MSR_P6_EVNTSEL0, val);
  763. val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
  764. wrmsrl(MSR_P6_EVNTSEL0, val);
  765. }
  766. static void intel_pmu_enable_all(void)
  767. {
  768. wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
  769. }
  770. static void amd_pmu_enable_all(void)
  771. {
  772. struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
  773. int idx;
  774. if (cpuc->enabled)
  775. return;
  776. cpuc->enabled = 1;
  777. barrier();
  778. for (idx = 0; idx < x86_pmu.num_counters; idx++) {
  779. struct perf_counter *counter = cpuc->counters[idx];
  780. u64 val;
  781. if (!test_bit(idx, cpuc->active_mask))
  782. continue;
  783. val = counter->hw.config;
  784. val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
  785. wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
  786. }
  787. }
  788. void hw_perf_enable(void)
  789. {
  790. if (!x86_pmu_initialized())
  791. return;
  792. x86_pmu.enable_all();
  793. }
  794. static inline u64 intel_pmu_get_status(void)
  795. {
  796. u64 status;
  797. rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
  798. return status;
  799. }
  800. static inline void intel_pmu_ack_status(u64 ack)
  801. {
  802. wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
  803. }
  804. static inline void x86_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
  805. {
  806. (void)checking_wrmsrl(hwc->config_base + idx,
  807. hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE);
  808. }
  809. static inline void x86_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
  810. {
  811. (void)checking_wrmsrl(hwc->config_base + idx, hwc->config);
  812. }
  813. static inline void
  814. intel_pmu_disable_fixed(struct hw_perf_counter *hwc, int __idx)
  815. {
  816. int idx = __idx - X86_PMC_IDX_FIXED;
  817. u64 ctrl_val, mask;
  818. mask = 0xfULL << (idx * 4);
  819. rdmsrl(hwc->config_base, ctrl_val);
  820. ctrl_val &= ~mask;
  821. (void)checking_wrmsrl(hwc->config_base, ctrl_val);
  822. }
  823. static inline void
  824. p6_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
  825. {
  826. struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
  827. u64 val = P6_NOP_COUNTER;
  828. if (cpuc->enabled)
  829. val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
  830. (void)checking_wrmsrl(hwc->config_base + idx, val);
  831. }
  832. static inline void
  833. intel_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
  834. {
  835. if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
  836. intel_pmu_disable_fixed(hwc, idx);
  837. return;
  838. }
  839. x86_pmu_disable_counter(hwc, idx);
  840. }
  841. static inline void
  842. amd_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
  843. {
  844. x86_pmu_disable_counter(hwc, idx);
  845. }
  846. static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]);
  847. /*
  848. * Set the next IRQ period, based on the hwc->period_left value.
  849. * To be called with the counter disabled in hw:
  850. */
  851. static int
  852. x86_perf_counter_set_period(struct perf_counter *counter,
  853. struct hw_perf_counter *hwc, int idx)
  854. {
  855. s64 left = atomic64_read(&hwc->period_left);
  856. s64 period = hwc->sample_period;
  857. int err, ret = 0;
  858. /*
  859. * If we are way outside a reasoable range then just skip forward:
  860. */
  861. if (unlikely(left <= -period)) {
  862. left = period;
  863. atomic64_set(&hwc->period_left, left);
  864. hwc->last_period = period;
  865. ret = 1;
  866. }
  867. if (unlikely(left <= 0)) {
  868. left += period;
  869. atomic64_set(&hwc->period_left, left);
  870. hwc->last_period = period;
  871. ret = 1;
  872. }
  873. /*
  874. * Quirk: certain CPUs dont like it if just 1 event is left:
  875. */
  876. if (unlikely(left < 2))
  877. left = 2;
  878. if (left > x86_pmu.max_period)
  879. left = x86_pmu.max_period;
  880. per_cpu(prev_left[idx], smp_processor_id()) = left;
  881. /*
  882. * The hw counter starts counting from this counter offset,
  883. * mark it to be able to extra future deltas:
  884. */
  885. atomic64_set(&hwc->prev_count, (u64)-left);
  886. err = checking_wrmsrl(hwc->counter_base + idx,
  887. (u64)(-left) & x86_pmu.counter_mask);
  888. perf_counter_update_userpage(counter);
  889. return ret;
  890. }
  891. static inline void
  892. intel_pmu_enable_fixed(struct hw_perf_counter *hwc, int __idx)
  893. {
  894. int idx = __idx - X86_PMC_IDX_FIXED;
  895. u64 ctrl_val, bits, mask;
  896. int err;
  897. /*
  898. * Enable IRQ generation (0x8),
  899. * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
  900. * if requested:
  901. */
  902. bits = 0x8ULL;
  903. if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
  904. bits |= 0x2;
  905. if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
  906. bits |= 0x1;
  907. bits <<= (idx * 4);
  908. mask = 0xfULL << (idx * 4);
  909. rdmsrl(hwc->config_base, ctrl_val);
  910. ctrl_val &= ~mask;
  911. ctrl_val |= bits;
  912. err = checking_wrmsrl(hwc->config_base, ctrl_val);
  913. }
  914. static void p6_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
  915. {
  916. struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
  917. u64 val;
  918. val = hwc->config;
  919. if (cpuc->enabled)
  920. val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
  921. (void)checking_wrmsrl(hwc->config_base + idx, val);
  922. }
  923. static void intel_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
  924. {
  925. if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
  926. intel_pmu_enable_fixed(hwc, idx);
  927. return;
  928. }
  929. x86_pmu_enable_counter(hwc, idx);
  930. }
  931. static void amd_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
  932. {
  933. struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
  934. if (cpuc->enabled)
  935. x86_pmu_enable_counter(hwc, idx);
  936. }
  937. static int
  938. fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc)
  939. {
  940. unsigned int event;
  941. if (!x86_pmu.num_counters_fixed)
  942. return -1;
  943. event = hwc->config & ARCH_PERFMON_EVENT_MASK;
  944. if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_INSTRUCTIONS)))
  945. return X86_PMC_IDX_FIXED_INSTRUCTIONS;
  946. if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_CPU_CYCLES)))
  947. return X86_PMC_IDX_FIXED_CPU_CYCLES;
  948. if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_BUS_CYCLES)))
  949. return X86_PMC_IDX_FIXED_BUS_CYCLES;
  950. return -1;
  951. }
  952. /*
  953. * Find a PMC slot for the freshly enabled / scheduled in counter:
  954. */
  955. static int x86_pmu_enable(struct perf_counter *counter)
  956. {
  957. struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
  958. struct hw_perf_counter *hwc = &counter->hw;
  959. int idx;
  960. idx = fixed_mode_idx(counter, hwc);
  961. if (idx >= 0) {
  962. /*
  963. * Try to get the fixed counter, if that is already taken
  964. * then try to get a generic counter:
  965. */
  966. if (test_and_set_bit(idx, cpuc->used_mask))
  967. goto try_generic;
  968. hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
  969. /*
  970. * We set it so that counter_base + idx in wrmsr/rdmsr maps to
  971. * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
  972. */
  973. hwc->counter_base =
  974. MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
  975. hwc->idx = idx;
  976. } else {
  977. idx = hwc->idx;
  978. /* Try to get the previous generic counter again */
  979. if (test_and_set_bit(idx, cpuc->used_mask)) {
  980. try_generic:
  981. idx = find_first_zero_bit(cpuc->used_mask,
  982. x86_pmu.num_counters);
  983. if (idx == x86_pmu.num_counters)
  984. return -EAGAIN;
  985. set_bit(idx, cpuc->used_mask);
  986. hwc->idx = idx;
  987. }
  988. hwc->config_base = x86_pmu.eventsel;
  989. hwc->counter_base = x86_pmu.perfctr;
  990. }
  991. perf_counters_lapic_init();
  992. x86_pmu.disable(hwc, idx);
  993. cpuc->counters[idx] = counter;
  994. set_bit(idx, cpuc->active_mask);
  995. x86_perf_counter_set_period(counter, hwc, idx);
  996. x86_pmu.enable(hwc, idx);
  997. perf_counter_update_userpage(counter);
  998. return 0;
  999. }
  1000. static void x86_pmu_unthrottle(struct perf_counter *counter)
  1001. {
  1002. struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
  1003. struct hw_perf_counter *hwc = &counter->hw;
  1004. if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX ||
  1005. cpuc->counters[hwc->idx] != counter))
  1006. return;
  1007. x86_pmu.enable(hwc, hwc->idx);
  1008. }
  1009. void perf_counter_print_debug(void)
  1010. {
  1011. u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
  1012. struct cpu_hw_counters *cpuc;
  1013. unsigned long flags;
  1014. int cpu, idx;
  1015. if (!x86_pmu.num_counters)
  1016. return;
  1017. local_irq_save(flags);
  1018. cpu = smp_processor_id();
  1019. cpuc = &per_cpu(cpu_hw_counters, cpu);
  1020. if (x86_pmu.version >= 2) {
  1021. rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
  1022. rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
  1023. rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
  1024. rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
  1025. pr_info("\n");
  1026. pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
  1027. pr_info("CPU#%d: status: %016llx\n", cpu, status);
  1028. pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
  1029. pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
  1030. }
  1031. pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used_mask);
  1032. for (idx = 0; idx < x86_pmu.num_counters; idx++) {
  1033. rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
  1034. rdmsrl(x86_pmu.perfctr + idx, pmc_count);
  1035. prev_left = per_cpu(prev_left[idx], cpu);
  1036. pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
  1037. cpu, idx, pmc_ctrl);
  1038. pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
  1039. cpu, idx, pmc_count);
  1040. pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
  1041. cpu, idx, prev_left);
  1042. }
  1043. for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
  1044. rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
  1045. pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
  1046. cpu, idx, pmc_count);
  1047. }
  1048. local_irq_restore(flags);
  1049. }
  1050. static void x86_pmu_disable(struct perf_counter *counter)
  1051. {
  1052. struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
  1053. struct hw_perf_counter *hwc = &counter->hw;
  1054. int idx = hwc->idx;
  1055. /*
  1056. * Must be done before we disable, otherwise the nmi handler
  1057. * could reenable again:
  1058. */
  1059. clear_bit(idx, cpuc->active_mask);
  1060. x86_pmu.disable(hwc, idx);
  1061. /*
  1062. * Make sure the cleared pointer becomes visible before we
  1063. * (potentially) free the counter:
  1064. */
  1065. barrier();
  1066. /*
  1067. * Drain the remaining delta count out of a counter
  1068. * that we are disabling:
  1069. */
  1070. x86_perf_counter_update(counter, hwc, idx);
  1071. cpuc->counters[idx] = NULL;
  1072. clear_bit(idx, cpuc->used_mask);
  1073. perf_counter_update_userpage(counter);
  1074. }
  1075. /*
  1076. * Save and restart an expired counter. Called by NMI contexts,
  1077. * so it has to be careful about preempting normal counter ops:
  1078. */
  1079. static int intel_pmu_save_and_restart(struct perf_counter *counter)
  1080. {
  1081. struct hw_perf_counter *hwc = &counter->hw;
  1082. int idx = hwc->idx;
  1083. int ret;
  1084. x86_perf_counter_update(counter, hwc, idx);
  1085. ret = x86_perf_counter_set_period(counter, hwc, idx);
  1086. if (counter->state == PERF_COUNTER_STATE_ACTIVE)
  1087. intel_pmu_enable_counter(hwc, idx);
  1088. return ret;
  1089. }
  1090. static void intel_pmu_reset(void)
  1091. {
  1092. unsigned long flags;
  1093. int idx;
  1094. if (!x86_pmu.num_counters)
  1095. return;
  1096. local_irq_save(flags);
  1097. printk("clearing PMU state on CPU#%d\n", smp_processor_id());
  1098. for (idx = 0; idx < x86_pmu.num_counters; idx++) {
  1099. checking_wrmsrl(x86_pmu.eventsel + idx, 0ull);
  1100. checking_wrmsrl(x86_pmu.perfctr + idx, 0ull);
  1101. }
  1102. for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
  1103. checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
  1104. }
  1105. local_irq_restore(flags);
  1106. }
  1107. static int p6_pmu_handle_irq(struct pt_regs *regs)
  1108. {
  1109. struct perf_sample_data data;
  1110. struct cpu_hw_counters *cpuc;
  1111. struct perf_counter *counter;
  1112. struct hw_perf_counter *hwc;
  1113. int idx, handled = 0;
  1114. u64 val;
  1115. data.regs = regs;
  1116. data.addr = 0;
  1117. cpuc = &__get_cpu_var(cpu_hw_counters);
  1118. for (idx = 0; idx < x86_pmu.num_counters; idx++) {
  1119. if (!test_bit(idx, cpuc->active_mask))
  1120. continue;
  1121. counter = cpuc->counters[idx];
  1122. hwc = &counter->hw;
  1123. val = x86_perf_counter_update(counter, hwc, idx);
  1124. if (val & (1ULL << (x86_pmu.counter_bits - 1)))
  1125. continue;
  1126. /*
  1127. * counter overflow
  1128. */
  1129. handled = 1;
  1130. data.period = counter->hw.last_period;
  1131. if (!x86_perf_counter_set_period(counter, hwc, idx))
  1132. continue;
  1133. if (perf_counter_overflow(counter, 1, &data))
  1134. p6_pmu_disable_counter(hwc, idx);
  1135. }
  1136. if (handled)
  1137. inc_irq_stat(apic_perf_irqs);
  1138. return handled;
  1139. }
  1140. /*
  1141. * This handler is triggered by the local APIC, so the APIC IRQ handling
  1142. * rules apply:
  1143. */
  1144. static int intel_pmu_handle_irq(struct pt_regs *regs)
  1145. {
  1146. struct perf_sample_data data;
  1147. struct cpu_hw_counters *cpuc;
  1148. int bit, loops;
  1149. u64 ack, status;
  1150. data.regs = regs;
  1151. data.addr = 0;
  1152. cpuc = &__get_cpu_var(cpu_hw_counters);
  1153. perf_disable();
  1154. status = intel_pmu_get_status();
  1155. if (!status) {
  1156. perf_enable();
  1157. return 0;
  1158. }
  1159. loops = 0;
  1160. again:
  1161. if (++loops > 100) {
  1162. WARN_ONCE(1, "perfcounters: irq loop stuck!\n");
  1163. perf_counter_print_debug();
  1164. intel_pmu_reset();
  1165. perf_enable();
  1166. return 1;
  1167. }
  1168. inc_irq_stat(apic_perf_irqs);
  1169. ack = status;
  1170. for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
  1171. struct perf_counter *counter = cpuc->counters[bit];
  1172. clear_bit(bit, (unsigned long *) &status);
  1173. if (!test_bit(bit, cpuc->active_mask))
  1174. continue;
  1175. if (!intel_pmu_save_and_restart(counter))
  1176. continue;
  1177. data.period = counter->hw.last_period;
  1178. if (perf_counter_overflow(counter, 1, &data))
  1179. intel_pmu_disable_counter(&counter->hw, bit);
  1180. }
  1181. intel_pmu_ack_status(ack);
  1182. /*
  1183. * Repeat if there is more work to be done:
  1184. */
  1185. status = intel_pmu_get_status();
  1186. if (status)
  1187. goto again;
  1188. perf_enable();
  1189. return 1;
  1190. }
  1191. static int amd_pmu_handle_irq(struct pt_regs *regs)
  1192. {
  1193. struct perf_sample_data data;
  1194. struct cpu_hw_counters *cpuc;
  1195. struct perf_counter *counter;
  1196. struct hw_perf_counter *hwc;
  1197. int idx, handled = 0;
  1198. u64 val;
  1199. data.regs = regs;
  1200. data.addr = 0;
  1201. cpuc = &__get_cpu_var(cpu_hw_counters);
  1202. for (idx = 0; idx < x86_pmu.num_counters; idx++) {
  1203. if (!test_bit(idx, cpuc->active_mask))
  1204. continue;
  1205. counter = cpuc->counters[idx];
  1206. hwc = &counter->hw;
  1207. val = x86_perf_counter_update(counter, hwc, idx);
  1208. if (val & (1ULL << (x86_pmu.counter_bits - 1)))
  1209. continue;
  1210. /*
  1211. * counter overflow
  1212. */
  1213. handled = 1;
  1214. data.period = counter->hw.last_period;
  1215. if (!x86_perf_counter_set_period(counter, hwc, idx))
  1216. continue;
  1217. if (perf_counter_overflow(counter, 1, &data))
  1218. amd_pmu_disable_counter(hwc, idx);
  1219. }
  1220. if (handled)
  1221. inc_irq_stat(apic_perf_irqs);
  1222. return handled;
  1223. }
  1224. void smp_perf_pending_interrupt(struct pt_regs *regs)
  1225. {
  1226. irq_enter();
  1227. ack_APIC_irq();
  1228. inc_irq_stat(apic_pending_irqs);
  1229. perf_counter_do_pending();
  1230. irq_exit();
  1231. }
  1232. void set_perf_counter_pending(void)
  1233. {
  1234. apic->send_IPI_self(LOCAL_PENDING_VECTOR);
  1235. }
  1236. void perf_counters_lapic_init(void)
  1237. {
  1238. if (!x86_pmu_initialized())
  1239. return;
  1240. /*
  1241. * Always use NMI for PMU
  1242. */
  1243. apic_write(APIC_LVTPC, APIC_DM_NMI);
  1244. }
  1245. static int __kprobes
  1246. perf_counter_nmi_handler(struct notifier_block *self,
  1247. unsigned long cmd, void *__args)
  1248. {
  1249. struct die_args *args = __args;
  1250. struct pt_regs *regs;
  1251. if (!atomic_read(&active_counters))
  1252. return NOTIFY_DONE;
  1253. switch (cmd) {
  1254. case DIE_NMI:
  1255. case DIE_NMI_IPI:
  1256. break;
  1257. default:
  1258. return NOTIFY_DONE;
  1259. }
  1260. regs = args->regs;
  1261. apic_write(APIC_LVTPC, APIC_DM_NMI);
  1262. /*
  1263. * Can't rely on the handled return value to say it was our NMI, two
  1264. * counters could trigger 'simultaneously' raising two back-to-back NMIs.
  1265. *
  1266. * If the first NMI handles both, the latter will be empty and daze
  1267. * the CPU.
  1268. */
  1269. x86_pmu.handle_irq(regs);
  1270. return NOTIFY_STOP;
  1271. }
  1272. static __read_mostly struct notifier_block perf_counter_nmi_notifier = {
  1273. .notifier_call = perf_counter_nmi_handler,
  1274. .next = NULL,
  1275. .priority = 1
  1276. };
  1277. static struct x86_pmu p6_pmu = {
  1278. .name = "p6",
  1279. .handle_irq = p6_pmu_handle_irq,
  1280. .disable_all = p6_pmu_disable_all,
  1281. .enable_all = p6_pmu_enable_all,
  1282. .enable = p6_pmu_enable_counter,
  1283. .disable = p6_pmu_disable_counter,
  1284. .eventsel = MSR_P6_EVNTSEL0,
  1285. .perfctr = MSR_P6_PERFCTR0,
  1286. .event_map = p6_pmu_event_map,
  1287. .raw_event = p6_pmu_raw_event,
  1288. .max_events = ARRAY_SIZE(p6_perfmon_event_map),
  1289. .max_period = (1ULL << 31) - 1,
  1290. .version = 0,
  1291. .num_counters = 2,
  1292. /*
  1293. * Counters have 40 bits implemented. However they are designed such
  1294. * that bits [32-39] are sign extensions of bit 31. As such the
  1295. * effective width of a counter for P6-like PMU is 32 bits only.
  1296. *
  1297. * See IA-32 Intel Architecture Software developer manual Vol 3B
  1298. */
  1299. .counter_bits = 32,
  1300. .counter_mask = (1ULL << 32) - 1,
  1301. };
  1302. static struct x86_pmu intel_pmu = {
  1303. .name = "Intel",
  1304. .handle_irq = intel_pmu_handle_irq,
  1305. .disable_all = intel_pmu_disable_all,
  1306. .enable_all = intel_pmu_enable_all,
  1307. .enable = intel_pmu_enable_counter,
  1308. .disable = intel_pmu_disable_counter,
  1309. .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
  1310. .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
  1311. .event_map = intel_pmu_event_map,
  1312. .raw_event = intel_pmu_raw_event,
  1313. .max_events = ARRAY_SIZE(intel_perfmon_event_map),
  1314. /*
  1315. * Intel PMCs cannot be accessed sanely above 32 bit width,
  1316. * so we install an artificial 1<<31 period regardless of
  1317. * the generic counter period:
  1318. */
  1319. .max_period = (1ULL << 31) - 1,
  1320. };
  1321. static struct x86_pmu amd_pmu = {
  1322. .name = "AMD",
  1323. .handle_irq = amd_pmu_handle_irq,
  1324. .disable_all = amd_pmu_disable_all,
  1325. .enable_all = amd_pmu_enable_all,
  1326. .enable = amd_pmu_enable_counter,
  1327. .disable = amd_pmu_disable_counter,
  1328. .eventsel = MSR_K7_EVNTSEL0,
  1329. .perfctr = MSR_K7_PERFCTR0,
  1330. .event_map = amd_pmu_event_map,
  1331. .raw_event = amd_pmu_raw_event,
  1332. .max_events = ARRAY_SIZE(amd_perfmon_event_map),
  1333. .num_counters = 4,
  1334. .counter_bits = 48,
  1335. .counter_mask = (1ULL << 48) - 1,
  1336. /* use highest bit to detect overflow */
  1337. .max_period = (1ULL << 47) - 1,
  1338. };
  1339. static int p6_pmu_init(void)
  1340. {
  1341. switch (boot_cpu_data.x86_model) {
  1342. case 1:
  1343. case 3: /* Pentium Pro */
  1344. case 5:
  1345. case 6: /* Pentium II */
  1346. case 7:
  1347. case 8:
  1348. case 11: /* Pentium III */
  1349. break;
  1350. case 9:
  1351. case 13:
  1352. /* Pentium M */
  1353. break;
  1354. default:
  1355. pr_cont("unsupported p6 CPU model %d ",
  1356. boot_cpu_data.x86_model);
  1357. return -ENODEV;
  1358. }
  1359. if (!cpu_has_apic) {
  1360. pr_info("no Local APIC, try rebooting with lapic");
  1361. return -ENODEV;
  1362. }
  1363. x86_pmu = p6_pmu;
  1364. return 0;
  1365. }
  1366. static int intel_pmu_init(void)
  1367. {
  1368. union cpuid10_edx edx;
  1369. union cpuid10_eax eax;
  1370. unsigned int unused;
  1371. unsigned int ebx;
  1372. int version;
  1373. if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
  1374. /* check for P6 processor family */
  1375. if (boot_cpu_data.x86 == 6) {
  1376. return p6_pmu_init();
  1377. } else {
  1378. return -ENODEV;
  1379. }
  1380. }
  1381. /*
  1382. * Check whether the Architectural PerfMon supports
  1383. * Branch Misses Retired Event or not.
  1384. */
  1385. cpuid(10, &eax.full, &ebx, &unused, &edx.full);
  1386. if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
  1387. return -ENODEV;
  1388. version = eax.split.version_id;
  1389. if (version < 2)
  1390. return -ENODEV;
  1391. x86_pmu = intel_pmu;
  1392. x86_pmu.version = version;
  1393. x86_pmu.num_counters = eax.split.num_counters;
  1394. x86_pmu.counter_bits = eax.split.bit_width;
  1395. x86_pmu.counter_mask = (1ULL << eax.split.bit_width) - 1;
  1396. /*
  1397. * Quirk: v2 perfmon does not report fixed-purpose counters, so
  1398. * assume at least 3 counters:
  1399. */
  1400. x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
  1401. /*
  1402. * Install the hw-cache-events table:
  1403. */
  1404. switch (boot_cpu_data.x86_model) {
  1405. case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
  1406. case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
  1407. case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
  1408. case 29: /* six-core 45 nm xeon "Dunnington" */
  1409. memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
  1410. sizeof(hw_cache_event_ids));
  1411. pr_cont("Core2 events, ");
  1412. break;
  1413. default:
  1414. case 26:
  1415. memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
  1416. sizeof(hw_cache_event_ids));
  1417. pr_cont("Nehalem/Corei7 events, ");
  1418. break;
  1419. case 28:
  1420. memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
  1421. sizeof(hw_cache_event_ids));
  1422. pr_cont("Atom events, ");
  1423. break;
  1424. }
  1425. return 0;
  1426. }
  1427. static int amd_pmu_init(void)
  1428. {
  1429. /* Performance-monitoring supported from K7 and later: */
  1430. if (boot_cpu_data.x86 < 6)
  1431. return -ENODEV;
  1432. x86_pmu = amd_pmu;
  1433. /* Events are common for all AMDs */
  1434. memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
  1435. sizeof(hw_cache_event_ids));
  1436. return 0;
  1437. }
  1438. void __init init_hw_perf_counters(void)
  1439. {
  1440. int err;
  1441. pr_info("Performance Counters: ");
  1442. switch (boot_cpu_data.x86_vendor) {
  1443. case X86_VENDOR_INTEL:
  1444. err = intel_pmu_init();
  1445. break;
  1446. case X86_VENDOR_AMD:
  1447. err = amd_pmu_init();
  1448. break;
  1449. default:
  1450. return;
  1451. }
  1452. if (err != 0) {
  1453. pr_cont("no PMU driver, software counters only.\n");
  1454. return;
  1455. }
  1456. pr_cont("%s PMU driver.\n", x86_pmu.name);
  1457. if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
  1458. WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!",
  1459. x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
  1460. x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
  1461. }
  1462. perf_counter_mask = (1 << x86_pmu.num_counters) - 1;
  1463. perf_max_counters = x86_pmu.num_counters;
  1464. if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
  1465. WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!",
  1466. x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
  1467. x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
  1468. }
  1469. perf_counter_mask |=
  1470. ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
  1471. x86_pmu.intel_ctrl = perf_counter_mask;
  1472. perf_counters_lapic_init();
  1473. register_die_notifier(&perf_counter_nmi_notifier);
  1474. pr_info("... version: %d\n", x86_pmu.version);
  1475. pr_info("... bit width: %d\n", x86_pmu.counter_bits);
  1476. pr_info("... generic counters: %d\n", x86_pmu.num_counters);
  1477. pr_info("... value mask: %016Lx\n", x86_pmu.counter_mask);
  1478. pr_info("... max period: %016Lx\n", x86_pmu.max_period);
  1479. pr_info("... fixed-purpose counters: %d\n", x86_pmu.num_counters_fixed);
  1480. pr_info("... counter mask: %016Lx\n", perf_counter_mask);
  1481. }
  1482. static inline void x86_pmu_read(struct perf_counter *counter)
  1483. {
  1484. x86_perf_counter_update(counter, &counter->hw, counter->hw.idx);
  1485. }
  1486. static const struct pmu pmu = {
  1487. .enable = x86_pmu_enable,
  1488. .disable = x86_pmu_disable,
  1489. .read = x86_pmu_read,
  1490. .unthrottle = x86_pmu_unthrottle,
  1491. };
  1492. const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
  1493. {
  1494. int err;
  1495. err = __hw_perf_counter_init(counter);
  1496. if (err)
  1497. return ERR_PTR(err);
  1498. return &pmu;
  1499. }
  1500. /*
  1501. * callchain support
  1502. */
  1503. static inline
  1504. void callchain_store(struct perf_callchain_entry *entry, u64 ip)
  1505. {
  1506. if (entry->nr < PERF_MAX_STACK_DEPTH)
  1507. entry->ip[entry->nr++] = ip;
  1508. }
  1509. static DEFINE_PER_CPU(struct perf_callchain_entry, irq_entry);
  1510. static DEFINE_PER_CPU(struct perf_callchain_entry, nmi_entry);
  1511. static DEFINE_PER_CPU(int, in_nmi_frame);
  1512. static void
  1513. backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
  1514. {
  1515. /* Ignore warnings */
  1516. }
  1517. static void backtrace_warning(void *data, char *msg)
  1518. {
  1519. /* Ignore warnings */
  1520. }
  1521. static int backtrace_stack(void *data, char *name)
  1522. {
  1523. per_cpu(in_nmi_frame, smp_processor_id()) =
  1524. x86_is_stack_id(NMI_STACK, name);
  1525. return 0;
  1526. }
  1527. static void backtrace_address(void *data, unsigned long addr, int reliable)
  1528. {
  1529. struct perf_callchain_entry *entry = data;
  1530. if (per_cpu(in_nmi_frame, smp_processor_id()))
  1531. return;
  1532. if (reliable)
  1533. callchain_store(entry, addr);
  1534. }
  1535. static const struct stacktrace_ops backtrace_ops = {
  1536. .warning = backtrace_warning,
  1537. .warning_symbol = backtrace_warning_symbol,
  1538. .stack = backtrace_stack,
  1539. .address = backtrace_address,
  1540. };
  1541. #include "../dumpstack.h"
  1542. static void
  1543. perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
  1544. {
  1545. callchain_store(entry, PERF_CONTEXT_KERNEL);
  1546. callchain_store(entry, regs->ip);
  1547. dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
  1548. }
  1549. /*
  1550. * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
  1551. */
  1552. static unsigned long
  1553. copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
  1554. {
  1555. unsigned long offset, addr = (unsigned long)from;
  1556. int type = in_nmi() ? KM_NMI : KM_IRQ0;
  1557. unsigned long size, len = 0;
  1558. struct page *page;
  1559. void *map;
  1560. int ret;
  1561. do {
  1562. ret = __get_user_pages_fast(addr, 1, 0, &page);
  1563. if (!ret)
  1564. break;
  1565. offset = addr & (PAGE_SIZE - 1);
  1566. size = min(PAGE_SIZE - offset, n - len);
  1567. map = kmap_atomic(page, type);
  1568. memcpy(to, map+offset, size);
  1569. kunmap_atomic(map, type);
  1570. put_page(page);
  1571. len += size;
  1572. to += size;
  1573. addr += size;
  1574. } while (len < n);
  1575. return len;
  1576. }
  1577. static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
  1578. {
  1579. unsigned long bytes;
  1580. bytes = copy_from_user_nmi(frame, fp, sizeof(*frame));
  1581. return bytes == sizeof(*frame);
  1582. }
  1583. static void
  1584. perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
  1585. {
  1586. struct stack_frame frame;
  1587. const void __user *fp;
  1588. if (!user_mode(regs))
  1589. regs = task_pt_regs(current);
  1590. fp = (void __user *)regs->bp;
  1591. callchain_store(entry, PERF_CONTEXT_USER);
  1592. callchain_store(entry, regs->ip);
  1593. while (entry->nr < PERF_MAX_STACK_DEPTH) {
  1594. frame.next_frame = NULL;
  1595. frame.return_address = 0;
  1596. if (!copy_stack_frame(fp, &frame))
  1597. break;
  1598. if ((unsigned long)fp < regs->sp)
  1599. break;
  1600. callchain_store(entry, frame.return_address);
  1601. fp = frame.next_frame;
  1602. }
  1603. }
  1604. static void
  1605. perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
  1606. {
  1607. int is_user;
  1608. if (!regs)
  1609. return;
  1610. is_user = user_mode(regs);
  1611. if (!current || current->pid == 0)
  1612. return;
  1613. if (is_user && current->state != TASK_RUNNING)
  1614. return;
  1615. if (!is_user)
  1616. perf_callchain_kernel(regs, entry);
  1617. if (current->mm)
  1618. perf_callchain_user(regs, entry);
  1619. }
  1620. struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
  1621. {
  1622. struct perf_callchain_entry *entry;
  1623. if (in_nmi())
  1624. entry = &__get_cpu_var(nmi_entry);
  1625. else
  1626. entry = &__get_cpu_var(irq_entry);
  1627. entry->nr = 0;
  1628. perf_do_callchain(regs, entry);
  1629. return entry;
  1630. }