x2apic_phys.c 5.3 KB

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  1. #include <linux/threads.h>
  2. #include <linux/cpumask.h>
  3. #include <linux/string.h>
  4. #include <linux/kernel.h>
  5. #include <linux/ctype.h>
  6. #include <linux/init.h>
  7. #include <linux/dmar.h>
  8. #include <asm/smp.h>
  9. #include <asm/apic.h>
  10. #include <asm/ipi.h>
  11. int x2apic_phys;
  12. static int set_x2apic_phys_mode(char *arg)
  13. {
  14. x2apic_phys = 1;
  15. return 0;
  16. }
  17. early_param("x2apic_phys", set_x2apic_phys_mode);
  18. static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  19. {
  20. if (x2apic_phys)
  21. return x2apic_enabled();
  22. else
  23. return 0;
  24. }
  25. /* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
  26. static const struct cpumask *x2apic_target_cpus(void)
  27. {
  28. return cpumask_of(0);
  29. }
  30. static void x2apic_vector_allocation_domain(int cpu, struct cpumask *retmask)
  31. {
  32. cpumask_clear(retmask);
  33. cpumask_set_cpu(cpu, retmask);
  34. }
  35. static void __x2apic_send_IPI_dest(unsigned int apicid, int vector,
  36. unsigned int dest)
  37. {
  38. unsigned long cfg;
  39. cfg = __prepare_ICR(0, vector, dest);
  40. /*
  41. * send the IPI.
  42. */
  43. native_x2apic_icr_write(cfg, apicid);
  44. }
  45. static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector)
  46. {
  47. unsigned long query_cpu;
  48. unsigned long flags;
  49. x2apic_wrmsr_fence();
  50. local_irq_save(flags);
  51. for_each_cpu(query_cpu, mask) {
  52. __x2apic_send_IPI_dest(per_cpu(x86_cpu_to_apicid, query_cpu),
  53. vector, APIC_DEST_PHYSICAL);
  54. }
  55. local_irq_restore(flags);
  56. }
  57. static void
  58. x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
  59. {
  60. unsigned long this_cpu = smp_processor_id();
  61. unsigned long query_cpu;
  62. unsigned long flags;
  63. x2apic_wrmsr_fence();
  64. local_irq_save(flags);
  65. for_each_cpu(query_cpu, mask) {
  66. if (query_cpu != this_cpu)
  67. __x2apic_send_IPI_dest(
  68. per_cpu(x86_cpu_to_apicid, query_cpu),
  69. vector, APIC_DEST_PHYSICAL);
  70. }
  71. local_irq_restore(flags);
  72. }
  73. static void x2apic_send_IPI_allbutself(int vector)
  74. {
  75. unsigned long this_cpu = smp_processor_id();
  76. unsigned long query_cpu;
  77. unsigned long flags;
  78. x2apic_wrmsr_fence();
  79. local_irq_save(flags);
  80. for_each_online_cpu(query_cpu) {
  81. if (query_cpu == this_cpu)
  82. continue;
  83. __x2apic_send_IPI_dest(per_cpu(x86_cpu_to_apicid, query_cpu),
  84. vector, APIC_DEST_PHYSICAL);
  85. }
  86. local_irq_restore(flags);
  87. }
  88. static void x2apic_send_IPI_all(int vector)
  89. {
  90. x2apic_send_IPI_mask(cpu_online_mask, vector);
  91. }
  92. static int x2apic_apic_id_registered(void)
  93. {
  94. return 1;
  95. }
  96. static unsigned int x2apic_cpu_mask_to_apicid(const struct cpumask *cpumask)
  97. {
  98. /*
  99. * We're using fixed IRQ delivery, can only return one phys APIC ID.
  100. * May as well be the first.
  101. */
  102. int cpu = cpumask_first(cpumask);
  103. if ((unsigned)cpu < nr_cpu_ids)
  104. return per_cpu(x86_cpu_to_apicid, cpu);
  105. else
  106. return BAD_APICID;
  107. }
  108. static unsigned int
  109. x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
  110. const struct cpumask *andmask)
  111. {
  112. int cpu;
  113. /*
  114. * We're using fixed IRQ delivery, can only return one phys APIC ID.
  115. * May as well be the first.
  116. */
  117. for_each_cpu_and(cpu, cpumask, andmask) {
  118. if (cpumask_test_cpu(cpu, cpu_online_mask))
  119. break;
  120. }
  121. if (cpu < nr_cpu_ids)
  122. return per_cpu(x86_cpu_to_apicid, cpu);
  123. return BAD_APICID;
  124. }
  125. static unsigned int x2apic_phys_get_apic_id(unsigned long x)
  126. {
  127. return x;
  128. }
  129. static unsigned long set_apic_id(unsigned int id)
  130. {
  131. return id;
  132. }
  133. static int x2apic_phys_pkg_id(int initial_apicid, int index_msb)
  134. {
  135. return current_cpu_data.initial_apicid >> index_msb;
  136. }
  137. static void x2apic_send_IPI_self(int vector)
  138. {
  139. apic_write(APIC_SELF_IPI, vector);
  140. }
  141. static void init_x2apic_ldr(void)
  142. {
  143. }
  144. struct apic apic_x2apic_phys = {
  145. .name = "physical x2apic",
  146. .probe = NULL,
  147. .acpi_madt_oem_check = x2apic_acpi_madt_oem_check,
  148. .apic_id_registered = x2apic_apic_id_registered,
  149. .irq_delivery_mode = dest_Fixed,
  150. .irq_dest_mode = 0, /* physical */
  151. .target_cpus = x2apic_target_cpus,
  152. .disable_esr = 0,
  153. .dest_logical = 0,
  154. .check_apicid_used = NULL,
  155. .check_apicid_present = NULL,
  156. .vector_allocation_domain = x2apic_vector_allocation_domain,
  157. .init_apic_ldr = init_x2apic_ldr,
  158. .ioapic_phys_id_map = NULL,
  159. .setup_apic_routing = NULL,
  160. .multi_timer_check = NULL,
  161. .apicid_to_node = NULL,
  162. .cpu_to_logical_apicid = NULL,
  163. .cpu_present_to_apicid = default_cpu_present_to_apicid,
  164. .apicid_to_cpu_present = NULL,
  165. .setup_portio_remap = NULL,
  166. .check_phys_apicid_present = default_check_phys_apicid_present,
  167. .enable_apic_mode = NULL,
  168. .phys_pkg_id = x2apic_phys_pkg_id,
  169. .mps_oem_check = NULL,
  170. .get_apic_id = x2apic_phys_get_apic_id,
  171. .set_apic_id = set_apic_id,
  172. .apic_id_mask = 0xFFFFFFFFu,
  173. .cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid,
  174. .cpu_mask_to_apicid_and = x2apic_cpu_mask_to_apicid_and,
  175. .send_IPI_mask = x2apic_send_IPI_mask,
  176. .send_IPI_mask_allbutself = x2apic_send_IPI_mask_allbutself,
  177. .send_IPI_allbutself = x2apic_send_IPI_allbutself,
  178. .send_IPI_all = x2apic_send_IPI_all,
  179. .send_IPI_self = x2apic_send_IPI_self,
  180. .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
  181. .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
  182. .wait_for_init_deassert = NULL,
  183. .smp_callin_clear_local_apic = NULL,
  184. .inquire_remote_apic = NULL,
  185. .read = native_apic_msr_read,
  186. .write = native_apic_msr_write,
  187. .icr_read = native_x2apic_icr_read,
  188. .icr_write = native_x2apic_icr_write,
  189. .wait_icr_idle = native_x2apic_wait_icr_idle,
  190. .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
  191. };