board-urquell.c 4.7 KB

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  1. /*
  2. * Renesas Technology Corp. SH7786 Urquell Support.
  3. *
  4. * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
  5. * Copyright (C) 2009 Paul Mundt
  6. *
  7. * Based on board-sh7785lcr.c
  8. * Copyright (C) 2008 Yoshihiro Shimoda
  9. *
  10. * This file is subject to the terms and conditions of the GNU General Public
  11. * License. See the file "COPYING" in the main directory of this archive
  12. * for more details.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/fb.h>
  17. #include <linux/smc91x.h>
  18. #include <linux/mtd/physmap.h>
  19. #include <linux/delay.h>
  20. #include <linux/gpio.h>
  21. #include <linux/irq.h>
  22. #include <mach/urquell.h>
  23. #include <cpu/sh7786.h>
  24. #include <asm/heartbeat.h>
  25. #include <asm/sizes.h>
  26. /*
  27. * bit 1234 5678
  28. *----------------------------
  29. * SW1 0101 0010 -> Pck 33MHz version
  30. * (1101 0010) Pck 66MHz version
  31. * SW2 0x1x xxxx -> little endian
  32. * 29bit mode
  33. * SW47 0001 1000 -> CS0 : on-board flash
  34. * CS1 : SRAM, registers, LAN, PCMCIA
  35. * 38400 bps for SCIF1
  36. *
  37. * Address
  38. * 0x00000000 - 0x04000000 (CS0) Nor Flash
  39. * 0x04000000 - 0x04200000 (CS1) SRAM
  40. * 0x05000000 - 0x05800000 (CS1) on board register
  41. * 0x05800000 - 0x06000000 (CS1) LAN91C111
  42. * 0x06000000 - 0x06400000 (CS1) PCMCIA
  43. * 0x08000000 - 0x10000000 (CS2-CS3) DDR3
  44. * 0x10000000 - 0x14000000 (CS4) PCIe
  45. * 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM
  46. * 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM
  47. * 0x18000000 - 0x1C000000 (CS6) ATA/NAND-Flash
  48. * 0x1C000000 - (CS7) SH7786 Control register
  49. */
  50. /* HeartBeat */
  51. static struct resource heartbeat_resources[] = {
  52. [0] = {
  53. .start = BOARDREG(SLEDR),
  54. .end = BOARDREG(SLEDR),
  55. .flags = IORESOURCE_MEM,
  56. },
  57. };
  58. static struct heartbeat_data heartbeat_data = {
  59. .regsize = 16,
  60. };
  61. static struct platform_device heartbeat_device = {
  62. .name = "heartbeat",
  63. .id = -1,
  64. .dev = {
  65. .platform_data = &heartbeat_data,
  66. },
  67. .num_resources = ARRAY_SIZE(heartbeat_resources),
  68. .resource = heartbeat_resources,
  69. };
  70. /* LAN91C111 */
  71. static struct smc91x_platdata smc91x_info = {
  72. .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
  73. };
  74. static struct resource smc91x_eth_resources[] = {
  75. [0] = {
  76. .name = "SMC91C111" ,
  77. .start = 0x05800300,
  78. .end = 0x0580030f,
  79. .flags = IORESOURCE_MEM,
  80. },
  81. [1] = {
  82. .start = 11,
  83. .flags = IORESOURCE_IRQ,
  84. },
  85. };
  86. static struct platform_device smc91x_eth_device = {
  87. .name = "smc91x",
  88. .num_resources = ARRAY_SIZE(smc91x_eth_resources),
  89. .resource = smc91x_eth_resources,
  90. .dev = {
  91. .platform_data = &smc91x_info,
  92. },
  93. };
  94. /* Nor Flash */
  95. static struct mtd_partition nor_flash_partitions[] = {
  96. {
  97. .name = "loader",
  98. .offset = 0x00000000,
  99. .size = SZ_512K,
  100. .mask_flags = MTD_WRITEABLE, /* Read-only */
  101. },
  102. {
  103. .name = "bootenv",
  104. .offset = MTDPART_OFS_APPEND,
  105. .size = SZ_512K,
  106. .mask_flags = MTD_WRITEABLE, /* Read-only */
  107. },
  108. {
  109. .name = "kernel",
  110. .offset = MTDPART_OFS_APPEND,
  111. .size = SZ_4M,
  112. },
  113. {
  114. .name = "data",
  115. .offset = MTDPART_OFS_APPEND,
  116. .size = MTDPART_SIZ_FULL,
  117. },
  118. };
  119. static struct physmap_flash_data nor_flash_data = {
  120. .width = 2,
  121. .parts = nor_flash_partitions,
  122. .nr_parts = ARRAY_SIZE(nor_flash_partitions),
  123. };
  124. static struct resource nor_flash_resources[] = {
  125. [0] = {
  126. .start = NOR_FLASH_ADDR,
  127. .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1,
  128. .flags = IORESOURCE_MEM,
  129. }
  130. };
  131. static struct platform_device nor_flash_device = {
  132. .name = "physmap-flash",
  133. .dev = {
  134. .platform_data = &nor_flash_data,
  135. },
  136. .num_resources = ARRAY_SIZE(nor_flash_resources),
  137. .resource = nor_flash_resources,
  138. };
  139. static struct platform_device *urquell_devices[] __initdata = {
  140. &heartbeat_device,
  141. &smc91x_eth_device,
  142. &nor_flash_device,
  143. };
  144. static int __init urquell_devices_setup(void)
  145. {
  146. /* USB */
  147. gpio_request(GPIO_FN_USB_OVC0, NULL);
  148. gpio_request(GPIO_FN_USB_PENC0, NULL);
  149. /* enable LAN */
  150. __raw_writew(__raw_readw(UBOARDREG(IRL2MSKR)) & ~0x00000001,
  151. UBOARDREG(IRL2MSKR));
  152. return platform_add_devices(urquell_devices,
  153. ARRAY_SIZE(urquell_devices));
  154. }
  155. device_initcall(urquell_devices_setup);
  156. static void urquell_power_off(void)
  157. {
  158. __raw_writew(0xa5a5, UBOARDREG(SRSTR));
  159. }
  160. static void __init urquell_init_irq(void)
  161. {
  162. plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK);
  163. }
  164. static int urquell_mode_pins(void)
  165. {
  166. return __raw_readw(UBOARDREG(MDSWMR));
  167. }
  168. /* Initialize the board */
  169. static void __init urquell_setup(char **cmdline_p)
  170. {
  171. printk(KERN_INFO "Renesas Technology Corp. Urquell support.\n");
  172. pm_power_off = urquell_power_off;
  173. }
  174. /*
  175. * The Machine Vector
  176. */
  177. static struct sh_machine_vector mv_urquell __initmv = {
  178. .mv_name = "Urquell",
  179. .mv_setup = urquell_setup,
  180. .mv_init_irq = urquell_init_irq,
  181. .mv_mode_pins = urquell_mode_pins,
  182. };