mpc8xx_pic.c 4.3 KB

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  1. #include <linux/kernel.h>
  2. #include <linux/module.h>
  3. #include <linux/stddef.h>
  4. #include <linux/init.h>
  5. #include <linux/sched.h>
  6. #include <linux/signal.h>
  7. #include <linux/irq.h>
  8. #include <linux/dma-mapping.h>
  9. #include <asm/prom.h>
  10. #include <asm/irq.h>
  11. #include <asm/io.h>
  12. #include <asm/8xx_immap.h>
  13. #include "mpc8xx_pic.h"
  14. #define PIC_VEC_SPURRIOUS 15
  15. extern int cpm_get_irq(struct pt_regs *regs);
  16. static struct irq_host *mpc8xx_pic_host;
  17. #define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
  18. static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
  19. static sysconf8xx_t __iomem *siu_reg;
  20. int cpm_get_irq(struct pt_regs *regs);
  21. static void mpc8xx_unmask_irq(unsigned int virq)
  22. {
  23. int bit, word;
  24. unsigned int irq_nr = (unsigned int)irq_map[virq].hwirq;
  25. bit = irq_nr & 0x1f;
  26. word = irq_nr >> 5;
  27. ppc_cached_irq_mask[word] |= (1 << (31-bit));
  28. out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
  29. }
  30. static void mpc8xx_mask_irq(unsigned int virq)
  31. {
  32. int bit, word;
  33. unsigned int irq_nr = (unsigned int)irq_map[virq].hwirq;
  34. bit = irq_nr & 0x1f;
  35. word = irq_nr >> 5;
  36. ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
  37. out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
  38. }
  39. static void mpc8xx_ack(unsigned int virq)
  40. {
  41. int bit;
  42. unsigned int irq_nr = (unsigned int)irq_map[virq].hwirq;
  43. bit = irq_nr & 0x1f;
  44. out_be32(&siu_reg->sc_sipend, 1 << (31-bit));
  45. }
  46. static void mpc8xx_end_irq(unsigned int virq)
  47. {
  48. int bit, word;
  49. unsigned int irq_nr = (unsigned int)irq_map[virq].hwirq;
  50. bit = irq_nr & 0x1f;
  51. word = irq_nr >> 5;
  52. ppc_cached_irq_mask[word] |= (1 << (31-bit));
  53. out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
  54. }
  55. static int mpc8xx_set_irq_type(unsigned int virq, unsigned int flow_type)
  56. {
  57. struct irq_desc *desc = get_irq_desc(virq);
  58. desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
  59. desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
  60. if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
  61. desc->status |= IRQ_LEVEL;
  62. if (flow_type & IRQ_TYPE_EDGE_FALLING) {
  63. irq_hw_number_t hw = (unsigned int)irq_map[virq].hwirq;
  64. unsigned int siel = in_be32(&siu_reg->sc_siel);
  65. /* only external IRQ senses are programmable */
  66. if ((hw & 1) == 0) {
  67. siel |= (0x80000000 >> hw);
  68. out_be32(&siu_reg->sc_siel, siel);
  69. desc->handle_irq = handle_edge_irq;
  70. }
  71. }
  72. return 0;
  73. }
  74. static struct irq_chip mpc8xx_pic = {
  75. .typename = " MPC8XX SIU ",
  76. .unmask = mpc8xx_unmask_irq,
  77. .mask = mpc8xx_mask_irq,
  78. .ack = mpc8xx_ack,
  79. .eoi = mpc8xx_end_irq,
  80. .set_type = mpc8xx_set_irq_type,
  81. };
  82. unsigned int mpc8xx_get_irq(void)
  83. {
  84. int irq;
  85. /* For MPC8xx, read the SIVEC register and shift the bits down
  86. * to get the irq number.
  87. */
  88. irq = in_be32(&siu_reg->sc_sivec) >> 26;
  89. if (irq == PIC_VEC_SPURRIOUS)
  90. irq = NO_IRQ;
  91. return irq_linear_revmap(mpc8xx_pic_host, irq);
  92. }
  93. static int mpc8xx_pic_host_map(struct irq_host *h, unsigned int virq,
  94. irq_hw_number_t hw)
  95. {
  96. pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq, hw);
  97. /* Set default irq handle */
  98. set_irq_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq);
  99. return 0;
  100. }
  101. static int mpc8xx_pic_host_xlate(struct irq_host *h, struct device_node *ct,
  102. u32 *intspec, unsigned int intsize,
  103. irq_hw_number_t *out_hwirq, unsigned int *out_flags)
  104. {
  105. static unsigned char map_pic_senses[4] = {
  106. IRQ_TYPE_EDGE_RISING,
  107. IRQ_TYPE_LEVEL_LOW,
  108. IRQ_TYPE_LEVEL_HIGH,
  109. IRQ_TYPE_EDGE_FALLING,
  110. };
  111. *out_hwirq = intspec[0];
  112. if (intsize > 1 && intspec[1] < 4)
  113. *out_flags = map_pic_senses[intspec[1]];
  114. else
  115. *out_flags = IRQ_TYPE_NONE;
  116. return 0;
  117. }
  118. static struct irq_host_ops mpc8xx_pic_host_ops = {
  119. .map = mpc8xx_pic_host_map,
  120. .xlate = mpc8xx_pic_host_xlate,
  121. };
  122. int mpc8xx_pic_init(void)
  123. {
  124. struct resource res;
  125. struct device_node *np;
  126. int ret;
  127. np = of_find_compatible_node(NULL, NULL, "fsl,pq1-pic");
  128. if (np == NULL)
  129. np = of_find_node_by_type(NULL, "mpc8xx-pic");
  130. if (np == NULL) {
  131. printk(KERN_ERR "Could not find fsl,pq1-pic node\n");
  132. return -ENOMEM;
  133. }
  134. ret = of_address_to_resource(np, 0, &res);
  135. if (ret)
  136. goto out;
  137. siu_reg = ioremap(res.start, res.end - res.start + 1);
  138. if (siu_reg == NULL) {
  139. ret = -EINVAL;
  140. goto out;
  141. }
  142. mpc8xx_pic_host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR,
  143. 64, &mpc8xx_pic_host_ops, 64);
  144. if (mpc8xx_pic_host == NULL) {
  145. printk(KERN_ERR "MPC8xx PIC: failed to allocate irq host!\n");
  146. ret = -ENOMEM;
  147. goto out;
  148. }
  149. return 0;
  150. out:
  151. of_node_put(np);
  152. return ret;
  153. }