fsl_msi.c 8.0 KB

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  1. /*
  2. * Copyright (C) 2007-2008 Freescale Semiconductor, Inc. All rights reserved.
  3. *
  4. * Author: Tony Li <tony.li@freescale.com>
  5. * Jason Jin <Jason.jin@freescale.com>
  6. *
  7. * The hwirq alloc and free code reuse from sysdev/mpic_msi.c
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * as published by the Free Software Foundation; version 2 of the
  12. * License.
  13. *
  14. */
  15. #include <linux/irq.h>
  16. #include <linux/bootmem.h>
  17. #include <linux/msi.h>
  18. #include <linux/pci.h>
  19. #include <linux/of_platform.h>
  20. #include <sysdev/fsl_soc.h>
  21. #include <asm/prom.h>
  22. #include <asm/hw_irq.h>
  23. #include <asm/ppc-pci.h>
  24. #include "fsl_msi.h"
  25. struct fsl_msi_feature {
  26. u32 fsl_pic_ip;
  27. u32 msiir_offset;
  28. };
  29. static struct fsl_msi *fsl_msi;
  30. static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
  31. {
  32. return in_be32(base + (reg >> 2));
  33. }
  34. /*
  35. * We do not need this actually. The MSIR register has been read once
  36. * in the cascade interrupt. So, this MSI interrupt has been acked
  37. */
  38. static void fsl_msi_end_irq(unsigned int virq)
  39. {
  40. }
  41. static struct irq_chip fsl_msi_chip = {
  42. .mask = mask_msi_irq,
  43. .unmask = unmask_msi_irq,
  44. .ack = fsl_msi_end_irq,
  45. .typename = " FSL-MSI ",
  46. };
  47. static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
  48. irq_hw_number_t hw)
  49. {
  50. struct irq_chip *chip = &fsl_msi_chip;
  51. get_irq_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING;
  52. set_irq_chip_and_handler(virq, chip, handle_edge_irq);
  53. return 0;
  54. }
  55. static struct irq_host_ops fsl_msi_host_ops = {
  56. .map = fsl_msi_host_map,
  57. };
  58. static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
  59. {
  60. int rc;
  61. rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS,
  62. msi_data->irqhost->of_node);
  63. if (rc)
  64. return rc;
  65. rc = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap);
  66. if (rc < 0) {
  67. msi_bitmap_free(&msi_data->bitmap);
  68. return rc;
  69. }
  70. return 0;
  71. }
  72. static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
  73. {
  74. if (type == PCI_CAP_ID_MSIX)
  75. pr_debug("fslmsi: MSI-X untested, trying anyway.\n");
  76. return 0;
  77. }
  78. static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
  79. {
  80. struct msi_desc *entry;
  81. struct fsl_msi *msi_data = fsl_msi;
  82. list_for_each_entry(entry, &pdev->msi_list, list) {
  83. if (entry->irq == NO_IRQ)
  84. continue;
  85. set_irq_msi(entry->irq, NULL);
  86. msi_bitmap_free_hwirqs(&msi_data->bitmap,
  87. virq_to_hw(entry->irq), 1);
  88. irq_dispose_mapping(entry->irq);
  89. }
  90. return;
  91. }
  92. static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
  93. struct msi_msg *msg)
  94. {
  95. struct fsl_msi *msi_data = fsl_msi;
  96. struct pci_controller *hose = pci_bus_to_host(pdev->bus);
  97. u32 base = 0;
  98. pci_bus_read_config_dword(hose->bus,
  99. PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
  100. msg->address_lo = msi_data->msi_addr_lo + base;
  101. msg->address_hi = msi_data->msi_addr_hi;
  102. msg->data = hwirq;
  103. pr_debug("%s: allocated srs: %d, ibs: %d\n",
  104. __func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG);
  105. }
  106. static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
  107. {
  108. int rc, hwirq;
  109. unsigned int virq;
  110. struct msi_desc *entry;
  111. struct msi_msg msg;
  112. struct fsl_msi *msi_data = fsl_msi;
  113. list_for_each_entry(entry, &pdev->msi_list, list) {
  114. hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
  115. if (hwirq < 0) {
  116. rc = hwirq;
  117. pr_debug("%s: fail allocating msi interrupt\n",
  118. __func__);
  119. goto out_free;
  120. }
  121. virq = irq_create_mapping(msi_data->irqhost, hwirq);
  122. if (virq == NO_IRQ) {
  123. pr_debug("%s: fail mapping hwirq 0x%x\n",
  124. __func__, hwirq);
  125. msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
  126. rc = -ENOSPC;
  127. goto out_free;
  128. }
  129. set_irq_msi(virq, entry);
  130. fsl_compose_msi_msg(pdev, hwirq, &msg);
  131. write_msi_msg(virq, &msg);
  132. }
  133. return 0;
  134. out_free:
  135. return rc;
  136. }
  137. static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
  138. {
  139. unsigned int cascade_irq;
  140. struct fsl_msi *msi_data = fsl_msi;
  141. int msir_index = -1;
  142. u32 msir_value = 0;
  143. u32 intr_index;
  144. u32 have_shift = 0;
  145. spin_lock(&desc->lock);
  146. if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
  147. if (desc->chip->mask_ack)
  148. desc->chip->mask_ack(irq);
  149. else {
  150. desc->chip->mask(irq);
  151. desc->chip->ack(irq);
  152. }
  153. }
  154. if (unlikely(desc->status & IRQ_INPROGRESS))
  155. goto unlock;
  156. msir_index = (int)desc->handler_data;
  157. if (msir_index >= NR_MSI_REG)
  158. cascade_irq = NO_IRQ;
  159. desc->status |= IRQ_INPROGRESS;
  160. switch (fsl_msi->feature & FSL_PIC_IP_MASK) {
  161. case FSL_PIC_IP_MPIC:
  162. msir_value = fsl_msi_read(msi_data->msi_regs,
  163. msir_index * 0x10);
  164. break;
  165. case FSL_PIC_IP_IPIC:
  166. msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
  167. break;
  168. }
  169. while (msir_value) {
  170. intr_index = ffs(msir_value) - 1;
  171. cascade_irq = irq_linear_revmap(msi_data->irqhost,
  172. msir_index * IRQS_PER_MSI_REG +
  173. intr_index + have_shift);
  174. if (cascade_irq != NO_IRQ)
  175. generic_handle_irq(cascade_irq);
  176. have_shift += intr_index + 1;
  177. msir_value = msir_value >> (intr_index + 1);
  178. }
  179. desc->status &= ~IRQ_INPROGRESS;
  180. switch (msi_data->feature & FSL_PIC_IP_MASK) {
  181. case FSL_PIC_IP_MPIC:
  182. desc->chip->eoi(irq);
  183. break;
  184. case FSL_PIC_IP_IPIC:
  185. if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
  186. desc->chip->unmask(irq);
  187. break;
  188. }
  189. unlock:
  190. spin_unlock(&desc->lock);
  191. }
  192. static int __devinit fsl_of_msi_probe(struct of_device *dev,
  193. const struct of_device_id *match)
  194. {
  195. struct fsl_msi *msi;
  196. struct resource res;
  197. int err, i, count;
  198. int rc;
  199. int virt_msir;
  200. const u32 *p;
  201. struct fsl_msi_feature *features = match->data;
  202. printk(KERN_DEBUG "Setting up Freescale MSI support\n");
  203. msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
  204. if (!msi) {
  205. dev_err(&dev->dev, "No memory for MSI structure\n");
  206. err = -ENOMEM;
  207. goto error_out;
  208. }
  209. msi->irqhost = irq_alloc_host(dev->node, IRQ_HOST_MAP_LINEAR,
  210. NR_MSI_IRQS, &fsl_msi_host_ops, 0);
  211. if (msi->irqhost == NULL) {
  212. dev_err(&dev->dev, "No memory for MSI irqhost\n");
  213. err = -ENOMEM;
  214. goto error_out;
  215. }
  216. /* Get the MSI reg base */
  217. err = of_address_to_resource(dev->node, 0, &res);
  218. if (err) {
  219. dev_err(&dev->dev, "%s resource error!\n",
  220. dev->node->full_name);
  221. goto error_out;
  222. }
  223. msi->msi_regs = ioremap(res.start, res.end - res.start + 1);
  224. if (!msi->msi_regs) {
  225. dev_err(&dev->dev, "ioremap problem failed\n");
  226. goto error_out;
  227. }
  228. msi->feature = features->fsl_pic_ip;
  229. msi->irqhost->host_data = msi;
  230. msi->msi_addr_hi = 0x0;
  231. msi->msi_addr_lo = features->msiir_offset + (res.start & 0xfffff);
  232. rc = fsl_msi_init_allocator(msi);
  233. if (rc) {
  234. dev_err(&dev->dev, "Error allocating MSI bitmap\n");
  235. goto error_out;
  236. }
  237. p = of_get_property(dev->node, "interrupts", &count);
  238. if (!p) {
  239. dev_err(&dev->dev, "no interrupts property found on %s\n",
  240. dev->node->full_name);
  241. err = -ENODEV;
  242. goto error_out;
  243. }
  244. if (count % 8 != 0) {
  245. dev_err(&dev->dev, "Malformed interrupts property on %s\n",
  246. dev->node->full_name);
  247. err = -EINVAL;
  248. goto error_out;
  249. }
  250. count /= sizeof(u32);
  251. for (i = 0; i < count / 2; i++) {
  252. if (i > NR_MSI_REG)
  253. break;
  254. virt_msir = irq_of_parse_and_map(dev->node, i);
  255. if (virt_msir != NO_IRQ) {
  256. set_irq_data(virt_msir, (void *)i);
  257. set_irq_chained_handler(virt_msir, fsl_msi_cascade);
  258. }
  259. }
  260. fsl_msi = msi;
  261. WARN_ON(ppc_md.setup_msi_irqs);
  262. ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
  263. ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
  264. ppc_md.msi_check_device = fsl_msi_check_device;
  265. return 0;
  266. error_out:
  267. kfree(msi);
  268. return err;
  269. }
  270. static const struct fsl_msi_feature mpic_msi_feature = {
  271. .fsl_pic_ip = FSL_PIC_IP_MPIC,
  272. .msiir_offset = 0x140,
  273. };
  274. static const struct fsl_msi_feature ipic_msi_feature = {
  275. .fsl_pic_ip = FSL_PIC_IP_IPIC,
  276. .msiir_offset = 0x38,
  277. };
  278. static const struct of_device_id fsl_of_msi_ids[] = {
  279. {
  280. .compatible = "fsl,mpic-msi",
  281. .data = (void *)&mpic_msi_feature,
  282. },
  283. {
  284. .compatible = "fsl,ipic-msi",
  285. .data = (void *)&ipic_msi_feature,
  286. },
  287. {}
  288. };
  289. static struct of_platform_driver fsl_of_msi_driver = {
  290. .name = "fsl-msi",
  291. .match_table = fsl_of_msi_ids,
  292. .probe = fsl_of_msi_probe,
  293. };
  294. static __init int fsl_of_msi_init(void)
  295. {
  296. return of_register_platform_driver(&fsl_of_msi_driver);
  297. }
  298. subsys_initcall(fsl_of_msi_init);