mpc8349emitx.dts 8.0 KB

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  1. /*
  2. * MPC8349E-mITX Device Tree Source
  3. *
  4. * Copyright 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "MPC8349EMITX";
  14. compatible = "MPC8349EMITX", "MPC834xMITX", "MPC83xxMITX";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. serial0 = &serial0;
  21. serial1 = &serial1;
  22. pci0 = &pci0;
  23. pci1 = &pci1;
  24. };
  25. cpus {
  26. #address-cells = <1>;
  27. #size-cells = <0>;
  28. PowerPC,8349@0 {
  29. device_type = "cpu";
  30. reg = <0x0>;
  31. d-cache-line-size = <32>;
  32. i-cache-line-size = <32>;
  33. d-cache-size = <32768>;
  34. i-cache-size = <32768>;
  35. timebase-frequency = <0>; // from bootloader
  36. bus-frequency = <0>; // from bootloader
  37. clock-frequency = <0>; // from bootloader
  38. };
  39. };
  40. memory {
  41. device_type = "memory";
  42. reg = <0x00000000 0x10000000>;
  43. };
  44. soc8349@e0000000 {
  45. #address-cells = <1>;
  46. #size-cells = <1>;
  47. device_type = "soc";
  48. compatible = "simple-bus";
  49. ranges = <0x0 0xe0000000 0x00100000>;
  50. reg = <0xe0000000 0x00000200>;
  51. bus-frequency = <0>; // from bootloader
  52. wdt@200 {
  53. device_type = "watchdog";
  54. compatible = "mpc83xx_wdt";
  55. reg = <0x200 0x100>;
  56. };
  57. i2c@3000 {
  58. #address-cells = <1>;
  59. #size-cells = <0>;
  60. cell-index = <0>;
  61. compatible = "fsl-i2c";
  62. reg = <0x3000 0x100>;
  63. interrupts = <14 0x8>;
  64. interrupt-parent = <&ipic>;
  65. dfsrr;
  66. };
  67. i2c@3100 {
  68. #address-cells = <1>;
  69. #size-cells = <0>;
  70. cell-index = <1>;
  71. compatible = "fsl-i2c";
  72. reg = <0x3100 0x100>;
  73. interrupts = <15 0x8>;
  74. interrupt-parent = <&ipic>;
  75. dfsrr;
  76. rtc@68 {
  77. compatible = "dallas,ds1339";
  78. reg = <0x68>;
  79. interrupts = <18 0x8>;
  80. interrupt-parent = <&ipic>;
  81. };
  82. mcu_pio: mcu@a {
  83. #gpio-cells = <2>;
  84. compatible = "fsl,mc9s08qg8-mpc8349emitx",
  85. "fsl,mcu-mpc8349emitx";
  86. reg = <0x0a>;
  87. gpio-controller;
  88. };
  89. };
  90. spi@7000 {
  91. cell-index = <0>;
  92. compatible = "fsl,spi";
  93. reg = <0x7000 0x1000>;
  94. interrupts = <16 0x8>;
  95. interrupt-parent = <&ipic>;
  96. mode = "cpu";
  97. };
  98. dma@82a8 {
  99. #address-cells = <1>;
  100. #size-cells = <1>;
  101. compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
  102. reg = <0x82a8 4>;
  103. ranges = <0 0x8100 0x1a8>;
  104. interrupt-parent = <&ipic>;
  105. interrupts = <71 8>;
  106. cell-index = <0>;
  107. dma-channel@0 {
  108. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  109. reg = <0 0x80>;
  110. cell-index = <0>;
  111. interrupt-parent = <&ipic>;
  112. interrupts = <71 8>;
  113. };
  114. dma-channel@80 {
  115. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  116. reg = <0x80 0x80>;
  117. cell-index = <1>;
  118. interrupt-parent = <&ipic>;
  119. interrupts = <71 8>;
  120. };
  121. dma-channel@100 {
  122. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  123. reg = <0x100 0x80>;
  124. cell-index = <2>;
  125. interrupt-parent = <&ipic>;
  126. interrupts = <71 8>;
  127. };
  128. dma-channel@180 {
  129. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  130. reg = <0x180 0x28>;
  131. cell-index = <3>;
  132. interrupt-parent = <&ipic>;
  133. interrupts = <71 8>;
  134. };
  135. };
  136. usb@22000 {
  137. compatible = "fsl-usb2-mph";
  138. reg = <0x22000 0x1000>;
  139. #address-cells = <1>;
  140. #size-cells = <0>;
  141. interrupt-parent = <&ipic>;
  142. interrupts = <39 0x8>;
  143. phy_type = "ulpi";
  144. port0;
  145. };
  146. usb@23000 {
  147. compatible = "fsl-usb2-dr";
  148. reg = <0x23000 0x1000>;
  149. #address-cells = <1>;
  150. #size-cells = <0>;
  151. interrupt-parent = <&ipic>;
  152. interrupts = <38 0x8>;
  153. dr_mode = "peripheral";
  154. phy_type = "ulpi";
  155. };
  156. enet0: ethernet@24000 {
  157. #address-cells = <1>;
  158. #size-cells = <1>;
  159. cell-index = <0>;
  160. device_type = "network";
  161. model = "TSEC";
  162. compatible = "gianfar";
  163. reg = <0x24000 0x1000>;
  164. ranges = <0x0 0x24000 0x1000>;
  165. local-mac-address = [ 00 00 00 00 00 00 ];
  166. interrupts = <32 0x8 33 0x8 34 0x8>;
  167. interrupt-parent = <&ipic>;
  168. tbi-handle = <&tbi0>;
  169. phy-handle = <&phy1c>;
  170. linux,network-index = <0>;
  171. mdio@520 {
  172. #address-cells = <1>;
  173. #size-cells = <0>;
  174. compatible = "fsl,gianfar-mdio";
  175. reg = <0x520 0x20>;
  176. /* Vitesse 8201 */
  177. phy1c: ethernet-phy@1c {
  178. interrupt-parent = <&ipic>;
  179. interrupts = <18 0x8>;
  180. reg = <0x1c>;
  181. device_type = "ethernet-phy";
  182. };
  183. tbi0: tbi-phy@11 {
  184. reg = <0x11>;
  185. device_type = "tbi-phy";
  186. };
  187. };
  188. };
  189. enet1: ethernet@25000 {
  190. #address-cells = <1>;
  191. #size-cells = <1>;
  192. cell-index = <1>;
  193. device_type = "network";
  194. model = "TSEC";
  195. compatible = "gianfar";
  196. reg = <0x25000 0x1000>;
  197. ranges = <0x0 0x25000 0x1000>;
  198. local-mac-address = [ 00 00 00 00 00 00 ];
  199. interrupts = <35 0x8 36 0x8 37 0x8>;
  200. interrupt-parent = <&ipic>;
  201. /* Vitesse 7385 isn't on the MDIO bus */
  202. fixed-link = <1 1 1000 0 0>;
  203. linux,network-index = <1>;
  204. tbi-handle = <&tbi1>;
  205. mdio@520 {
  206. #address-cells = <1>;
  207. #size-cells = <0>;
  208. compatible = "fsl,gianfar-tbi";
  209. reg = <0x520 0x20>;
  210. tbi1: tbi-phy@11 {
  211. reg = <0x11>;
  212. device_type = "tbi-phy";
  213. };
  214. };
  215. };
  216. serial0: serial@4500 {
  217. cell-index = <0>;
  218. device_type = "serial";
  219. compatible = "ns16550";
  220. reg = <0x4500 0x100>;
  221. clock-frequency = <0>; // from bootloader
  222. interrupts = <9 0x8>;
  223. interrupt-parent = <&ipic>;
  224. };
  225. serial1: serial@4600 {
  226. cell-index = <1>;
  227. device_type = "serial";
  228. compatible = "ns16550";
  229. reg = <0x4600 0x100>;
  230. clock-frequency = <0>; // from bootloader
  231. interrupts = <10 0x8>;
  232. interrupt-parent = <&ipic>;
  233. };
  234. crypto@30000 {
  235. compatible = "fsl,sec2.0";
  236. reg = <0x30000 0x10000>;
  237. interrupts = <11 0x8>;
  238. interrupt-parent = <&ipic>;
  239. fsl,num-channels = <4>;
  240. fsl,channel-fifo-len = <24>;
  241. fsl,exec-units-mask = <0x7e>;
  242. fsl,descriptor-types-mask = <0x01010ebf>;
  243. };
  244. ipic: pic@700 {
  245. interrupt-controller;
  246. #address-cells = <0>;
  247. #interrupt-cells = <2>;
  248. reg = <0x700 0x100>;
  249. device_type = "ipic";
  250. };
  251. };
  252. pci0: pci@e0008500 {
  253. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  254. interrupt-map = <
  255. /* IDSEL 0x10 - SATA */
  256. 0x8000 0x0 0x0 0x1 &ipic 22 0x8 /* SATA_INTA */
  257. >;
  258. interrupt-parent = <&ipic>;
  259. interrupts = <66 0x8>;
  260. bus-range = <0x0 0x0>;
  261. ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
  262. 0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
  263. 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>;
  264. clock-frequency = <66666666>;
  265. #interrupt-cells = <1>;
  266. #size-cells = <2>;
  267. #address-cells = <3>;
  268. reg = <0xe0008500 0x100 /* internal registers */
  269. 0xe0008300 0x8>; /* config space access registers */
  270. compatible = "fsl,mpc8349-pci";
  271. device_type = "pci";
  272. };
  273. pci1: pci@e0008600 {
  274. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  275. interrupt-map = <
  276. /* IDSEL 0x0E - MiniPCI Slot */
  277. 0x7000 0x0 0x0 0x1 &ipic 21 0x8 /* PCI_INTA */
  278. /* IDSEL 0x0F - PCI Slot */
  279. 0x7800 0x0 0x0 0x1 &ipic 20 0x8 /* PCI_INTA */
  280. 0x7800 0x0 0x0 0x2 &ipic 21 0x8 /* PCI_INTB */
  281. >;
  282. interrupt-parent = <&ipic>;
  283. interrupts = <67 0x8>;
  284. bus-range = <0x0 0x0>;
  285. ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
  286. 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
  287. 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x01000000>;
  288. clock-frequency = <66666666>;
  289. #interrupt-cells = <1>;
  290. #size-cells = <2>;
  291. #address-cells = <3>;
  292. reg = <0xe0008600 0x100 /* internal registers */
  293. 0xe0008380 0x8>; /* config space access registers */
  294. compatible = "fsl,mpc8349-pci";
  295. device_type = "pci";
  296. };
  297. localbus@e0005000 {
  298. #address-cells = <2>;
  299. #size-cells = <1>;
  300. compatible = "fsl,mpc8349e-localbus",
  301. "fsl,pq2pro-localbus";
  302. reg = <0xe0005000 0xd8>;
  303. ranges = <0x3 0x0 0xf0000000 0x210>;
  304. pata@3,0 {
  305. compatible = "fsl,mpc8349emitx-pata", "ata-generic";
  306. reg = <0x3 0x0 0x10 0x3 0x20c 0x4>;
  307. reg-shift = <1>;
  308. pio-mode = <6>;
  309. interrupts = <23 0x8>;
  310. interrupt-parent = <&ipic>;
  311. };
  312. };
  313. };