cpu-feature-overrides.h 2.0 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2004 Cavium Networks
  7. */
  8. #ifndef __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
  9. #define __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
  10. #include <linux/types.h>
  11. #include <asm/mipsregs.h>
  12. /*
  13. * Cavium Octeons are MIPS64v2 processors
  14. */
  15. #define cpu_dcache_line_size() 128
  16. #define cpu_icache_line_size() 128
  17. #define cpu_has_4kex 1
  18. #define cpu_has_3k_cache 0
  19. #define cpu_has_4k_cache 0
  20. #define cpu_has_tx39_cache 0
  21. #define cpu_has_fpu 0
  22. #define cpu_has_counter 1
  23. #define cpu_has_watch 1
  24. #define cpu_has_divec 1
  25. #define cpu_has_vce 0
  26. #define cpu_has_cache_cdex_p 0
  27. #define cpu_has_cache_cdex_s 0
  28. #define cpu_has_prefetch 1
  29. /*
  30. * We should disable LL/SC on non SMP systems as it is faster to
  31. * disable interrupts for atomic access than a LL/SC. Unfortunatly we
  32. * cannot as this breaks asm/futex.h
  33. */
  34. #define cpu_has_llsc 1
  35. #define cpu_has_vtag_icache 1
  36. #define cpu_has_dc_aliases 0
  37. #define cpu_has_ic_fills_f_dc 0
  38. #define cpu_has_64bits 1
  39. #define cpu_has_octeon_cache 1
  40. #define cpu_has_saa octeon_has_saa()
  41. #define cpu_has_mips32r1 0
  42. #define cpu_has_mips32r2 0
  43. #define cpu_has_mips64r1 0
  44. #define cpu_has_mips64r2 1
  45. #define cpu_has_mips_r2_exec_hazard 0
  46. #define cpu_has_dsp 0
  47. #define cpu_has_mipsmt 0
  48. #define cpu_has_userlocal 0
  49. #define cpu_has_vint 0
  50. #define cpu_has_veic 0
  51. #define cpu_hwrena_impl_bits 0xc0000000
  52. #define ARCH_HAS_READ_CURRENT_TIMER 1
  53. #define ARCH_HAS_IRQ_PER_CPU 1
  54. #define ARCH_HAS_SPINLOCK_PREFETCH 1
  55. #define spin_lock_prefetch(x) prefetch(x)
  56. #define PREFETCH_STRIDE 128
  57. static inline int read_current_timer(unsigned long *result)
  58. {
  59. asm volatile ("rdhwr %0,$31\n"
  60. #ifndef CONFIG_64BIT
  61. "\tsll %0, 0"
  62. #endif
  63. : "=r" (*result));
  64. return 0;
  65. }
  66. static inline int octeon_has_saa(void)
  67. {
  68. int id;
  69. asm volatile ("mfc0 %0, $15,0" : "=r" (id));
  70. return id >= 0x000d0300;
  71. }
  72. #endif