bcache.h 1.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960
  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (c) 1997, 1999 by Ralf Baechle
  7. * Copyright (c) 1999 Silicon Graphics, Inc.
  8. */
  9. #ifndef _ASM_BCACHE_H
  10. #define _ASM_BCACHE_H
  11. /* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent,
  12. chipset implemented caches. On machines with other CPUs the CPU does the
  13. cache thing itself. */
  14. struct bcache_ops {
  15. void (*bc_enable)(void);
  16. void (*bc_disable)(void);
  17. void (*bc_wback_inv)(unsigned long page, unsigned long size);
  18. void (*bc_inv)(unsigned long page, unsigned long size);
  19. };
  20. extern void indy_sc_init(void);
  21. #ifdef CONFIG_BOARD_SCACHE
  22. extern struct bcache_ops *bcops;
  23. static inline void bc_enable(void)
  24. {
  25. bcops->bc_enable();
  26. }
  27. static inline void bc_disable(void)
  28. {
  29. bcops->bc_disable();
  30. }
  31. static inline void bc_wback_inv(unsigned long page, unsigned long size)
  32. {
  33. bcops->bc_wback_inv(page, size);
  34. }
  35. static inline void bc_inv(unsigned long page, unsigned long size)
  36. {
  37. bcops->bc_inv(page, size);
  38. }
  39. #else /* !defined(CONFIG_BOARD_SCACHE) */
  40. /* Not R4000 / R4400 / R4600 / R5000. */
  41. #define bc_enable() do { } while (0)
  42. #define bc_disable() do { } while (0)
  43. #define bc_wback_inv(page, size) do { } while (0)
  44. #define bc_inv(page, size) do { } while (0)
  45. #endif /* !defined(CONFIG_BOARD_SCACHE) */
  46. #endif /* _ASM_BCACHE_H */