interrupt.S 6.3 KB

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  1. /*
  2. * File: arch/blackfin/mach-common/interrupt.S
  3. * Based on:
  4. * Author: D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>
  5. * Kenneth Albanowski <kjahds@kjahds.com>
  6. *
  7. * Created: ?
  8. * Description: Interrupt Entries
  9. *
  10. * Modified:
  11. * Copyright 2004-2006 Analog Devices Inc.
  12. *
  13. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License as published by
  17. * the Free Software Foundation; either version 2 of the License, or
  18. * (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, see the file COPYING, or write
  27. * to the Free Software Foundation, Inc.,
  28. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  29. */
  30. #include <asm/blackfin.h>
  31. #include <mach/irq.h>
  32. #include <linux/linkage.h>
  33. #include <asm/entry.h>
  34. #include <asm/asm-offsets.h>
  35. #include <asm/trace.h>
  36. #include <asm/traps.h>
  37. #include <asm/thread_info.h>
  38. #include <asm/context.S>
  39. .extern _ret_from_exception
  40. #ifdef CONFIG_I_ENTRY_L1
  41. .section .l1.text
  42. #else
  43. .text
  44. #endif
  45. .align 4 /* just in case */
  46. /* Common interrupt entry code. First we do CLI, then push
  47. * RETI, to keep interrupts disabled, but to allow this state to be changed
  48. * by local_bh_enable.
  49. * R0 contains the interrupt number, while R1 may contain the value of IPEND,
  50. * or garbage if IPEND won't be needed by the ISR. */
  51. __common_int_entry:
  52. [--sp] = fp;
  53. [--sp] = usp;
  54. [--sp] = i0;
  55. [--sp] = i1;
  56. [--sp] = i2;
  57. [--sp] = i3;
  58. [--sp] = m0;
  59. [--sp] = m1;
  60. [--sp] = m2;
  61. [--sp] = m3;
  62. [--sp] = l0;
  63. [--sp] = l1;
  64. [--sp] = l2;
  65. [--sp] = l3;
  66. [--sp] = b0;
  67. [--sp] = b1;
  68. [--sp] = b2;
  69. [--sp] = b3;
  70. [--sp] = a0.x;
  71. [--sp] = a0.w;
  72. [--sp] = a1.x;
  73. [--sp] = a1.w;
  74. [--sp] = LC0;
  75. [--sp] = LC1;
  76. [--sp] = LT0;
  77. [--sp] = LT1;
  78. [--sp] = LB0;
  79. [--sp] = LB1;
  80. [--sp] = ASTAT;
  81. [--sp] = r0; /* Skip reserved */
  82. [--sp] = RETS;
  83. r2 = RETI;
  84. [--sp] = r2;
  85. [--sp] = RETX;
  86. [--sp] = RETN;
  87. [--sp] = RETE;
  88. [--sp] = SEQSTAT;
  89. [--sp] = r1; /* IPEND - R1 may or may not be set up before jumping here. */
  90. /* Switch to other method of keeping interrupts disabled. */
  91. #ifdef CONFIG_DEBUG_HWERR
  92. r1 = 0x3f;
  93. sti r1;
  94. #else
  95. cli r1;
  96. #endif
  97. [--sp] = RETI; /* orig_pc */
  98. /* Clear all L registers. */
  99. r1 = 0 (x);
  100. l0 = r1;
  101. l1 = r1;
  102. l2 = r1;
  103. l3 = r1;
  104. #ifdef CONFIG_FRAME_POINTER
  105. fp = 0;
  106. #endif
  107. #if ANOMALY_05000283 || ANOMALY_05000315
  108. cc = r7 == r7;
  109. p5.h = HI(CHIPID);
  110. p5.l = LO(CHIPID);
  111. if cc jump 1f;
  112. r7.l = W[p5];
  113. 1:
  114. #endif
  115. r1 = sp;
  116. SP += -12;
  117. #ifdef CONFIG_IPIPE
  118. call ___ipipe_grab_irq
  119. SP += 12;
  120. cc = r0 == 0;
  121. if cc jump .Lcommon_restore_context;
  122. #else /* CONFIG_IPIPE */
  123. call _do_irq;
  124. SP += 12;
  125. #endif /* CONFIG_IPIPE */
  126. call _return_from_int;
  127. .Lcommon_restore_context:
  128. RESTORE_CONTEXT
  129. rti;
  130. /* interrupt routine for ivhw - 5 */
  131. ENTRY(_evt_ivhw)
  132. /* In case a single action kicks off multiple memory transactions, (like
  133. * a cache line fetch, - this can cause multiple hardware errors, let's
  134. * catch them all. First - make sure all the actions are complete, and
  135. * the core sees the hardware errors.
  136. */
  137. SSYNC;
  138. SSYNC;
  139. SAVE_ALL_SYS
  140. #ifdef CONFIG_FRAME_POINTER
  141. fp = 0;
  142. #endif
  143. #if ANOMALY_05000283 || ANOMALY_05000315
  144. cc = r7 == r7;
  145. p5.h = HI(CHIPID);
  146. p5.l = LO(CHIPID);
  147. if cc jump 1f;
  148. r7.l = W[p5];
  149. 1:
  150. #endif
  151. /* Handle all stacked hardware errors
  152. * To make sure we don't hang forever, only do it 10 times
  153. */
  154. R0 = 0;
  155. R2 = 10;
  156. 1:
  157. P0.L = LO(ILAT);
  158. P0.H = HI(ILAT);
  159. R1 = [P0];
  160. CC = BITTST(R1, EVT_IVHW_P);
  161. IF ! CC JUMP 2f;
  162. /* OK a hardware error is pending - clear it */
  163. R1 = EVT_IVHW_P;
  164. [P0] = R1;
  165. R0 += 1;
  166. CC = R1 == R2;
  167. if CC JUMP 2f;
  168. JUMP 1b;
  169. 2:
  170. # We are going to dump something out, so make sure we print IPEND properly
  171. p2.l = lo(IPEND);
  172. p2.h = hi(IPEND);
  173. r0 = [p2];
  174. [sp + PT_IPEND] = r0;
  175. /* set the EXCAUSE to HWERR for trap_c */
  176. r0 = [sp + PT_SEQSTAT];
  177. R1.L = LO(VEC_HWERR);
  178. R1.H = HI(VEC_HWERR);
  179. R0 = R0 | R1;
  180. [sp + PT_SEQSTAT] = R0;
  181. r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
  182. SP += -12;
  183. call _trap_c;
  184. SP += 12;
  185. #ifdef EBIU_ERRMST
  186. /* make sure EBIU_ERRMST is clear */
  187. p0.l = LO(EBIU_ERRMST);
  188. p0.h = HI(EBIU_ERRMST);
  189. r0.l = (CORE_ERROR | CORE_MERROR);
  190. w[p0] = r0.l;
  191. #endif
  192. call _ret_from_exception;
  193. .Lcommon_restore_all_sys:
  194. RESTORE_ALL_SYS
  195. rti;
  196. ENDPROC(_evt_ivhw)
  197. /* Interrupt routine for evt2 (NMI).
  198. * We don't actually use this, so just return.
  199. * For inner circle type details, please see:
  200. * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:nmi
  201. */
  202. ENTRY(_evt_nmi)
  203. .weak _evt_nmi
  204. rtn;
  205. ENDPROC(_evt_nmi)
  206. /* interrupt routine for core timer - 6 */
  207. ENTRY(_evt_timer)
  208. TIMER_INTERRUPT_ENTRY(EVT_IVTMR_P)
  209. /* interrupt routine for evt7 - 7 */
  210. ENTRY(_evt_evt7)
  211. INTERRUPT_ENTRY(EVT_IVG7_P)
  212. ENTRY(_evt_evt8)
  213. INTERRUPT_ENTRY(EVT_IVG8_P)
  214. ENTRY(_evt_evt9)
  215. INTERRUPT_ENTRY(EVT_IVG9_P)
  216. ENTRY(_evt_evt10)
  217. INTERRUPT_ENTRY(EVT_IVG10_P)
  218. ENTRY(_evt_evt11)
  219. INTERRUPT_ENTRY(EVT_IVG11_P)
  220. ENTRY(_evt_evt12)
  221. INTERRUPT_ENTRY(EVT_IVG12_P)
  222. ENTRY(_evt_evt13)
  223. INTERRUPT_ENTRY(EVT_IVG13_P)
  224. /* interrupt routine for system_call - 15 */
  225. ENTRY(_evt_system_call)
  226. SAVE_CONTEXT_SYSCALL
  227. #ifdef CONFIG_FRAME_POINTER
  228. fp = 0;
  229. #endif
  230. call _system_call;
  231. jump .Lcommon_restore_context;
  232. ENDPROC(_evt_system_call)
  233. #ifdef CONFIG_IPIPE
  234. ENTRY(___ipipe_call_irqtail)
  235. p0 = r0;
  236. r0.l = 1f;
  237. r0.h = 1f;
  238. reti = r0;
  239. rti;
  240. 1:
  241. [--sp] = rets;
  242. [--sp] = ( r7:4, p5:3 );
  243. sp += -12;
  244. call (p0);
  245. sp += 12;
  246. ( r7:4, p5:3 ) = [sp++];
  247. rets = [sp++];
  248. [--sp] = reti;
  249. reti = [sp++]; /* IRQs are off. */
  250. r0.h = 3f;
  251. r0.l = 3f;
  252. p0.l = lo(EVT14);
  253. p0.h = hi(EVT14);
  254. [p0] = r0;
  255. csync;
  256. r0 = 0x401f (z);
  257. sti r0;
  258. raise 14;
  259. [--sp] = reti; /* IRQs on. */
  260. 2:
  261. jump 2b; /* Likely paranoid. */
  262. 3:
  263. sp += 4; /* Discard saved RETI */
  264. r0.h = _evt14_softirq;
  265. r0.l = _evt14_softirq;
  266. p0.l = lo(EVT14);
  267. p0.h = hi(EVT14);
  268. [p0] = r0;
  269. csync;
  270. p0.l = _bfin_irq_flags;
  271. p0.h = _bfin_irq_flags;
  272. r0 = [p0];
  273. sti r0;
  274. rts;
  275. ENDPROC(___ipipe_call_irqtail)
  276. #endif /* CONFIG_IPIPE */