timer32k.c 6.0 KB

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  1. /*
  2. * linux/arch/arm/mach-omap1/timer32k.c
  3. *
  4. * OMAP 32K Timer
  5. *
  6. * Copyright (C) 2004 - 2005 Nokia Corporation
  7. * Partial timer rewrite and additional dynamic tick timer support by
  8. * Tony Lindgen <tony@atomide.com> and
  9. * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10. * OMAP Dual-mode timer framework support by Timo Teras
  11. *
  12. * MPU timer code based on the older MPU timer code for OMAP
  13. * Copyright (C) 2000 RidgeRun, Inc.
  14. * Author: Greg Lonnon <glonnon@ridgerun.com>
  15. *
  16. * This program is free software; you can redistribute it and/or modify it
  17. * under the terms of the GNU General Public License as published by the
  18. * Free Software Foundation; either version 2 of the License, or (at your
  19. * option) any later version.
  20. *
  21. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  22. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  24. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  25. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  27. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  28. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31. *
  32. * You should have received a copy of the GNU General Public License along
  33. * with this program; if not, write to the Free Software Foundation, Inc.,
  34. * 675 Mass Ave, Cambridge, MA 02139, USA.
  35. */
  36. #include <linux/kernel.h>
  37. #include <linux/init.h>
  38. #include <linux/delay.h>
  39. #include <linux/interrupt.h>
  40. #include <linux/sched.h>
  41. #include <linux/spinlock.h>
  42. #include <linux/err.h>
  43. #include <linux/clk.h>
  44. #include <linux/clocksource.h>
  45. #include <linux/clockchips.h>
  46. #include <linux/io.h>
  47. #include <asm/system.h>
  48. #include <mach/hardware.h>
  49. #include <asm/leds.h>
  50. #include <asm/irq.h>
  51. #include <asm/mach/irq.h>
  52. #include <asm/mach/time.h>
  53. #include <mach/dmtimer.h>
  54. struct sys_timer omap_timer;
  55. /*
  56. * ---------------------------------------------------------------------------
  57. * 32KHz OS timer
  58. *
  59. * This currently works only on 16xx, as 1510 does not have the continuous
  60. * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
  61. * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
  62. * on 1510 would be possible, but the timer would not be as accurate as
  63. * with the 32KHz synchronized timer.
  64. * ---------------------------------------------------------------------------
  65. */
  66. #if defined(CONFIG_ARCH_OMAP16XX)
  67. #define TIMER_32K_SYNCHRONIZED 0xfffbc410
  68. #else
  69. #error OMAP 32KHz timer does not currently work on 15XX!
  70. #endif
  71. /* 16xx specific defines */
  72. #define OMAP1_32K_TIMER_BASE 0xfffb9000
  73. #define OMAP1_32K_TIMER_CR 0x08
  74. #define OMAP1_32K_TIMER_TVR 0x00
  75. #define OMAP1_32K_TIMER_TCR 0x04
  76. #define OMAP_32K_TICKS_PER_SEC (32768)
  77. /*
  78. * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
  79. * so with HZ = 128, TVR = 255.
  80. */
  81. #define OMAP_32K_TIMER_TICK_PERIOD ((OMAP_32K_TICKS_PER_SEC / HZ) - 1)
  82. #define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
  83. (((nr_jiffies) * (clock_rate)) / HZ)
  84. static inline void omap_32k_timer_write(int val, int reg)
  85. {
  86. omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
  87. }
  88. static inline unsigned long omap_32k_timer_read(int reg)
  89. {
  90. return omap_readl(OMAP1_32K_TIMER_BASE + reg) & 0xffffff;
  91. }
  92. static inline void omap_32k_timer_start(unsigned long load_val)
  93. {
  94. if (!load_val)
  95. load_val = 1;
  96. omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR);
  97. omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR);
  98. }
  99. static inline void omap_32k_timer_stop(void)
  100. {
  101. omap_32k_timer_write(0x0, OMAP1_32K_TIMER_CR);
  102. }
  103. #define omap_32k_timer_ack_irq()
  104. static int omap_32k_timer_set_next_event(unsigned long delta,
  105. struct clock_event_device *dev)
  106. {
  107. omap_32k_timer_start(delta);
  108. return 0;
  109. }
  110. static void omap_32k_timer_set_mode(enum clock_event_mode mode,
  111. struct clock_event_device *evt)
  112. {
  113. omap_32k_timer_stop();
  114. switch (mode) {
  115. case CLOCK_EVT_MODE_PERIODIC:
  116. omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
  117. break;
  118. case CLOCK_EVT_MODE_ONESHOT:
  119. case CLOCK_EVT_MODE_UNUSED:
  120. case CLOCK_EVT_MODE_SHUTDOWN:
  121. break;
  122. case CLOCK_EVT_MODE_RESUME:
  123. break;
  124. }
  125. }
  126. static struct clock_event_device clockevent_32k_timer = {
  127. .name = "32k-timer",
  128. .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
  129. .shift = 32,
  130. .set_next_event = omap_32k_timer_set_next_event,
  131. .set_mode = omap_32k_timer_set_mode,
  132. };
  133. /*
  134. * The 32KHz synchronized timer is an additional timer on 16xx.
  135. * It is always running.
  136. */
  137. static inline unsigned long omap_32k_sync_timer_read(void)
  138. {
  139. return omap_readl(TIMER_32K_SYNCHRONIZED);
  140. }
  141. static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id)
  142. {
  143. struct clock_event_device *evt = &clockevent_32k_timer;
  144. omap_32k_timer_ack_irq();
  145. evt->event_handler(evt);
  146. return IRQ_HANDLED;
  147. }
  148. static struct irqaction omap_32k_timer_irq = {
  149. .name = "32KHz timer",
  150. .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
  151. .handler = omap_32k_timer_interrupt,
  152. };
  153. static __init void omap_init_32k_timer(void)
  154. {
  155. setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
  156. clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC,
  157. NSEC_PER_SEC,
  158. clockevent_32k_timer.shift);
  159. clockevent_32k_timer.max_delta_ns =
  160. clockevent_delta2ns(0xfffffffe, &clockevent_32k_timer);
  161. clockevent_32k_timer.min_delta_ns =
  162. clockevent_delta2ns(1, &clockevent_32k_timer);
  163. clockevent_32k_timer.cpumask = cpumask_of(0);
  164. clockevents_register_device(&clockevent_32k_timer);
  165. }
  166. /*
  167. * ---------------------------------------------------------------------------
  168. * Timer initialization
  169. * ---------------------------------------------------------------------------
  170. */
  171. static void __init omap_timer_init(void)
  172. {
  173. #ifdef CONFIG_OMAP_DM_TIMER
  174. omap_dm_timer_init();
  175. #endif
  176. omap_init_32k_timer();
  177. }
  178. struct sys_timer omap_timer = {
  179. .init = omap_timer_init,
  180. };