board-fsample.c 8.3 KB

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  1. /*
  2. * linux/arch/arm/mach-omap1/board-fsample.c
  3. *
  4. * Modified from board-perseus2.c
  5. *
  6. * Original OMAP730 support by Jean Pihet <j-pihet@ti.com>
  7. * Updated for 2.6 by Kevin Hilman <kjh@hilman.org>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/delay.h>
  17. #include <linux/mtd/mtd.h>
  18. #include <linux/mtd/nand.h>
  19. #include <linux/mtd/partitions.h>
  20. #include <linux/input.h>
  21. #include <mach/hardware.h>
  22. #include <asm/mach-types.h>
  23. #include <asm/mach/arch.h>
  24. #include <asm/mach/flash.h>
  25. #include <asm/mach/map.h>
  26. #include <mach/tc.h>
  27. #include <mach/gpio.h>
  28. #include <mach/mux.h>
  29. #include <mach/fpga.h>
  30. #include <mach/nand.h>
  31. #include <mach/keypad.h>
  32. #include <mach/common.h>
  33. #include <mach/board.h>
  34. /* fsample is pretty close to p2-sample */
  35. #define fsample_cpld_read(reg) __raw_readb(reg)
  36. #define fsample_cpld_write(val, reg) __raw_writeb(val, reg)
  37. #define FSAMPLE_CPLD_BASE 0xE8100000
  38. #define FSAMPLE_CPLD_SIZE SZ_4K
  39. #define FSAMPLE_CPLD_START 0x05080000
  40. #define FSAMPLE_CPLD_REG_A (FSAMPLE_CPLD_BASE + 0x00)
  41. #define FSAMPLE_CPLD_SWITCH (FSAMPLE_CPLD_BASE + 0x02)
  42. #define FSAMPLE_CPLD_UART (FSAMPLE_CPLD_BASE + 0x02)
  43. #define FSAMPLE_CPLD_REG_B (FSAMPLE_CPLD_BASE + 0x04)
  44. #define FSAMPLE_CPLD_VERSION (FSAMPLE_CPLD_BASE + 0x06)
  45. #define FSAMPLE_CPLD_SET_CLR (FSAMPLE_CPLD_BASE + 0x06)
  46. #define FSAMPLE_CPLD_BIT_BT_RESET 0
  47. #define FSAMPLE_CPLD_BIT_LCD_RESET 1
  48. #define FSAMPLE_CPLD_BIT_CAM_PWDN 2
  49. #define FSAMPLE_CPLD_BIT_CHARGER_ENABLE 3
  50. #define FSAMPLE_CPLD_BIT_SD_MMC_EN 4
  51. #define FSAMPLE_CPLD_BIT_aGPS_PWREN 5
  52. #define FSAMPLE_CPLD_BIT_BACKLIGHT 6
  53. #define FSAMPLE_CPLD_BIT_aGPS_EN_RESET 7
  54. #define FSAMPLE_CPLD_BIT_aGPS_SLEEPx_N 8
  55. #define FSAMPLE_CPLD_BIT_OTG_RESET 9
  56. #define fsample_cpld_set(bit) \
  57. fsample_cpld_write((((bit) & 15) << 4) | 0x0f, FSAMPLE_CPLD_SET_CLR)
  58. #define fsample_cpld_clear(bit) \
  59. fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR)
  60. static int fsample_keymap[] = {
  61. KEY(0,0,KEY_UP),
  62. KEY(0,1,KEY_RIGHT),
  63. KEY(0,2,KEY_LEFT),
  64. KEY(0,3,KEY_DOWN),
  65. KEY(0,4,KEY_ENTER),
  66. KEY(1,0,KEY_F10),
  67. KEY(1,1,KEY_SEND),
  68. KEY(1,2,KEY_END),
  69. KEY(1,3,KEY_VOLUMEDOWN),
  70. KEY(1,4,KEY_VOLUMEUP),
  71. KEY(1,5,KEY_RECORD),
  72. KEY(2,0,KEY_F9),
  73. KEY(2,1,KEY_3),
  74. KEY(2,2,KEY_6),
  75. KEY(2,3,KEY_9),
  76. KEY(2,4,KEY_KPDOT),
  77. KEY(3,0,KEY_BACK),
  78. KEY(3,1,KEY_2),
  79. KEY(3,2,KEY_5),
  80. KEY(3,3,KEY_8),
  81. KEY(3,4,KEY_0),
  82. KEY(3,5,KEY_KPSLASH),
  83. KEY(4,0,KEY_HOME),
  84. KEY(4,1,KEY_1),
  85. KEY(4,2,KEY_4),
  86. KEY(4,3,KEY_7),
  87. KEY(4,4,KEY_KPASTERISK),
  88. KEY(4,5,KEY_POWER),
  89. 0
  90. };
  91. static struct resource smc91x_resources[] = {
  92. [0] = {
  93. .start = H2P2_DBG_FPGA_ETHR_START, /* Physical */
  94. .end = H2P2_DBG_FPGA_ETHR_START + 0xf,
  95. .flags = IORESOURCE_MEM,
  96. },
  97. [1] = {
  98. .start = INT_730_MPU_EXT_NIRQ,
  99. .end = 0,
  100. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
  101. },
  102. };
  103. static struct mtd_partition nor_partitions[] = {
  104. /* bootloader (U-Boot, etc) in first sector */
  105. {
  106. .name = "bootloader",
  107. .offset = 0,
  108. .size = SZ_128K,
  109. .mask_flags = MTD_WRITEABLE, /* force read-only */
  110. },
  111. /* bootloader params in the next sector */
  112. {
  113. .name = "params",
  114. .offset = MTDPART_OFS_APPEND,
  115. .size = SZ_128K,
  116. .mask_flags = 0,
  117. },
  118. /* kernel */
  119. {
  120. .name = "kernel",
  121. .offset = MTDPART_OFS_APPEND,
  122. .size = SZ_2M,
  123. .mask_flags = 0
  124. },
  125. /* rest of flash is a file system */
  126. {
  127. .name = "rootfs",
  128. .offset = MTDPART_OFS_APPEND,
  129. .size = MTDPART_SIZ_FULL,
  130. .mask_flags = 0
  131. },
  132. };
  133. static struct flash_platform_data nor_data = {
  134. .map_name = "cfi_probe",
  135. .width = 2,
  136. .parts = nor_partitions,
  137. .nr_parts = ARRAY_SIZE(nor_partitions),
  138. };
  139. static struct resource nor_resource = {
  140. .start = OMAP_CS0_PHYS,
  141. .end = OMAP_CS0_PHYS + SZ_32M - 1,
  142. .flags = IORESOURCE_MEM,
  143. };
  144. static struct platform_device nor_device = {
  145. .name = "omapflash",
  146. .id = 0,
  147. .dev = {
  148. .platform_data = &nor_data,
  149. },
  150. .num_resources = 1,
  151. .resource = &nor_resource,
  152. };
  153. static struct omap_nand_platform_data nand_data = {
  154. .options = NAND_SAMSUNG_LP_OPTIONS,
  155. };
  156. static struct resource nand_resource = {
  157. .start = OMAP_CS3_PHYS,
  158. .end = OMAP_CS3_PHYS + SZ_4K - 1,
  159. .flags = IORESOURCE_MEM,
  160. };
  161. static struct platform_device nand_device = {
  162. .name = "omapnand",
  163. .id = 0,
  164. .dev = {
  165. .platform_data = &nand_data,
  166. },
  167. .num_resources = 1,
  168. .resource = &nand_resource,
  169. };
  170. static struct platform_device smc91x_device = {
  171. .name = "smc91x",
  172. .id = 0,
  173. .num_resources = ARRAY_SIZE(smc91x_resources),
  174. .resource = smc91x_resources,
  175. };
  176. static struct resource kp_resources[] = {
  177. [0] = {
  178. .start = INT_730_MPUIO_KEYPAD,
  179. .end = INT_730_MPUIO_KEYPAD,
  180. .flags = IORESOURCE_IRQ,
  181. },
  182. };
  183. static struct omap_kp_platform_data kp_data = {
  184. .rows = 8,
  185. .cols = 8,
  186. .keymap = fsample_keymap,
  187. .keymapsize = ARRAY_SIZE(fsample_keymap),
  188. .delay = 4,
  189. };
  190. static struct platform_device kp_device = {
  191. .name = "omap-keypad",
  192. .id = -1,
  193. .dev = {
  194. .platform_data = &kp_data,
  195. },
  196. .num_resources = ARRAY_SIZE(kp_resources),
  197. .resource = kp_resources,
  198. };
  199. static struct platform_device lcd_device = {
  200. .name = "lcd_p2",
  201. .id = -1,
  202. };
  203. static struct platform_device *devices[] __initdata = {
  204. &nor_device,
  205. &nand_device,
  206. &smc91x_device,
  207. &kp_device,
  208. &lcd_device,
  209. };
  210. #define P2_NAND_RB_GPIO_PIN 62
  211. static int nand_dev_ready(struct omap_nand_platform_data *data)
  212. {
  213. return gpio_get_value(P2_NAND_RB_GPIO_PIN);
  214. }
  215. static struct omap_uart_config fsample_uart_config __initdata = {
  216. .enabled_uarts = ((1 << 0) | (1 << 1)),
  217. };
  218. static struct omap_lcd_config fsample_lcd_config __initdata = {
  219. .ctrl_name = "internal",
  220. };
  221. static struct omap_board_config_kernel fsample_config[] = {
  222. { OMAP_TAG_UART, &fsample_uart_config },
  223. { OMAP_TAG_LCD, &fsample_lcd_config },
  224. };
  225. static void __init omap_fsample_init(void)
  226. {
  227. if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0)
  228. BUG();
  229. nand_data.dev_ready = nand_dev_ready;
  230. omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
  231. omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
  232. platform_add_devices(devices, ARRAY_SIZE(devices));
  233. omap_board_config = fsample_config;
  234. omap_board_config_size = ARRAY_SIZE(fsample_config);
  235. omap_serial_init();
  236. omap_register_i2c_bus(1, 100, NULL, 0);
  237. }
  238. static void __init fsample_init_smc91x(void)
  239. {
  240. fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
  241. mdelay(50);
  242. fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
  243. H2P2_DBG_FPGA_LAN_RESET);
  244. mdelay(50);
  245. }
  246. static void __init omap_fsample_init_irq(void)
  247. {
  248. omap1_init_common_hw();
  249. omap_init_irq();
  250. omap_gpio_init();
  251. fsample_init_smc91x();
  252. }
  253. /* Only FPGA needs to be mapped here. All others are done with ioremap */
  254. static struct map_desc omap_fsample_io_desc[] __initdata = {
  255. {
  256. .virtual = H2P2_DBG_FPGA_BASE,
  257. .pfn = __phys_to_pfn(H2P2_DBG_FPGA_START),
  258. .length = H2P2_DBG_FPGA_SIZE,
  259. .type = MT_DEVICE
  260. },
  261. {
  262. .virtual = FSAMPLE_CPLD_BASE,
  263. .pfn = __phys_to_pfn(FSAMPLE_CPLD_START),
  264. .length = FSAMPLE_CPLD_SIZE,
  265. .type = MT_DEVICE
  266. }
  267. };
  268. static void __init omap_fsample_map_io(void)
  269. {
  270. omap1_map_common_io();
  271. iotable_init(omap_fsample_io_desc,
  272. ARRAY_SIZE(omap_fsample_io_desc));
  273. /* Early, board-dependent init */
  274. /*
  275. * Hold GSM Reset until needed
  276. */
  277. omap_writew(omap_readw(OMAP730_DSP_M_CTL) & ~1, OMAP730_DSP_M_CTL);
  278. /*
  279. * UARTs -> done automagically by 8250 driver
  280. */
  281. /*
  282. * CSx timings, GPIO Mux ... setup
  283. */
  284. /* Flash: CS0 timings setup */
  285. omap_writel(0x0000fff3, OMAP730_FLASH_CFG_0);
  286. omap_writel(0x00000088, OMAP730_FLASH_ACFG_0);
  287. /*
  288. * Ethernet support through the debug board
  289. * CS1 timings setup
  290. */
  291. omap_writel(0x0000fff3, OMAP730_FLASH_CFG_1);
  292. omap_writel(0x00000000, OMAP730_FLASH_ACFG_1);
  293. /*
  294. * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
  295. * It is used as the Ethernet controller interrupt
  296. */
  297. omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, OMAP730_IO_CONF_9);
  298. }
  299. MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
  300. /* Maintainer: Brian Swetland <swetland@google.com> */
  301. .phys_io = 0xfff00000,
  302. .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
  303. .boot_params = 0x10000100,
  304. .map_io = omap_fsample_map_io,
  305. .init_irq = omap_fsample_init_irq,
  306. .init_machine = omap_fsample_init,
  307. .timer = &omap_timer,
  308. MACHINE_END