qe.txt 1.8 KB

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  1. * Freescale QUICC Engine module (QE)
  2. This represents qe module that is installed on PowerQUICC II Pro.
  3. NOTE: This is an interim binding; it should be updated to fit
  4. in with the CPM binding later in this document.
  5. Basically, it is a bus of devices, that could act more or less
  6. as a complete entity (UCC, USB etc ). All of them should be siblings on
  7. the "root" qe node, using the common properties from there.
  8. The description below applies to the qe of MPC8360 and
  9. more nodes and properties would be extended in the future.
  10. i) Root QE device
  11. Required properties:
  12. - compatible : should be "fsl,qe";
  13. - model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
  14. - reg : offset and length of the device registers.
  15. - bus-frequency : the clock frequency for QUICC Engine.
  16. - fsl,qe-num-riscs: define how many RISC engines the QE has.
  17. - fsl,qe-num-snums: define how many serial number(SNUM) the QE can use for the
  18. threads.
  19. Recommended properties
  20. - brg-frequency : the internal clock source frequency for baud-rate
  21. generators in Hz.
  22. Example:
  23. qe@e0100000 {
  24. #address-cells = <1>;
  25. #size-cells = <1>;
  26. #interrupt-cells = <2>;
  27. compatible = "fsl,qe";
  28. ranges = <0 e0100000 00100000>;
  29. reg = <e0100000 480>;
  30. brg-frequency = <0>;
  31. bus-frequency = <179A7B00>;
  32. }
  33. * Multi-User RAM (MURAM)
  34. Required properties:
  35. - compatible : should be "fsl,qe-muram", "fsl,cpm-muram".
  36. - mode : the could be "host" or "slave".
  37. - ranges : Should be defined as specified in 1) to describe the
  38. translation of MURAM addresses.
  39. - data-only : sub-node which defines the address area under MURAM
  40. bus that can be allocated as data/parameter
  41. Example:
  42. muram@10000 {
  43. compatible = "fsl,qe-muram", "fsl,cpm-muram";
  44. ranges = <0 00010000 0000c000>;
  45. data-only@0{
  46. compatible = "fsl,qe-muram-data",
  47. "fsl,cpm-muram-data";
  48. reg = <0 c000>;
  49. };
  50. };