da850.dtsi 4.9 KB

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  1. /*
  2. * Copyright 2012 DENX Software Engineering GmbH
  3. * Heiko Schocher <hs@denx.de>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2 of the License, or (at your
  8. * option) any later version.
  9. */
  10. /include/ "skeleton.dtsi"
  11. / {
  12. arm {
  13. #address-cells = <1>;
  14. #size-cells = <1>;
  15. ranges;
  16. intc: interrupt-controller {
  17. compatible = "ti,cp-intc";
  18. interrupt-controller;
  19. #interrupt-cells = <1>;
  20. ti,intc-size = <100>;
  21. reg = <0xfffee000 0x2000>;
  22. };
  23. };
  24. soc {
  25. compatible = "simple-bus";
  26. model = "da850";
  27. #address-cells = <1>;
  28. #size-cells = <1>;
  29. ranges = <0x0 0x01c00000 0x400000>;
  30. interrupt-parent = <&intc>;
  31. pmx_core: pinmux@1c14120 {
  32. compatible = "pinctrl-single";
  33. reg = <0x14120 0x50>;
  34. #address-cells = <1>;
  35. #size-cells = <0>;
  36. pinctrl-single,bit-per-mux;
  37. pinctrl-single,register-width = <32>;
  38. pinctrl-single,function-mask = <0xffffffff>;
  39. status = "disabled";
  40. nand_cs3_pins: pinmux_nand_pins {
  41. pinctrl-single,bits = <
  42. /* EMA_OE, EMA_WE */
  43. 0x1c 0x00110000 0x00ff0000
  44. /* EMA_CS[4],EMA_CS[3]*/
  45. 0x1c 0x00000110 0x00000ff0
  46. /*
  47. * EMA_D[0], EMA_D[1], EMA_D[2],
  48. * EMA_D[3], EMA_D[4], EMA_D[5],
  49. * EMA_D[6], EMA_D[7]
  50. */
  51. 0x24 0x11111111 0xffffffff
  52. /* EMA_A[1], EMA_A[2] */
  53. 0x30 0x01100000 0x0ff00000
  54. >;
  55. };
  56. i2c0_pins: pinmux_i2c0_pins {
  57. pinctrl-single,bits = <
  58. /* I2C0_SDA,I2C0_SCL */
  59. 0x10 0x00002200 0x0000ff00
  60. >;
  61. };
  62. mmc0_pins: pinmux_mmc_pins {
  63. pinctrl-single,bits = <
  64. /* MMCSD0_DAT[3] MMCSD0_DAT[2]
  65. * MMCSD0_DAT[1] MMCSD0_DAT[0]
  66. * MMCSD0_CMD MMCSD0_CLK
  67. */
  68. 0x28 0x00222222 0x00ffffff
  69. >;
  70. };
  71. ehrpwm0a_pins: pinmux_ehrpwm0a_pins {
  72. pinctrl-single,bits = <
  73. /* EPWM0A */
  74. 0xc 0x00000002 0x0000000f
  75. >;
  76. };
  77. ehrpwm0b_pins: pinmux_ehrpwm0b_pins {
  78. pinctrl-single,bits = <
  79. /* EPWM0B */
  80. 0xc 0x00000020 0x000000f0
  81. >;
  82. };
  83. ehrpwm1a_pins: pinmux_ehrpwm1a_pins {
  84. pinctrl-single,bits = <
  85. /* EPWM1A */
  86. 0x14 0x00000002 0x0000000f
  87. >;
  88. };
  89. ehrpwm1b_pins: pinmux_ehrpwm1b_pins {
  90. pinctrl-single,bits = <
  91. /* EPWM1B */
  92. 0x14 0x00000020 0x000000f0
  93. >;
  94. };
  95. ecap0_pins: pinmux_ecap0_pins {
  96. pinctrl-single,bits = <
  97. /* ECAP0_APWM0 */
  98. 0x8 0x20000000 0xf0000000
  99. >;
  100. };
  101. ecap1_pins: pinmux_ecap1_pins {
  102. pinctrl-single,bits = <
  103. /* ECAP1_APWM1 */
  104. 0x4 0x40000000 0xf0000000
  105. >;
  106. };
  107. ecap2_pins: pinmux_ecap2_pins {
  108. pinctrl-single,bits = <
  109. /* ECAP2_APWM2 */
  110. 0x4 0x00000004 0x0000000f
  111. >;
  112. };
  113. };
  114. serial0: serial@1c42000 {
  115. compatible = "ns16550a";
  116. reg = <0x42000 0x100>;
  117. clock-frequency = <150000000>;
  118. reg-shift = <2>;
  119. interrupts = <25>;
  120. status = "disabled";
  121. };
  122. serial1: serial@1d0c000 {
  123. compatible = "ns16550a";
  124. reg = <0x10c000 0x100>;
  125. clock-frequency = <150000000>;
  126. reg-shift = <2>;
  127. interrupts = <53>;
  128. status = "disabled";
  129. };
  130. serial2: serial@1d0d000 {
  131. compatible = "ns16550a";
  132. reg = <0x10d000 0x100>;
  133. clock-frequency = <150000000>;
  134. reg-shift = <2>;
  135. interrupts = <61>;
  136. status = "disabled";
  137. };
  138. rtc0: rtc@1c23000 {
  139. compatible = "ti,da830-rtc";
  140. reg = <0x23000 0x1000>;
  141. interrupts = <19
  142. 19>;
  143. status = "disabled";
  144. };
  145. i2c0: i2c@1c22000 {
  146. compatible = "ti,davinci-i2c";
  147. reg = <0x22000 0x1000>;
  148. interrupts = <15>;
  149. #address-cells = <1>;
  150. #size-cells = <0>;
  151. status = "disabled";
  152. };
  153. wdt: wdt@1c21000 {
  154. compatible = "ti,davinci-wdt";
  155. reg = <0x21000 0x1000>;
  156. status = "disabled";
  157. };
  158. mmc0: mmc@1c40000 {
  159. compatible = "ti,da830-mmc";
  160. reg = <0x40000 0x1000>;
  161. interrupts = <16>;
  162. status = "disabled";
  163. };
  164. ehrpwm0: ehrpwm@01f00000 {
  165. compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
  166. #pwm-cells = <3>;
  167. reg = <0x300000 0x2000>;
  168. status = "disabled";
  169. };
  170. ehrpwm1: ehrpwm@01f02000 {
  171. compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
  172. #pwm-cells = <3>;
  173. reg = <0x302000 0x2000>;
  174. status = "disabled";
  175. };
  176. ecap0: ecap@01f06000 {
  177. compatible = "ti,da850-ecap", "ti,am33xx-ecap";
  178. #pwm-cells = <3>;
  179. reg = <0x306000 0x80>;
  180. status = "disabled";
  181. };
  182. ecap1: ecap@01f07000 {
  183. compatible = "ti,da850-ecap", "ti,am33xx-ecap";
  184. #pwm-cells = <3>;
  185. reg = <0x307000 0x80>;
  186. status = "disabled";
  187. };
  188. ecap2: ecap@01f08000 {
  189. compatible = "ti,da850-ecap", "ti,am33xx-ecap";
  190. #pwm-cells = <3>;
  191. reg = <0x308000 0x80>;
  192. status = "disabled";
  193. };
  194. };
  195. nand_cs3@62000000 {
  196. compatible = "ti,davinci-nand";
  197. reg = <0x62000000 0x807ff
  198. 0x68000000 0x8000>;
  199. ti,davinci-chipselect = <1>;
  200. ti,davinci-mask-ale = <0>;
  201. ti,davinci-mask-cle = <0>;
  202. ti,davinci-mask-chipsel = <0>;
  203. ti,davinci-ecc-mode = "hw";
  204. ti,davinci-ecc-bits = <4>;
  205. ti,davinci-nand-use-bbt;
  206. status = "disabled";
  207. };
  208. };