omap_hsmmc.c 59 KB

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  1. /*
  2. * drivers/mmc/host/omap_hsmmc.c
  3. *
  4. * Driver for OMAP2430/3430 MMC controller.
  5. *
  6. * Copyright (C) 2007 Texas Instruments.
  7. *
  8. * Authors:
  9. * Syed Mohammed Khasim <x0khasim@ti.com>
  10. * Madhusudhan <madhu.cr@ti.com>
  11. * Mohit Jalori <mjalori@ti.com>
  12. *
  13. * This file is licensed under the terms of the GNU General Public License
  14. * version 2. This program is licensed "as is" without any warranty of any
  15. * kind, whether express or implied.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/init.h>
  19. #include <linux/debugfs.h>
  20. #include <linux/seq_file.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/delay.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/workqueue.h>
  26. #include <linux/timer.h>
  27. #include <linux/clk.h>
  28. #include <linux/mmc/host.h>
  29. #include <linux/mmc/core.h>
  30. #include <linux/mmc/mmc.h>
  31. #include <linux/io.h>
  32. #include <linux/semaphore.h>
  33. #include <linux/gpio.h>
  34. #include <linux/regulator/consumer.h>
  35. #include <plat/dma.h>
  36. #include <mach/hardware.h>
  37. #include <plat/board.h>
  38. #include <plat/mmc.h>
  39. #include <plat/cpu.h>
  40. /* OMAP HSMMC Host Controller Registers */
  41. #define OMAP_HSMMC_SYSCONFIG 0x0010
  42. #define OMAP_HSMMC_SYSSTATUS 0x0014
  43. #define OMAP_HSMMC_CON 0x002C
  44. #define OMAP_HSMMC_BLK 0x0104
  45. #define OMAP_HSMMC_ARG 0x0108
  46. #define OMAP_HSMMC_CMD 0x010C
  47. #define OMAP_HSMMC_RSP10 0x0110
  48. #define OMAP_HSMMC_RSP32 0x0114
  49. #define OMAP_HSMMC_RSP54 0x0118
  50. #define OMAP_HSMMC_RSP76 0x011C
  51. #define OMAP_HSMMC_DATA 0x0120
  52. #define OMAP_HSMMC_HCTL 0x0128
  53. #define OMAP_HSMMC_SYSCTL 0x012C
  54. #define OMAP_HSMMC_STAT 0x0130
  55. #define OMAP_HSMMC_IE 0x0134
  56. #define OMAP_HSMMC_ISE 0x0138
  57. #define OMAP_HSMMC_CAPA 0x0140
  58. #define VS18 (1 << 26)
  59. #define VS30 (1 << 25)
  60. #define SDVS18 (0x5 << 9)
  61. #define SDVS30 (0x6 << 9)
  62. #define SDVS33 (0x7 << 9)
  63. #define SDVS_MASK 0x00000E00
  64. #define SDVSCLR 0xFFFFF1FF
  65. #define SDVSDET 0x00000400
  66. #define AUTOIDLE 0x1
  67. #define SDBP (1 << 8)
  68. #define DTO 0xe
  69. #define ICE 0x1
  70. #define ICS 0x2
  71. #define CEN (1 << 2)
  72. #define CLKD_MASK 0x0000FFC0
  73. #define CLKD_SHIFT 6
  74. #define DTO_MASK 0x000F0000
  75. #define DTO_SHIFT 16
  76. #define INT_EN_MASK 0x307F0033
  77. #define BWR_ENABLE (1 << 4)
  78. #define BRR_ENABLE (1 << 5)
  79. #define DTO_ENABLE (1 << 20)
  80. #define INIT_STREAM (1 << 1)
  81. #define DP_SELECT (1 << 21)
  82. #define DDIR (1 << 4)
  83. #define DMA_EN 0x1
  84. #define MSBS (1 << 5)
  85. #define BCE (1 << 1)
  86. #define FOUR_BIT (1 << 1)
  87. #define DW8 (1 << 5)
  88. #define CC 0x1
  89. #define TC 0x02
  90. #define OD 0x1
  91. #define ERR (1 << 15)
  92. #define CMD_TIMEOUT (1 << 16)
  93. #define DATA_TIMEOUT (1 << 20)
  94. #define CMD_CRC (1 << 17)
  95. #define DATA_CRC (1 << 21)
  96. #define CARD_ERR (1 << 28)
  97. #define STAT_CLEAR 0xFFFFFFFF
  98. #define INIT_STREAM_CMD 0x00000000
  99. #define DUAL_VOLT_OCR_BIT 7
  100. #define SRC (1 << 25)
  101. #define SRD (1 << 26)
  102. #define SOFTRESET (1 << 1)
  103. #define RESETDONE (1 << 0)
  104. /*
  105. * FIXME: Most likely all the data using these _DEVID defines should come
  106. * from the platform_data, or implemented in controller and slot specific
  107. * functions.
  108. */
  109. #define OMAP_MMC1_DEVID 0
  110. #define OMAP_MMC2_DEVID 1
  111. #define OMAP_MMC3_DEVID 2
  112. #define OMAP_MMC4_DEVID 3
  113. #define OMAP_MMC5_DEVID 4
  114. #define MMC_TIMEOUT_MS 20
  115. #define OMAP_MMC_MASTER_CLOCK 96000000
  116. #define DRIVER_NAME "mmci-omap-hs"
  117. /* Timeouts for entering power saving states on inactivity, msec */
  118. #define OMAP_MMC_DISABLED_TIMEOUT 100
  119. #define OMAP_MMC_SLEEP_TIMEOUT 1000
  120. #define OMAP_MMC_OFF_TIMEOUT 8000
  121. /*
  122. * One controller can have multiple slots, like on some omap boards using
  123. * omap.c controller driver. Luckily this is not currently done on any known
  124. * omap_hsmmc.c device.
  125. */
  126. #define mmc_slot(host) (host->pdata->slots[host->slot_id])
  127. /*
  128. * MMC Host controller read/write API's
  129. */
  130. #define OMAP_HSMMC_READ(base, reg) \
  131. __raw_readl((base) + OMAP_HSMMC_##reg)
  132. #define OMAP_HSMMC_WRITE(base, reg, val) \
  133. __raw_writel((val), (base) + OMAP_HSMMC_##reg)
  134. struct omap_hsmmc_host {
  135. struct device *dev;
  136. struct mmc_host *mmc;
  137. struct mmc_request *mrq;
  138. struct mmc_command *cmd;
  139. struct mmc_data *data;
  140. struct clk *fclk;
  141. struct clk *iclk;
  142. struct clk *dbclk;
  143. /*
  144. * vcc == configured supply
  145. * vcc_aux == optional
  146. * - MMC1, supply for DAT4..DAT7
  147. * - MMC2/MMC2, external level shifter voltage supply, for
  148. * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
  149. */
  150. struct regulator *vcc;
  151. struct regulator *vcc_aux;
  152. struct work_struct mmc_carddetect_work;
  153. void __iomem *base;
  154. resource_size_t mapbase;
  155. spinlock_t irq_lock; /* Prevent races with irq handler */
  156. unsigned int id;
  157. unsigned int dma_len;
  158. unsigned int dma_sg_idx;
  159. unsigned char bus_mode;
  160. unsigned char power_mode;
  161. u32 *buffer;
  162. u32 bytesleft;
  163. int suspended;
  164. int irq;
  165. int use_dma, dma_ch;
  166. int dma_line_tx, dma_line_rx;
  167. int slot_id;
  168. int got_dbclk;
  169. int response_busy;
  170. int context_loss;
  171. int dpm_state;
  172. int vdd;
  173. int protect_card;
  174. int reqs_blocked;
  175. int use_reg;
  176. int req_in_progress;
  177. struct omap_mmc_platform_data *pdata;
  178. };
  179. static int omap_hsmmc_card_detect(struct device *dev, int slot)
  180. {
  181. struct omap_mmc_platform_data *mmc = dev->platform_data;
  182. /* NOTE: assumes card detect signal is active-low */
  183. return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
  184. }
  185. static int omap_hsmmc_get_wp(struct device *dev, int slot)
  186. {
  187. struct omap_mmc_platform_data *mmc = dev->platform_data;
  188. /* NOTE: assumes write protect signal is active-high */
  189. return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
  190. }
  191. static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
  192. {
  193. struct omap_mmc_platform_data *mmc = dev->platform_data;
  194. /* NOTE: assumes card detect signal is active-low */
  195. return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
  196. }
  197. #ifdef CONFIG_PM
  198. static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
  199. {
  200. struct omap_mmc_platform_data *mmc = dev->platform_data;
  201. disable_irq(mmc->slots[0].card_detect_irq);
  202. return 0;
  203. }
  204. static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
  205. {
  206. struct omap_mmc_platform_data *mmc = dev->platform_data;
  207. enable_irq(mmc->slots[0].card_detect_irq);
  208. return 0;
  209. }
  210. #else
  211. #define omap_hsmmc_suspend_cdirq NULL
  212. #define omap_hsmmc_resume_cdirq NULL
  213. #endif
  214. #ifdef CONFIG_REGULATOR
  215. static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
  216. int vdd)
  217. {
  218. struct omap_hsmmc_host *host =
  219. platform_get_drvdata(to_platform_device(dev));
  220. int ret;
  221. if (mmc_slot(host).before_set_reg)
  222. mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
  223. if (power_on)
  224. ret = mmc_regulator_set_ocr(host->vcc, vdd);
  225. else
  226. ret = mmc_regulator_set_ocr(host->vcc, 0);
  227. if (mmc_slot(host).after_set_reg)
  228. mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
  229. return ret;
  230. }
  231. static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on,
  232. int vdd)
  233. {
  234. struct omap_hsmmc_host *host =
  235. platform_get_drvdata(to_platform_device(dev));
  236. int ret = 0;
  237. /*
  238. * If we don't see a Vcc regulator, assume it's a fixed
  239. * voltage always-on regulator.
  240. */
  241. if (!host->vcc)
  242. return 0;
  243. if (mmc_slot(host).before_set_reg)
  244. mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
  245. /*
  246. * Assume Vcc regulator is used only to power the card ... OMAP
  247. * VDDS is used to power the pins, optionally with a transceiver to
  248. * support cards using voltages other than VDDS (1.8V nominal). When a
  249. * transceiver is used, DAT3..7 are muxed as transceiver control pins.
  250. *
  251. * In some cases this regulator won't support enable/disable;
  252. * e.g. it's a fixed rail for a WLAN chip.
  253. *
  254. * In other cases vcc_aux switches interface power. Example, for
  255. * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
  256. * chips/cards need an interface voltage rail too.
  257. */
  258. if (power_on) {
  259. ret = mmc_regulator_set_ocr(host->vcc, vdd);
  260. /* Enable interface voltage rail, if needed */
  261. if (ret == 0 && host->vcc_aux) {
  262. ret = regulator_enable(host->vcc_aux);
  263. if (ret < 0)
  264. ret = mmc_regulator_set_ocr(host->vcc, 0);
  265. }
  266. } else {
  267. if (host->vcc_aux)
  268. ret = regulator_disable(host->vcc_aux);
  269. if (ret == 0)
  270. ret = mmc_regulator_set_ocr(host->vcc, 0);
  271. }
  272. if (mmc_slot(host).after_set_reg)
  273. mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
  274. return ret;
  275. }
  276. static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
  277. int vdd, int cardsleep)
  278. {
  279. struct omap_hsmmc_host *host =
  280. platform_get_drvdata(to_platform_device(dev));
  281. int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
  282. return regulator_set_mode(host->vcc, mode);
  283. }
  284. static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep,
  285. int vdd, int cardsleep)
  286. {
  287. struct omap_hsmmc_host *host =
  288. platform_get_drvdata(to_platform_device(dev));
  289. int err, mode;
  290. /*
  291. * If we don't see a Vcc regulator, assume it's a fixed
  292. * voltage always-on regulator.
  293. */
  294. if (!host->vcc)
  295. return 0;
  296. mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
  297. if (!host->vcc_aux)
  298. return regulator_set_mode(host->vcc, mode);
  299. if (cardsleep) {
  300. /* VCC can be turned off if card is asleep */
  301. if (sleep)
  302. err = mmc_regulator_set_ocr(host->vcc, 0);
  303. else
  304. err = mmc_regulator_set_ocr(host->vcc, vdd);
  305. } else
  306. err = regulator_set_mode(host->vcc, mode);
  307. if (err)
  308. return err;
  309. if (!mmc_slot(host).vcc_aux_disable_is_sleep)
  310. return regulator_set_mode(host->vcc_aux, mode);
  311. if (sleep)
  312. return regulator_disable(host->vcc_aux);
  313. else
  314. return regulator_enable(host->vcc_aux);
  315. }
  316. static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
  317. {
  318. struct regulator *reg;
  319. int ret = 0;
  320. int ocr_value = 0;
  321. switch (host->id) {
  322. case OMAP_MMC1_DEVID:
  323. /* On-chip level shifting via PBIAS0/PBIAS1 */
  324. mmc_slot(host).set_power = omap_hsmmc_1_set_power;
  325. mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
  326. break;
  327. case OMAP_MMC2_DEVID:
  328. case OMAP_MMC3_DEVID:
  329. /* Off-chip level shifting, or none */
  330. mmc_slot(host).set_power = omap_hsmmc_23_set_power;
  331. mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep;
  332. break;
  333. default:
  334. pr_err("MMC%d configuration not supported!\n", host->id);
  335. return -EINVAL;
  336. }
  337. reg = regulator_get(host->dev, "vmmc");
  338. if (IS_ERR(reg)) {
  339. dev_dbg(host->dev, "vmmc regulator missing\n");
  340. /*
  341. * HACK: until fixed.c regulator is usable,
  342. * we don't require a main regulator
  343. * for MMC2 or MMC3
  344. */
  345. if (host->id == OMAP_MMC1_DEVID) {
  346. ret = PTR_ERR(reg);
  347. goto err;
  348. }
  349. } else {
  350. host->vcc = reg;
  351. ocr_value = mmc_regulator_get_ocrmask(reg);
  352. if (!mmc_slot(host).ocr_mask) {
  353. mmc_slot(host).ocr_mask = ocr_value;
  354. } else {
  355. if (!(mmc_slot(host).ocr_mask & ocr_value)) {
  356. pr_err("MMC%d ocrmask %x is not supported\n",
  357. host->id, mmc_slot(host).ocr_mask);
  358. mmc_slot(host).ocr_mask = 0;
  359. return -EINVAL;
  360. }
  361. }
  362. mmc_slot(host).ocr_mask = mmc_regulator_get_ocrmask(reg);
  363. /* Allow an aux regulator */
  364. reg = regulator_get(host->dev, "vmmc_aux");
  365. host->vcc_aux = IS_ERR(reg) ? NULL : reg;
  366. /*
  367. * UGLY HACK: workaround regulator framework bugs.
  368. * When the bootloader leaves a supply active, it's
  369. * initialized with zero usecount ... and we can't
  370. * disable it without first enabling it. Until the
  371. * framework is fixed, we need a workaround like this
  372. * (which is safe for MMC, but not in general).
  373. */
  374. if (regulator_is_enabled(host->vcc) > 0) {
  375. regulator_enable(host->vcc);
  376. regulator_disable(host->vcc);
  377. }
  378. if (host->vcc_aux) {
  379. if (regulator_is_enabled(reg) > 0) {
  380. regulator_enable(reg);
  381. regulator_disable(reg);
  382. }
  383. }
  384. }
  385. return 0;
  386. err:
  387. mmc_slot(host).set_power = NULL;
  388. mmc_slot(host).set_sleep = NULL;
  389. return ret;
  390. }
  391. static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
  392. {
  393. regulator_put(host->vcc);
  394. regulator_put(host->vcc_aux);
  395. mmc_slot(host).set_power = NULL;
  396. mmc_slot(host).set_sleep = NULL;
  397. }
  398. static inline int omap_hsmmc_have_reg(void)
  399. {
  400. return 1;
  401. }
  402. #else
  403. static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
  404. {
  405. return -EINVAL;
  406. }
  407. static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
  408. {
  409. }
  410. static inline int omap_hsmmc_have_reg(void)
  411. {
  412. return 0;
  413. }
  414. #endif
  415. static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
  416. {
  417. int ret;
  418. if (gpio_is_valid(pdata->slots[0].switch_pin)) {
  419. pdata->suspend = omap_hsmmc_suspend_cdirq;
  420. pdata->resume = omap_hsmmc_resume_cdirq;
  421. if (pdata->slots[0].cover)
  422. pdata->slots[0].get_cover_state =
  423. omap_hsmmc_get_cover_state;
  424. else
  425. pdata->slots[0].card_detect = omap_hsmmc_card_detect;
  426. pdata->slots[0].card_detect_irq =
  427. gpio_to_irq(pdata->slots[0].switch_pin);
  428. ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
  429. if (ret)
  430. return ret;
  431. ret = gpio_direction_input(pdata->slots[0].switch_pin);
  432. if (ret)
  433. goto err_free_sp;
  434. } else
  435. pdata->slots[0].switch_pin = -EINVAL;
  436. if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
  437. pdata->slots[0].get_ro = omap_hsmmc_get_wp;
  438. ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
  439. if (ret)
  440. goto err_free_cd;
  441. ret = gpio_direction_input(pdata->slots[0].gpio_wp);
  442. if (ret)
  443. goto err_free_wp;
  444. } else
  445. pdata->slots[0].gpio_wp = -EINVAL;
  446. return 0;
  447. err_free_wp:
  448. gpio_free(pdata->slots[0].gpio_wp);
  449. err_free_cd:
  450. if (gpio_is_valid(pdata->slots[0].switch_pin))
  451. err_free_sp:
  452. gpio_free(pdata->slots[0].switch_pin);
  453. return ret;
  454. }
  455. static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
  456. {
  457. if (gpio_is_valid(pdata->slots[0].gpio_wp))
  458. gpio_free(pdata->slots[0].gpio_wp);
  459. if (gpio_is_valid(pdata->slots[0].switch_pin))
  460. gpio_free(pdata->slots[0].switch_pin);
  461. }
  462. /*
  463. * Stop clock to the card
  464. */
  465. static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
  466. {
  467. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  468. OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
  469. if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
  470. dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
  471. }
  472. static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
  473. struct mmc_command *cmd)
  474. {
  475. unsigned int irq_mask;
  476. if (host->use_dma)
  477. irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
  478. else
  479. irq_mask = INT_EN_MASK;
  480. /* Disable timeout for erases */
  481. if (cmd->opcode == MMC_ERASE)
  482. irq_mask &= ~DTO_ENABLE;
  483. OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
  484. OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
  485. OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
  486. }
  487. static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
  488. {
  489. OMAP_HSMMC_WRITE(host->base, ISE, 0);
  490. OMAP_HSMMC_WRITE(host->base, IE, 0);
  491. OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
  492. }
  493. #ifdef CONFIG_PM
  494. /*
  495. * Restore the MMC host context, if it was lost as result of a
  496. * power state change.
  497. */
  498. static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
  499. {
  500. struct mmc_ios *ios = &host->mmc->ios;
  501. struct omap_mmc_platform_data *pdata = host->pdata;
  502. int context_loss = 0;
  503. u32 hctl, capa, con;
  504. u16 dsor = 0;
  505. unsigned long timeout;
  506. if (pdata->get_context_loss_count) {
  507. context_loss = pdata->get_context_loss_count(host->dev);
  508. if (context_loss < 0)
  509. return 1;
  510. }
  511. dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
  512. context_loss == host->context_loss ? "not " : "");
  513. if (host->context_loss == context_loss)
  514. return 1;
  515. /* Wait for hardware reset */
  516. timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
  517. while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
  518. && time_before(jiffies, timeout))
  519. ;
  520. /* Do software reset */
  521. OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
  522. timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
  523. while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
  524. && time_before(jiffies, timeout))
  525. ;
  526. OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
  527. OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
  528. if (host->id == OMAP_MMC1_DEVID) {
  529. if (host->power_mode != MMC_POWER_OFF &&
  530. (1 << ios->vdd) <= MMC_VDD_23_24)
  531. hctl = SDVS18;
  532. else
  533. hctl = SDVS30;
  534. capa = VS30 | VS18;
  535. } else {
  536. hctl = SDVS18;
  537. capa = VS18;
  538. }
  539. OMAP_HSMMC_WRITE(host->base, HCTL,
  540. OMAP_HSMMC_READ(host->base, HCTL) | hctl);
  541. OMAP_HSMMC_WRITE(host->base, CAPA,
  542. OMAP_HSMMC_READ(host->base, CAPA) | capa);
  543. OMAP_HSMMC_WRITE(host->base, HCTL,
  544. OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
  545. timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
  546. while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
  547. && time_before(jiffies, timeout))
  548. ;
  549. omap_hsmmc_disable_irq(host);
  550. /* Do not initialize card-specific things if the power is off */
  551. if (host->power_mode == MMC_POWER_OFF)
  552. goto out;
  553. con = OMAP_HSMMC_READ(host->base, CON);
  554. switch (ios->bus_width) {
  555. case MMC_BUS_WIDTH_8:
  556. OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
  557. break;
  558. case MMC_BUS_WIDTH_4:
  559. OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
  560. OMAP_HSMMC_WRITE(host->base, HCTL,
  561. OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
  562. break;
  563. case MMC_BUS_WIDTH_1:
  564. OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
  565. OMAP_HSMMC_WRITE(host->base, HCTL,
  566. OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
  567. break;
  568. }
  569. if (ios->clock) {
  570. dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
  571. if (dsor < 1)
  572. dsor = 1;
  573. if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
  574. dsor++;
  575. if (dsor > 250)
  576. dsor = 250;
  577. }
  578. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  579. OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
  580. OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
  581. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  582. OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
  583. timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
  584. while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
  585. && time_before(jiffies, timeout))
  586. ;
  587. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  588. OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
  589. con = OMAP_HSMMC_READ(host->base, CON);
  590. if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
  591. OMAP_HSMMC_WRITE(host->base, CON, con | OD);
  592. else
  593. OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
  594. out:
  595. host->context_loss = context_loss;
  596. dev_dbg(mmc_dev(host->mmc), "context is restored\n");
  597. return 0;
  598. }
  599. /*
  600. * Save the MMC host context (store the number of power state changes so far).
  601. */
  602. static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
  603. {
  604. struct omap_mmc_platform_data *pdata = host->pdata;
  605. int context_loss;
  606. if (pdata->get_context_loss_count) {
  607. context_loss = pdata->get_context_loss_count(host->dev);
  608. if (context_loss < 0)
  609. return;
  610. host->context_loss = context_loss;
  611. }
  612. }
  613. #else
  614. static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
  615. {
  616. return 0;
  617. }
  618. static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
  619. {
  620. }
  621. #endif
  622. /*
  623. * Send init stream sequence to card
  624. * before sending IDLE command
  625. */
  626. static void send_init_stream(struct omap_hsmmc_host *host)
  627. {
  628. int reg = 0;
  629. unsigned long timeout;
  630. if (host->protect_card)
  631. return;
  632. disable_irq(host->irq);
  633. OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
  634. OMAP_HSMMC_WRITE(host->base, CON,
  635. OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
  636. OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
  637. timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
  638. while ((reg != CC) && time_before(jiffies, timeout))
  639. reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
  640. OMAP_HSMMC_WRITE(host->base, CON,
  641. OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
  642. OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
  643. OMAP_HSMMC_READ(host->base, STAT);
  644. enable_irq(host->irq);
  645. }
  646. static inline
  647. int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
  648. {
  649. int r = 1;
  650. if (mmc_slot(host).get_cover_state)
  651. r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
  652. return r;
  653. }
  654. static ssize_t
  655. omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
  656. char *buf)
  657. {
  658. struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
  659. struct omap_hsmmc_host *host = mmc_priv(mmc);
  660. return sprintf(buf, "%s\n",
  661. omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
  662. }
  663. static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
  664. static ssize_t
  665. omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
  666. char *buf)
  667. {
  668. struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
  669. struct omap_hsmmc_host *host = mmc_priv(mmc);
  670. return sprintf(buf, "%s\n", mmc_slot(host).name);
  671. }
  672. static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
  673. /*
  674. * Configure the response type and send the cmd.
  675. */
  676. static void
  677. omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
  678. struct mmc_data *data)
  679. {
  680. int cmdreg = 0, resptype = 0, cmdtype = 0;
  681. dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
  682. mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
  683. host->cmd = cmd;
  684. omap_hsmmc_enable_irq(host, cmd);
  685. host->response_busy = 0;
  686. if (cmd->flags & MMC_RSP_PRESENT) {
  687. if (cmd->flags & MMC_RSP_136)
  688. resptype = 1;
  689. else if (cmd->flags & MMC_RSP_BUSY) {
  690. resptype = 3;
  691. host->response_busy = 1;
  692. } else
  693. resptype = 2;
  694. }
  695. /*
  696. * Unlike OMAP1 controller, the cmdtype does not seem to be based on
  697. * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
  698. * a val of 0x3, rest 0x0.
  699. */
  700. if (cmd == host->mrq->stop)
  701. cmdtype = 0x3;
  702. cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
  703. if (data) {
  704. cmdreg |= DP_SELECT | MSBS | BCE;
  705. if (data->flags & MMC_DATA_READ)
  706. cmdreg |= DDIR;
  707. else
  708. cmdreg &= ~(DDIR);
  709. }
  710. if (host->use_dma)
  711. cmdreg |= DMA_EN;
  712. host->req_in_progress = 1;
  713. OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
  714. OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
  715. }
  716. static int
  717. omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
  718. {
  719. if (data->flags & MMC_DATA_WRITE)
  720. return DMA_TO_DEVICE;
  721. else
  722. return DMA_FROM_DEVICE;
  723. }
  724. static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
  725. {
  726. int dma_ch;
  727. spin_lock(&host->irq_lock);
  728. host->req_in_progress = 0;
  729. dma_ch = host->dma_ch;
  730. spin_unlock(&host->irq_lock);
  731. omap_hsmmc_disable_irq(host);
  732. /* Do not complete the request if DMA is still in progress */
  733. if (mrq->data && host->use_dma && dma_ch != -1)
  734. return;
  735. host->mrq = NULL;
  736. mmc_request_done(host->mmc, mrq);
  737. }
  738. /*
  739. * Notify the transfer complete to MMC core
  740. */
  741. static void
  742. omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
  743. {
  744. if (!data) {
  745. struct mmc_request *mrq = host->mrq;
  746. /* TC before CC from CMD6 - don't know why, but it happens */
  747. if (host->cmd && host->cmd->opcode == 6 &&
  748. host->response_busy) {
  749. host->response_busy = 0;
  750. return;
  751. }
  752. omap_hsmmc_request_done(host, mrq);
  753. return;
  754. }
  755. host->data = NULL;
  756. if (!data->error)
  757. data->bytes_xfered += data->blocks * (data->blksz);
  758. else
  759. data->bytes_xfered = 0;
  760. if (!data->stop) {
  761. omap_hsmmc_request_done(host, data->mrq);
  762. return;
  763. }
  764. omap_hsmmc_start_command(host, data->stop, NULL);
  765. }
  766. /*
  767. * Notify the core about command completion
  768. */
  769. static void
  770. omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
  771. {
  772. host->cmd = NULL;
  773. if (cmd->flags & MMC_RSP_PRESENT) {
  774. if (cmd->flags & MMC_RSP_136) {
  775. /* response type 2 */
  776. cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
  777. cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
  778. cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
  779. cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
  780. } else {
  781. /* response types 1, 1b, 3, 4, 5, 6 */
  782. cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
  783. }
  784. }
  785. if ((host->data == NULL && !host->response_busy) || cmd->error)
  786. omap_hsmmc_request_done(host, cmd->mrq);
  787. }
  788. /*
  789. * DMA clean up for command errors
  790. */
  791. static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
  792. {
  793. int dma_ch;
  794. host->data->error = errno;
  795. spin_lock(&host->irq_lock);
  796. dma_ch = host->dma_ch;
  797. host->dma_ch = -1;
  798. spin_unlock(&host->irq_lock);
  799. if (host->use_dma && dma_ch != -1) {
  800. dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
  801. omap_hsmmc_get_dma_dir(host, host->data));
  802. omap_free_dma(dma_ch);
  803. }
  804. host->data = NULL;
  805. }
  806. /*
  807. * Readable error output
  808. */
  809. #ifdef CONFIG_MMC_DEBUG
  810. static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status)
  811. {
  812. /* --- means reserved bit without definition at documentation */
  813. static const char *omap_hsmmc_status_bits[] = {
  814. "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
  815. "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
  816. "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
  817. "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
  818. };
  819. char res[256];
  820. char *buf = res;
  821. int len, i;
  822. len = sprintf(buf, "MMC IRQ 0x%x :", status);
  823. buf += len;
  824. for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
  825. if (status & (1 << i)) {
  826. len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
  827. buf += len;
  828. }
  829. dev_dbg(mmc_dev(host->mmc), "%s\n", res);
  830. }
  831. #endif /* CONFIG_MMC_DEBUG */
  832. /*
  833. * MMC controller internal state machines reset
  834. *
  835. * Used to reset command or data internal state machines, using respectively
  836. * SRC or SRD bit of SYSCTL register
  837. * Can be called from interrupt context
  838. */
  839. static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
  840. unsigned long bit)
  841. {
  842. unsigned long i = 0;
  843. unsigned long limit = (loops_per_jiffy *
  844. msecs_to_jiffies(MMC_TIMEOUT_MS));
  845. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  846. OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
  847. /*
  848. * OMAP4 ES2 and greater has an updated reset logic.
  849. * Monitor a 0->1 transition first
  850. */
  851. if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
  852. while ((!(OMAP_HSMMC_READ(host, SYSCTL) & bit))
  853. && (i++ < limit))
  854. cpu_relax();
  855. }
  856. i = 0;
  857. while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
  858. (i++ < limit))
  859. cpu_relax();
  860. if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
  861. dev_err(mmc_dev(host->mmc),
  862. "Timeout waiting on controller reset in %s\n",
  863. __func__);
  864. }
  865. static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
  866. {
  867. struct mmc_data *data;
  868. int end_cmd = 0, end_trans = 0;
  869. if (!host->req_in_progress) {
  870. do {
  871. OMAP_HSMMC_WRITE(host->base, STAT, status);
  872. /* Flush posted write */
  873. status = OMAP_HSMMC_READ(host->base, STAT);
  874. } while (status & INT_EN_MASK);
  875. return;
  876. }
  877. data = host->data;
  878. dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
  879. if (status & ERR) {
  880. #ifdef CONFIG_MMC_DEBUG
  881. omap_hsmmc_report_irq(host, status);
  882. #endif
  883. if ((status & CMD_TIMEOUT) ||
  884. (status & CMD_CRC)) {
  885. if (host->cmd) {
  886. if (status & CMD_TIMEOUT) {
  887. omap_hsmmc_reset_controller_fsm(host,
  888. SRC);
  889. host->cmd->error = -ETIMEDOUT;
  890. } else {
  891. host->cmd->error = -EILSEQ;
  892. }
  893. end_cmd = 1;
  894. }
  895. if (host->data || host->response_busy) {
  896. if (host->data)
  897. omap_hsmmc_dma_cleanup(host,
  898. -ETIMEDOUT);
  899. host->response_busy = 0;
  900. omap_hsmmc_reset_controller_fsm(host, SRD);
  901. }
  902. }
  903. if ((status & DATA_TIMEOUT) ||
  904. (status & DATA_CRC)) {
  905. if (host->data || host->response_busy) {
  906. int err = (status & DATA_TIMEOUT) ?
  907. -ETIMEDOUT : -EILSEQ;
  908. if (host->data)
  909. omap_hsmmc_dma_cleanup(host, err);
  910. else
  911. host->mrq->cmd->error = err;
  912. host->response_busy = 0;
  913. omap_hsmmc_reset_controller_fsm(host, SRD);
  914. end_trans = 1;
  915. }
  916. }
  917. if (status & CARD_ERR) {
  918. dev_dbg(mmc_dev(host->mmc),
  919. "Ignoring card err CMD%d\n", host->cmd->opcode);
  920. if (host->cmd)
  921. end_cmd = 1;
  922. if (host->data)
  923. end_trans = 1;
  924. }
  925. }
  926. OMAP_HSMMC_WRITE(host->base, STAT, status);
  927. if (end_cmd || ((status & CC) && host->cmd))
  928. omap_hsmmc_cmd_done(host, host->cmd);
  929. if ((end_trans || (status & TC)) && host->mrq)
  930. omap_hsmmc_xfer_done(host, data);
  931. }
  932. /*
  933. * MMC controller IRQ handler
  934. */
  935. static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
  936. {
  937. struct omap_hsmmc_host *host = dev_id;
  938. int status;
  939. status = OMAP_HSMMC_READ(host->base, STAT);
  940. do {
  941. omap_hsmmc_do_irq(host, status);
  942. /* Flush posted write */
  943. status = OMAP_HSMMC_READ(host->base, STAT);
  944. } while (status & INT_EN_MASK);
  945. return IRQ_HANDLED;
  946. }
  947. static void set_sd_bus_power(struct omap_hsmmc_host *host)
  948. {
  949. unsigned long i;
  950. OMAP_HSMMC_WRITE(host->base, HCTL,
  951. OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
  952. for (i = 0; i < loops_per_jiffy; i++) {
  953. if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
  954. break;
  955. cpu_relax();
  956. }
  957. }
  958. /*
  959. * Switch MMC interface voltage ... only relevant for MMC1.
  960. *
  961. * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
  962. * The MMC2 transceiver controls are used instead of DAT4..DAT7.
  963. * Some chips, like eMMC ones, use internal transceivers.
  964. */
  965. static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
  966. {
  967. u32 reg_val = 0;
  968. int ret;
  969. /* Disable the clocks */
  970. clk_disable(host->fclk);
  971. clk_disable(host->iclk);
  972. if (host->got_dbclk)
  973. clk_disable(host->dbclk);
  974. /* Turn the power off */
  975. ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
  976. /* Turn the power ON with given VDD 1.8 or 3.0v */
  977. if (!ret)
  978. ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
  979. vdd);
  980. clk_enable(host->iclk);
  981. clk_enable(host->fclk);
  982. if (host->got_dbclk)
  983. clk_enable(host->dbclk);
  984. if (ret != 0)
  985. goto err;
  986. OMAP_HSMMC_WRITE(host->base, HCTL,
  987. OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
  988. reg_val = OMAP_HSMMC_READ(host->base, HCTL);
  989. /*
  990. * If a MMC dual voltage card is detected, the set_ios fn calls
  991. * this fn with VDD bit set for 1.8V. Upon card removal from the
  992. * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
  993. *
  994. * Cope with a bit of slop in the range ... per data sheets:
  995. * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
  996. * but recommended values are 1.71V to 1.89V
  997. * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
  998. * but recommended values are 2.7V to 3.3V
  999. *
  1000. * Board setup code shouldn't permit anything very out-of-range.
  1001. * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
  1002. * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
  1003. */
  1004. if ((1 << vdd) <= MMC_VDD_23_24)
  1005. reg_val |= SDVS18;
  1006. else
  1007. reg_val |= SDVS30;
  1008. OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
  1009. set_sd_bus_power(host);
  1010. return 0;
  1011. err:
  1012. dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
  1013. return ret;
  1014. }
  1015. /* Protect the card while the cover is open */
  1016. static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
  1017. {
  1018. if (!mmc_slot(host).get_cover_state)
  1019. return;
  1020. host->reqs_blocked = 0;
  1021. if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
  1022. if (host->protect_card) {
  1023. printk(KERN_INFO "%s: cover is closed, "
  1024. "card is now accessible\n",
  1025. mmc_hostname(host->mmc));
  1026. host->protect_card = 0;
  1027. }
  1028. } else {
  1029. if (!host->protect_card) {
  1030. printk(KERN_INFO "%s: cover is open, "
  1031. "card is now inaccessible\n",
  1032. mmc_hostname(host->mmc));
  1033. host->protect_card = 1;
  1034. }
  1035. }
  1036. }
  1037. /*
  1038. * Work Item to notify the core about card insertion/removal
  1039. */
  1040. static void omap_hsmmc_detect(struct work_struct *work)
  1041. {
  1042. struct omap_hsmmc_host *host =
  1043. container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
  1044. struct omap_mmc_slot_data *slot = &mmc_slot(host);
  1045. int carddetect;
  1046. if (host->suspended)
  1047. return;
  1048. sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
  1049. if (slot->card_detect)
  1050. carddetect = slot->card_detect(host->dev, host->slot_id);
  1051. else {
  1052. omap_hsmmc_protect_card(host);
  1053. carddetect = -ENOSYS;
  1054. }
  1055. if (carddetect)
  1056. mmc_detect_change(host->mmc, (HZ * 200) / 1000);
  1057. else
  1058. mmc_detect_change(host->mmc, (HZ * 50) / 1000);
  1059. }
  1060. /*
  1061. * ISR for handling card insertion and removal
  1062. */
  1063. static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
  1064. {
  1065. struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
  1066. if (host->suspended)
  1067. return IRQ_HANDLED;
  1068. schedule_work(&host->mmc_carddetect_work);
  1069. return IRQ_HANDLED;
  1070. }
  1071. static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
  1072. struct mmc_data *data)
  1073. {
  1074. int sync_dev;
  1075. if (data->flags & MMC_DATA_WRITE)
  1076. sync_dev = host->dma_line_tx;
  1077. else
  1078. sync_dev = host->dma_line_rx;
  1079. return sync_dev;
  1080. }
  1081. static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
  1082. struct mmc_data *data,
  1083. struct scatterlist *sgl)
  1084. {
  1085. int blksz, nblk, dma_ch;
  1086. dma_ch = host->dma_ch;
  1087. if (data->flags & MMC_DATA_WRITE) {
  1088. omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
  1089. (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
  1090. omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
  1091. sg_dma_address(sgl), 0, 0);
  1092. } else {
  1093. omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
  1094. (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
  1095. omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
  1096. sg_dma_address(sgl), 0, 0);
  1097. }
  1098. blksz = host->data->blksz;
  1099. nblk = sg_dma_len(sgl) / blksz;
  1100. omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
  1101. blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
  1102. omap_hsmmc_get_dma_sync_dev(host, data),
  1103. !(data->flags & MMC_DATA_WRITE));
  1104. omap_start_dma(dma_ch);
  1105. }
  1106. /*
  1107. * DMA call back function
  1108. */
  1109. static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
  1110. {
  1111. struct omap_hsmmc_host *host = cb_data;
  1112. struct mmc_data *data = host->mrq->data;
  1113. int dma_ch, req_in_progress;
  1114. if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
  1115. dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
  1116. ch_status);
  1117. return;
  1118. }
  1119. spin_lock(&host->irq_lock);
  1120. if (host->dma_ch < 0) {
  1121. spin_unlock(&host->irq_lock);
  1122. return;
  1123. }
  1124. host->dma_sg_idx++;
  1125. if (host->dma_sg_idx < host->dma_len) {
  1126. /* Fire up the next transfer. */
  1127. omap_hsmmc_config_dma_params(host, data,
  1128. data->sg + host->dma_sg_idx);
  1129. spin_unlock(&host->irq_lock);
  1130. return;
  1131. }
  1132. dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
  1133. omap_hsmmc_get_dma_dir(host, data));
  1134. req_in_progress = host->req_in_progress;
  1135. dma_ch = host->dma_ch;
  1136. host->dma_ch = -1;
  1137. spin_unlock(&host->irq_lock);
  1138. omap_free_dma(dma_ch);
  1139. /* If DMA has finished after TC, complete the request */
  1140. if (!req_in_progress) {
  1141. struct mmc_request *mrq = host->mrq;
  1142. host->mrq = NULL;
  1143. mmc_request_done(host->mmc, mrq);
  1144. }
  1145. }
  1146. /*
  1147. * Routine to configure and start DMA for the MMC card
  1148. */
  1149. static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
  1150. struct mmc_request *req)
  1151. {
  1152. int dma_ch = 0, ret = 0, i;
  1153. struct mmc_data *data = req->data;
  1154. /* Sanity check: all the SG entries must be aligned by block size. */
  1155. for (i = 0; i < data->sg_len; i++) {
  1156. struct scatterlist *sgl;
  1157. sgl = data->sg + i;
  1158. if (sgl->length % data->blksz)
  1159. return -EINVAL;
  1160. }
  1161. if ((data->blksz % 4) != 0)
  1162. /* REVISIT: The MMC buffer increments only when MSB is written.
  1163. * Return error for blksz which is non multiple of four.
  1164. */
  1165. return -EINVAL;
  1166. BUG_ON(host->dma_ch != -1);
  1167. ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
  1168. "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
  1169. if (ret != 0) {
  1170. dev_err(mmc_dev(host->mmc),
  1171. "%s: omap_request_dma() failed with %d\n",
  1172. mmc_hostname(host->mmc), ret);
  1173. return ret;
  1174. }
  1175. host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
  1176. data->sg_len, omap_hsmmc_get_dma_dir(host, data));
  1177. host->dma_ch = dma_ch;
  1178. host->dma_sg_idx = 0;
  1179. omap_hsmmc_config_dma_params(host, data, data->sg);
  1180. return 0;
  1181. }
  1182. static void set_data_timeout(struct omap_hsmmc_host *host,
  1183. unsigned int timeout_ns,
  1184. unsigned int timeout_clks)
  1185. {
  1186. unsigned int timeout, cycle_ns;
  1187. uint32_t reg, clkd, dto = 0;
  1188. reg = OMAP_HSMMC_READ(host->base, SYSCTL);
  1189. clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
  1190. if (clkd == 0)
  1191. clkd = 1;
  1192. cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
  1193. timeout = timeout_ns / cycle_ns;
  1194. timeout += timeout_clks;
  1195. if (timeout) {
  1196. while ((timeout & 0x80000000) == 0) {
  1197. dto += 1;
  1198. timeout <<= 1;
  1199. }
  1200. dto = 31 - dto;
  1201. timeout <<= 1;
  1202. if (timeout && dto)
  1203. dto += 1;
  1204. if (dto >= 13)
  1205. dto -= 13;
  1206. else
  1207. dto = 0;
  1208. if (dto > 14)
  1209. dto = 14;
  1210. }
  1211. reg &= ~DTO_MASK;
  1212. reg |= dto << DTO_SHIFT;
  1213. OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
  1214. }
  1215. /*
  1216. * Configure block length for MMC/SD cards and initiate the transfer.
  1217. */
  1218. static int
  1219. omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
  1220. {
  1221. int ret;
  1222. host->data = req->data;
  1223. if (req->data == NULL) {
  1224. OMAP_HSMMC_WRITE(host->base, BLK, 0);
  1225. /*
  1226. * Set an arbitrary 100ms data timeout for commands with
  1227. * busy signal.
  1228. */
  1229. if (req->cmd->flags & MMC_RSP_BUSY)
  1230. set_data_timeout(host, 100000000U, 0);
  1231. return 0;
  1232. }
  1233. OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
  1234. | (req->data->blocks << 16));
  1235. set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
  1236. if (host->use_dma) {
  1237. ret = omap_hsmmc_start_dma_transfer(host, req);
  1238. if (ret != 0) {
  1239. dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
  1240. return ret;
  1241. }
  1242. }
  1243. return 0;
  1244. }
  1245. /*
  1246. * Request function. for read/write operation
  1247. */
  1248. static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
  1249. {
  1250. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1251. int err;
  1252. BUG_ON(host->req_in_progress);
  1253. BUG_ON(host->dma_ch != -1);
  1254. if (host->protect_card) {
  1255. if (host->reqs_blocked < 3) {
  1256. /*
  1257. * Ensure the controller is left in a consistent
  1258. * state by resetting the command and data state
  1259. * machines.
  1260. */
  1261. omap_hsmmc_reset_controller_fsm(host, SRD);
  1262. omap_hsmmc_reset_controller_fsm(host, SRC);
  1263. host->reqs_blocked += 1;
  1264. }
  1265. req->cmd->error = -EBADF;
  1266. if (req->data)
  1267. req->data->error = -EBADF;
  1268. req->cmd->retries = 0;
  1269. mmc_request_done(mmc, req);
  1270. return;
  1271. } else if (host->reqs_blocked)
  1272. host->reqs_blocked = 0;
  1273. WARN_ON(host->mrq != NULL);
  1274. host->mrq = req;
  1275. err = omap_hsmmc_prepare_data(host, req);
  1276. if (err) {
  1277. req->cmd->error = err;
  1278. if (req->data)
  1279. req->data->error = err;
  1280. host->mrq = NULL;
  1281. mmc_request_done(mmc, req);
  1282. return;
  1283. }
  1284. omap_hsmmc_start_command(host, req->cmd, req->data);
  1285. }
  1286. /* Routine to configure clock values. Exposed API to core */
  1287. static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  1288. {
  1289. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1290. u16 dsor = 0;
  1291. unsigned long regval;
  1292. unsigned long timeout;
  1293. u32 con;
  1294. int do_send_init_stream = 0;
  1295. mmc_host_enable(host->mmc);
  1296. if (ios->power_mode != host->power_mode) {
  1297. switch (ios->power_mode) {
  1298. case MMC_POWER_OFF:
  1299. mmc_slot(host).set_power(host->dev, host->slot_id,
  1300. 0, 0);
  1301. host->vdd = 0;
  1302. break;
  1303. case MMC_POWER_UP:
  1304. mmc_slot(host).set_power(host->dev, host->slot_id,
  1305. 1, ios->vdd);
  1306. host->vdd = ios->vdd;
  1307. break;
  1308. case MMC_POWER_ON:
  1309. do_send_init_stream = 1;
  1310. break;
  1311. }
  1312. host->power_mode = ios->power_mode;
  1313. }
  1314. /* FIXME: set registers based only on changes to ios */
  1315. con = OMAP_HSMMC_READ(host->base, CON);
  1316. switch (mmc->ios.bus_width) {
  1317. case MMC_BUS_WIDTH_8:
  1318. OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
  1319. break;
  1320. case MMC_BUS_WIDTH_4:
  1321. OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
  1322. OMAP_HSMMC_WRITE(host->base, HCTL,
  1323. OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
  1324. break;
  1325. case MMC_BUS_WIDTH_1:
  1326. OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
  1327. OMAP_HSMMC_WRITE(host->base, HCTL,
  1328. OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
  1329. break;
  1330. }
  1331. if (host->id == OMAP_MMC1_DEVID) {
  1332. /* Only MMC1 can interface at 3V without some flavor
  1333. * of external transceiver; but they all handle 1.8V.
  1334. */
  1335. if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
  1336. (ios->vdd == DUAL_VOLT_OCR_BIT)) {
  1337. /*
  1338. * The mmc_select_voltage fn of the core does
  1339. * not seem to set the power_mode to
  1340. * MMC_POWER_UP upon recalculating the voltage.
  1341. * vdd 1.8v.
  1342. */
  1343. if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
  1344. dev_dbg(mmc_dev(host->mmc),
  1345. "Switch operation failed\n");
  1346. }
  1347. }
  1348. if (ios->clock) {
  1349. dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
  1350. if (dsor < 1)
  1351. dsor = 1;
  1352. if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
  1353. dsor++;
  1354. if (dsor > 250)
  1355. dsor = 250;
  1356. }
  1357. omap_hsmmc_stop_clock(host);
  1358. regval = OMAP_HSMMC_READ(host->base, SYSCTL);
  1359. regval = regval & ~(CLKD_MASK);
  1360. regval = regval | (dsor << 6) | (DTO << 16);
  1361. OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
  1362. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  1363. OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
  1364. /* Wait till the ICS bit is set */
  1365. timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
  1366. while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
  1367. && time_before(jiffies, timeout))
  1368. msleep(1);
  1369. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  1370. OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
  1371. if (do_send_init_stream)
  1372. send_init_stream(host);
  1373. con = OMAP_HSMMC_READ(host->base, CON);
  1374. if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
  1375. OMAP_HSMMC_WRITE(host->base, CON, con | OD);
  1376. else
  1377. OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
  1378. if (host->power_mode == MMC_POWER_OFF)
  1379. mmc_host_disable(host->mmc);
  1380. else
  1381. mmc_host_lazy_disable(host->mmc);
  1382. }
  1383. static int omap_hsmmc_get_cd(struct mmc_host *mmc)
  1384. {
  1385. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1386. if (!mmc_slot(host).card_detect)
  1387. return -ENOSYS;
  1388. return mmc_slot(host).card_detect(host->dev, host->slot_id);
  1389. }
  1390. static int omap_hsmmc_get_ro(struct mmc_host *mmc)
  1391. {
  1392. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1393. if (!mmc_slot(host).get_ro)
  1394. return -ENOSYS;
  1395. return mmc_slot(host).get_ro(host->dev, 0);
  1396. }
  1397. static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
  1398. {
  1399. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1400. if (mmc_slot(host).init_card)
  1401. mmc_slot(host).init_card(card);
  1402. }
  1403. static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
  1404. {
  1405. u32 hctl, capa, value;
  1406. /* Only MMC1 supports 3.0V */
  1407. if (host->id == OMAP_MMC1_DEVID) {
  1408. hctl = SDVS30;
  1409. capa = VS30 | VS18;
  1410. } else {
  1411. hctl = SDVS18;
  1412. capa = VS18;
  1413. }
  1414. value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
  1415. OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
  1416. value = OMAP_HSMMC_READ(host->base, CAPA);
  1417. OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
  1418. /* Set the controller to AUTO IDLE mode */
  1419. value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
  1420. OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
  1421. /* Set SD bus power bit */
  1422. set_sd_bus_power(host);
  1423. }
  1424. /*
  1425. * Dynamic power saving handling, FSM:
  1426. * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF
  1427. * ^___________| | |
  1428. * |______________________|______________________|
  1429. *
  1430. * ENABLED: mmc host is fully functional
  1431. * DISABLED: fclk is off
  1432. * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep
  1433. * REGSLEEP: fclk is off, voltage regulator is asleep
  1434. * OFF: fclk is off, voltage regulator is off
  1435. *
  1436. * Transition handlers return the timeout for the next state transition
  1437. * or negative error.
  1438. */
  1439. enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF};
  1440. /* Handler for [ENABLED -> DISABLED] transition */
  1441. static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host)
  1442. {
  1443. omap_hsmmc_context_save(host);
  1444. clk_disable(host->fclk);
  1445. host->dpm_state = DISABLED;
  1446. dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n");
  1447. if (host->power_mode == MMC_POWER_OFF)
  1448. return 0;
  1449. return OMAP_MMC_SLEEP_TIMEOUT;
  1450. }
  1451. /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
  1452. static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host)
  1453. {
  1454. int err, new_state;
  1455. if (!mmc_try_claim_host(host->mmc))
  1456. return 0;
  1457. clk_enable(host->fclk);
  1458. omap_hsmmc_context_restore(host);
  1459. if (mmc_card_can_sleep(host->mmc)) {
  1460. err = mmc_card_sleep(host->mmc);
  1461. if (err < 0) {
  1462. clk_disable(host->fclk);
  1463. mmc_release_host(host->mmc);
  1464. return err;
  1465. }
  1466. new_state = CARDSLEEP;
  1467. } else {
  1468. new_state = REGSLEEP;
  1469. }
  1470. if (mmc_slot(host).set_sleep)
  1471. mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0,
  1472. new_state == CARDSLEEP);
  1473. /* FIXME: turn off bus power and perhaps interrupts too */
  1474. clk_disable(host->fclk);
  1475. host->dpm_state = new_state;
  1476. mmc_release_host(host->mmc);
  1477. dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n",
  1478. host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
  1479. if (mmc_slot(host).no_off)
  1480. return 0;
  1481. if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
  1482. mmc_slot(host).card_detect ||
  1483. (mmc_slot(host).get_cover_state &&
  1484. mmc_slot(host).get_cover_state(host->dev, host->slot_id)))
  1485. return OMAP_MMC_OFF_TIMEOUT;
  1486. return 0;
  1487. }
  1488. /* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */
  1489. static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host)
  1490. {
  1491. if (!mmc_try_claim_host(host->mmc))
  1492. return 0;
  1493. if (mmc_slot(host).no_off)
  1494. return 0;
  1495. if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
  1496. mmc_slot(host).card_detect ||
  1497. (mmc_slot(host).get_cover_state &&
  1498. mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) {
  1499. mmc_release_host(host->mmc);
  1500. return 0;
  1501. }
  1502. mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
  1503. host->vdd = 0;
  1504. host->power_mode = MMC_POWER_OFF;
  1505. dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n",
  1506. host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
  1507. host->dpm_state = OFF;
  1508. mmc_release_host(host->mmc);
  1509. return 0;
  1510. }
  1511. /* Handler for [DISABLED -> ENABLED] transition */
  1512. static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host)
  1513. {
  1514. int err;
  1515. err = clk_enable(host->fclk);
  1516. if (err < 0)
  1517. return err;
  1518. omap_hsmmc_context_restore(host);
  1519. host->dpm_state = ENABLED;
  1520. dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n");
  1521. return 0;
  1522. }
  1523. /* Handler for [SLEEP -> ENABLED] transition */
  1524. static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host)
  1525. {
  1526. if (!mmc_try_claim_host(host->mmc))
  1527. return 0;
  1528. clk_enable(host->fclk);
  1529. omap_hsmmc_context_restore(host);
  1530. if (mmc_slot(host).set_sleep)
  1531. mmc_slot(host).set_sleep(host->dev, host->slot_id, 0,
  1532. host->vdd, host->dpm_state == CARDSLEEP);
  1533. if (mmc_card_can_sleep(host->mmc))
  1534. mmc_card_awake(host->mmc);
  1535. dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n",
  1536. host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
  1537. host->dpm_state = ENABLED;
  1538. mmc_release_host(host->mmc);
  1539. return 0;
  1540. }
  1541. /* Handler for [OFF -> ENABLED] transition */
  1542. static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host)
  1543. {
  1544. clk_enable(host->fclk);
  1545. omap_hsmmc_context_restore(host);
  1546. omap_hsmmc_conf_bus_power(host);
  1547. mmc_power_restore_host(host->mmc);
  1548. host->dpm_state = ENABLED;
  1549. dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n");
  1550. return 0;
  1551. }
  1552. /*
  1553. * Bring MMC host to ENABLED from any other PM state.
  1554. */
  1555. static int omap_hsmmc_enable(struct mmc_host *mmc)
  1556. {
  1557. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1558. switch (host->dpm_state) {
  1559. case DISABLED:
  1560. return omap_hsmmc_disabled_to_enabled(host);
  1561. case CARDSLEEP:
  1562. case REGSLEEP:
  1563. return omap_hsmmc_sleep_to_enabled(host);
  1564. case OFF:
  1565. return omap_hsmmc_off_to_enabled(host);
  1566. default:
  1567. dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
  1568. return -EINVAL;
  1569. }
  1570. }
  1571. /*
  1572. * Bring MMC host in PM state (one level deeper).
  1573. */
  1574. static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy)
  1575. {
  1576. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1577. switch (host->dpm_state) {
  1578. case ENABLED: {
  1579. int delay;
  1580. delay = omap_hsmmc_enabled_to_disabled(host);
  1581. if (lazy || delay < 0)
  1582. return delay;
  1583. return 0;
  1584. }
  1585. case DISABLED:
  1586. return omap_hsmmc_disabled_to_sleep(host);
  1587. case CARDSLEEP:
  1588. case REGSLEEP:
  1589. return omap_hsmmc_sleep_to_off(host);
  1590. default:
  1591. dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
  1592. return -EINVAL;
  1593. }
  1594. }
  1595. static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
  1596. {
  1597. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1598. int err;
  1599. err = clk_enable(host->fclk);
  1600. if (err)
  1601. return err;
  1602. dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
  1603. omap_hsmmc_context_restore(host);
  1604. return 0;
  1605. }
  1606. static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
  1607. {
  1608. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1609. omap_hsmmc_context_save(host);
  1610. clk_disable(host->fclk);
  1611. dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
  1612. return 0;
  1613. }
  1614. static const struct mmc_host_ops omap_hsmmc_ops = {
  1615. .enable = omap_hsmmc_enable_fclk,
  1616. .disable = omap_hsmmc_disable_fclk,
  1617. .request = omap_hsmmc_request,
  1618. .set_ios = omap_hsmmc_set_ios,
  1619. .get_cd = omap_hsmmc_get_cd,
  1620. .get_ro = omap_hsmmc_get_ro,
  1621. .init_card = omap_hsmmc_init_card,
  1622. /* NYET -- enable_sdio_irq */
  1623. };
  1624. static const struct mmc_host_ops omap_hsmmc_ps_ops = {
  1625. .enable = omap_hsmmc_enable,
  1626. .disable = omap_hsmmc_disable,
  1627. .request = omap_hsmmc_request,
  1628. .set_ios = omap_hsmmc_set_ios,
  1629. .get_cd = omap_hsmmc_get_cd,
  1630. .get_ro = omap_hsmmc_get_ro,
  1631. .init_card = omap_hsmmc_init_card,
  1632. /* NYET -- enable_sdio_irq */
  1633. };
  1634. #ifdef CONFIG_DEBUG_FS
  1635. static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
  1636. {
  1637. struct mmc_host *mmc = s->private;
  1638. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1639. int context_loss = 0;
  1640. if (host->pdata->get_context_loss_count)
  1641. context_loss = host->pdata->get_context_loss_count(host->dev);
  1642. seq_printf(s, "mmc%d:\n"
  1643. " enabled:\t%d\n"
  1644. " dpm_state:\t%d\n"
  1645. " nesting_cnt:\t%d\n"
  1646. " ctx_loss:\t%d:%d\n"
  1647. "\nregs:\n",
  1648. mmc->index, mmc->enabled ? 1 : 0,
  1649. host->dpm_state, mmc->nesting_cnt,
  1650. host->context_loss, context_loss);
  1651. if (host->suspended || host->dpm_state == OFF) {
  1652. seq_printf(s, "host suspended, can't read registers\n");
  1653. return 0;
  1654. }
  1655. if (clk_enable(host->fclk) != 0) {
  1656. seq_printf(s, "can't read the regs\n");
  1657. return 0;
  1658. }
  1659. seq_printf(s, "SYSCONFIG:\t0x%08x\n",
  1660. OMAP_HSMMC_READ(host->base, SYSCONFIG));
  1661. seq_printf(s, "CON:\t\t0x%08x\n",
  1662. OMAP_HSMMC_READ(host->base, CON));
  1663. seq_printf(s, "HCTL:\t\t0x%08x\n",
  1664. OMAP_HSMMC_READ(host->base, HCTL));
  1665. seq_printf(s, "SYSCTL:\t\t0x%08x\n",
  1666. OMAP_HSMMC_READ(host->base, SYSCTL));
  1667. seq_printf(s, "IE:\t\t0x%08x\n",
  1668. OMAP_HSMMC_READ(host->base, IE));
  1669. seq_printf(s, "ISE:\t\t0x%08x\n",
  1670. OMAP_HSMMC_READ(host->base, ISE));
  1671. seq_printf(s, "CAPA:\t\t0x%08x\n",
  1672. OMAP_HSMMC_READ(host->base, CAPA));
  1673. clk_disable(host->fclk);
  1674. return 0;
  1675. }
  1676. static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
  1677. {
  1678. return single_open(file, omap_hsmmc_regs_show, inode->i_private);
  1679. }
  1680. static const struct file_operations mmc_regs_fops = {
  1681. .open = omap_hsmmc_regs_open,
  1682. .read = seq_read,
  1683. .llseek = seq_lseek,
  1684. .release = single_release,
  1685. };
  1686. static void omap_hsmmc_debugfs(struct mmc_host *mmc)
  1687. {
  1688. if (mmc->debugfs_root)
  1689. debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
  1690. mmc, &mmc_regs_fops);
  1691. }
  1692. #else
  1693. static void omap_hsmmc_debugfs(struct mmc_host *mmc)
  1694. {
  1695. }
  1696. #endif
  1697. static int __init omap_hsmmc_probe(struct platform_device *pdev)
  1698. {
  1699. struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
  1700. struct mmc_host *mmc;
  1701. struct omap_hsmmc_host *host = NULL;
  1702. struct resource *res;
  1703. int ret, irq;
  1704. if (pdata == NULL) {
  1705. dev_err(&pdev->dev, "Platform Data is missing\n");
  1706. return -ENXIO;
  1707. }
  1708. if (pdata->nr_slots == 0) {
  1709. dev_err(&pdev->dev, "No Slots\n");
  1710. return -ENXIO;
  1711. }
  1712. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1713. irq = platform_get_irq(pdev, 0);
  1714. if (res == NULL || irq < 0)
  1715. return -ENXIO;
  1716. res->start += pdata->reg_offset;
  1717. res->end += pdata->reg_offset;
  1718. res = request_mem_region(res->start, res->end - res->start + 1,
  1719. pdev->name);
  1720. if (res == NULL)
  1721. return -EBUSY;
  1722. ret = omap_hsmmc_gpio_init(pdata);
  1723. if (ret)
  1724. goto err;
  1725. mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
  1726. if (!mmc) {
  1727. ret = -ENOMEM;
  1728. goto err_alloc;
  1729. }
  1730. host = mmc_priv(mmc);
  1731. host->mmc = mmc;
  1732. host->pdata = pdata;
  1733. host->dev = &pdev->dev;
  1734. host->use_dma = 1;
  1735. host->dev->dma_mask = &pdata->dma_mask;
  1736. host->dma_ch = -1;
  1737. host->irq = irq;
  1738. host->id = pdev->id;
  1739. host->slot_id = 0;
  1740. host->mapbase = res->start;
  1741. host->base = ioremap(host->mapbase, SZ_4K);
  1742. host->power_mode = MMC_POWER_OFF;
  1743. platform_set_drvdata(pdev, host);
  1744. INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
  1745. if (mmc_slot(host).power_saving)
  1746. mmc->ops = &omap_hsmmc_ps_ops;
  1747. else
  1748. mmc->ops = &omap_hsmmc_ops;
  1749. /*
  1750. * If regulator_disable can only put vcc_aux to sleep then there is
  1751. * no off state.
  1752. */
  1753. if (mmc_slot(host).vcc_aux_disable_is_sleep)
  1754. mmc_slot(host).no_off = 1;
  1755. mmc->f_min = 400000;
  1756. mmc->f_max = 52000000;
  1757. spin_lock_init(&host->irq_lock);
  1758. host->iclk = clk_get(&pdev->dev, "ick");
  1759. if (IS_ERR(host->iclk)) {
  1760. ret = PTR_ERR(host->iclk);
  1761. host->iclk = NULL;
  1762. goto err1;
  1763. }
  1764. host->fclk = clk_get(&pdev->dev, "fck");
  1765. if (IS_ERR(host->fclk)) {
  1766. ret = PTR_ERR(host->fclk);
  1767. host->fclk = NULL;
  1768. clk_put(host->iclk);
  1769. goto err1;
  1770. }
  1771. omap_hsmmc_context_save(host);
  1772. mmc->caps |= MMC_CAP_DISABLE;
  1773. mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT);
  1774. /* we start off in DISABLED state */
  1775. host->dpm_state = DISABLED;
  1776. if (mmc_host_enable(host->mmc) != 0) {
  1777. clk_put(host->iclk);
  1778. clk_put(host->fclk);
  1779. goto err1;
  1780. }
  1781. if (clk_enable(host->iclk) != 0) {
  1782. mmc_host_disable(host->mmc);
  1783. clk_put(host->iclk);
  1784. clk_put(host->fclk);
  1785. goto err1;
  1786. }
  1787. if (cpu_is_omap2430()) {
  1788. host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
  1789. /*
  1790. * MMC can still work without debounce clock.
  1791. */
  1792. if (IS_ERR(host->dbclk))
  1793. dev_warn(mmc_dev(host->mmc),
  1794. "Failed to get debounce clock\n");
  1795. else
  1796. host->got_dbclk = 1;
  1797. if (host->got_dbclk)
  1798. if (clk_enable(host->dbclk) != 0)
  1799. dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
  1800. " clk failed\n");
  1801. }
  1802. /* Since we do only SG emulation, we can have as many segs
  1803. * as we want. */
  1804. mmc->max_phys_segs = 1024;
  1805. mmc->max_hw_segs = 1024;
  1806. mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
  1807. mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
  1808. mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
  1809. mmc->max_seg_size = mmc->max_req_size;
  1810. mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
  1811. MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
  1812. mmc->caps |= mmc_slot(host).caps;
  1813. if (mmc->caps & MMC_CAP_8_BIT_DATA)
  1814. mmc->caps |= MMC_CAP_4_BIT_DATA;
  1815. if (mmc_slot(host).nonremovable)
  1816. mmc->caps |= MMC_CAP_NONREMOVABLE;
  1817. omap_hsmmc_conf_bus_power(host);
  1818. /* Select DMA lines */
  1819. switch (host->id) {
  1820. case OMAP_MMC1_DEVID:
  1821. host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
  1822. host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
  1823. break;
  1824. case OMAP_MMC2_DEVID:
  1825. host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
  1826. host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
  1827. break;
  1828. case OMAP_MMC3_DEVID:
  1829. host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
  1830. host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
  1831. break;
  1832. case OMAP_MMC4_DEVID:
  1833. host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
  1834. host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
  1835. break;
  1836. case OMAP_MMC5_DEVID:
  1837. host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
  1838. host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
  1839. break;
  1840. default:
  1841. dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
  1842. goto err_irq;
  1843. }
  1844. /* Request IRQ for MMC operations */
  1845. ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
  1846. mmc_hostname(mmc), host);
  1847. if (ret) {
  1848. dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
  1849. goto err_irq;
  1850. }
  1851. if (pdata->init != NULL) {
  1852. if (pdata->init(&pdev->dev) != 0) {
  1853. dev_dbg(mmc_dev(host->mmc),
  1854. "Unable to configure MMC IRQs\n");
  1855. goto err_irq_cd_init;
  1856. }
  1857. }
  1858. if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
  1859. ret = omap_hsmmc_reg_get(host);
  1860. if (ret)
  1861. goto err_reg;
  1862. host->use_reg = 1;
  1863. }
  1864. mmc->ocr_avail = mmc_slot(host).ocr_mask;
  1865. /* Request IRQ for card detect */
  1866. if ((mmc_slot(host).card_detect_irq)) {
  1867. ret = request_irq(mmc_slot(host).card_detect_irq,
  1868. omap_hsmmc_cd_handler,
  1869. IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
  1870. | IRQF_DISABLED,
  1871. mmc_hostname(mmc), host);
  1872. if (ret) {
  1873. dev_dbg(mmc_dev(host->mmc),
  1874. "Unable to grab MMC CD IRQ\n");
  1875. goto err_irq_cd;
  1876. }
  1877. }
  1878. omap_hsmmc_disable_irq(host);
  1879. mmc_host_lazy_disable(host->mmc);
  1880. omap_hsmmc_protect_card(host);
  1881. mmc_add_host(mmc);
  1882. if (mmc_slot(host).name != NULL) {
  1883. ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
  1884. if (ret < 0)
  1885. goto err_slot_name;
  1886. }
  1887. if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
  1888. ret = device_create_file(&mmc->class_dev,
  1889. &dev_attr_cover_switch);
  1890. if (ret < 0)
  1891. goto err_slot_name;
  1892. }
  1893. omap_hsmmc_debugfs(mmc);
  1894. return 0;
  1895. err_slot_name:
  1896. mmc_remove_host(mmc);
  1897. free_irq(mmc_slot(host).card_detect_irq, host);
  1898. err_irq_cd:
  1899. if (host->use_reg)
  1900. omap_hsmmc_reg_put(host);
  1901. err_reg:
  1902. if (host->pdata->cleanup)
  1903. host->pdata->cleanup(&pdev->dev);
  1904. err_irq_cd_init:
  1905. free_irq(host->irq, host);
  1906. err_irq:
  1907. mmc_host_disable(host->mmc);
  1908. clk_disable(host->iclk);
  1909. clk_put(host->fclk);
  1910. clk_put(host->iclk);
  1911. if (host->got_dbclk) {
  1912. clk_disable(host->dbclk);
  1913. clk_put(host->dbclk);
  1914. }
  1915. err1:
  1916. iounmap(host->base);
  1917. platform_set_drvdata(pdev, NULL);
  1918. mmc_free_host(mmc);
  1919. err_alloc:
  1920. omap_hsmmc_gpio_free(pdata);
  1921. err:
  1922. release_mem_region(res->start, res->end - res->start + 1);
  1923. return ret;
  1924. }
  1925. static int omap_hsmmc_remove(struct platform_device *pdev)
  1926. {
  1927. struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
  1928. struct resource *res;
  1929. if (host) {
  1930. mmc_host_enable(host->mmc);
  1931. mmc_remove_host(host->mmc);
  1932. if (host->use_reg)
  1933. omap_hsmmc_reg_put(host);
  1934. if (host->pdata->cleanup)
  1935. host->pdata->cleanup(&pdev->dev);
  1936. free_irq(host->irq, host);
  1937. if (mmc_slot(host).card_detect_irq)
  1938. free_irq(mmc_slot(host).card_detect_irq, host);
  1939. flush_scheduled_work();
  1940. mmc_host_disable(host->mmc);
  1941. clk_disable(host->iclk);
  1942. clk_put(host->fclk);
  1943. clk_put(host->iclk);
  1944. if (host->got_dbclk) {
  1945. clk_disable(host->dbclk);
  1946. clk_put(host->dbclk);
  1947. }
  1948. mmc_free_host(host->mmc);
  1949. iounmap(host->base);
  1950. omap_hsmmc_gpio_free(pdev->dev.platform_data);
  1951. }
  1952. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1953. if (res)
  1954. release_mem_region(res->start, res->end - res->start + 1);
  1955. platform_set_drvdata(pdev, NULL);
  1956. return 0;
  1957. }
  1958. #ifdef CONFIG_PM
  1959. static int omap_hsmmc_suspend(struct device *dev)
  1960. {
  1961. int ret = 0;
  1962. struct platform_device *pdev = to_platform_device(dev);
  1963. struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
  1964. if (host && host->suspended)
  1965. return 0;
  1966. if (host) {
  1967. host->suspended = 1;
  1968. if (host->pdata->suspend) {
  1969. ret = host->pdata->suspend(&pdev->dev,
  1970. host->slot_id);
  1971. if (ret) {
  1972. dev_dbg(mmc_dev(host->mmc),
  1973. "Unable to handle MMC board"
  1974. " level suspend\n");
  1975. host->suspended = 0;
  1976. return ret;
  1977. }
  1978. }
  1979. cancel_work_sync(&host->mmc_carddetect_work);
  1980. ret = mmc_suspend_host(host->mmc);
  1981. mmc_host_enable(host->mmc);
  1982. if (ret == 0) {
  1983. omap_hsmmc_disable_irq(host);
  1984. OMAP_HSMMC_WRITE(host->base, HCTL,
  1985. OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
  1986. mmc_host_disable(host->mmc);
  1987. clk_disable(host->iclk);
  1988. if (host->got_dbclk)
  1989. clk_disable(host->dbclk);
  1990. } else {
  1991. host->suspended = 0;
  1992. if (host->pdata->resume) {
  1993. ret = host->pdata->resume(&pdev->dev,
  1994. host->slot_id);
  1995. if (ret)
  1996. dev_dbg(mmc_dev(host->mmc),
  1997. "Unmask interrupt failed\n");
  1998. }
  1999. mmc_host_disable(host->mmc);
  2000. }
  2001. }
  2002. return ret;
  2003. }
  2004. /* Routine to resume the MMC device */
  2005. static int omap_hsmmc_resume(struct device *dev)
  2006. {
  2007. int ret = 0;
  2008. struct platform_device *pdev = to_platform_device(dev);
  2009. struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
  2010. if (host && !host->suspended)
  2011. return 0;
  2012. if (host) {
  2013. ret = clk_enable(host->iclk);
  2014. if (ret)
  2015. goto clk_en_err;
  2016. if (mmc_host_enable(host->mmc) != 0) {
  2017. clk_disable(host->iclk);
  2018. goto clk_en_err;
  2019. }
  2020. if (host->got_dbclk)
  2021. clk_enable(host->dbclk);
  2022. omap_hsmmc_conf_bus_power(host);
  2023. if (host->pdata->resume) {
  2024. ret = host->pdata->resume(&pdev->dev, host->slot_id);
  2025. if (ret)
  2026. dev_dbg(mmc_dev(host->mmc),
  2027. "Unmask interrupt failed\n");
  2028. }
  2029. omap_hsmmc_protect_card(host);
  2030. /* Notify the core to resume the host */
  2031. ret = mmc_resume_host(host->mmc);
  2032. if (ret == 0)
  2033. host->suspended = 0;
  2034. mmc_host_lazy_disable(host->mmc);
  2035. }
  2036. return ret;
  2037. clk_en_err:
  2038. dev_dbg(mmc_dev(host->mmc),
  2039. "Failed to enable MMC clocks during resume\n");
  2040. return ret;
  2041. }
  2042. #else
  2043. #define omap_hsmmc_suspend NULL
  2044. #define omap_hsmmc_resume NULL
  2045. #endif
  2046. static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
  2047. .suspend = omap_hsmmc_suspend,
  2048. .resume = omap_hsmmc_resume,
  2049. };
  2050. static struct platform_driver omap_hsmmc_driver = {
  2051. .remove = omap_hsmmc_remove,
  2052. .driver = {
  2053. .name = DRIVER_NAME,
  2054. .owner = THIS_MODULE,
  2055. .pm = &omap_hsmmc_dev_pm_ops,
  2056. },
  2057. };
  2058. static int __init omap_hsmmc_init(void)
  2059. {
  2060. /* Register the MMC driver */
  2061. return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
  2062. }
  2063. static void __exit omap_hsmmc_cleanup(void)
  2064. {
  2065. /* Unregister MMC driver */
  2066. platform_driver_unregister(&omap_hsmmc_driver);
  2067. }
  2068. module_init(omap_hsmmc_init);
  2069. module_exit(omap_hsmmc_cleanup);
  2070. MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
  2071. MODULE_LICENSE("GPL");
  2072. MODULE_ALIAS("platform:" DRIVER_NAME);
  2073. MODULE_AUTHOR("Texas Instruments Inc");