xhci.c 73 KB

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  1. /*
  2. * xHCI host controller driver
  3. *
  4. * Copyright (C) 2008 Intel Corp.
  5. *
  6. * Author: Sarah Sharp
  7. * Some code borrowed from the Linux EHCI driver.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16. * for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software Foundation,
  20. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/pci.h>
  23. #include <linux/irq.h>
  24. #include <linux/log2.h>
  25. #include <linux/module.h>
  26. #include <linux/moduleparam.h>
  27. #include <linux/slab.h>
  28. #include "xhci.h"
  29. #define DRIVER_AUTHOR "Sarah Sharp"
  30. #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
  31. /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
  32. static int link_quirk;
  33. module_param(link_quirk, int, S_IRUGO | S_IWUSR);
  34. MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
  35. /* TODO: copied from ehci-hcd.c - can this be refactored? */
  36. /*
  37. * handshake - spin reading hc until handshake completes or fails
  38. * @ptr: address of hc register to be read
  39. * @mask: bits to look at in result of read
  40. * @done: value of those bits when handshake succeeds
  41. * @usec: timeout in microseconds
  42. *
  43. * Returns negative errno, or zero on success
  44. *
  45. * Success happens when the "mask" bits have the specified value (hardware
  46. * handshake done). There are two failure modes: "usec" have passed (major
  47. * hardware flakeout), or the register reads as all-ones (hardware removed).
  48. */
  49. static int handshake(struct xhci_hcd *xhci, void __iomem *ptr,
  50. u32 mask, u32 done, int usec)
  51. {
  52. u32 result;
  53. do {
  54. result = xhci_readl(xhci, ptr);
  55. if (result == ~(u32)0) /* card removed */
  56. return -ENODEV;
  57. result &= mask;
  58. if (result == done)
  59. return 0;
  60. udelay(1);
  61. usec--;
  62. } while (usec > 0);
  63. return -ETIMEDOUT;
  64. }
  65. /*
  66. * Disable interrupts and begin the xHCI halting process.
  67. */
  68. void xhci_quiesce(struct xhci_hcd *xhci)
  69. {
  70. u32 halted;
  71. u32 cmd;
  72. u32 mask;
  73. mask = ~(XHCI_IRQS);
  74. halted = xhci_readl(xhci, &xhci->op_regs->status) & STS_HALT;
  75. if (!halted)
  76. mask &= ~CMD_RUN;
  77. cmd = xhci_readl(xhci, &xhci->op_regs->command);
  78. cmd &= mask;
  79. xhci_writel(xhci, cmd, &xhci->op_regs->command);
  80. }
  81. /*
  82. * Force HC into halt state.
  83. *
  84. * Disable any IRQs and clear the run/stop bit.
  85. * HC will complete any current and actively pipelined transactions, and
  86. * should halt within 16 microframes of the run/stop bit being cleared.
  87. * Read HC Halted bit in the status register to see when the HC is finished.
  88. * XXX: shouldn't we set HC_STATE_HALT here somewhere?
  89. */
  90. int xhci_halt(struct xhci_hcd *xhci)
  91. {
  92. xhci_dbg(xhci, "// Halt the HC\n");
  93. xhci_quiesce(xhci);
  94. return handshake(xhci, &xhci->op_regs->status,
  95. STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
  96. }
  97. /*
  98. * Set the run bit and wait for the host to be running.
  99. */
  100. int xhci_start(struct xhci_hcd *xhci)
  101. {
  102. u32 temp;
  103. int ret;
  104. temp = xhci_readl(xhci, &xhci->op_regs->command);
  105. temp |= (CMD_RUN);
  106. xhci_dbg(xhci, "// Turn on HC, cmd = 0x%x.\n",
  107. temp);
  108. xhci_writel(xhci, temp, &xhci->op_regs->command);
  109. /*
  110. * Wait for the HCHalted Status bit to be 0 to indicate the host is
  111. * running.
  112. */
  113. ret = handshake(xhci, &xhci->op_regs->status,
  114. STS_HALT, 0, XHCI_MAX_HALT_USEC);
  115. if (ret == -ETIMEDOUT)
  116. xhci_err(xhci, "Host took too long to start, "
  117. "waited %u microseconds.\n",
  118. XHCI_MAX_HALT_USEC);
  119. return ret;
  120. }
  121. /*
  122. * Reset a halted HC, and set the internal HC state to HC_STATE_HALT.
  123. *
  124. * This resets pipelines, timers, counters, state machines, etc.
  125. * Transactions will be terminated immediately, and operational registers
  126. * will be set to their defaults.
  127. */
  128. int xhci_reset(struct xhci_hcd *xhci)
  129. {
  130. u32 command;
  131. u32 state;
  132. int ret;
  133. state = xhci_readl(xhci, &xhci->op_regs->status);
  134. if ((state & STS_HALT) == 0) {
  135. xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
  136. return 0;
  137. }
  138. xhci_dbg(xhci, "// Reset the HC\n");
  139. command = xhci_readl(xhci, &xhci->op_regs->command);
  140. command |= CMD_RESET;
  141. xhci_writel(xhci, command, &xhci->op_regs->command);
  142. /* XXX: Why does EHCI set this here? Shouldn't other code do this? */
  143. xhci_to_hcd(xhci)->state = HC_STATE_HALT;
  144. ret = handshake(xhci, &xhci->op_regs->command,
  145. CMD_RESET, 0, 250 * 1000);
  146. if (ret)
  147. return ret;
  148. xhci_dbg(xhci, "Wait for controller to be ready for doorbell rings\n");
  149. /*
  150. * xHCI cannot write to any doorbells or operational registers other
  151. * than status until the "Controller Not Ready" flag is cleared.
  152. */
  153. return handshake(xhci, &xhci->op_regs->status, STS_CNR, 0, 250 * 1000);
  154. }
  155. /*
  156. * Free IRQs
  157. * free all IRQs request
  158. */
  159. static void xhci_free_irq(struct xhci_hcd *xhci)
  160. {
  161. int i;
  162. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  163. /* return if using legacy interrupt */
  164. if (xhci_to_hcd(xhci)->irq >= 0)
  165. return;
  166. if (xhci->msix_entries) {
  167. for (i = 0; i < xhci->msix_count; i++)
  168. if (xhci->msix_entries[i].vector)
  169. free_irq(xhci->msix_entries[i].vector,
  170. xhci_to_hcd(xhci));
  171. } else if (pdev->irq >= 0)
  172. free_irq(pdev->irq, xhci_to_hcd(xhci));
  173. return;
  174. }
  175. /*
  176. * Set up MSI
  177. */
  178. static int xhci_setup_msi(struct xhci_hcd *xhci)
  179. {
  180. int ret;
  181. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  182. ret = pci_enable_msi(pdev);
  183. if (ret) {
  184. xhci_err(xhci, "failed to allocate MSI entry\n");
  185. return ret;
  186. }
  187. ret = request_irq(pdev->irq, (irq_handler_t)xhci_msi_irq,
  188. 0, "xhci_hcd", xhci_to_hcd(xhci));
  189. if (ret) {
  190. xhci_err(xhci, "disable MSI interrupt\n");
  191. pci_disable_msi(pdev);
  192. }
  193. return ret;
  194. }
  195. /*
  196. * Set up MSI-X
  197. */
  198. static int xhci_setup_msix(struct xhci_hcd *xhci)
  199. {
  200. int i, ret = 0;
  201. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  202. /*
  203. * calculate number of msi-x vectors supported.
  204. * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
  205. * with max number of interrupters based on the xhci HCSPARAMS1.
  206. * - num_online_cpus: maximum msi-x vectors per CPUs core.
  207. * Add additional 1 vector to ensure always available interrupt.
  208. */
  209. xhci->msix_count = min(num_online_cpus() + 1,
  210. HCS_MAX_INTRS(xhci->hcs_params1));
  211. xhci->msix_entries =
  212. kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
  213. GFP_KERNEL);
  214. if (!xhci->msix_entries) {
  215. xhci_err(xhci, "Failed to allocate MSI-X entries\n");
  216. return -ENOMEM;
  217. }
  218. for (i = 0; i < xhci->msix_count; i++) {
  219. xhci->msix_entries[i].entry = i;
  220. xhci->msix_entries[i].vector = 0;
  221. }
  222. ret = pci_enable_msix(pdev, xhci->msix_entries, xhci->msix_count);
  223. if (ret) {
  224. xhci_err(xhci, "Failed to enable MSI-X\n");
  225. goto free_entries;
  226. }
  227. for (i = 0; i < xhci->msix_count; i++) {
  228. ret = request_irq(xhci->msix_entries[i].vector,
  229. (irq_handler_t)xhci_msi_irq,
  230. 0, "xhci_hcd", xhci_to_hcd(xhci));
  231. if (ret)
  232. goto disable_msix;
  233. }
  234. return ret;
  235. disable_msix:
  236. xhci_err(xhci, "disable MSI-X interrupt\n");
  237. xhci_free_irq(xhci);
  238. pci_disable_msix(pdev);
  239. free_entries:
  240. kfree(xhci->msix_entries);
  241. xhci->msix_entries = NULL;
  242. return ret;
  243. }
  244. /* Free any IRQs and disable MSI-X */
  245. static void xhci_cleanup_msix(struct xhci_hcd *xhci)
  246. {
  247. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  248. xhci_free_irq(xhci);
  249. if (xhci->msix_entries) {
  250. pci_disable_msix(pdev);
  251. kfree(xhci->msix_entries);
  252. xhci->msix_entries = NULL;
  253. } else {
  254. pci_disable_msi(pdev);
  255. }
  256. return;
  257. }
  258. /*
  259. * Initialize memory for HCD and xHC (one-time init).
  260. *
  261. * Program the PAGESIZE register, initialize the device context array, create
  262. * device contexts (?), set up a command ring segment (or two?), create event
  263. * ring (one for now).
  264. */
  265. int xhci_init(struct usb_hcd *hcd)
  266. {
  267. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  268. int retval = 0;
  269. xhci_dbg(xhci, "xhci_init\n");
  270. spin_lock_init(&xhci->lock);
  271. if (link_quirk) {
  272. xhci_dbg(xhci, "QUIRK: Not clearing Link TRB chain bits.\n");
  273. xhci->quirks |= XHCI_LINK_TRB_QUIRK;
  274. } else {
  275. xhci_dbg(xhci, "xHCI doesn't need link TRB QUIRK\n");
  276. }
  277. retval = xhci_mem_init(xhci, GFP_KERNEL);
  278. xhci_dbg(xhci, "Finished xhci_init\n");
  279. return retval;
  280. }
  281. /*-------------------------------------------------------------------------*/
  282. #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
  283. void xhci_event_ring_work(unsigned long arg)
  284. {
  285. unsigned long flags;
  286. int temp;
  287. u64 temp_64;
  288. struct xhci_hcd *xhci = (struct xhci_hcd *) arg;
  289. int i, j;
  290. xhci_dbg(xhci, "Poll event ring: %lu\n", jiffies);
  291. spin_lock_irqsave(&xhci->lock, flags);
  292. temp = xhci_readl(xhci, &xhci->op_regs->status);
  293. xhci_dbg(xhci, "op reg status = 0x%x\n", temp);
  294. if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING)) {
  295. xhci_dbg(xhci, "HW died, polling stopped.\n");
  296. spin_unlock_irqrestore(&xhci->lock, flags);
  297. return;
  298. }
  299. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  300. xhci_dbg(xhci, "ir_set 0 pending = 0x%x\n", temp);
  301. xhci_dbg(xhci, "No-op commands handled = %d\n", xhci->noops_handled);
  302. xhci_dbg(xhci, "HC error bitmask = 0x%x\n", xhci->error_bitmask);
  303. xhci->error_bitmask = 0;
  304. xhci_dbg(xhci, "Event ring:\n");
  305. xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
  306. xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
  307. temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
  308. temp_64 &= ~ERST_PTR_MASK;
  309. xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
  310. xhci_dbg(xhci, "Command ring:\n");
  311. xhci_debug_segment(xhci, xhci->cmd_ring->deq_seg);
  312. xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
  313. xhci_dbg_cmd_ptrs(xhci);
  314. for (i = 0; i < MAX_HC_SLOTS; ++i) {
  315. if (!xhci->devs[i])
  316. continue;
  317. for (j = 0; j < 31; ++j) {
  318. xhci_dbg_ep_rings(xhci, i, j, &xhci->devs[i]->eps[j]);
  319. }
  320. }
  321. if (xhci->noops_submitted != NUM_TEST_NOOPS)
  322. if (xhci_setup_one_noop(xhci))
  323. xhci_ring_cmd_db(xhci);
  324. spin_unlock_irqrestore(&xhci->lock, flags);
  325. if (!xhci->zombie)
  326. mod_timer(&xhci->event_ring_timer, jiffies + POLL_TIMEOUT * HZ);
  327. else
  328. xhci_dbg(xhci, "Quit polling the event ring.\n");
  329. }
  330. #endif
  331. /*
  332. * Start the HC after it was halted.
  333. *
  334. * This function is called by the USB core when the HC driver is added.
  335. * Its opposite is xhci_stop().
  336. *
  337. * xhci_init() must be called once before this function can be called.
  338. * Reset the HC, enable device slot contexts, program DCBAAP, and
  339. * set command ring pointer and event ring pointer.
  340. *
  341. * Setup MSI-X vectors and enable interrupts.
  342. */
  343. int xhci_run(struct usb_hcd *hcd)
  344. {
  345. u32 temp;
  346. u64 temp_64;
  347. u32 ret;
  348. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  349. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  350. void (*doorbell)(struct xhci_hcd *) = NULL;
  351. hcd->uses_new_polling = 1;
  352. xhci_dbg(xhci, "xhci_run\n");
  353. /* unregister the legacy interrupt */
  354. if (hcd->irq)
  355. free_irq(hcd->irq, hcd);
  356. hcd->irq = -1;
  357. ret = xhci_setup_msix(xhci);
  358. if (ret)
  359. /* fall back to msi*/
  360. ret = xhci_setup_msi(xhci);
  361. if (ret) {
  362. /* fall back to legacy interrupt*/
  363. ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
  364. hcd->irq_descr, hcd);
  365. if (ret) {
  366. xhci_err(xhci, "request interrupt %d failed\n",
  367. pdev->irq);
  368. return ret;
  369. }
  370. hcd->irq = pdev->irq;
  371. }
  372. #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
  373. init_timer(&xhci->event_ring_timer);
  374. xhci->event_ring_timer.data = (unsigned long) xhci;
  375. xhci->event_ring_timer.function = xhci_event_ring_work;
  376. /* Poll the event ring */
  377. xhci->event_ring_timer.expires = jiffies + POLL_TIMEOUT * HZ;
  378. xhci->zombie = 0;
  379. xhci_dbg(xhci, "Setting event ring polling timer\n");
  380. add_timer(&xhci->event_ring_timer);
  381. #endif
  382. xhci_dbg(xhci, "Command ring memory map follows:\n");
  383. xhci_debug_ring(xhci, xhci->cmd_ring);
  384. xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
  385. xhci_dbg_cmd_ptrs(xhci);
  386. xhci_dbg(xhci, "ERST memory map follows:\n");
  387. xhci_dbg_erst(xhci, &xhci->erst);
  388. xhci_dbg(xhci, "Event ring:\n");
  389. xhci_debug_ring(xhci, xhci->event_ring);
  390. xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
  391. temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
  392. temp_64 &= ~ERST_PTR_MASK;
  393. xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
  394. xhci_dbg(xhci, "// Set the interrupt modulation register\n");
  395. temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
  396. temp &= ~ER_IRQ_INTERVAL_MASK;
  397. temp |= (u32) 160;
  398. xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
  399. /* Set the HCD state before we enable the irqs */
  400. hcd->state = HC_STATE_RUNNING;
  401. temp = xhci_readl(xhci, &xhci->op_regs->command);
  402. temp |= (CMD_EIE);
  403. xhci_dbg(xhci, "// Enable interrupts, cmd = 0x%x.\n",
  404. temp);
  405. xhci_writel(xhci, temp, &xhci->op_regs->command);
  406. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  407. xhci_dbg(xhci, "// Enabling event ring interrupter %p by writing 0x%x to irq_pending\n",
  408. xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
  409. xhci_writel(xhci, ER_IRQ_ENABLE(temp),
  410. &xhci->ir_set->irq_pending);
  411. xhci_print_ir_set(xhci, xhci->ir_set, 0);
  412. if (NUM_TEST_NOOPS > 0)
  413. doorbell = xhci_setup_one_noop(xhci);
  414. if (xhci->quirks & XHCI_NEC_HOST)
  415. xhci_queue_vendor_command(xhci, 0, 0, 0,
  416. TRB_TYPE(TRB_NEC_GET_FW));
  417. if (xhci_start(xhci)) {
  418. xhci_halt(xhci);
  419. return -ENODEV;
  420. }
  421. if (doorbell)
  422. (*doorbell)(xhci);
  423. if (xhci->quirks & XHCI_NEC_HOST)
  424. xhci_ring_cmd_db(xhci);
  425. xhci_dbg(xhci, "Finished xhci_run\n");
  426. return 0;
  427. }
  428. /*
  429. * Stop xHCI driver.
  430. *
  431. * This function is called by the USB core when the HC driver is removed.
  432. * Its opposite is xhci_run().
  433. *
  434. * Disable device contexts, disable IRQs, and quiesce the HC.
  435. * Reset the HC, finish any completed transactions, and cleanup memory.
  436. */
  437. void xhci_stop(struct usb_hcd *hcd)
  438. {
  439. u32 temp;
  440. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  441. spin_lock_irq(&xhci->lock);
  442. xhci_halt(xhci);
  443. xhci_reset(xhci);
  444. xhci_cleanup_msix(xhci);
  445. spin_unlock_irq(&xhci->lock);
  446. #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
  447. /* Tell the event ring poll function not to reschedule */
  448. xhci->zombie = 1;
  449. del_timer_sync(&xhci->event_ring_timer);
  450. #endif
  451. xhci_dbg(xhci, "// Disabling event ring interrupts\n");
  452. temp = xhci_readl(xhci, &xhci->op_regs->status);
  453. xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
  454. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  455. xhci_writel(xhci, ER_IRQ_DISABLE(temp),
  456. &xhci->ir_set->irq_pending);
  457. xhci_print_ir_set(xhci, xhci->ir_set, 0);
  458. xhci_dbg(xhci, "cleaning up memory\n");
  459. xhci_mem_cleanup(xhci);
  460. xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
  461. xhci_readl(xhci, &xhci->op_regs->status));
  462. }
  463. /*
  464. * Shutdown HC (not bus-specific)
  465. *
  466. * This is called when the machine is rebooting or halting. We assume that the
  467. * machine will be powered off, and the HC's internal state will be reset.
  468. * Don't bother to free memory.
  469. */
  470. void xhci_shutdown(struct usb_hcd *hcd)
  471. {
  472. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  473. spin_lock_irq(&xhci->lock);
  474. xhci_halt(xhci);
  475. xhci_cleanup_msix(xhci);
  476. spin_unlock_irq(&xhci->lock);
  477. xhci_dbg(xhci, "xhci_shutdown completed - status = %x\n",
  478. xhci_readl(xhci, &xhci->op_regs->status));
  479. }
  480. /*-------------------------------------------------------------------------*/
  481. /**
  482. * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
  483. * HCDs. Find the index for an endpoint given its descriptor. Use the return
  484. * value to right shift 1 for the bitmask.
  485. *
  486. * Index = (epnum * 2) + direction - 1,
  487. * where direction = 0 for OUT, 1 for IN.
  488. * For control endpoints, the IN index is used (OUT index is unused), so
  489. * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
  490. */
  491. unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
  492. {
  493. unsigned int index;
  494. if (usb_endpoint_xfer_control(desc))
  495. index = (unsigned int) (usb_endpoint_num(desc)*2);
  496. else
  497. index = (unsigned int) (usb_endpoint_num(desc)*2) +
  498. (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
  499. return index;
  500. }
  501. /* Find the flag for this endpoint (for use in the control context). Use the
  502. * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
  503. * bit 1, etc.
  504. */
  505. unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
  506. {
  507. return 1 << (xhci_get_endpoint_index(desc) + 1);
  508. }
  509. /* Find the flag for this endpoint (for use in the control context). Use the
  510. * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
  511. * bit 1, etc.
  512. */
  513. unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
  514. {
  515. return 1 << (ep_index + 1);
  516. }
  517. /* Compute the last valid endpoint context index. Basically, this is the
  518. * endpoint index plus one. For slot contexts with more than valid endpoint,
  519. * we find the most significant bit set in the added contexts flags.
  520. * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
  521. * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
  522. */
  523. unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
  524. {
  525. return fls(added_ctxs) - 1;
  526. }
  527. /* Returns 1 if the arguments are OK;
  528. * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
  529. */
  530. int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
  531. struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
  532. const char *func) {
  533. struct xhci_hcd *xhci;
  534. struct xhci_virt_device *virt_dev;
  535. if (!hcd || (check_ep && !ep) || !udev) {
  536. printk(KERN_DEBUG "xHCI %s called with invalid args\n",
  537. func);
  538. return -EINVAL;
  539. }
  540. if (!udev->parent) {
  541. printk(KERN_DEBUG "xHCI %s called for root hub\n",
  542. func);
  543. return 0;
  544. }
  545. if (check_virt_dev) {
  546. xhci = hcd_to_xhci(hcd);
  547. if (!udev->slot_id || !xhci->devs
  548. || !xhci->devs[udev->slot_id]) {
  549. printk(KERN_DEBUG "xHCI %s called with unaddressed "
  550. "device\n", func);
  551. return -EINVAL;
  552. }
  553. virt_dev = xhci->devs[udev->slot_id];
  554. if (virt_dev->udev != udev) {
  555. printk(KERN_DEBUG "xHCI %s called with udev and "
  556. "virt_dev does not match\n", func);
  557. return -EINVAL;
  558. }
  559. }
  560. return 1;
  561. }
  562. static int xhci_configure_endpoint(struct xhci_hcd *xhci,
  563. struct usb_device *udev, struct xhci_command *command,
  564. bool ctx_change, bool must_succeed);
  565. /*
  566. * Full speed devices may have a max packet size greater than 8 bytes, but the
  567. * USB core doesn't know that until it reads the first 8 bytes of the
  568. * descriptor. If the usb_device's max packet size changes after that point,
  569. * we need to issue an evaluate context command and wait on it.
  570. */
  571. static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
  572. unsigned int ep_index, struct urb *urb)
  573. {
  574. struct xhci_container_ctx *in_ctx;
  575. struct xhci_container_ctx *out_ctx;
  576. struct xhci_input_control_ctx *ctrl_ctx;
  577. struct xhci_ep_ctx *ep_ctx;
  578. int max_packet_size;
  579. int hw_max_packet_size;
  580. int ret = 0;
  581. out_ctx = xhci->devs[slot_id]->out_ctx;
  582. ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
  583. hw_max_packet_size = MAX_PACKET_DECODED(ep_ctx->ep_info2);
  584. max_packet_size = urb->dev->ep0.desc.wMaxPacketSize;
  585. if (hw_max_packet_size != max_packet_size) {
  586. xhci_dbg(xhci, "Max Packet Size for ep 0 changed.\n");
  587. xhci_dbg(xhci, "Max packet size in usb_device = %d\n",
  588. max_packet_size);
  589. xhci_dbg(xhci, "Max packet size in xHCI HW = %d\n",
  590. hw_max_packet_size);
  591. xhci_dbg(xhci, "Issuing evaluate context command.\n");
  592. /* Set up the modified control endpoint 0 */
  593. xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
  594. xhci->devs[slot_id]->out_ctx, ep_index);
  595. in_ctx = xhci->devs[slot_id]->in_ctx;
  596. ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
  597. ep_ctx->ep_info2 &= ~MAX_PACKET_MASK;
  598. ep_ctx->ep_info2 |= MAX_PACKET(max_packet_size);
  599. /* Set up the input context flags for the command */
  600. /* FIXME: This won't work if a non-default control endpoint
  601. * changes max packet sizes.
  602. */
  603. ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
  604. ctrl_ctx->add_flags = EP0_FLAG;
  605. ctrl_ctx->drop_flags = 0;
  606. xhci_dbg(xhci, "Slot %d input context\n", slot_id);
  607. xhci_dbg_ctx(xhci, in_ctx, ep_index);
  608. xhci_dbg(xhci, "Slot %d output context\n", slot_id);
  609. xhci_dbg_ctx(xhci, out_ctx, ep_index);
  610. ret = xhci_configure_endpoint(xhci, urb->dev, NULL,
  611. true, false);
  612. /* Clean up the input context for later use by bandwidth
  613. * functions.
  614. */
  615. ctrl_ctx->add_flags = SLOT_FLAG;
  616. }
  617. return ret;
  618. }
  619. /*
  620. * non-error returns are a promise to giveback() the urb later
  621. * we drop ownership so next owner (or urb unlink) can get it
  622. */
  623. int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
  624. {
  625. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  626. unsigned long flags;
  627. int ret = 0;
  628. unsigned int slot_id, ep_index;
  629. struct urb_priv *urb_priv;
  630. int size, i;
  631. if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
  632. true, true, __func__) <= 0)
  633. return -EINVAL;
  634. slot_id = urb->dev->slot_id;
  635. ep_index = xhci_get_endpoint_index(&urb->ep->desc);
  636. if (!HCD_HW_ACCESSIBLE(hcd)) {
  637. if (!in_interrupt())
  638. xhci_dbg(xhci, "urb submitted during PCI suspend\n");
  639. ret = -ESHUTDOWN;
  640. goto exit;
  641. }
  642. if (usb_endpoint_xfer_isoc(&urb->ep->desc))
  643. size = urb->number_of_packets;
  644. else
  645. size = 1;
  646. urb_priv = kzalloc(sizeof(struct urb_priv) +
  647. size * sizeof(struct xhci_td *), mem_flags);
  648. if (!urb_priv)
  649. return -ENOMEM;
  650. for (i = 0; i < size; i++) {
  651. urb_priv->td[i] = kzalloc(sizeof(struct xhci_td), mem_flags);
  652. if (!urb_priv->td[i]) {
  653. urb_priv->length = i;
  654. xhci_urb_free_priv(xhci, urb_priv);
  655. return -ENOMEM;
  656. }
  657. }
  658. urb_priv->length = size;
  659. urb_priv->td_cnt = 0;
  660. urb->hcpriv = urb_priv;
  661. if (usb_endpoint_xfer_control(&urb->ep->desc)) {
  662. /* Check to see if the max packet size for the default control
  663. * endpoint changed during FS device enumeration
  664. */
  665. if (urb->dev->speed == USB_SPEED_FULL) {
  666. ret = xhci_check_maxpacket(xhci, slot_id,
  667. ep_index, urb);
  668. if (ret < 0)
  669. return ret;
  670. }
  671. /* We have a spinlock and interrupts disabled, so we must pass
  672. * atomic context to this function, which may allocate memory.
  673. */
  674. spin_lock_irqsave(&xhci->lock, flags);
  675. if (xhci->xhc_state & XHCI_STATE_DYING)
  676. goto dying;
  677. ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
  678. slot_id, ep_index);
  679. spin_unlock_irqrestore(&xhci->lock, flags);
  680. } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
  681. spin_lock_irqsave(&xhci->lock, flags);
  682. if (xhci->xhc_state & XHCI_STATE_DYING)
  683. goto dying;
  684. if (xhci->devs[slot_id]->eps[ep_index].ep_state &
  685. EP_GETTING_STREAMS) {
  686. xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
  687. "is transitioning to using streams.\n");
  688. ret = -EINVAL;
  689. } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
  690. EP_GETTING_NO_STREAMS) {
  691. xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
  692. "is transitioning to "
  693. "not having streams.\n");
  694. ret = -EINVAL;
  695. } else {
  696. ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
  697. slot_id, ep_index);
  698. }
  699. spin_unlock_irqrestore(&xhci->lock, flags);
  700. } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
  701. spin_lock_irqsave(&xhci->lock, flags);
  702. if (xhci->xhc_state & XHCI_STATE_DYING)
  703. goto dying;
  704. ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
  705. slot_id, ep_index);
  706. spin_unlock_irqrestore(&xhci->lock, flags);
  707. } else {
  708. spin_lock_irqsave(&xhci->lock, flags);
  709. if (xhci->xhc_state & XHCI_STATE_DYING)
  710. goto dying;
  711. ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
  712. slot_id, ep_index);
  713. spin_unlock_irqrestore(&xhci->lock, flags);
  714. }
  715. exit:
  716. return ret;
  717. dying:
  718. xhci_urb_free_priv(xhci, urb_priv);
  719. urb->hcpriv = NULL;
  720. xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
  721. "non-responsive xHCI host.\n",
  722. urb->ep->desc.bEndpointAddress, urb);
  723. spin_unlock_irqrestore(&xhci->lock, flags);
  724. return -ESHUTDOWN;
  725. }
  726. /* Get the right ring for the given URB.
  727. * If the endpoint supports streams, boundary check the URB's stream ID.
  728. * If the endpoint doesn't support streams, return the singular endpoint ring.
  729. */
  730. static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
  731. struct urb *urb)
  732. {
  733. unsigned int slot_id;
  734. unsigned int ep_index;
  735. unsigned int stream_id;
  736. struct xhci_virt_ep *ep;
  737. slot_id = urb->dev->slot_id;
  738. ep_index = xhci_get_endpoint_index(&urb->ep->desc);
  739. stream_id = urb->stream_id;
  740. ep = &xhci->devs[slot_id]->eps[ep_index];
  741. /* Common case: no streams */
  742. if (!(ep->ep_state & EP_HAS_STREAMS))
  743. return ep->ring;
  744. if (stream_id == 0) {
  745. xhci_warn(xhci,
  746. "WARN: Slot ID %u, ep index %u has streams, "
  747. "but URB has no stream ID.\n",
  748. slot_id, ep_index);
  749. return NULL;
  750. }
  751. if (stream_id < ep->stream_info->num_streams)
  752. return ep->stream_info->stream_rings[stream_id];
  753. xhci_warn(xhci,
  754. "WARN: Slot ID %u, ep index %u has "
  755. "stream IDs 1 to %u allocated, "
  756. "but stream ID %u is requested.\n",
  757. slot_id, ep_index,
  758. ep->stream_info->num_streams - 1,
  759. stream_id);
  760. return NULL;
  761. }
  762. /*
  763. * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
  764. * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
  765. * should pick up where it left off in the TD, unless a Set Transfer Ring
  766. * Dequeue Pointer is issued.
  767. *
  768. * The TRBs that make up the buffers for the canceled URB will be "removed" from
  769. * the ring. Since the ring is a contiguous structure, they can't be physically
  770. * removed. Instead, there are two options:
  771. *
  772. * 1) If the HC is in the middle of processing the URB to be canceled, we
  773. * simply move the ring's dequeue pointer past those TRBs using the Set
  774. * Transfer Ring Dequeue Pointer command. This will be the common case,
  775. * when drivers timeout on the last submitted URB and attempt to cancel.
  776. *
  777. * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
  778. * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
  779. * HC will need to invalidate the any TRBs it has cached after the stop
  780. * endpoint command, as noted in the xHCI 0.95 errata.
  781. *
  782. * 3) The TD may have completed by the time the Stop Endpoint Command
  783. * completes, so software needs to handle that case too.
  784. *
  785. * This function should protect against the TD enqueueing code ringing the
  786. * doorbell while this code is waiting for a Stop Endpoint command to complete.
  787. * It also needs to account for multiple cancellations on happening at the same
  788. * time for the same endpoint.
  789. *
  790. * Note that this function can be called in any context, or so says
  791. * usb_hcd_unlink_urb()
  792. */
  793. int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
  794. {
  795. unsigned long flags;
  796. int ret, i;
  797. u32 temp;
  798. struct xhci_hcd *xhci;
  799. struct urb_priv *urb_priv;
  800. struct xhci_td *td;
  801. unsigned int ep_index;
  802. struct xhci_ring *ep_ring;
  803. struct xhci_virt_ep *ep;
  804. xhci = hcd_to_xhci(hcd);
  805. spin_lock_irqsave(&xhci->lock, flags);
  806. /* Make sure the URB hasn't completed or been unlinked already */
  807. ret = usb_hcd_check_unlink_urb(hcd, urb, status);
  808. if (ret || !urb->hcpriv)
  809. goto done;
  810. temp = xhci_readl(xhci, &xhci->op_regs->status);
  811. if (temp == 0xffffffff) {
  812. xhci_dbg(xhci, "HW died, freeing TD.\n");
  813. urb_priv = urb->hcpriv;
  814. usb_hcd_unlink_urb_from_ep(hcd, urb);
  815. spin_unlock_irqrestore(&xhci->lock, flags);
  816. usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, -ESHUTDOWN);
  817. xhci_urb_free_priv(xhci, urb_priv);
  818. return ret;
  819. }
  820. if (xhci->xhc_state & XHCI_STATE_DYING) {
  821. xhci_dbg(xhci, "Ep 0x%x: URB %p to be canceled on "
  822. "non-responsive xHCI host.\n",
  823. urb->ep->desc.bEndpointAddress, urb);
  824. /* Let the stop endpoint command watchdog timer (which set this
  825. * state) finish cleaning up the endpoint TD lists. We must
  826. * have caught it in the middle of dropping a lock and giving
  827. * back an URB.
  828. */
  829. goto done;
  830. }
  831. xhci_dbg(xhci, "Cancel URB %p\n", urb);
  832. xhci_dbg(xhci, "Event ring:\n");
  833. xhci_debug_ring(xhci, xhci->event_ring);
  834. ep_index = xhci_get_endpoint_index(&urb->ep->desc);
  835. ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
  836. ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
  837. if (!ep_ring) {
  838. ret = -EINVAL;
  839. goto done;
  840. }
  841. xhci_dbg(xhci, "Endpoint ring:\n");
  842. xhci_debug_ring(xhci, ep_ring);
  843. urb_priv = urb->hcpriv;
  844. for (i = urb_priv->td_cnt; i < urb_priv->length; i++) {
  845. td = urb_priv->td[i];
  846. list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
  847. }
  848. /* Queue a stop endpoint command, but only if this is
  849. * the first cancellation to be handled.
  850. */
  851. if (!(ep->ep_state & EP_HALT_PENDING)) {
  852. ep->ep_state |= EP_HALT_PENDING;
  853. ep->stop_cmds_pending++;
  854. ep->stop_cmd_timer.expires = jiffies +
  855. XHCI_STOP_EP_CMD_TIMEOUT * HZ;
  856. add_timer(&ep->stop_cmd_timer);
  857. xhci_queue_stop_endpoint(xhci, urb->dev->slot_id, ep_index);
  858. xhci_ring_cmd_db(xhci);
  859. }
  860. done:
  861. spin_unlock_irqrestore(&xhci->lock, flags);
  862. return ret;
  863. }
  864. /* Drop an endpoint from a new bandwidth configuration for this device.
  865. * Only one call to this function is allowed per endpoint before
  866. * check_bandwidth() or reset_bandwidth() must be called.
  867. * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
  868. * add the endpoint to the schedule with possibly new parameters denoted by a
  869. * different endpoint descriptor in usb_host_endpoint.
  870. * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
  871. * not allowed.
  872. *
  873. * The USB core will not allow URBs to be queued to an endpoint that is being
  874. * disabled, so there's no need for mutual exclusion to protect
  875. * the xhci->devs[slot_id] structure.
  876. */
  877. int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
  878. struct usb_host_endpoint *ep)
  879. {
  880. struct xhci_hcd *xhci;
  881. struct xhci_container_ctx *in_ctx, *out_ctx;
  882. struct xhci_input_control_ctx *ctrl_ctx;
  883. struct xhci_slot_ctx *slot_ctx;
  884. unsigned int last_ctx;
  885. unsigned int ep_index;
  886. struct xhci_ep_ctx *ep_ctx;
  887. u32 drop_flag;
  888. u32 new_add_flags, new_drop_flags, new_slot_info;
  889. int ret;
  890. ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
  891. if (ret <= 0)
  892. return ret;
  893. xhci = hcd_to_xhci(hcd);
  894. xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
  895. drop_flag = xhci_get_endpoint_flag(&ep->desc);
  896. if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
  897. xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
  898. __func__, drop_flag);
  899. return 0;
  900. }
  901. in_ctx = xhci->devs[udev->slot_id]->in_ctx;
  902. out_ctx = xhci->devs[udev->slot_id]->out_ctx;
  903. ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
  904. ep_index = xhci_get_endpoint_index(&ep->desc);
  905. ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
  906. /* If the HC already knows the endpoint is disabled,
  907. * or the HCD has noted it is disabled, ignore this request
  908. */
  909. if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED ||
  910. ctrl_ctx->drop_flags & xhci_get_endpoint_flag(&ep->desc)) {
  911. xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
  912. __func__, ep);
  913. return 0;
  914. }
  915. ctrl_ctx->drop_flags |= drop_flag;
  916. new_drop_flags = ctrl_ctx->drop_flags;
  917. ctrl_ctx->add_flags &= ~drop_flag;
  918. new_add_flags = ctrl_ctx->add_flags;
  919. last_ctx = xhci_last_valid_endpoint(ctrl_ctx->add_flags);
  920. slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
  921. /* Update the last valid endpoint context, if we deleted the last one */
  922. if ((slot_ctx->dev_info & LAST_CTX_MASK) > LAST_CTX(last_ctx)) {
  923. slot_ctx->dev_info &= ~LAST_CTX_MASK;
  924. slot_ctx->dev_info |= LAST_CTX(last_ctx);
  925. }
  926. new_slot_info = slot_ctx->dev_info;
  927. xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
  928. xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
  929. (unsigned int) ep->desc.bEndpointAddress,
  930. udev->slot_id,
  931. (unsigned int) new_drop_flags,
  932. (unsigned int) new_add_flags,
  933. (unsigned int) new_slot_info);
  934. return 0;
  935. }
  936. /* Add an endpoint to a new possible bandwidth configuration for this device.
  937. * Only one call to this function is allowed per endpoint before
  938. * check_bandwidth() or reset_bandwidth() must be called.
  939. * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
  940. * add the endpoint to the schedule with possibly new parameters denoted by a
  941. * different endpoint descriptor in usb_host_endpoint.
  942. * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
  943. * not allowed.
  944. *
  945. * The USB core will not allow URBs to be queued to an endpoint until the
  946. * configuration or alt setting is installed in the device, so there's no need
  947. * for mutual exclusion to protect the xhci->devs[slot_id] structure.
  948. */
  949. int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
  950. struct usb_host_endpoint *ep)
  951. {
  952. struct xhci_hcd *xhci;
  953. struct xhci_container_ctx *in_ctx, *out_ctx;
  954. unsigned int ep_index;
  955. struct xhci_ep_ctx *ep_ctx;
  956. struct xhci_slot_ctx *slot_ctx;
  957. struct xhci_input_control_ctx *ctrl_ctx;
  958. u32 added_ctxs;
  959. unsigned int last_ctx;
  960. u32 new_add_flags, new_drop_flags, new_slot_info;
  961. int ret = 0;
  962. ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
  963. if (ret <= 0) {
  964. /* So we won't queue a reset ep command for a root hub */
  965. ep->hcpriv = NULL;
  966. return ret;
  967. }
  968. xhci = hcd_to_xhci(hcd);
  969. added_ctxs = xhci_get_endpoint_flag(&ep->desc);
  970. last_ctx = xhci_last_valid_endpoint(added_ctxs);
  971. if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
  972. /* FIXME when we have to issue an evaluate endpoint command to
  973. * deal with ep0 max packet size changing once we get the
  974. * descriptors
  975. */
  976. xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
  977. __func__, added_ctxs);
  978. return 0;
  979. }
  980. in_ctx = xhci->devs[udev->slot_id]->in_ctx;
  981. out_ctx = xhci->devs[udev->slot_id]->out_ctx;
  982. ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
  983. ep_index = xhci_get_endpoint_index(&ep->desc);
  984. ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
  985. /* If the HCD has already noted the endpoint is enabled,
  986. * ignore this request.
  987. */
  988. if (ctrl_ctx->add_flags & xhci_get_endpoint_flag(&ep->desc)) {
  989. xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
  990. __func__, ep);
  991. return 0;
  992. }
  993. /*
  994. * Configuration and alternate setting changes must be done in
  995. * process context, not interrupt context (or so documenation
  996. * for usb_set_interface() and usb_set_configuration() claim).
  997. */
  998. if (xhci_endpoint_init(xhci, xhci->devs[udev->slot_id],
  999. udev, ep, GFP_NOIO) < 0) {
  1000. dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
  1001. __func__, ep->desc.bEndpointAddress);
  1002. return -ENOMEM;
  1003. }
  1004. ctrl_ctx->add_flags |= added_ctxs;
  1005. new_add_flags = ctrl_ctx->add_flags;
  1006. /* If xhci_endpoint_disable() was called for this endpoint, but the
  1007. * xHC hasn't been notified yet through the check_bandwidth() call,
  1008. * this re-adds a new state for the endpoint from the new endpoint
  1009. * descriptors. We must drop and re-add this endpoint, so we leave the
  1010. * drop flags alone.
  1011. */
  1012. new_drop_flags = ctrl_ctx->drop_flags;
  1013. slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
  1014. /* Update the last valid endpoint context, if we just added one past */
  1015. if ((slot_ctx->dev_info & LAST_CTX_MASK) < LAST_CTX(last_ctx)) {
  1016. slot_ctx->dev_info &= ~LAST_CTX_MASK;
  1017. slot_ctx->dev_info |= LAST_CTX(last_ctx);
  1018. }
  1019. new_slot_info = slot_ctx->dev_info;
  1020. /* Store the usb_device pointer for later use */
  1021. ep->hcpriv = udev;
  1022. xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
  1023. (unsigned int) ep->desc.bEndpointAddress,
  1024. udev->slot_id,
  1025. (unsigned int) new_drop_flags,
  1026. (unsigned int) new_add_flags,
  1027. (unsigned int) new_slot_info);
  1028. return 0;
  1029. }
  1030. static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
  1031. {
  1032. struct xhci_input_control_ctx *ctrl_ctx;
  1033. struct xhci_ep_ctx *ep_ctx;
  1034. struct xhci_slot_ctx *slot_ctx;
  1035. int i;
  1036. /* When a device's add flag and drop flag are zero, any subsequent
  1037. * configure endpoint command will leave that endpoint's state
  1038. * untouched. Make sure we don't leave any old state in the input
  1039. * endpoint contexts.
  1040. */
  1041. ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
  1042. ctrl_ctx->drop_flags = 0;
  1043. ctrl_ctx->add_flags = 0;
  1044. slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
  1045. slot_ctx->dev_info &= ~LAST_CTX_MASK;
  1046. /* Endpoint 0 is always valid */
  1047. slot_ctx->dev_info |= LAST_CTX(1);
  1048. for (i = 1; i < 31; ++i) {
  1049. ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
  1050. ep_ctx->ep_info = 0;
  1051. ep_ctx->ep_info2 = 0;
  1052. ep_ctx->deq = 0;
  1053. ep_ctx->tx_info = 0;
  1054. }
  1055. }
  1056. static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
  1057. struct usb_device *udev, int *cmd_status)
  1058. {
  1059. int ret;
  1060. switch (*cmd_status) {
  1061. case COMP_ENOMEM:
  1062. dev_warn(&udev->dev, "Not enough host controller resources "
  1063. "for new device state.\n");
  1064. ret = -ENOMEM;
  1065. /* FIXME: can we allocate more resources for the HC? */
  1066. break;
  1067. case COMP_BW_ERR:
  1068. dev_warn(&udev->dev, "Not enough bandwidth "
  1069. "for new device state.\n");
  1070. ret = -ENOSPC;
  1071. /* FIXME: can we go back to the old state? */
  1072. break;
  1073. case COMP_TRB_ERR:
  1074. /* the HCD set up something wrong */
  1075. dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
  1076. "add flag = 1, "
  1077. "and endpoint is not disabled.\n");
  1078. ret = -EINVAL;
  1079. break;
  1080. case COMP_SUCCESS:
  1081. dev_dbg(&udev->dev, "Successful Endpoint Configure command\n");
  1082. ret = 0;
  1083. break;
  1084. default:
  1085. xhci_err(xhci, "ERROR: unexpected command completion "
  1086. "code 0x%x.\n", *cmd_status);
  1087. ret = -EINVAL;
  1088. break;
  1089. }
  1090. return ret;
  1091. }
  1092. static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
  1093. struct usb_device *udev, int *cmd_status)
  1094. {
  1095. int ret;
  1096. struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
  1097. switch (*cmd_status) {
  1098. case COMP_EINVAL:
  1099. dev_warn(&udev->dev, "WARN: xHCI driver setup invalid evaluate "
  1100. "context command.\n");
  1101. ret = -EINVAL;
  1102. break;
  1103. case COMP_EBADSLT:
  1104. dev_warn(&udev->dev, "WARN: slot not enabled for"
  1105. "evaluate context command.\n");
  1106. case COMP_CTX_STATE:
  1107. dev_warn(&udev->dev, "WARN: invalid context state for "
  1108. "evaluate context command.\n");
  1109. xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
  1110. ret = -EINVAL;
  1111. break;
  1112. case COMP_SUCCESS:
  1113. dev_dbg(&udev->dev, "Successful evaluate context command\n");
  1114. ret = 0;
  1115. break;
  1116. default:
  1117. xhci_err(xhci, "ERROR: unexpected command completion "
  1118. "code 0x%x.\n", *cmd_status);
  1119. ret = -EINVAL;
  1120. break;
  1121. }
  1122. return ret;
  1123. }
  1124. /* Issue a configure endpoint command or evaluate context command
  1125. * and wait for it to finish.
  1126. */
  1127. static int xhci_configure_endpoint(struct xhci_hcd *xhci,
  1128. struct usb_device *udev,
  1129. struct xhci_command *command,
  1130. bool ctx_change, bool must_succeed)
  1131. {
  1132. int ret;
  1133. int timeleft;
  1134. unsigned long flags;
  1135. struct xhci_container_ctx *in_ctx;
  1136. struct completion *cmd_completion;
  1137. int *cmd_status;
  1138. struct xhci_virt_device *virt_dev;
  1139. spin_lock_irqsave(&xhci->lock, flags);
  1140. virt_dev = xhci->devs[udev->slot_id];
  1141. if (command) {
  1142. in_ctx = command->in_ctx;
  1143. cmd_completion = command->completion;
  1144. cmd_status = &command->status;
  1145. command->command_trb = xhci->cmd_ring->enqueue;
  1146. list_add_tail(&command->cmd_list, &virt_dev->cmd_list);
  1147. } else {
  1148. in_ctx = virt_dev->in_ctx;
  1149. cmd_completion = &virt_dev->cmd_completion;
  1150. cmd_status = &virt_dev->cmd_status;
  1151. }
  1152. init_completion(cmd_completion);
  1153. if (!ctx_change)
  1154. ret = xhci_queue_configure_endpoint(xhci, in_ctx->dma,
  1155. udev->slot_id, must_succeed);
  1156. else
  1157. ret = xhci_queue_evaluate_context(xhci, in_ctx->dma,
  1158. udev->slot_id);
  1159. if (ret < 0) {
  1160. if (command)
  1161. list_del(&command->cmd_list);
  1162. spin_unlock_irqrestore(&xhci->lock, flags);
  1163. xhci_dbg(xhci, "FIXME allocate a new ring segment\n");
  1164. return -ENOMEM;
  1165. }
  1166. xhci_ring_cmd_db(xhci);
  1167. spin_unlock_irqrestore(&xhci->lock, flags);
  1168. /* Wait for the configure endpoint command to complete */
  1169. timeleft = wait_for_completion_interruptible_timeout(
  1170. cmd_completion,
  1171. USB_CTRL_SET_TIMEOUT);
  1172. if (timeleft <= 0) {
  1173. xhci_warn(xhci, "%s while waiting for %s command\n",
  1174. timeleft == 0 ? "Timeout" : "Signal",
  1175. ctx_change == 0 ?
  1176. "configure endpoint" :
  1177. "evaluate context");
  1178. /* FIXME cancel the configure endpoint command */
  1179. return -ETIME;
  1180. }
  1181. if (!ctx_change)
  1182. return xhci_configure_endpoint_result(xhci, udev, cmd_status);
  1183. return xhci_evaluate_context_result(xhci, udev, cmd_status);
  1184. }
  1185. /* Called after one or more calls to xhci_add_endpoint() or
  1186. * xhci_drop_endpoint(). If this call fails, the USB core is expected
  1187. * to call xhci_reset_bandwidth().
  1188. *
  1189. * Since we are in the middle of changing either configuration or
  1190. * installing a new alt setting, the USB core won't allow URBs to be
  1191. * enqueued for any endpoint on the old config or interface. Nothing
  1192. * else should be touching the xhci->devs[slot_id] structure, so we
  1193. * don't need to take the xhci->lock for manipulating that.
  1194. */
  1195. int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
  1196. {
  1197. int i;
  1198. int ret = 0;
  1199. struct xhci_hcd *xhci;
  1200. struct xhci_virt_device *virt_dev;
  1201. struct xhci_input_control_ctx *ctrl_ctx;
  1202. struct xhci_slot_ctx *slot_ctx;
  1203. ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
  1204. if (ret <= 0)
  1205. return ret;
  1206. xhci = hcd_to_xhci(hcd);
  1207. xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
  1208. virt_dev = xhci->devs[udev->slot_id];
  1209. /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
  1210. ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
  1211. ctrl_ctx->add_flags |= SLOT_FLAG;
  1212. ctrl_ctx->add_flags &= ~EP0_FLAG;
  1213. ctrl_ctx->drop_flags &= ~SLOT_FLAG;
  1214. ctrl_ctx->drop_flags &= ~EP0_FLAG;
  1215. xhci_dbg(xhci, "New Input Control Context:\n");
  1216. slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
  1217. xhci_dbg_ctx(xhci, virt_dev->in_ctx,
  1218. LAST_CTX_TO_EP_NUM(slot_ctx->dev_info));
  1219. ret = xhci_configure_endpoint(xhci, udev, NULL,
  1220. false, false);
  1221. if (ret) {
  1222. /* Callee should call reset_bandwidth() */
  1223. return ret;
  1224. }
  1225. xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
  1226. xhci_dbg_ctx(xhci, virt_dev->out_ctx,
  1227. LAST_CTX_TO_EP_NUM(slot_ctx->dev_info));
  1228. xhci_zero_in_ctx(xhci, virt_dev);
  1229. /* Install new rings and free or cache any old rings */
  1230. for (i = 1; i < 31; ++i) {
  1231. if (!virt_dev->eps[i].new_ring)
  1232. continue;
  1233. /* Only cache or free the old ring if it exists.
  1234. * It may not if this is the first add of an endpoint.
  1235. */
  1236. if (virt_dev->eps[i].ring) {
  1237. xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
  1238. }
  1239. virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
  1240. virt_dev->eps[i].new_ring = NULL;
  1241. }
  1242. return ret;
  1243. }
  1244. void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
  1245. {
  1246. struct xhci_hcd *xhci;
  1247. struct xhci_virt_device *virt_dev;
  1248. int i, ret;
  1249. ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
  1250. if (ret <= 0)
  1251. return;
  1252. xhci = hcd_to_xhci(hcd);
  1253. xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
  1254. virt_dev = xhci->devs[udev->slot_id];
  1255. /* Free any rings allocated for added endpoints */
  1256. for (i = 0; i < 31; ++i) {
  1257. if (virt_dev->eps[i].new_ring) {
  1258. xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
  1259. virt_dev->eps[i].new_ring = NULL;
  1260. }
  1261. }
  1262. xhci_zero_in_ctx(xhci, virt_dev);
  1263. }
  1264. static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
  1265. struct xhci_container_ctx *in_ctx,
  1266. struct xhci_container_ctx *out_ctx,
  1267. u32 add_flags, u32 drop_flags)
  1268. {
  1269. struct xhci_input_control_ctx *ctrl_ctx;
  1270. ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
  1271. ctrl_ctx->add_flags = add_flags;
  1272. ctrl_ctx->drop_flags = drop_flags;
  1273. xhci_slot_copy(xhci, in_ctx, out_ctx);
  1274. ctrl_ctx->add_flags |= SLOT_FLAG;
  1275. xhci_dbg(xhci, "Input Context:\n");
  1276. xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
  1277. }
  1278. void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
  1279. unsigned int slot_id, unsigned int ep_index,
  1280. struct xhci_dequeue_state *deq_state)
  1281. {
  1282. struct xhci_container_ctx *in_ctx;
  1283. struct xhci_ep_ctx *ep_ctx;
  1284. u32 added_ctxs;
  1285. dma_addr_t addr;
  1286. xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
  1287. xhci->devs[slot_id]->out_ctx, ep_index);
  1288. in_ctx = xhci->devs[slot_id]->in_ctx;
  1289. ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
  1290. addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
  1291. deq_state->new_deq_ptr);
  1292. if (addr == 0) {
  1293. xhci_warn(xhci, "WARN Cannot submit config ep after "
  1294. "reset ep command\n");
  1295. xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
  1296. deq_state->new_deq_seg,
  1297. deq_state->new_deq_ptr);
  1298. return;
  1299. }
  1300. ep_ctx->deq = addr | deq_state->new_cycle_state;
  1301. added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
  1302. xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
  1303. xhci->devs[slot_id]->out_ctx, added_ctxs, added_ctxs);
  1304. }
  1305. void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
  1306. struct usb_device *udev, unsigned int ep_index)
  1307. {
  1308. struct xhci_dequeue_state deq_state;
  1309. struct xhci_virt_ep *ep;
  1310. xhci_dbg(xhci, "Cleaning up stalled endpoint ring\n");
  1311. ep = &xhci->devs[udev->slot_id]->eps[ep_index];
  1312. /* We need to move the HW's dequeue pointer past this TD,
  1313. * or it will attempt to resend it on the next doorbell ring.
  1314. */
  1315. xhci_find_new_dequeue_state(xhci, udev->slot_id,
  1316. ep_index, ep->stopped_stream, ep->stopped_td,
  1317. &deq_state);
  1318. /* HW with the reset endpoint quirk will use the saved dequeue state to
  1319. * issue a configure endpoint command later.
  1320. */
  1321. if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
  1322. xhci_dbg(xhci, "Queueing new dequeue state\n");
  1323. xhci_queue_new_dequeue_state(xhci, udev->slot_id,
  1324. ep_index, ep->stopped_stream, &deq_state);
  1325. } else {
  1326. /* Better hope no one uses the input context between now and the
  1327. * reset endpoint completion!
  1328. * XXX: No idea how this hardware will react when stream rings
  1329. * are enabled.
  1330. */
  1331. xhci_dbg(xhci, "Setting up input context for "
  1332. "configure endpoint command\n");
  1333. xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
  1334. ep_index, &deq_state);
  1335. }
  1336. }
  1337. /* Deal with stalled endpoints. The core should have sent the control message
  1338. * to clear the halt condition. However, we need to make the xHCI hardware
  1339. * reset its sequence number, since a device will expect a sequence number of
  1340. * zero after the halt condition is cleared.
  1341. * Context: in_interrupt
  1342. */
  1343. void xhci_endpoint_reset(struct usb_hcd *hcd,
  1344. struct usb_host_endpoint *ep)
  1345. {
  1346. struct xhci_hcd *xhci;
  1347. struct usb_device *udev;
  1348. unsigned int ep_index;
  1349. unsigned long flags;
  1350. int ret;
  1351. struct xhci_virt_ep *virt_ep;
  1352. xhci = hcd_to_xhci(hcd);
  1353. udev = (struct usb_device *) ep->hcpriv;
  1354. /* Called with a root hub endpoint (or an endpoint that wasn't added
  1355. * with xhci_add_endpoint()
  1356. */
  1357. if (!ep->hcpriv)
  1358. return;
  1359. ep_index = xhci_get_endpoint_index(&ep->desc);
  1360. virt_ep = &xhci->devs[udev->slot_id]->eps[ep_index];
  1361. if (!virt_ep->stopped_td) {
  1362. xhci_dbg(xhci, "Endpoint 0x%x not halted, refusing to reset.\n",
  1363. ep->desc.bEndpointAddress);
  1364. return;
  1365. }
  1366. if (usb_endpoint_xfer_control(&ep->desc)) {
  1367. xhci_dbg(xhci, "Control endpoint stall already handled.\n");
  1368. return;
  1369. }
  1370. xhci_dbg(xhci, "Queueing reset endpoint command\n");
  1371. spin_lock_irqsave(&xhci->lock, flags);
  1372. ret = xhci_queue_reset_ep(xhci, udev->slot_id, ep_index);
  1373. /*
  1374. * Can't change the ring dequeue pointer until it's transitioned to the
  1375. * stopped state, which is only upon a successful reset endpoint
  1376. * command. Better hope that last command worked!
  1377. */
  1378. if (!ret) {
  1379. xhci_cleanup_stalled_ring(xhci, udev, ep_index);
  1380. kfree(virt_ep->stopped_td);
  1381. xhci_ring_cmd_db(xhci);
  1382. }
  1383. virt_ep->stopped_td = NULL;
  1384. virt_ep->stopped_trb = NULL;
  1385. virt_ep->stopped_stream = 0;
  1386. spin_unlock_irqrestore(&xhci->lock, flags);
  1387. if (ret)
  1388. xhci_warn(xhci, "FIXME allocate a new ring segment\n");
  1389. }
  1390. static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
  1391. struct usb_device *udev, struct usb_host_endpoint *ep,
  1392. unsigned int slot_id)
  1393. {
  1394. int ret;
  1395. unsigned int ep_index;
  1396. unsigned int ep_state;
  1397. if (!ep)
  1398. return -EINVAL;
  1399. ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
  1400. if (ret <= 0)
  1401. return -EINVAL;
  1402. if (ep->ss_ep_comp.bmAttributes == 0) {
  1403. xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
  1404. " descriptor for ep 0x%x does not support streams\n",
  1405. ep->desc.bEndpointAddress);
  1406. return -EINVAL;
  1407. }
  1408. ep_index = xhci_get_endpoint_index(&ep->desc);
  1409. ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
  1410. if (ep_state & EP_HAS_STREAMS ||
  1411. ep_state & EP_GETTING_STREAMS) {
  1412. xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
  1413. "already has streams set up.\n",
  1414. ep->desc.bEndpointAddress);
  1415. xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
  1416. "dynamic stream context array reallocation.\n");
  1417. return -EINVAL;
  1418. }
  1419. if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
  1420. xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
  1421. "endpoint 0x%x; URBs are pending.\n",
  1422. ep->desc.bEndpointAddress);
  1423. return -EINVAL;
  1424. }
  1425. return 0;
  1426. }
  1427. static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
  1428. unsigned int *num_streams, unsigned int *num_stream_ctxs)
  1429. {
  1430. unsigned int max_streams;
  1431. /* The stream context array size must be a power of two */
  1432. *num_stream_ctxs = roundup_pow_of_two(*num_streams);
  1433. /*
  1434. * Find out how many primary stream array entries the host controller
  1435. * supports. Later we may use secondary stream arrays (similar to 2nd
  1436. * level page entries), but that's an optional feature for xHCI host
  1437. * controllers. xHCs must support at least 4 stream IDs.
  1438. */
  1439. max_streams = HCC_MAX_PSA(xhci->hcc_params);
  1440. if (*num_stream_ctxs > max_streams) {
  1441. xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
  1442. max_streams);
  1443. *num_stream_ctxs = max_streams;
  1444. *num_streams = max_streams;
  1445. }
  1446. }
  1447. /* Returns an error code if one of the endpoint already has streams.
  1448. * This does not change any data structures, it only checks and gathers
  1449. * information.
  1450. */
  1451. static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
  1452. struct usb_device *udev,
  1453. struct usb_host_endpoint **eps, unsigned int num_eps,
  1454. unsigned int *num_streams, u32 *changed_ep_bitmask)
  1455. {
  1456. unsigned int max_streams;
  1457. unsigned int endpoint_flag;
  1458. int i;
  1459. int ret;
  1460. for (i = 0; i < num_eps; i++) {
  1461. ret = xhci_check_streams_endpoint(xhci, udev,
  1462. eps[i], udev->slot_id);
  1463. if (ret < 0)
  1464. return ret;
  1465. max_streams = USB_SS_MAX_STREAMS(
  1466. eps[i]->ss_ep_comp.bmAttributes);
  1467. if (max_streams < (*num_streams - 1)) {
  1468. xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
  1469. eps[i]->desc.bEndpointAddress,
  1470. max_streams);
  1471. *num_streams = max_streams+1;
  1472. }
  1473. endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
  1474. if (*changed_ep_bitmask & endpoint_flag)
  1475. return -EINVAL;
  1476. *changed_ep_bitmask |= endpoint_flag;
  1477. }
  1478. return 0;
  1479. }
  1480. static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
  1481. struct usb_device *udev,
  1482. struct usb_host_endpoint **eps, unsigned int num_eps)
  1483. {
  1484. u32 changed_ep_bitmask = 0;
  1485. unsigned int slot_id;
  1486. unsigned int ep_index;
  1487. unsigned int ep_state;
  1488. int i;
  1489. slot_id = udev->slot_id;
  1490. if (!xhci->devs[slot_id])
  1491. return 0;
  1492. for (i = 0; i < num_eps; i++) {
  1493. ep_index = xhci_get_endpoint_index(&eps[i]->desc);
  1494. ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
  1495. /* Are streams already being freed for the endpoint? */
  1496. if (ep_state & EP_GETTING_NO_STREAMS) {
  1497. xhci_warn(xhci, "WARN Can't disable streams for "
  1498. "endpoint 0x%x\n, "
  1499. "streams are being disabled already.",
  1500. eps[i]->desc.bEndpointAddress);
  1501. return 0;
  1502. }
  1503. /* Are there actually any streams to free? */
  1504. if (!(ep_state & EP_HAS_STREAMS) &&
  1505. !(ep_state & EP_GETTING_STREAMS)) {
  1506. xhci_warn(xhci, "WARN Can't disable streams for "
  1507. "endpoint 0x%x\n, "
  1508. "streams are already disabled!",
  1509. eps[i]->desc.bEndpointAddress);
  1510. xhci_warn(xhci, "WARN xhci_free_streams() called "
  1511. "with non-streams endpoint\n");
  1512. return 0;
  1513. }
  1514. changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
  1515. }
  1516. return changed_ep_bitmask;
  1517. }
  1518. /*
  1519. * The USB device drivers use this function (though the HCD interface in USB
  1520. * core) to prepare a set of bulk endpoints to use streams. Streams are used to
  1521. * coordinate mass storage command queueing across multiple endpoints (basically
  1522. * a stream ID == a task ID).
  1523. *
  1524. * Setting up streams involves allocating the same size stream context array
  1525. * for each endpoint and issuing a configure endpoint command for all endpoints.
  1526. *
  1527. * Don't allow the call to succeed if one endpoint only supports one stream
  1528. * (which means it doesn't support streams at all).
  1529. *
  1530. * Drivers may get less stream IDs than they asked for, if the host controller
  1531. * hardware or endpoints claim they can't support the number of requested
  1532. * stream IDs.
  1533. */
  1534. int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
  1535. struct usb_host_endpoint **eps, unsigned int num_eps,
  1536. unsigned int num_streams, gfp_t mem_flags)
  1537. {
  1538. int i, ret;
  1539. struct xhci_hcd *xhci;
  1540. struct xhci_virt_device *vdev;
  1541. struct xhci_command *config_cmd;
  1542. unsigned int ep_index;
  1543. unsigned int num_stream_ctxs;
  1544. unsigned long flags;
  1545. u32 changed_ep_bitmask = 0;
  1546. if (!eps)
  1547. return -EINVAL;
  1548. /* Add one to the number of streams requested to account for
  1549. * stream 0 that is reserved for xHCI usage.
  1550. */
  1551. num_streams += 1;
  1552. xhci = hcd_to_xhci(hcd);
  1553. xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
  1554. num_streams);
  1555. config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
  1556. if (!config_cmd) {
  1557. xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
  1558. return -ENOMEM;
  1559. }
  1560. /* Check to make sure all endpoints are not already configured for
  1561. * streams. While we're at it, find the maximum number of streams that
  1562. * all the endpoints will support and check for duplicate endpoints.
  1563. */
  1564. spin_lock_irqsave(&xhci->lock, flags);
  1565. ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
  1566. num_eps, &num_streams, &changed_ep_bitmask);
  1567. if (ret < 0) {
  1568. xhci_free_command(xhci, config_cmd);
  1569. spin_unlock_irqrestore(&xhci->lock, flags);
  1570. return ret;
  1571. }
  1572. if (num_streams <= 1) {
  1573. xhci_warn(xhci, "WARN: endpoints can't handle "
  1574. "more than one stream.\n");
  1575. xhci_free_command(xhci, config_cmd);
  1576. spin_unlock_irqrestore(&xhci->lock, flags);
  1577. return -EINVAL;
  1578. }
  1579. vdev = xhci->devs[udev->slot_id];
  1580. /* Mark each endpoint as being in transistion, so
  1581. * xhci_urb_enqueue() will reject all URBs.
  1582. */
  1583. for (i = 0; i < num_eps; i++) {
  1584. ep_index = xhci_get_endpoint_index(&eps[i]->desc);
  1585. vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
  1586. }
  1587. spin_unlock_irqrestore(&xhci->lock, flags);
  1588. /* Setup internal data structures and allocate HW data structures for
  1589. * streams (but don't install the HW structures in the input context
  1590. * until we're sure all memory allocation succeeded).
  1591. */
  1592. xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
  1593. xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
  1594. num_stream_ctxs, num_streams);
  1595. for (i = 0; i < num_eps; i++) {
  1596. ep_index = xhci_get_endpoint_index(&eps[i]->desc);
  1597. vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
  1598. num_stream_ctxs,
  1599. num_streams, mem_flags);
  1600. if (!vdev->eps[ep_index].stream_info)
  1601. goto cleanup;
  1602. /* Set maxPstreams in endpoint context and update deq ptr to
  1603. * point to stream context array. FIXME
  1604. */
  1605. }
  1606. /* Set up the input context for a configure endpoint command. */
  1607. for (i = 0; i < num_eps; i++) {
  1608. struct xhci_ep_ctx *ep_ctx;
  1609. ep_index = xhci_get_endpoint_index(&eps[i]->desc);
  1610. ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
  1611. xhci_endpoint_copy(xhci, config_cmd->in_ctx,
  1612. vdev->out_ctx, ep_index);
  1613. xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
  1614. vdev->eps[ep_index].stream_info);
  1615. }
  1616. /* Tell the HW to drop its old copy of the endpoint context info
  1617. * and add the updated copy from the input context.
  1618. */
  1619. xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
  1620. vdev->out_ctx, changed_ep_bitmask, changed_ep_bitmask);
  1621. /* Issue and wait for the configure endpoint command */
  1622. ret = xhci_configure_endpoint(xhci, udev, config_cmd,
  1623. false, false);
  1624. /* xHC rejected the configure endpoint command for some reason, so we
  1625. * leave the old ring intact and free our internal streams data
  1626. * structure.
  1627. */
  1628. if (ret < 0)
  1629. goto cleanup;
  1630. spin_lock_irqsave(&xhci->lock, flags);
  1631. for (i = 0; i < num_eps; i++) {
  1632. ep_index = xhci_get_endpoint_index(&eps[i]->desc);
  1633. vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
  1634. xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
  1635. udev->slot_id, ep_index);
  1636. vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
  1637. }
  1638. xhci_free_command(xhci, config_cmd);
  1639. spin_unlock_irqrestore(&xhci->lock, flags);
  1640. /* Subtract 1 for stream 0, which drivers can't use */
  1641. return num_streams - 1;
  1642. cleanup:
  1643. /* If it didn't work, free the streams! */
  1644. for (i = 0; i < num_eps; i++) {
  1645. ep_index = xhci_get_endpoint_index(&eps[i]->desc);
  1646. xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
  1647. vdev->eps[ep_index].stream_info = NULL;
  1648. /* FIXME Unset maxPstreams in endpoint context and
  1649. * update deq ptr to point to normal string ring.
  1650. */
  1651. vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
  1652. vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
  1653. xhci_endpoint_zero(xhci, vdev, eps[i]);
  1654. }
  1655. xhci_free_command(xhci, config_cmd);
  1656. return -ENOMEM;
  1657. }
  1658. /* Transition the endpoint from using streams to being a "normal" endpoint
  1659. * without streams.
  1660. *
  1661. * Modify the endpoint context state, submit a configure endpoint command,
  1662. * and free all endpoint rings for streams if that completes successfully.
  1663. */
  1664. int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
  1665. struct usb_host_endpoint **eps, unsigned int num_eps,
  1666. gfp_t mem_flags)
  1667. {
  1668. int i, ret;
  1669. struct xhci_hcd *xhci;
  1670. struct xhci_virt_device *vdev;
  1671. struct xhci_command *command;
  1672. unsigned int ep_index;
  1673. unsigned long flags;
  1674. u32 changed_ep_bitmask;
  1675. xhci = hcd_to_xhci(hcd);
  1676. vdev = xhci->devs[udev->slot_id];
  1677. /* Set up a configure endpoint command to remove the streams rings */
  1678. spin_lock_irqsave(&xhci->lock, flags);
  1679. changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
  1680. udev, eps, num_eps);
  1681. if (changed_ep_bitmask == 0) {
  1682. spin_unlock_irqrestore(&xhci->lock, flags);
  1683. return -EINVAL;
  1684. }
  1685. /* Use the xhci_command structure from the first endpoint. We may have
  1686. * allocated too many, but the driver may call xhci_free_streams() for
  1687. * each endpoint it grouped into one call to xhci_alloc_streams().
  1688. */
  1689. ep_index = xhci_get_endpoint_index(&eps[0]->desc);
  1690. command = vdev->eps[ep_index].stream_info->free_streams_command;
  1691. for (i = 0; i < num_eps; i++) {
  1692. struct xhci_ep_ctx *ep_ctx;
  1693. ep_index = xhci_get_endpoint_index(&eps[i]->desc);
  1694. ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
  1695. xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
  1696. EP_GETTING_NO_STREAMS;
  1697. xhci_endpoint_copy(xhci, command->in_ctx,
  1698. vdev->out_ctx, ep_index);
  1699. xhci_setup_no_streams_ep_input_ctx(xhci, ep_ctx,
  1700. &vdev->eps[ep_index]);
  1701. }
  1702. xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
  1703. vdev->out_ctx, changed_ep_bitmask, changed_ep_bitmask);
  1704. spin_unlock_irqrestore(&xhci->lock, flags);
  1705. /* Issue and wait for the configure endpoint command,
  1706. * which must succeed.
  1707. */
  1708. ret = xhci_configure_endpoint(xhci, udev, command,
  1709. false, true);
  1710. /* xHC rejected the configure endpoint command for some reason, so we
  1711. * leave the streams rings intact.
  1712. */
  1713. if (ret < 0)
  1714. return ret;
  1715. spin_lock_irqsave(&xhci->lock, flags);
  1716. for (i = 0; i < num_eps; i++) {
  1717. ep_index = xhci_get_endpoint_index(&eps[i]->desc);
  1718. xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
  1719. vdev->eps[ep_index].stream_info = NULL;
  1720. /* FIXME Unset maxPstreams in endpoint context and
  1721. * update deq ptr to point to normal string ring.
  1722. */
  1723. vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
  1724. vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
  1725. }
  1726. spin_unlock_irqrestore(&xhci->lock, flags);
  1727. return 0;
  1728. }
  1729. /*
  1730. * This submits a Reset Device Command, which will set the device state to 0,
  1731. * set the device address to 0, and disable all the endpoints except the default
  1732. * control endpoint. The USB core should come back and call
  1733. * xhci_address_device(), and then re-set up the configuration. If this is
  1734. * called because of a usb_reset_and_verify_device(), then the old alternate
  1735. * settings will be re-installed through the normal bandwidth allocation
  1736. * functions.
  1737. *
  1738. * Wait for the Reset Device command to finish. Remove all structures
  1739. * associated with the endpoints that were disabled. Clear the input device
  1740. * structure? Cache the rings? Reset the control endpoint 0 max packet size?
  1741. */
  1742. int xhci_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
  1743. {
  1744. int ret, i;
  1745. unsigned long flags;
  1746. struct xhci_hcd *xhci;
  1747. unsigned int slot_id;
  1748. struct xhci_virt_device *virt_dev;
  1749. struct xhci_command *reset_device_cmd;
  1750. int timeleft;
  1751. int last_freed_endpoint;
  1752. ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
  1753. if (ret <= 0)
  1754. return ret;
  1755. xhci = hcd_to_xhci(hcd);
  1756. slot_id = udev->slot_id;
  1757. virt_dev = xhci->devs[slot_id];
  1758. xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
  1759. /* Allocate the command structure that holds the struct completion.
  1760. * Assume we're in process context, since the normal device reset
  1761. * process has to wait for the device anyway. Storage devices are
  1762. * reset as part of error handling, so use GFP_NOIO instead of
  1763. * GFP_KERNEL.
  1764. */
  1765. reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
  1766. if (!reset_device_cmd) {
  1767. xhci_dbg(xhci, "Couldn't allocate command structure.\n");
  1768. return -ENOMEM;
  1769. }
  1770. /* Attempt to submit the Reset Device command to the command ring */
  1771. spin_lock_irqsave(&xhci->lock, flags);
  1772. reset_device_cmd->command_trb = xhci->cmd_ring->enqueue;
  1773. list_add_tail(&reset_device_cmd->cmd_list, &virt_dev->cmd_list);
  1774. ret = xhci_queue_reset_device(xhci, slot_id);
  1775. if (ret) {
  1776. xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
  1777. list_del(&reset_device_cmd->cmd_list);
  1778. spin_unlock_irqrestore(&xhci->lock, flags);
  1779. goto command_cleanup;
  1780. }
  1781. xhci_ring_cmd_db(xhci);
  1782. spin_unlock_irqrestore(&xhci->lock, flags);
  1783. /* Wait for the Reset Device command to finish */
  1784. timeleft = wait_for_completion_interruptible_timeout(
  1785. reset_device_cmd->completion,
  1786. USB_CTRL_SET_TIMEOUT);
  1787. if (timeleft <= 0) {
  1788. xhci_warn(xhci, "%s while waiting for reset device command\n",
  1789. timeleft == 0 ? "Timeout" : "Signal");
  1790. spin_lock_irqsave(&xhci->lock, flags);
  1791. /* The timeout might have raced with the event ring handler, so
  1792. * only delete from the list if the item isn't poisoned.
  1793. */
  1794. if (reset_device_cmd->cmd_list.next != LIST_POISON1)
  1795. list_del(&reset_device_cmd->cmd_list);
  1796. spin_unlock_irqrestore(&xhci->lock, flags);
  1797. ret = -ETIME;
  1798. goto command_cleanup;
  1799. }
  1800. /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
  1801. * unless we tried to reset a slot ID that wasn't enabled,
  1802. * or the device wasn't in the addressed or configured state.
  1803. */
  1804. ret = reset_device_cmd->status;
  1805. switch (ret) {
  1806. case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
  1807. case COMP_CTX_STATE: /* 0.96 completion code for same thing */
  1808. xhci_info(xhci, "Can't reset device (slot ID %u) in %s state\n",
  1809. slot_id,
  1810. xhci_get_slot_state(xhci, virt_dev->out_ctx));
  1811. xhci_info(xhci, "Not freeing device rings.\n");
  1812. /* Don't treat this as an error. May change my mind later. */
  1813. ret = 0;
  1814. goto command_cleanup;
  1815. case COMP_SUCCESS:
  1816. xhci_dbg(xhci, "Successful reset device command.\n");
  1817. break;
  1818. default:
  1819. if (xhci_is_vendor_info_code(xhci, ret))
  1820. break;
  1821. xhci_warn(xhci, "Unknown completion code %u for "
  1822. "reset device command.\n", ret);
  1823. ret = -EINVAL;
  1824. goto command_cleanup;
  1825. }
  1826. /* Everything but endpoint 0 is disabled, so free or cache the rings. */
  1827. last_freed_endpoint = 1;
  1828. for (i = 1; i < 31; ++i) {
  1829. if (!virt_dev->eps[i].ring)
  1830. continue;
  1831. xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
  1832. last_freed_endpoint = i;
  1833. }
  1834. xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
  1835. xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
  1836. ret = 0;
  1837. command_cleanup:
  1838. xhci_free_command(xhci, reset_device_cmd);
  1839. return ret;
  1840. }
  1841. /*
  1842. * At this point, the struct usb_device is about to go away, the device has
  1843. * disconnected, and all traffic has been stopped and the endpoints have been
  1844. * disabled. Free any HC data structures associated with that device.
  1845. */
  1846. void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
  1847. {
  1848. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  1849. struct xhci_virt_device *virt_dev;
  1850. unsigned long flags;
  1851. u32 state;
  1852. int i, ret;
  1853. ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
  1854. if (ret <= 0)
  1855. return;
  1856. virt_dev = xhci->devs[udev->slot_id];
  1857. /* Stop any wayward timer functions (which may grab the lock) */
  1858. for (i = 0; i < 31; ++i) {
  1859. virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
  1860. del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
  1861. }
  1862. spin_lock_irqsave(&xhci->lock, flags);
  1863. /* Don't disable the slot if the host controller is dead. */
  1864. state = xhci_readl(xhci, &xhci->op_regs->status);
  1865. if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING)) {
  1866. xhci_free_virt_device(xhci, udev->slot_id);
  1867. spin_unlock_irqrestore(&xhci->lock, flags);
  1868. return;
  1869. }
  1870. if (xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) {
  1871. spin_unlock_irqrestore(&xhci->lock, flags);
  1872. xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
  1873. return;
  1874. }
  1875. xhci_ring_cmd_db(xhci);
  1876. spin_unlock_irqrestore(&xhci->lock, flags);
  1877. /*
  1878. * Event command completion handler will free any data structures
  1879. * associated with the slot. XXX Can free sleep?
  1880. */
  1881. }
  1882. /*
  1883. * Returns 0 if the xHC ran out of device slots, the Enable Slot command
  1884. * timed out, or allocating memory failed. Returns 1 on success.
  1885. */
  1886. int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
  1887. {
  1888. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  1889. unsigned long flags;
  1890. int timeleft;
  1891. int ret;
  1892. spin_lock_irqsave(&xhci->lock, flags);
  1893. ret = xhci_queue_slot_control(xhci, TRB_ENABLE_SLOT, 0);
  1894. if (ret) {
  1895. spin_unlock_irqrestore(&xhci->lock, flags);
  1896. xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
  1897. return 0;
  1898. }
  1899. xhci_ring_cmd_db(xhci);
  1900. spin_unlock_irqrestore(&xhci->lock, flags);
  1901. /* XXX: how much time for xHC slot assignment? */
  1902. timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
  1903. USB_CTRL_SET_TIMEOUT);
  1904. if (timeleft <= 0) {
  1905. xhci_warn(xhci, "%s while waiting for a slot\n",
  1906. timeleft == 0 ? "Timeout" : "Signal");
  1907. /* FIXME cancel the enable slot request */
  1908. return 0;
  1909. }
  1910. if (!xhci->slot_id) {
  1911. xhci_err(xhci, "Error while assigning device slot ID\n");
  1912. return 0;
  1913. }
  1914. /* xhci_alloc_virt_device() does not touch rings; no need to lock */
  1915. if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_KERNEL)) {
  1916. /* Disable slot, if we can do it without mem alloc */
  1917. xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
  1918. spin_lock_irqsave(&xhci->lock, flags);
  1919. if (!xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id))
  1920. xhci_ring_cmd_db(xhci);
  1921. spin_unlock_irqrestore(&xhci->lock, flags);
  1922. return 0;
  1923. }
  1924. udev->slot_id = xhci->slot_id;
  1925. /* Is this a LS or FS device under a HS hub? */
  1926. /* Hub or peripherial? */
  1927. return 1;
  1928. }
  1929. /*
  1930. * Issue an Address Device command (which will issue a SetAddress request to
  1931. * the device).
  1932. * We should be protected by the usb_address0_mutex in khubd's hub_port_init, so
  1933. * we should only issue and wait on one address command at the same time.
  1934. *
  1935. * We add one to the device address issued by the hardware because the USB core
  1936. * uses address 1 for the root hubs (even though they're not really devices).
  1937. */
  1938. int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
  1939. {
  1940. unsigned long flags;
  1941. int timeleft;
  1942. struct xhci_virt_device *virt_dev;
  1943. int ret = 0;
  1944. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  1945. struct xhci_slot_ctx *slot_ctx;
  1946. struct xhci_input_control_ctx *ctrl_ctx;
  1947. u64 temp_64;
  1948. if (!udev->slot_id) {
  1949. xhci_dbg(xhci, "Bad Slot ID %d\n", udev->slot_id);
  1950. return -EINVAL;
  1951. }
  1952. virt_dev = xhci->devs[udev->slot_id];
  1953. /* If this is a Set Address to an unconfigured device, setup ep 0 */
  1954. if (!udev->config)
  1955. xhci_setup_addressable_virt_dev(xhci, udev);
  1956. else
  1957. xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
  1958. /* Otherwise, assume the core has the device configured how it wants */
  1959. xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
  1960. xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
  1961. spin_lock_irqsave(&xhci->lock, flags);
  1962. ret = xhci_queue_address_device(xhci, virt_dev->in_ctx->dma,
  1963. udev->slot_id);
  1964. if (ret) {
  1965. spin_unlock_irqrestore(&xhci->lock, flags);
  1966. xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
  1967. return ret;
  1968. }
  1969. xhci_ring_cmd_db(xhci);
  1970. spin_unlock_irqrestore(&xhci->lock, flags);
  1971. /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
  1972. timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
  1973. USB_CTRL_SET_TIMEOUT);
  1974. /* FIXME: From section 4.3.4: "Software shall be responsible for timing
  1975. * the SetAddress() "recovery interval" required by USB and aborting the
  1976. * command on a timeout.
  1977. */
  1978. if (timeleft <= 0) {
  1979. xhci_warn(xhci, "%s while waiting for a slot\n",
  1980. timeleft == 0 ? "Timeout" : "Signal");
  1981. /* FIXME cancel the address device command */
  1982. return -ETIME;
  1983. }
  1984. switch (virt_dev->cmd_status) {
  1985. case COMP_CTX_STATE:
  1986. case COMP_EBADSLT:
  1987. xhci_err(xhci, "Setup ERROR: address device command for slot %d.\n",
  1988. udev->slot_id);
  1989. ret = -EINVAL;
  1990. break;
  1991. case COMP_TX_ERR:
  1992. dev_warn(&udev->dev, "Device not responding to set address.\n");
  1993. ret = -EPROTO;
  1994. break;
  1995. case COMP_SUCCESS:
  1996. xhci_dbg(xhci, "Successful Address Device command\n");
  1997. break;
  1998. default:
  1999. xhci_err(xhci, "ERROR: unexpected command completion "
  2000. "code 0x%x.\n", virt_dev->cmd_status);
  2001. xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
  2002. xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
  2003. ret = -EINVAL;
  2004. break;
  2005. }
  2006. if (ret) {
  2007. return ret;
  2008. }
  2009. temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
  2010. xhci_dbg(xhci, "Op regs DCBAA ptr = %#016llx\n", temp_64);
  2011. xhci_dbg(xhci, "Slot ID %d dcbaa entry @%p = %#016llx\n",
  2012. udev->slot_id,
  2013. &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
  2014. (unsigned long long)
  2015. xhci->dcbaa->dev_context_ptrs[udev->slot_id]);
  2016. xhci_dbg(xhci, "Output Context DMA address = %#08llx\n",
  2017. (unsigned long long)virt_dev->out_ctx->dma);
  2018. xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
  2019. xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
  2020. xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
  2021. xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
  2022. /*
  2023. * USB core uses address 1 for the roothubs, so we add one to the
  2024. * address given back to us by the HC.
  2025. */
  2026. slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
  2027. udev->devnum = (slot_ctx->dev_state & DEV_ADDR_MASK) + 1;
  2028. /* Zero the input context control for later use */
  2029. ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
  2030. ctrl_ctx->add_flags = 0;
  2031. ctrl_ctx->drop_flags = 0;
  2032. xhci_dbg(xhci, "Device address = %d\n", udev->devnum);
  2033. /* XXX Meh, not sure if anyone else but choose_address uses this. */
  2034. set_bit(udev->devnum, udev->bus->devmap.devicemap);
  2035. return 0;
  2036. }
  2037. /* Once a hub descriptor is fetched for a device, we need to update the xHC's
  2038. * internal data structures for the device.
  2039. */
  2040. int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
  2041. struct usb_tt *tt, gfp_t mem_flags)
  2042. {
  2043. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  2044. struct xhci_virt_device *vdev;
  2045. struct xhci_command *config_cmd;
  2046. struct xhci_input_control_ctx *ctrl_ctx;
  2047. struct xhci_slot_ctx *slot_ctx;
  2048. unsigned long flags;
  2049. unsigned think_time;
  2050. int ret;
  2051. /* Ignore root hubs */
  2052. if (!hdev->parent)
  2053. return 0;
  2054. vdev = xhci->devs[hdev->slot_id];
  2055. if (!vdev) {
  2056. xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
  2057. return -EINVAL;
  2058. }
  2059. config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
  2060. if (!config_cmd) {
  2061. xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
  2062. return -ENOMEM;
  2063. }
  2064. spin_lock_irqsave(&xhci->lock, flags);
  2065. xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
  2066. ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx);
  2067. ctrl_ctx->add_flags |= SLOT_FLAG;
  2068. slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
  2069. slot_ctx->dev_info |= DEV_HUB;
  2070. if (tt->multi)
  2071. slot_ctx->dev_info |= DEV_MTT;
  2072. if (xhci->hci_version > 0x95) {
  2073. xhci_dbg(xhci, "xHCI version %x needs hub "
  2074. "TT think time and number of ports\n",
  2075. (unsigned int) xhci->hci_version);
  2076. slot_ctx->dev_info2 |= XHCI_MAX_PORTS(hdev->maxchild);
  2077. /* Set TT think time - convert from ns to FS bit times.
  2078. * 0 = 8 FS bit times, 1 = 16 FS bit times,
  2079. * 2 = 24 FS bit times, 3 = 32 FS bit times.
  2080. */
  2081. think_time = tt->think_time;
  2082. if (think_time != 0)
  2083. think_time = (think_time / 666) - 1;
  2084. slot_ctx->tt_info |= TT_THINK_TIME(think_time);
  2085. } else {
  2086. xhci_dbg(xhci, "xHCI version %x doesn't need hub "
  2087. "TT think time or number of ports\n",
  2088. (unsigned int) xhci->hci_version);
  2089. }
  2090. slot_ctx->dev_state = 0;
  2091. spin_unlock_irqrestore(&xhci->lock, flags);
  2092. xhci_dbg(xhci, "Set up %s for hub device.\n",
  2093. (xhci->hci_version > 0x95) ?
  2094. "configure endpoint" : "evaluate context");
  2095. xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
  2096. xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
  2097. /* Issue and wait for the configure endpoint or
  2098. * evaluate context command.
  2099. */
  2100. if (xhci->hci_version > 0x95)
  2101. ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
  2102. false, false);
  2103. else
  2104. ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
  2105. true, false);
  2106. xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
  2107. xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
  2108. xhci_free_command(xhci, config_cmd);
  2109. return ret;
  2110. }
  2111. int xhci_get_frame(struct usb_hcd *hcd)
  2112. {
  2113. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  2114. /* EHCI mods by the periodic size. Why? */
  2115. return xhci_readl(xhci, &xhci->run_regs->microframe_index) >> 3;
  2116. }
  2117. MODULE_DESCRIPTION(DRIVER_DESC);
  2118. MODULE_AUTHOR(DRIVER_AUTHOR);
  2119. MODULE_LICENSE("GPL");
  2120. static int __init xhci_hcd_init(void)
  2121. {
  2122. #ifdef CONFIG_PCI
  2123. int retval = 0;
  2124. retval = xhci_register_pci();
  2125. if (retval < 0) {
  2126. printk(KERN_DEBUG "Problem registering PCI driver.");
  2127. return retval;
  2128. }
  2129. #endif
  2130. /*
  2131. * Check the compiler generated sizes of structures that must be laid
  2132. * out in specific ways for hardware access.
  2133. */
  2134. BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
  2135. BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
  2136. BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
  2137. /* xhci_device_control has eight fields, and also
  2138. * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
  2139. */
  2140. BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
  2141. BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
  2142. BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
  2143. BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 7*32/8);
  2144. BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
  2145. /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
  2146. BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
  2147. BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
  2148. return 0;
  2149. }
  2150. module_init(xhci_hcd_init);
  2151. static void __exit xhci_hcd_cleanup(void)
  2152. {
  2153. #ifdef CONFIG_PCI
  2154. xhci_unregister_pci();
  2155. #endif
  2156. }
  2157. module_exit(xhci_hcd_cleanup);