ar5008_phy.c 29 KB

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  1. /*
  2. * Copyright (c) 2008-2010 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include "hw.h"
  17. #include "hw-ops.h"
  18. #include "../regd.h"
  19. #include "ar9002_phy.h"
  20. /* All code below is for non single-chip solutions */
  21. /**
  22. * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
  23. * @rfbuf:
  24. * @reg32:
  25. * @numBits:
  26. * @firstBit:
  27. * @column:
  28. *
  29. * Performs analog "swizzling" of parameters into their location.
  30. * Used on external AR2133/AR5133 radios.
  31. */
  32. static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
  33. u32 numBits, u32 firstBit,
  34. u32 column)
  35. {
  36. u32 tmp32, mask, arrayEntry, lastBit;
  37. int32_t bitPosition, bitsLeft;
  38. tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
  39. arrayEntry = (firstBit - 1) / 8;
  40. bitPosition = (firstBit - 1) % 8;
  41. bitsLeft = numBits;
  42. while (bitsLeft > 0) {
  43. lastBit = (bitPosition + bitsLeft > 8) ?
  44. 8 : bitPosition + bitsLeft;
  45. mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
  46. (column * 8);
  47. rfBuf[arrayEntry] &= ~mask;
  48. rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
  49. (column * 8)) & mask;
  50. bitsLeft -= 8 - bitPosition;
  51. tmp32 = tmp32 >> (8 - bitPosition);
  52. bitPosition = 0;
  53. arrayEntry++;
  54. }
  55. }
  56. /*
  57. * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
  58. * rf_pwd_icsyndiv.
  59. *
  60. * Theoretical Rules:
  61. * if 2 GHz band
  62. * if forceBiasAuto
  63. * if synth_freq < 2412
  64. * bias = 0
  65. * else if 2412 <= synth_freq <= 2422
  66. * bias = 1
  67. * else // synth_freq > 2422
  68. * bias = 2
  69. * else if forceBias > 0
  70. * bias = forceBias & 7
  71. * else
  72. * no change, use value from ini file
  73. * else
  74. * no change, invalid band
  75. *
  76. * 1st Mod:
  77. * 2422 also uses value of 2
  78. * <approved>
  79. *
  80. * 2nd Mod:
  81. * Less than 2412 uses value of 0, 2412 and above uses value of 2
  82. */
  83. static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
  84. {
  85. struct ath_common *common = ath9k_hw_common(ah);
  86. u32 tmp_reg;
  87. int reg_writes = 0;
  88. u32 new_bias = 0;
  89. if (!AR_SREV_5416(ah) || synth_freq >= 3000)
  90. return;
  91. BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
  92. if (synth_freq < 2412)
  93. new_bias = 0;
  94. else if (synth_freq < 2422)
  95. new_bias = 1;
  96. else
  97. new_bias = 2;
  98. /* pre-reverse this field */
  99. tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
  100. ath_print(common, ATH_DBG_CONFIG,
  101. "Force rf_pwd_icsyndiv to %1d on %4d\n",
  102. new_bias, synth_freq);
  103. /* swizzle rf_pwd_icsyndiv */
  104. ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
  105. /* write Bank 6 with new params */
  106. REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
  107. }
  108. /**
  109. * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
  110. * @ah: atheros hardware stucture
  111. * @chan:
  112. *
  113. * For the external AR2133/AR5133 radios, takes the MHz channel value and set
  114. * the channel value. Assumes writes enabled to analog bus and bank6 register
  115. * cache in ah->analogBank6Data.
  116. */
  117. static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
  118. {
  119. struct ath_common *common = ath9k_hw_common(ah);
  120. u32 channelSel = 0;
  121. u32 bModeSynth = 0;
  122. u32 aModeRefSel = 0;
  123. u32 reg32 = 0;
  124. u16 freq;
  125. struct chan_centers centers;
  126. ath9k_hw_get_channel_centers(ah, chan, &centers);
  127. freq = centers.synth_center;
  128. if (freq < 4800) {
  129. u32 txctl;
  130. if (((freq - 2192) % 5) == 0) {
  131. channelSel = ((freq - 672) * 2 - 3040) / 10;
  132. bModeSynth = 0;
  133. } else if (((freq - 2224) % 5) == 0) {
  134. channelSel = ((freq - 704) * 2 - 3040) / 10;
  135. bModeSynth = 1;
  136. } else {
  137. ath_print(common, ATH_DBG_FATAL,
  138. "Invalid channel %u MHz\n", freq);
  139. return -EINVAL;
  140. }
  141. channelSel = (channelSel << 2) & 0xff;
  142. channelSel = ath9k_hw_reverse_bits(channelSel, 8);
  143. txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
  144. if (freq == 2484) {
  145. REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
  146. txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
  147. } else {
  148. REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
  149. txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
  150. }
  151. } else if ((freq % 20) == 0 && freq >= 5120) {
  152. channelSel =
  153. ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
  154. aModeRefSel = ath9k_hw_reverse_bits(1, 2);
  155. } else if ((freq % 10) == 0) {
  156. channelSel =
  157. ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
  158. if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
  159. aModeRefSel = ath9k_hw_reverse_bits(2, 2);
  160. else
  161. aModeRefSel = ath9k_hw_reverse_bits(1, 2);
  162. } else if ((freq % 5) == 0) {
  163. channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
  164. aModeRefSel = ath9k_hw_reverse_bits(1, 2);
  165. } else {
  166. ath_print(common, ATH_DBG_FATAL,
  167. "Invalid channel %u MHz\n", freq);
  168. return -EINVAL;
  169. }
  170. ar5008_hw_force_bias(ah, freq);
  171. reg32 =
  172. (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
  173. (1 << 5) | 0x1;
  174. REG_WRITE(ah, AR_PHY(0x37), reg32);
  175. ah->curchan = chan;
  176. ah->curchan_rad_index = -1;
  177. return 0;
  178. }
  179. /**
  180. * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
  181. * @ah: atheros hardware structure
  182. * @chan:
  183. *
  184. * For non single-chip solutions. Converts to baseband spur frequency given the
  185. * input channel frequency and compute register settings below.
  186. */
  187. static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
  188. struct ath9k_channel *chan)
  189. {
  190. int bb_spur = AR_NO_SPUR;
  191. int bin, cur_bin;
  192. int spur_freq_sd;
  193. int spur_delta_phase;
  194. int denominator;
  195. int upper, lower, cur_vit_mask;
  196. int tmp, new;
  197. int i;
  198. int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
  199. AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
  200. };
  201. int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
  202. AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
  203. };
  204. int inc[4] = { 0, 100, 0, 0 };
  205. int8_t mask_m[123];
  206. int8_t mask_p[123];
  207. int8_t mask_amt;
  208. int tmp_mask;
  209. int cur_bb_spur;
  210. bool is2GHz = IS_CHAN_2GHZ(chan);
  211. memset(&mask_m, 0, sizeof(int8_t) * 123);
  212. memset(&mask_p, 0, sizeof(int8_t) * 123);
  213. for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
  214. cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
  215. if (AR_NO_SPUR == cur_bb_spur)
  216. break;
  217. cur_bb_spur = cur_bb_spur - (chan->channel * 10);
  218. if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
  219. bb_spur = cur_bb_spur;
  220. break;
  221. }
  222. }
  223. if (AR_NO_SPUR == bb_spur)
  224. return;
  225. bin = bb_spur * 32;
  226. tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
  227. new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
  228. AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
  229. AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
  230. AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
  231. REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
  232. new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
  233. AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
  234. AR_PHY_SPUR_REG_MASK_RATE_SELECT |
  235. AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
  236. SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
  237. REG_WRITE(ah, AR_PHY_SPUR_REG, new);
  238. spur_delta_phase = ((bb_spur * 524288) / 100) &
  239. AR_PHY_TIMING11_SPUR_DELTA_PHASE;
  240. denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
  241. spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
  242. new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
  243. SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
  244. SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
  245. REG_WRITE(ah, AR_PHY_TIMING11, new);
  246. cur_bin = -6000;
  247. upper = bin + 100;
  248. lower = bin - 100;
  249. for (i = 0; i < 4; i++) {
  250. int pilot_mask = 0;
  251. int chan_mask = 0;
  252. int bp = 0;
  253. for (bp = 0; bp < 30; bp++) {
  254. if ((cur_bin > lower) && (cur_bin < upper)) {
  255. pilot_mask = pilot_mask | 0x1 << bp;
  256. chan_mask = chan_mask | 0x1 << bp;
  257. }
  258. cur_bin += 100;
  259. }
  260. cur_bin += inc[i];
  261. REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
  262. REG_WRITE(ah, chan_mask_reg[i], chan_mask);
  263. }
  264. cur_vit_mask = 6100;
  265. upper = bin + 120;
  266. lower = bin - 120;
  267. for (i = 0; i < 123; i++) {
  268. if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
  269. /* workaround for gcc bug #37014 */
  270. volatile int tmp_v = abs(cur_vit_mask - bin);
  271. if (tmp_v < 75)
  272. mask_amt = 1;
  273. else
  274. mask_amt = 0;
  275. if (cur_vit_mask < 0)
  276. mask_m[abs(cur_vit_mask / 100)] = mask_amt;
  277. else
  278. mask_p[cur_vit_mask / 100] = mask_amt;
  279. }
  280. cur_vit_mask -= 100;
  281. }
  282. tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
  283. | (mask_m[48] << 26) | (mask_m[49] << 24)
  284. | (mask_m[50] << 22) | (mask_m[51] << 20)
  285. | (mask_m[52] << 18) | (mask_m[53] << 16)
  286. | (mask_m[54] << 14) | (mask_m[55] << 12)
  287. | (mask_m[56] << 10) | (mask_m[57] << 8)
  288. | (mask_m[58] << 6) | (mask_m[59] << 4)
  289. | (mask_m[60] << 2) | (mask_m[61] << 0);
  290. REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
  291. REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
  292. tmp_mask = (mask_m[31] << 28)
  293. | (mask_m[32] << 26) | (mask_m[33] << 24)
  294. | (mask_m[34] << 22) | (mask_m[35] << 20)
  295. | (mask_m[36] << 18) | (mask_m[37] << 16)
  296. | (mask_m[48] << 14) | (mask_m[39] << 12)
  297. | (mask_m[40] << 10) | (mask_m[41] << 8)
  298. | (mask_m[42] << 6) | (mask_m[43] << 4)
  299. | (mask_m[44] << 2) | (mask_m[45] << 0);
  300. REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
  301. REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
  302. tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
  303. | (mask_m[18] << 26) | (mask_m[18] << 24)
  304. | (mask_m[20] << 22) | (mask_m[20] << 20)
  305. | (mask_m[22] << 18) | (mask_m[22] << 16)
  306. | (mask_m[24] << 14) | (mask_m[24] << 12)
  307. | (mask_m[25] << 10) | (mask_m[26] << 8)
  308. | (mask_m[27] << 6) | (mask_m[28] << 4)
  309. | (mask_m[29] << 2) | (mask_m[30] << 0);
  310. REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
  311. REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
  312. tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
  313. | (mask_m[2] << 26) | (mask_m[3] << 24)
  314. | (mask_m[4] << 22) | (mask_m[5] << 20)
  315. | (mask_m[6] << 18) | (mask_m[7] << 16)
  316. | (mask_m[8] << 14) | (mask_m[9] << 12)
  317. | (mask_m[10] << 10) | (mask_m[11] << 8)
  318. | (mask_m[12] << 6) | (mask_m[13] << 4)
  319. | (mask_m[14] << 2) | (mask_m[15] << 0);
  320. REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
  321. REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
  322. tmp_mask = (mask_p[15] << 28)
  323. | (mask_p[14] << 26) | (mask_p[13] << 24)
  324. | (mask_p[12] << 22) | (mask_p[11] << 20)
  325. | (mask_p[10] << 18) | (mask_p[9] << 16)
  326. | (mask_p[8] << 14) | (mask_p[7] << 12)
  327. | (mask_p[6] << 10) | (mask_p[5] << 8)
  328. | (mask_p[4] << 6) | (mask_p[3] << 4)
  329. | (mask_p[2] << 2) | (mask_p[1] << 0);
  330. REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
  331. REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
  332. tmp_mask = (mask_p[30] << 28)
  333. | (mask_p[29] << 26) | (mask_p[28] << 24)
  334. | (mask_p[27] << 22) | (mask_p[26] << 20)
  335. | (mask_p[25] << 18) | (mask_p[24] << 16)
  336. | (mask_p[23] << 14) | (mask_p[22] << 12)
  337. | (mask_p[21] << 10) | (mask_p[20] << 8)
  338. | (mask_p[19] << 6) | (mask_p[18] << 4)
  339. | (mask_p[17] << 2) | (mask_p[16] << 0);
  340. REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
  341. REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
  342. tmp_mask = (mask_p[45] << 28)
  343. | (mask_p[44] << 26) | (mask_p[43] << 24)
  344. | (mask_p[42] << 22) | (mask_p[41] << 20)
  345. | (mask_p[40] << 18) | (mask_p[39] << 16)
  346. | (mask_p[38] << 14) | (mask_p[37] << 12)
  347. | (mask_p[36] << 10) | (mask_p[35] << 8)
  348. | (mask_p[34] << 6) | (mask_p[33] << 4)
  349. | (mask_p[32] << 2) | (mask_p[31] << 0);
  350. REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
  351. REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
  352. tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
  353. | (mask_p[59] << 26) | (mask_p[58] << 24)
  354. | (mask_p[57] << 22) | (mask_p[56] << 20)
  355. | (mask_p[55] << 18) | (mask_p[54] << 16)
  356. | (mask_p[53] << 14) | (mask_p[52] << 12)
  357. | (mask_p[51] << 10) | (mask_p[50] << 8)
  358. | (mask_p[49] << 6) | (mask_p[48] << 4)
  359. | (mask_p[47] << 2) | (mask_p[46] << 0);
  360. REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
  361. REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
  362. }
  363. /**
  364. * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
  365. * @ah: atheros hardware structure
  366. *
  367. * Only required for older devices with external AR2133/AR5133 radios.
  368. */
  369. static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
  370. {
  371. #define ATH_ALLOC_BANK(bank, size) do { \
  372. bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
  373. if (!bank) { \
  374. ath_print(common, ATH_DBG_FATAL, \
  375. "Cannot allocate RF banks\n"); \
  376. return -ENOMEM; \
  377. } \
  378. } while (0);
  379. struct ath_common *common = ath9k_hw_common(ah);
  380. BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
  381. ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
  382. ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
  383. ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
  384. ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
  385. ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
  386. ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
  387. ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
  388. ATH_ALLOC_BANK(ah->addac5416_21,
  389. ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
  390. ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
  391. return 0;
  392. #undef ATH_ALLOC_BANK
  393. }
  394. /**
  395. * ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
  396. * @ah: atheros hardware struture
  397. * For the external AR2133/AR5133 radios banks.
  398. */
  399. static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
  400. {
  401. #define ATH_FREE_BANK(bank) do { \
  402. kfree(bank); \
  403. bank = NULL; \
  404. } while (0);
  405. BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
  406. ATH_FREE_BANK(ah->analogBank0Data);
  407. ATH_FREE_BANK(ah->analogBank1Data);
  408. ATH_FREE_BANK(ah->analogBank2Data);
  409. ATH_FREE_BANK(ah->analogBank3Data);
  410. ATH_FREE_BANK(ah->analogBank6Data);
  411. ATH_FREE_BANK(ah->analogBank6TPCData);
  412. ATH_FREE_BANK(ah->analogBank7Data);
  413. ATH_FREE_BANK(ah->addac5416_21);
  414. ATH_FREE_BANK(ah->bank6Temp);
  415. #undef ATH_FREE_BANK
  416. }
  417. /* *
  418. * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
  419. * @ah: atheros hardware structure
  420. * @chan:
  421. * @modesIndex:
  422. *
  423. * Used for the external AR2133/AR5133 radios.
  424. *
  425. * Reads the EEPROM header info from the device structure and programs
  426. * all rf registers. This routine requires access to the analog
  427. * rf device. This is not required for single-chip devices.
  428. */
  429. static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
  430. struct ath9k_channel *chan,
  431. u16 modesIndex)
  432. {
  433. u32 eepMinorRev;
  434. u32 ob5GHz = 0, db5GHz = 0;
  435. u32 ob2GHz = 0, db2GHz = 0;
  436. int regWrites = 0;
  437. /*
  438. * Software does not need to program bank data
  439. * for single chip devices, that is AR9280 or anything
  440. * after that.
  441. */
  442. if (AR_SREV_9280_10_OR_LATER(ah))
  443. return true;
  444. /* Setup rf parameters */
  445. eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
  446. /* Setup Bank 0 Write */
  447. RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
  448. /* Setup Bank 1 Write */
  449. RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
  450. /* Setup Bank 2 Write */
  451. RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
  452. /* Setup Bank 6 Write */
  453. RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
  454. modesIndex);
  455. {
  456. int i;
  457. for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
  458. ah->analogBank6Data[i] =
  459. INI_RA(&ah->iniBank6TPC, i, modesIndex);
  460. }
  461. }
  462. /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
  463. if (eepMinorRev >= 2) {
  464. if (IS_CHAN_2GHZ(chan)) {
  465. ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
  466. db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
  467. ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
  468. ob2GHz, 3, 197, 0);
  469. ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
  470. db2GHz, 3, 194, 0);
  471. } else {
  472. ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
  473. db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
  474. ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
  475. ob5GHz, 3, 203, 0);
  476. ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
  477. db5GHz, 3, 200, 0);
  478. }
  479. }
  480. /* Setup Bank 7 Setup */
  481. RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
  482. /* Write Analog registers */
  483. REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
  484. regWrites);
  485. REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
  486. regWrites);
  487. REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
  488. regWrites);
  489. REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
  490. regWrites);
  491. REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
  492. regWrites);
  493. REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
  494. regWrites);
  495. return true;
  496. }
  497. static void ar5008_hw_init_bb(struct ath_hw *ah,
  498. struct ath9k_channel *chan)
  499. {
  500. u32 synthDelay;
  501. synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
  502. if (IS_CHAN_B(chan))
  503. synthDelay = (4 * synthDelay) / 22;
  504. else
  505. synthDelay /= 10;
  506. REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
  507. udelay(synthDelay + BASE_ACTIVATE_DELAY);
  508. }
  509. static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
  510. {
  511. int rx_chainmask, tx_chainmask;
  512. rx_chainmask = ah->rxchainmask;
  513. tx_chainmask = ah->txchainmask;
  514. switch (rx_chainmask) {
  515. case 0x5:
  516. REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
  517. AR_PHY_SWAP_ALT_CHAIN);
  518. case 0x3:
  519. if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
  520. REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
  521. REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
  522. break;
  523. }
  524. case 0x1:
  525. case 0x2:
  526. case 0x7:
  527. REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
  528. REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
  529. break;
  530. default:
  531. break;
  532. }
  533. REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
  534. if (tx_chainmask == 0x5) {
  535. REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
  536. AR_PHY_SWAP_ALT_CHAIN);
  537. }
  538. if (AR_SREV_9100(ah))
  539. REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
  540. REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
  541. }
  542. static void ar5008_hw_override_ini(struct ath_hw *ah,
  543. struct ath9k_channel *chan)
  544. {
  545. u32 val;
  546. /*
  547. * Set the RX_ABORT and RX_DIS and clear if off only after
  548. * RXE is set for MAC. This prevents frames with corrupted
  549. * descriptor status.
  550. */
  551. REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
  552. if (AR_SREV_9280_10_OR_LATER(ah)) {
  553. val = REG_READ(ah, AR_PCU_MISC_MODE2);
  554. if (!AR_SREV_9271(ah))
  555. val &= ~AR_PCU_MISC_MODE2_HWWAR1;
  556. if (AR_SREV_9287_10_OR_LATER(ah))
  557. val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
  558. REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
  559. }
  560. if (!AR_SREV_5416_20_OR_LATER(ah) ||
  561. AR_SREV_9280_10_OR_LATER(ah))
  562. return;
  563. /*
  564. * Disable BB clock gating
  565. * Necessary to avoid issues on AR5416 2.0
  566. */
  567. REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
  568. /*
  569. * Disable RIFS search on some chips to avoid baseband
  570. * hang issues.
  571. */
  572. if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
  573. val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
  574. val &= ~AR_PHY_RIFS_INIT_DELAY;
  575. REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
  576. }
  577. }
  578. static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
  579. struct ath9k_channel *chan)
  580. {
  581. u32 phymode;
  582. u32 enableDacFifo = 0;
  583. if (AR_SREV_9285_10_OR_LATER(ah))
  584. enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
  585. AR_PHY_FC_ENABLE_DAC_FIFO);
  586. phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
  587. | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
  588. if (IS_CHAN_HT40(chan)) {
  589. phymode |= AR_PHY_FC_DYN2040_EN;
  590. if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
  591. (chan->chanmode == CHANNEL_G_HT40PLUS))
  592. phymode |= AR_PHY_FC_DYN2040_PRI_CH;
  593. }
  594. REG_WRITE(ah, AR_PHY_TURBO, phymode);
  595. ath9k_hw_set11nmac2040(ah);
  596. REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
  597. REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
  598. }
  599. static int ar5008_hw_process_ini(struct ath_hw *ah,
  600. struct ath9k_channel *chan)
  601. {
  602. struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
  603. int i, regWrites = 0;
  604. struct ieee80211_channel *channel = chan->chan;
  605. u32 modesIndex, freqIndex;
  606. switch (chan->chanmode) {
  607. case CHANNEL_A:
  608. case CHANNEL_A_HT20:
  609. modesIndex = 1;
  610. freqIndex = 1;
  611. break;
  612. case CHANNEL_A_HT40PLUS:
  613. case CHANNEL_A_HT40MINUS:
  614. modesIndex = 2;
  615. freqIndex = 1;
  616. break;
  617. case CHANNEL_G:
  618. case CHANNEL_G_HT20:
  619. case CHANNEL_B:
  620. modesIndex = 4;
  621. freqIndex = 2;
  622. break;
  623. case CHANNEL_G_HT40PLUS:
  624. case CHANNEL_G_HT40MINUS:
  625. modesIndex = 3;
  626. freqIndex = 2;
  627. break;
  628. default:
  629. return -EINVAL;
  630. }
  631. if (AR_SREV_9287_12_OR_LATER(ah)) {
  632. /* Enable ASYNC FIFO */
  633. REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
  634. AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
  635. REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
  636. REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
  637. AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
  638. REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
  639. AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
  640. }
  641. /*
  642. * Set correct baseband to analog shift setting to
  643. * access analog chips.
  644. */
  645. REG_WRITE(ah, AR_PHY(0), 0x00000007);
  646. /* Write ADDAC shifts */
  647. REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
  648. ah->eep_ops->set_addac(ah, chan);
  649. if (AR_SREV_5416_22_OR_LATER(ah)) {
  650. REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
  651. } else {
  652. struct ar5416IniArray temp;
  653. u32 addacSize =
  654. sizeof(u32) * ah->iniAddac.ia_rows *
  655. ah->iniAddac.ia_columns;
  656. /* For AR5416 2.0/2.1 */
  657. memcpy(ah->addac5416_21,
  658. ah->iniAddac.ia_array, addacSize);
  659. /* override CLKDRV value at [row, column] = [31, 1] */
  660. (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
  661. temp.ia_array = ah->addac5416_21;
  662. temp.ia_columns = ah->iniAddac.ia_columns;
  663. temp.ia_rows = ah->iniAddac.ia_rows;
  664. REG_WRITE_ARRAY(&temp, 1, regWrites);
  665. }
  666. REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
  667. for (i = 0; i < ah->iniModes.ia_rows; i++) {
  668. u32 reg = INI_RA(&ah->iniModes, i, 0);
  669. u32 val = INI_RA(&ah->iniModes, i, modesIndex);
  670. if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
  671. val &= ~AR_AN_TOP2_PWDCLKIND;
  672. REG_WRITE(ah, reg, val);
  673. if (reg >= 0x7800 && reg < 0x78a0
  674. && ah->config.analog_shiftreg) {
  675. udelay(100);
  676. }
  677. DO_DELAY(regWrites);
  678. }
  679. if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
  680. REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
  681. if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
  682. AR_SREV_9287_10_OR_LATER(ah))
  683. REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
  684. if (AR_SREV_9271_10(ah))
  685. REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
  686. modesIndex, regWrites);
  687. /* Write common array parameters */
  688. for (i = 0; i < ah->iniCommon.ia_rows; i++) {
  689. u32 reg = INI_RA(&ah->iniCommon, i, 0);
  690. u32 val = INI_RA(&ah->iniCommon, i, 1);
  691. REG_WRITE(ah, reg, val);
  692. if (reg >= 0x7800 && reg < 0x78a0
  693. && ah->config.analog_shiftreg) {
  694. udelay(100);
  695. }
  696. DO_DELAY(regWrites);
  697. }
  698. if (AR_SREV_9271(ah)) {
  699. if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
  700. REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
  701. modesIndex, regWrites);
  702. else
  703. REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
  704. modesIndex, regWrites);
  705. }
  706. REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
  707. if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
  708. REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
  709. regWrites);
  710. }
  711. ar5008_hw_override_ini(ah, chan);
  712. ar5008_hw_set_channel_regs(ah, chan);
  713. ar5008_hw_init_chain_masks(ah);
  714. ath9k_olc_init(ah);
  715. /* Set TX power */
  716. ah->eep_ops->set_txpower(ah, chan,
  717. ath9k_regd_get_ctl(regulatory, chan),
  718. channel->max_antenna_gain * 2,
  719. channel->max_power * 2,
  720. min((u32) MAX_RATE_POWER,
  721. (u32) regulatory->power_limit));
  722. /* Write analog registers */
  723. if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
  724. ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
  725. "ar5416SetRfRegs failed\n");
  726. return -EIO;
  727. }
  728. return 0;
  729. }
  730. static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
  731. {
  732. u32 rfMode = 0;
  733. if (chan == NULL)
  734. return;
  735. rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
  736. ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
  737. if (!AR_SREV_9280_10_OR_LATER(ah))
  738. rfMode |= (IS_CHAN_5GHZ(chan)) ?
  739. AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
  740. if ((AR_SREV_9280_20(ah) || AR_SREV_9300_20_OR_LATER(ah))
  741. && IS_CHAN_A_5MHZ_SPACED(chan))
  742. rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
  743. REG_WRITE(ah, AR_PHY_MODE, rfMode);
  744. }
  745. static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
  746. {
  747. REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
  748. }
  749. static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
  750. struct ath9k_channel *chan)
  751. {
  752. u32 coef_scaled, ds_coef_exp, ds_coef_man;
  753. u32 clockMhzScaled = 0x64000000;
  754. struct chan_centers centers;
  755. if (IS_CHAN_HALF_RATE(chan))
  756. clockMhzScaled = clockMhzScaled >> 1;
  757. else if (IS_CHAN_QUARTER_RATE(chan))
  758. clockMhzScaled = clockMhzScaled >> 2;
  759. ath9k_hw_get_channel_centers(ah, chan, &centers);
  760. coef_scaled = clockMhzScaled / centers.synth_center;
  761. ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
  762. &ds_coef_exp);
  763. REG_RMW_FIELD(ah, AR_PHY_TIMING3,
  764. AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
  765. REG_RMW_FIELD(ah, AR_PHY_TIMING3,
  766. AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
  767. coef_scaled = (9 * coef_scaled) / 10;
  768. ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
  769. &ds_coef_exp);
  770. REG_RMW_FIELD(ah, AR_PHY_HALFGI,
  771. AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
  772. REG_RMW_FIELD(ah, AR_PHY_HALFGI,
  773. AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
  774. }
  775. static bool ar5008_hw_rfbus_req(struct ath_hw *ah)
  776. {
  777. REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
  778. return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
  779. AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
  780. }
  781. static void ar5008_hw_rfbus_done(struct ath_hw *ah)
  782. {
  783. u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
  784. if (IS_CHAN_B(ah->curchan))
  785. synthDelay = (4 * synthDelay) / 22;
  786. else
  787. synthDelay /= 10;
  788. udelay(synthDelay + BASE_ACTIVATE_DELAY);
  789. REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
  790. }
  791. static void ar5008_hw_enable_rfkill(struct ath_hw *ah)
  792. {
  793. REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
  794. AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
  795. REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
  796. AR_GPIO_INPUT_MUX2_RFSILENT);
  797. ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
  798. REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
  799. }
  800. static void ar5008_restore_chainmask(struct ath_hw *ah)
  801. {
  802. int rx_chainmask = ah->rxchainmask;
  803. if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
  804. REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
  805. REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
  806. }
  807. }
  808. static void ar5008_set_diversity(struct ath_hw *ah, bool value)
  809. {
  810. u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
  811. if (value)
  812. v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
  813. else
  814. v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
  815. REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
  816. }
  817. static u32 ar9100_hw_compute_pll_control(struct ath_hw *ah,
  818. struct ath9k_channel *chan)
  819. {
  820. if (chan && IS_CHAN_5GHZ(chan))
  821. return 0x1450;
  822. return 0x1458;
  823. }
  824. static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah,
  825. struct ath9k_channel *chan)
  826. {
  827. u32 pll;
  828. pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
  829. if (chan && IS_CHAN_HALF_RATE(chan))
  830. pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
  831. else if (chan && IS_CHAN_QUARTER_RATE(chan))
  832. pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
  833. if (chan && IS_CHAN_5GHZ(chan))
  834. pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
  835. else
  836. pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
  837. return pll;
  838. }
  839. static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah,
  840. struct ath9k_channel *chan)
  841. {
  842. u32 pll;
  843. pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
  844. if (chan && IS_CHAN_HALF_RATE(chan))
  845. pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
  846. else if (chan && IS_CHAN_QUARTER_RATE(chan))
  847. pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
  848. if (chan && IS_CHAN_5GHZ(chan))
  849. pll |= SM(0xa, AR_RTC_PLL_DIV);
  850. else
  851. pll |= SM(0xb, AR_RTC_PLL_DIV);
  852. return pll;
  853. }
  854. void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
  855. {
  856. struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
  857. priv_ops->rf_set_freq = ar5008_hw_set_channel;
  858. priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
  859. priv_ops->rf_alloc_ext_banks = ar5008_hw_rf_alloc_ext_banks;
  860. priv_ops->rf_free_ext_banks = ar5008_hw_rf_free_ext_banks;
  861. priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
  862. priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
  863. priv_ops->init_bb = ar5008_hw_init_bb;
  864. priv_ops->process_ini = ar5008_hw_process_ini;
  865. priv_ops->set_rfmode = ar5008_hw_set_rfmode;
  866. priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;
  867. priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
  868. priv_ops->rfbus_req = ar5008_hw_rfbus_req;
  869. priv_ops->rfbus_done = ar5008_hw_rfbus_done;
  870. priv_ops->enable_rfkill = ar5008_hw_enable_rfkill;
  871. priv_ops->restore_chainmask = ar5008_restore_chainmask;
  872. priv_ops->set_diversity = ar5008_set_diversity;
  873. if (AR_SREV_9100(ah))
  874. priv_ops->compute_pll_control = ar9100_hw_compute_pll_control;
  875. else if (AR_SREV_9160_10_OR_LATER(ah))
  876. priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
  877. else
  878. priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
  879. }