be_main.c 69 KB

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  1. /*
  2. * Copyright (C) 2005 - 2010 ServerEngines
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License version 2
  7. * as published by the Free Software Foundation. The full GNU General
  8. * Public License is included in this distribution in the file called COPYING.
  9. *
  10. * Contact Information:
  11. * linux-drivers@serverengines.com
  12. *
  13. * ServerEngines
  14. * 209 N. Fair Oaks Ave
  15. * Sunnyvale, CA 94085
  16. */
  17. #include "be.h"
  18. #include "be_cmds.h"
  19. #include <asm/div64.h>
  20. MODULE_VERSION(DRV_VER);
  21. MODULE_DEVICE_TABLE(pci, be_dev_ids);
  22. MODULE_DESCRIPTION(DRV_DESC " " DRV_VER);
  23. MODULE_AUTHOR("ServerEngines Corporation");
  24. MODULE_LICENSE("GPL");
  25. static unsigned int rx_frag_size = 2048;
  26. static unsigned int num_vfs;
  27. module_param(rx_frag_size, uint, S_IRUGO);
  28. module_param(num_vfs, uint, S_IRUGO);
  29. MODULE_PARM_DESC(rx_frag_size, "Size of a fragment that holds rcvd data.");
  30. MODULE_PARM_DESC(num_vfs, "Number of PCI VFs to initialize");
  31. static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = {
  32. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
  33. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
  34. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
  35. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
  36. { 0 }
  37. };
  38. MODULE_DEVICE_TABLE(pci, be_dev_ids);
  39. static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q)
  40. {
  41. struct be_dma_mem *mem = &q->dma_mem;
  42. if (mem->va)
  43. pci_free_consistent(adapter->pdev, mem->size,
  44. mem->va, mem->dma);
  45. }
  46. static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q,
  47. u16 len, u16 entry_size)
  48. {
  49. struct be_dma_mem *mem = &q->dma_mem;
  50. memset(q, 0, sizeof(*q));
  51. q->len = len;
  52. q->entry_size = entry_size;
  53. mem->size = len * entry_size;
  54. mem->va = pci_alloc_consistent(adapter->pdev, mem->size, &mem->dma);
  55. if (!mem->va)
  56. return -1;
  57. memset(mem->va, 0, mem->size);
  58. return 0;
  59. }
  60. static void be_intr_set(struct be_adapter *adapter, bool enable)
  61. {
  62. u8 __iomem *addr = adapter->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
  63. u32 reg = ioread32(addr);
  64. u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  65. if (adapter->eeh_err)
  66. return;
  67. if (!enabled && enable)
  68. reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  69. else if (enabled && !enable)
  70. reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  71. else
  72. return;
  73. iowrite32(reg, addr);
  74. }
  75. static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
  76. {
  77. u32 val = 0;
  78. val |= qid & DB_RQ_RING_ID_MASK;
  79. val |= posted << DB_RQ_NUM_POSTED_SHIFT;
  80. wmb();
  81. iowrite32(val, adapter->db + DB_RQ_OFFSET);
  82. }
  83. static void be_txq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
  84. {
  85. u32 val = 0;
  86. val |= qid & DB_TXULP_RING_ID_MASK;
  87. val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT;
  88. wmb();
  89. iowrite32(val, adapter->db + DB_TXULP1_OFFSET);
  90. }
  91. static void be_eq_notify(struct be_adapter *adapter, u16 qid,
  92. bool arm, bool clear_int, u16 num_popped)
  93. {
  94. u32 val = 0;
  95. val |= qid & DB_EQ_RING_ID_MASK;
  96. if (adapter->eeh_err)
  97. return;
  98. if (arm)
  99. val |= 1 << DB_EQ_REARM_SHIFT;
  100. if (clear_int)
  101. val |= 1 << DB_EQ_CLR_SHIFT;
  102. val |= 1 << DB_EQ_EVNT_SHIFT;
  103. val |= num_popped << DB_EQ_NUM_POPPED_SHIFT;
  104. iowrite32(val, adapter->db + DB_EQ_OFFSET);
  105. }
  106. void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, u16 num_popped)
  107. {
  108. u32 val = 0;
  109. val |= qid & DB_CQ_RING_ID_MASK;
  110. if (adapter->eeh_err)
  111. return;
  112. if (arm)
  113. val |= 1 << DB_CQ_REARM_SHIFT;
  114. val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
  115. iowrite32(val, adapter->db + DB_CQ_OFFSET);
  116. }
  117. static int be_mac_addr_set(struct net_device *netdev, void *p)
  118. {
  119. struct be_adapter *adapter = netdev_priv(netdev);
  120. struct sockaddr *addr = p;
  121. int status = 0;
  122. if (!is_valid_ether_addr(addr->sa_data))
  123. return -EADDRNOTAVAIL;
  124. /* MAC addr configuration will be done in hardware for VFs
  125. * by their corresponding PFs. Just copy to netdev addr here
  126. */
  127. if (!be_physfn(adapter))
  128. goto netdev_addr;
  129. status = be_cmd_pmac_del(adapter, adapter->if_handle, adapter->pmac_id);
  130. if (status)
  131. return status;
  132. status = be_cmd_pmac_add(adapter, (u8 *)addr->sa_data,
  133. adapter->if_handle, &adapter->pmac_id);
  134. netdev_addr:
  135. if (!status)
  136. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  137. return status;
  138. }
  139. void netdev_stats_update(struct be_adapter *adapter)
  140. {
  141. struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats.cmd.va);
  142. struct be_rxf_stats *rxf_stats = &hw_stats->rxf;
  143. struct be_port_rxf_stats *port_stats =
  144. &rxf_stats->port[adapter->port_num];
  145. struct net_device_stats *dev_stats = &adapter->netdev->stats;
  146. struct be_erx_stats *erx_stats = &hw_stats->erx;
  147. dev_stats->rx_packets = drvr_stats(adapter)->be_rx_pkts;
  148. dev_stats->tx_packets = drvr_stats(adapter)->be_tx_pkts;
  149. dev_stats->rx_bytes = drvr_stats(adapter)->be_rx_bytes;
  150. dev_stats->tx_bytes = drvr_stats(adapter)->be_tx_bytes;
  151. /* bad pkts received */
  152. dev_stats->rx_errors = port_stats->rx_crc_errors +
  153. port_stats->rx_alignment_symbol_errors +
  154. port_stats->rx_in_range_errors +
  155. port_stats->rx_out_range_errors +
  156. port_stats->rx_frame_too_long +
  157. port_stats->rx_dropped_too_small +
  158. port_stats->rx_dropped_too_short +
  159. port_stats->rx_dropped_header_too_small +
  160. port_stats->rx_dropped_tcp_length +
  161. port_stats->rx_dropped_runt +
  162. port_stats->rx_tcp_checksum_errs +
  163. port_stats->rx_ip_checksum_errs +
  164. port_stats->rx_udp_checksum_errs;
  165. /* no space in linux buffers: best possible approximation */
  166. dev_stats->rx_dropped =
  167. erx_stats->rx_drops_no_fragments[adapter->rx_obj.q.id];
  168. /* detailed rx errors */
  169. dev_stats->rx_length_errors = port_stats->rx_in_range_errors +
  170. port_stats->rx_out_range_errors +
  171. port_stats->rx_frame_too_long;
  172. /* receive ring buffer overflow */
  173. dev_stats->rx_over_errors = 0;
  174. dev_stats->rx_crc_errors = port_stats->rx_crc_errors;
  175. /* frame alignment errors */
  176. dev_stats->rx_frame_errors = port_stats->rx_alignment_symbol_errors;
  177. /* receiver fifo overrun */
  178. /* drops_no_pbuf is no per i/f, it's per BE card */
  179. dev_stats->rx_fifo_errors = port_stats->rx_fifo_overflow +
  180. port_stats->rx_input_fifo_overflow +
  181. rxf_stats->rx_drops_no_pbuf;
  182. /* receiver missed packetd */
  183. dev_stats->rx_missed_errors = 0;
  184. /* packet transmit problems */
  185. dev_stats->tx_errors = 0;
  186. /* no space available in linux */
  187. dev_stats->tx_dropped = 0;
  188. dev_stats->multicast = port_stats->rx_multicast_frames;
  189. dev_stats->collisions = 0;
  190. /* detailed tx_errors */
  191. dev_stats->tx_aborted_errors = 0;
  192. dev_stats->tx_carrier_errors = 0;
  193. dev_stats->tx_fifo_errors = 0;
  194. dev_stats->tx_heartbeat_errors = 0;
  195. dev_stats->tx_window_errors = 0;
  196. }
  197. void be_link_status_update(struct be_adapter *adapter, bool link_up)
  198. {
  199. struct net_device *netdev = adapter->netdev;
  200. /* If link came up or went down */
  201. if (adapter->link_up != link_up) {
  202. adapter->link_speed = -1;
  203. if (link_up) {
  204. netif_start_queue(netdev);
  205. netif_carrier_on(netdev);
  206. printk(KERN_INFO "%s: Link up\n", netdev->name);
  207. } else {
  208. netif_stop_queue(netdev);
  209. netif_carrier_off(netdev);
  210. printk(KERN_INFO "%s: Link down\n", netdev->name);
  211. }
  212. adapter->link_up = link_up;
  213. }
  214. }
  215. /* Update the EQ delay n BE based on the RX frags consumed / sec */
  216. static void be_rx_eqd_update(struct be_adapter *adapter)
  217. {
  218. struct be_eq_obj *rx_eq = &adapter->rx_eq;
  219. struct be_drvr_stats *stats = &adapter->stats.drvr_stats;
  220. ulong now = jiffies;
  221. u32 eqd;
  222. if (!rx_eq->enable_aic)
  223. return;
  224. /* Wrapped around */
  225. if (time_before(now, stats->rx_fps_jiffies)) {
  226. stats->rx_fps_jiffies = now;
  227. return;
  228. }
  229. /* Update once a second */
  230. if ((now - stats->rx_fps_jiffies) < HZ)
  231. return;
  232. stats->be_rx_fps = (stats->be_rx_frags - stats->be_prev_rx_frags) /
  233. ((now - stats->rx_fps_jiffies) / HZ);
  234. stats->rx_fps_jiffies = now;
  235. stats->be_prev_rx_frags = stats->be_rx_frags;
  236. eqd = stats->be_rx_fps / 110000;
  237. eqd = eqd << 3;
  238. if (eqd > rx_eq->max_eqd)
  239. eqd = rx_eq->max_eqd;
  240. if (eqd < rx_eq->min_eqd)
  241. eqd = rx_eq->min_eqd;
  242. if (eqd < 10)
  243. eqd = 0;
  244. if (eqd != rx_eq->cur_eqd)
  245. be_cmd_modify_eqd(adapter, rx_eq->q.id, eqd);
  246. rx_eq->cur_eqd = eqd;
  247. }
  248. static struct net_device_stats *be_get_stats(struct net_device *dev)
  249. {
  250. return &dev->stats;
  251. }
  252. static u32 be_calc_rate(u64 bytes, unsigned long ticks)
  253. {
  254. u64 rate = bytes;
  255. do_div(rate, ticks / HZ);
  256. rate <<= 3; /* bytes/sec -> bits/sec */
  257. do_div(rate, 1000000ul); /* MB/Sec */
  258. return rate;
  259. }
  260. static void be_tx_rate_update(struct be_adapter *adapter)
  261. {
  262. struct be_drvr_stats *stats = drvr_stats(adapter);
  263. ulong now = jiffies;
  264. /* Wrapped around? */
  265. if (time_before(now, stats->be_tx_jiffies)) {
  266. stats->be_tx_jiffies = now;
  267. return;
  268. }
  269. /* Update tx rate once in two seconds */
  270. if ((now - stats->be_tx_jiffies) > 2 * HZ) {
  271. stats->be_tx_rate = be_calc_rate(stats->be_tx_bytes
  272. - stats->be_tx_bytes_prev,
  273. now - stats->be_tx_jiffies);
  274. stats->be_tx_jiffies = now;
  275. stats->be_tx_bytes_prev = stats->be_tx_bytes;
  276. }
  277. }
  278. static void be_tx_stats_update(struct be_adapter *adapter,
  279. u32 wrb_cnt, u32 copied, u32 gso_segs, bool stopped)
  280. {
  281. struct be_drvr_stats *stats = drvr_stats(adapter);
  282. stats->be_tx_reqs++;
  283. stats->be_tx_wrbs += wrb_cnt;
  284. stats->be_tx_bytes += copied;
  285. stats->be_tx_pkts += (gso_segs ? gso_segs : 1);
  286. if (stopped)
  287. stats->be_tx_stops++;
  288. }
  289. /* Determine number of WRB entries needed to xmit data in an skb */
  290. static u32 wrb_cnt_for_skb(struct sk_buff *skb, bool *dummy)
  291. {
  292. int cnt = (skb->len > skb->data_len);
  293. cnt += skb_shinfo(skb)->nr_frags;
  294. /* to account for hdr wrb */
  295. cnt++;
  296. if (cnt & 1) {
  297. /* add a dummy to make it an even num */
  298. cnt++;
  299. *dummy = true;
  300. } else
  301. *dummy = false;
  302. BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT);
  303. return cnt;
  304. }
  305. static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len)
  306. {
  307. wrb->frag_pa_hi = upper_32_bits(addr);
  308. wrb->frag_pa_lo = addr & 0xFFFFFFFF;
  309. wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK;
  310. }
  311. static void wrb_fill_hdr(struct be_eth_hdr_wrb *hdr, struct sk_buff *skb,
  312. bool vlan, u32 wrb_cnt, u32 len)
  313. {
  314. memset(hdr, 0, sizeof(*hdr));
  315. AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1);
  316. if (skb_is_gso(skb)) {
  317. AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1);
  318. AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss,
  319. hdr, skb_shinfo(skb)->gso_size);
  320. if (skb_is_gso_v6(skb))
  321. AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso6, hdr, 1);
  322. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  323. if (is_tcp_pkt(skb))
  324. AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1);
  325. else if (is_udp_pkt(skb))
  326. AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1);
  327. }
  328. if (vlan && vlan_tx_tag_present(skb)) {
  329. AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1);
  330. AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag,
  331. hdr, vlan_tx_tag_get(skb));
  332. }
  333. AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1);
  334. AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1);
  335. AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt);
  336. AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len);
  337. }
  338. static void unmap_tx_frag(struct pci_dev *pdev, struct be_eth_wrb *wrb,
  339. bool unmap_single)
  340. {
  341. dma_addr_t dma;
  342. be_dws_le_to_cpu(wrb, sizeof(*wrb));
  343. dma = (u64)wrb->frag_pa_hi << 32 | (u64)wrb->frag_pa_lo;
  344. if (wrb->frag_len) {
  345. if (unmap_single)
  346. pci_unmap_single(pdev, dma, wrb->frag_len,
  347. PCI_DMA_TODEVICE);
  348. else
  349. pci_unmap_page(pdev, dma, wrb->frag_len,
  350. PCI_DMA_TODEVICE);
  351. }
  352. }
  353. static int make_tx_wrbs(struct be_adapter *adapter,
  354. struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb)
  355. {
  356. dma_addr_t busaddr;
  357. int i, copied = 0;
  358. struct pci_dev *pdev = adapter->pdev;
  359. struct sk_buff *first_skb = skb;
  360. struct be_queue_info *txq = &adapter->tx_obj.q;
  361. struct be_eth_wrb *wrb;
  362. struct be_eth_hdr_wrb *hdr;
  363. bool map_single = false;
  364. u16 map_head;
  365. hdr = queue_head_node(txq);
  366. queue_head_inc(txq);
  367. map_head = txq->head;
  368. if (skb->len > skb->data_len) {
  369. int len = skb_headlen(skb);
  370. busaddr = pci_map_single(pdev, skb->data, len,
  371. PCI_DMA_TODEVICE);
  372. if (pci_dma_mapping_error(pdev, busaddr))
  373. goto dma_err;
  374. map_single = true;
  375. wrb = queue_head_node(txq);
  376. wrb_fill(wrb, busaddr, len);
  377. be_dws_cpu_to_le(wrb, sizeof(*wrb));
  378. queue_head_inc(txq);
  379. copied += len;
  380. }
  381. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  382. struct skb_frag_struct *frag =
  383. &skb_shinfo(skb)->frags[i];
  384. busaddr = pci_map_page(pdev, frag->page,
  385. frag->page_offset,
  386. frag->size, PCI_DMA_TODEVICE);
  387. if (pci_dma_mapping_error(pdev, busaddr))
  388. goto dma_err;
  389. wrb = queue_head_node(txq);
  390. wrb_fill(wrb, busaddr, frag->size);
  391. be_dws_cpu_to_le(wrb, sizeof(*wrb));
  392. queue_head_inc(txq);
  393. copied += frag->size;
  394. }
  395. if (dummy_wrb) {
  396. wrb = queue_head_node(txq);
  397. wrb_fill(wrb, 0, 0);
  398. be_dws_cpu_to_le(wrb, sizeof(*wrb));
  399. queue_head_inc(txq);
  400. }
  401. wrb_fill_hdr(hdr, first_skb, adapter->vlan_grp ? true : false,
  402. wrb_cnt, copied);
  403. be_dws_cpu_to_le(hdr, sizeof(*hdr));
  404. return copied;
  405. dma_err:
  406. txq->head = map_head;
  407. while (copied) {
  408. wrb = queue_head_node(txq);
  409. unmap_tx_frag(pdev, wrb, map_single);
  410. map_single = false;
  411. copied -= wrb->frag_len;
  412. queue_head_inc(txq);
  413. }
  414. return 0;
  415. }
  416. static netdev_tx_t be_xmit(struct sk_buff *skb,
  417. struct net_device *netdev)
  418. {
  419. struct be_adapter *adapter = netdev_priv(netdev);
  420. struct be_tx_obj *tx_obj = &adapter->tx_obj;
  421. struct be_queue_info *txq = &tx_obj->q;
  422. u32 wrb_cnt = 0, copied = 0;
  423. u32 start = txq->head;
  424. bool dummy_wrb, stopped = false;
  425. wrb_cnt = wrb_cnt_for_skb(skb, &dummy_wrb);
  426. copied = make_tx_wrbs(adapter, skb, wrb_cnt, dummy_wrb);
  427. if (copied) {
  428. /* record the sent skb in the sent_skb table */
  429. BUG_ON(tx_obj->sent_skb_list[start]);
  430. tx_obj->sent_skb_list[start] = skb;
  431. /* Ensure txq has space for the next skb; Else stop the queue
  432. * *BEFORE* ringing the tx doorbell, so that we serialze the
  433. * tx compls of the current transmit which'll wake up the queue
  434. */
  435. atomic_add(wrb_cnt, &txq->used);
  436. if ((BE_MAX_TX_FRAG_COUNT + atomic_read(&txq->used)) >=
  437. txq->len) {
  438. netif_stop_queue(netdev);
  439. stopped = true;
  440. }
  441. be_txq_notify(adapter, txq->id, wrb_cnt);
  442. be_tx_stats_update(adapter, wrb_cnt, copied,
  443. skb_shinfo(skb)->gso_segs, stopped);
  444. } else {
  445. txq->head = start;
  446. dev_kfree_skb_any(skb);
  447. }
  448. return NETDEV_TX_OK;
  449. }
  450. static int be_change_mtu(struct net_device *netdev, int new_mtu)
  451. {
  452. struct be_adapter *adapter = netdev_priv(netdev);
  453. if (new_mtu < BE_MIN_MTU ||
  454. new_mtu > (BE_MAX_JUMBO_FRAME_SIZE -
  455. (ETH_HLEN + ETH_FCS_LEN))) {
  456. dev_info(&adapter->pdev->dev,
  457. "MTU must be between %d and %d bytes\n",
  458. BE_MIN_MTU,
  459. (BE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN)));
  460. return -EINVAL;
  461. }
  462. dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n",
  463. netdev->mtu, new_mtu);
  464. netdev->mtu = new_mtu;
  465. return 0;
  466. }
  467. /*
  468. * A max of 64 (BE_NUM_VLANS_SUPPORTED) vlans can be configured in BE.
  469. * If the user configures more, place BE in vlan promiscuous mode.
  470. */
  471. static int be_vid_config(struct be_adapter *adapter)
  472. {
  473. u16 vtag[BE_NUM_VLANS_SUPPORTED];
  474. u16 ntags = 0, i;
  475. int status = 0;
  476. if (adapter->vlans_added <= adapter->max_vlans) {
  477. /* Construct VLAN Table to give to HW */
  478. for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
  479. if (adapter->vlan_tag[i]) {
  480. vtag[ntags] = cpu_to_le16(i);
  481. ntags++;
  482. }
  483. }
  484. status = be_cmd_vlan_config(adapter, adapter->if_handle,
  485. vtag, ntags, 1, 0);
  486. } else {
  487. status = be_cmd_vlan_config(adapter, adapter->if_handle,
  488. NULL, 0, 1, 1);
  489. }
  490. return status;
  491. }
  492. static void be_vlan_register(struct net_device *netdev, struct vlan_group *grp)
  493. {
  494. struct be_adapter *adapter = netdev_priv(netdev);
  495. struct be_eq_obj *rx_eq = &adapter->rx_eq;
  496. struct be_eq_obj *tx_eq = &adapter->tx_eq;
  497. be_eq_notify(adapter, rx_eq->q.id, false, false, 0);
  498. be_eq_notify(adapter, tx_eq->q.id, false, false, 0);
  499. adapter->vlan_grp = grp;
  500. be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
  501. be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
  502. }
  503. static void be_vlan_add_vid(struct net_device *netdev, u16 vid)
  504. {
  505. struct be_adapter *adapter = netdev_priv(netdev);
  506. if (!be_physfn(adapter))
  507. return;
  508. adapter->vlan_tag[vid] = 1;
  509. adapter->vlans_added++;
  510. if (adapter->vlans_added <= (adapter->max_vlans + 1))
  511. be_vid_config(adapter);
  512. }
  513. static void be_vlan_rem_vid(struct net_device *netdev, u16 vid)
  514. {
  515. struct be_adapter *adapter = netdev_priv(netdev);
  516. if (!be_physfn(adapter))
  517. return;
  518. adapter->vlan_tag[vid] = 0;
  519. vlan_group_set_device(adapter->vlan_grp, vid, NULL);
  520. adapter->vlans_added--;
  521. if (adapter->vlans_added <= adapter->max_vlans)
  522. be_vid_config(adapter);
  523. }
  524. static void be_set_multicast_list(struct net_device *netdev)
  525. {
  526. struct be_adapter *adapter = netdev_priv(netdev);
  527. if (netdev->flags & IFF_PROMISC) {
  528. be_cmd_promiscuous_config(adapter, adapter->port_num, 1);
  529. adapter->promiscuous = true;
  530. goto done;
  531. }
  532. /* BE was previously in promiscous mode; disable it */
  533. if (adapter->promiscuous) {
  534. adapter->promiscuous = false;
  535. be_cmd_promiscuous_config(adapter, adapter->port_num, 0);
  536. }
  537. /* Enable multicast promisc if num configured exceeds what we support */
  538. if (netdev->flags & IFF_ALLMULTI ||
  539. netdev_mc_count(netdev) > BE_MAX_MC) {
  540. be_cmd_multicast_set(adapter, adapter->if_handle, NULL,
  541. &adapter->mc_cmd_mem);
  542. goto done;
  543. }
  544. be_cmd_multicast_set(adapter, adapter->if_handle, netdev,
  545. &adapter->mc_cmd_mem);
  546. done:
  547. return;
  548. }
  549. static int be_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
  550. {
  551. struct be_adapter *adapter = netdev_priv(netdev);
  552. int status;
  553. if (!adapter->sriov_enabled)
  554. return -EPERM;
  555. if (!is_valid_ether_addr(mac) || (vf >= num_vfs))
  556. return -EINVAL;
  557. if (adapter->vf_cfg[vf].vf_pmac_id != BE_INVALID_PMAC_ID)
  558. status = be_cmd_pmac_del(adapter,
  559. adapter->vf_cfg[vf].vf_if_handle,
  560. adapter->vf_cfg[vf].vf_pmac_id);
  561. status = be_cmd_pmac_add(adapter, mac,
  562. adapter->vf_cfg[vf].vf_if_handle,
  563. &adapter->vf_cfg[vf].vf_pmac_id);
  564. if (status)
  565. dev_err(&adapter->pdev->dev, "MAC %pM set on VF %d Failed\n",
  566. mac, vf);
  567. else
  568. memcpy(adapter->vf_cfg[vf].vf_mac_addr, mac, ETH_ALEN);
  569. return status;
  570. }
  571. static int be_get_vf_config(struct net_device *netdev, int vf,
  572. struct ifla_vf_info *vi)
  573. {
  574. struct be_adapter *adapter = netdev_priv(netdev);
  575. if (!adapter->sriov_enabled)
  576. return -EPERM;
  577. if (vf >= num_vfs)
  578. return -EINVAL;
  579. vi->vf = vf;
  580. vi->tx_rate = 0;
  581. vi->vlan = 0;
  582. vi->qos = 0;
  583. memcpy(&vi->mac, adapter->vf_cfg[vf].vf_mac_addr, ETH_ALEN);
  584. return 0;
  585. }
  586. static void be_rx_rate_update(struct be_adapter *adapter)
  587. {
  588. struct be_drvr_stats *stats = drvr_stats(adapter);
  589. ulong now = jiffies;
  590. /* Wrapped around */
  591. if (time_before(now, stats->be_rx_jiffies)) {
  592. stats->be_rx_jiffies = now;
  593. return;
  594. }
  595. /* Update the rate once in two seconds */
  596. if ((now - stats->be_rx_jiffies) < 2 * HZ)
  597. return;
  598. stats->be_rx_rate = be_calc_rate(stats->be_rx_bytes
  599. - stats->be_rx_bytes_prev,
  600. now - stats->be_rx_jiffies);
  601. stats->be_rx_jiffies = now;
  602. stats->be_rx_bytes_prev = stats->be_rx_bytes;
  603. }
  604. static void be_rx_stats_update(struct be_adapter *adapter,
  605. u32 pktsize, u16 numfrags)
  606. {
  607. struct be_drvr_stats *stats = drvr_stats(adapter);
  608. stats->be_rx_compl++;
  609. stats->be_rx_frags += numfrags;
  610. stats->be_rx_bytes += pktsize;
  611. stats->be_rx_pkts++;
  612. }
  613. static inline bool do_pkt_csum(struct be_eth_rx_compl *rxcp, bool cso)
  614. {
  615. u8 l4_cksm, ip_version, ipcksm, tcpf = 0, udpf = 0, ipv6_chk;
  616. l4_cksm = AMAP_GET_BITS(struct amap_eth_rx_compl, l4_cksm, rxcp);
  617. ipcksm = AMAP_GET_BITS(struct amap_eth_rx_compl, ipcksm, rxcp);
  618. ip_version = AMAP_GET_BITS(struct amap_eth_rx_compl, ip_version, rxcp);
  619. if (ip_version) {
  620. tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
  621. udpf = AMAP_GET_BITS(struct amap_eth_rx_compl, udpf, rxcp);
  622. }
  623. ipv6_chk = (ip_version && (tcpf || udpf));
  624. return ((l4_cksm && ipv6_chk && ipcksm) && cso) ? false : true;
  625. }
  626. static struct be_rx_page_info *
  627. get_rx_page_info(struct be_adapter *adapter, u16 frag_idx)
  628. {
  629. struct be_rx_page_info *rx_page_info;
  630. struct be_queue_info *rxq = &adapter->rx_obj.q;
  631. rx_page_info = &adapter->rx_obj.page_info_tbl[frag_idx];
  632. BUG_ON(!rx_page_info->page);
  633. if (rx_page_info->last_page_user) {
  634. pci_unmap_page(adapter->pdev, dma_unmap_addr(rx_page_info, bus),
  635. adapter->big_page_size, PCI_DMA_FROMDEVICE);
  636. rx_page_info->last_page_user = false;
  637. }
  638. atomic_dec(&rxq->used);
  639. return rx_page_info;
  640. }
  641. /* Throwaway the data in the Rx completion */
  642. static void be_rx_compl_discard(struct be_adapter *adapter,
  643. struct be_eth_rx_compl *rxcp)
  644. {
  645. struct be_queue_info *rxq = &adapter->rx_obj.q;
  646. struct be_rx_page_info *page_info;
  647. u16 rxq_idx, i, num_rcvd;
  648. rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
  649. num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
  650. for (i = 0; i < num_rcvd; i++) {
  651. page_info = get_rx_page_info(adapter, rxq_idx);
  652. put_page(page_info->page);
  653. memset(page_info, 0, sizeof(*page_info));
  654. index_inc(&rxq_idx, rxq->len);
  655. }
  656. }
  657. /*
  658. * skb_fill_rx_data forms a complete skb for an ether frame
  659. * indicated by rxcp.
  660. */
  661. static void skb_fill_rx_data(struct be_adapter *adapter,
  662. struct sk_buff *skb, struct be_eth_rx_compl *rxcp,
  663. u16 num_rcvd)
  664. {
  665. struct be_queue_info *rxq = &adapter->rx_obj.q;
  666. struct be_rx_page_info *page_info;
  667. u16 rxq_idx, i, j;
  668. u32 pktsize, hdr_len, curr_frag_len, size;
  669. u8 *start;
  670. rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
  671. pktsize = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
  672. page_info = get_rx_page_info(adapter, rxq_idx);
  673. start = page_address(page_info->page) + page_info->page_offset;
  674. prefetch(start);
  675. /* Copy data in the first descriptor of this completion */
  676. curr_frag_len = min(pktsize, rx_frag_size);
  677. /* Copy the header portion into skb_data */
  678. hdr_len = min((u32)BE_HDR_LEN, curr_frag_len);
  679. memcpy(skb->data, start, hdr_len);
  680. skb->len = curr_frag_len;
  681. if (curr_frag_len <= BE_HDR_LEN) { /* tiny packet */
  682. /* Complete packet has now been moved to data */
  683. put_page(page_info->page);
  684. skb->data_len = 0;
  685. skb->tail += curr_frag_len;
  686. } else {
  687. skb_shinfo(skb)->nr_frags = 1;
  688. skb_shinfo(skb)->frags[0].page = page_info->page;
  689. skb_shinfo(skb)->frags[0].page_offset =
  690. page_info->page_offset + hdr_len;
  691. skb_shinfo(skb)->frags[0].size = curr_frag_len - hdr_len;
  692. skb->data_len = curr_frag_len - hdr_len;
  693. skb->tail += hdr_len;
  694. }
  695. page_info->page = NULL;
  696. if (pktsize <= rx_frag_size) {
  697. BUG_ON(num_rcvd != 1);
  698. goto done;
  699. }
  700. /* More frags present for this completion */
  701. size = pktsize;
  702. for (i = 1, j = 0; i < num_rcvd; i++) {
  703. size -= curr_frag_len;
  704. index_inc(&rxq_idx, rxq->len);
  705. page_info = get_rx_page_info(adapter, rxq_idx);
  706. curr_frag_len = min(size, rx_frag_size);
  707. /* Coalesce all frags from the same physical page in one slot */
  708. if (page_info->page_offset == 0) {
  709. /* Fresh page */
  710. j++;
  711. skb_shinfo(skb)->frags[j].page = page_info->page;
  712. skb_shinfo(skb)->frags[j].page_offset =
  713. page_info->page_offset;
  714. skb_shinfo(skb)->frags[j].size = 0;
  715. skb_shinfo(skb)->nr_frags++;
  716. } else {
  717. put_page(page_info->page);
  718. }
  719. skb_shinfo(skb)->frags[j].size += curr_frag_len;
  720. skb->len += curr_frag_len;
  721. skb->data_len += curr_frag_len;
  722. page_info->page = NULL;
  723. }
  724. BUG_ON(j > MAX_SKB_FRAGS);
  725. done:
  726. be_rx_stats_update(adapter, pktsize, num_rcvd);
  727. }
  728. /* Process the RX completion indicated by rxcp when GRO is disabled */
  729. static void be_rx_compl_process(struct be_adapter *adapter,
  730. struct be_eth_rx_compl *rxcp)
  731. {
  732. struct sk_buff *skb;
  733. u32 vlanf, vid;
  734. u16 num_rcvd;
  735. u8 vtm;
  736. num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
  737. /* Is it a flush compl that has no data */
  738. if (unlikely(num_rcvd == 0))
  739. return;
  740. skb = netdev_alloc_skb_ip_align(adapter->netdev, BE_HDR_LEN);
  741. if (unlikely(!skb)) {
  742. if (net_ratelimit())
  743. dev_warn(&adapter->pdev->dev, "skb alloc failed\n");
  744. be_rx_compl_discard(adapter, rxcp);
  745. return;
  746. }
  747. skb_fill_rx_data(adapter, skb, rxcp, num_rcvd);
  748. if (do_pkt_csum(rxcp, adapter->rx_csum))
  749. skb->ip_summed = CHECKSUM_NONE;
  750. else
  751. skb->ip_summed = CHECKSUM_UNNECESSARY;
  752. skb->truesize = skb->len + sizeof(struct sk_buff);
  753. skb->protocol = eth_type_trans(skb, adapter->netdev);
  754. vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
  755. vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
  756. /* vlanf could be wrongly set in some cards.
  757. * ignore if vtm is not set */
  758. if ((adapter->cap & 0x400) && !vtm)
  759. vlanf = 0;
  760. if (unlikely(vlanf)) {
  761. if (!adapter->vlan_grp || adapter->vlans_added == 0) {
  762. kfree_skb(skb);
  763. return;
  764. }
  765. vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
  766. vid = swab16(vid);
  767. vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, vid);
  768. } else {
  769. netif_receive_skb(skb);
  770. }
  771. }
  772. /* Process the RX completion indicated by rxcp when GRO is enabled */
  773. static void be_rx_compl_process_gro(struct be_adapter *adapter,
  774. struct be_eth_rx_compl *rxcp)
  775. {
  776. struct be_rx_page_info *page_info;
  777. struct sk_buff *skb = NULL;
  778. struct be_queue_info *rxq = &adapter->rx_obj.q;
  779. struct be_eq_obj *eq_obj = &adapter->rx_eq;
  780. u32 num_rcvd, pkt_size, remaining, vlanf, curr_frag_len;
  781. u16 i, rxq_idx = 0, vid, j;
  782. u8 vtm;
  783. num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
  784. /* Is it a flush compl that has no data */
  785. if (unlikely(num_rcvd == 0))
  786. return;
  787. pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
  788. vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
  789. rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
  790. vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
  791. /* vlanf could be wrongly set in some cards.
  792. * ignore if vtm is not set */
  793. if ((adapter->cap & 0x400) && !vtm)
  794. vlanf = 0;
  795. skb = napi_get_frags(&eq_obj->napi);
  796. if (!skb) {
  797. be_rx_compl_discard(adapter, rxcp);
  798. return;
  799. }
  800. remaining = pkt_size;
  801. for (i = 0, j = -1; i < num_rcvd; i++) {
  802. page_info = get_rx_page_info(adapter, rxq_idx);
  803. curr_frag_len = min(remaining, rx_frag_size);
  804. /* Coalesce all frags from the same physical page in one slot */
  805. if (i == 0 || page_info->page_offset == 0) {
  806. /* First frag or Fresh page */
  807. j++;
  808. skb_shinfo(skb)->frags[j].page = page_info->page;
  809. skb_shinfo(skb)->frags[j].page_offset =
  810. page_info->page_offset;
  811. skb_shinfo(skb)->frags[j].size = 0;
  812. } else {
  813. put_page(page_info->page);
  814. }
  815. skb_shinfo(skb)->frags[j].size += curr_frag_len;
  816. remaining -= curr_frag_len;
  817. index_inc(&rxq_idx, rxq->len);
  818. memset(page_info, 0, sizeof(*page_info));
  819. }
  820. BUG_ON(j > MAX_SKB_FRAGS);
  821. skb_shinfo(skb)->nr_frags = j + 1;
  822. skb->len = pkt_size;
  823. skb->data_len = pkt_size;
  824. skb->truesize += pkt_size;
  825. skb->ip_summed = CHECKSUM_UNNECESSARY;
  826. if (likely(!vlanf)) {
  827. napi_gro_frags(&eq_obj->napi);
  828. } else {
  829. vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
  830. vid = swab16(vid);
  831. if (!adapter->vlan_grp || adapter->vlans_added == 0)
  832. return;
  833. vlan_gro_frags(&eq_obj->napi, adapter->vlan_grp, vid);
  834. }
  835. be_rx_stats_update(adapter, pkt_size, num_rcvd);
  836. }
  837. static struct be_eth_rx_compl *be_rx_compl_get(struct be_adapter *adapter)
  838. {
  839. struct be_eth_rx_compl *rxcp = queue_tail_node(&adapter->rx_obj.cq);
  840. if (rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] == 0)
  841. return NULL;
  842. rmb();
  843. be_dws_le_to_cpu(rxcp, sizeof(*rxcp));
  844. queue_tail_inc(&adapter->rx_obj.cq);
  845. return rxcp;
  846. }
  847. /* To reset the valid bit, we need to reset the whole word as
  848. * when walking the queue the valid entries are little-endian
  849. * and invalid entries are host endian
  850. */
  851. static inline void be_rx_compl_reset(struct be_eth_rx_compl *rxcp)
  852. {
  853. rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] = 0;
  854. }
  855. static inline struct page *be_alloc_pages(u32 size)
  856. {
  857. gfp_t alloc_flags = GFP_ATOMIC;
  858. u32 order = get_order(size);
  859. if (order > 0)
  860. alloc_flags |= __GFP_COMP;
  861. return alloc_pages(alloc_flags, order);
  862. }
  863. /*
  864. * Allocate a page, split it to fragments of size rx_frag_size and post as
  865. * receive buffers to BE
  866. */
  867. static void be_post_rx_frags(struct be_adapter *adapter)
  868. {
  869. struct be_rx_page_info *page_info_tbl = adapter->rx_obj.page_info_tbl;
  870. struct be_rx_page_info *page_info = NULL, *prev_page_info = NULL;
  871. struct be_queue_info *rxq = &adapter->rx_obj.q;
  872. struct page *pagep = NULL;
  873. struct be_eth_rx_d *rxd;
  874. u64 page_dmaaddr = 0, frag_dmaaddr;
  875. u32 posted, page_offset = 0;
  876. page_info = &page_info_tbl[rxq->head];
  877. for (posted = 0; posted < MAX_RX_POST && !page_info->page; posted++) {
  878. if (!pagep) {
  879. pagep = be_alloc_pages(adapter->big_page_size);
  880. if (unlikely(!pagep)) {
  881. drvr_stats(adapter)->be_ethrx_post_fail++;
  882. break;
  883. }
  884. page_dmaaddr = pci_map_page(adapter->pdev, pagep, 0,
  885. adapter->big_page_size,
  886. PCI_DMA_FROMDEVICE);
  887. page_info->page_offset = 0;
  888. } else {
  889. get_page(pagep);
  890. page_info->page_offset = page_offset + rx_frag_size;
  891. }
  892. page_offset = page_info->page_offset;
  893. page_info->page = pagep;
  894. dma_unmap_addr_set(page_info, bus, page_dmaaddr);
  895. frag_dmaaddr = page_dmaaddr + page_info->page_offset;
  896. rxd = queue_head_node(rxq);
  897. rxd->fragpa_lo = cpu_to_le32(frag_dmaaddr & 0xFFFFFFFF);
  898. rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr));
  899. /* Any space left in the current big page for another frag? */
  900. if ((page_offset + rx_frag_size + rx_frag_size) >
  901. adapter->big_page_size) {
  902. pagep = NULL;
  903. page_info->last_page_user = true;
  904. }
  905. prev_page_info = page_info;
  906. queue_head_inc(rxq);
  907. page_info = &page_info_tbl[rxq->head];
  908. }
  909. if (pagep)
  910. prev_page_info->last_page_user = true;
  911. if (posted) {
  912. atomic_add(posted, &rxq->used);
  913. be_rxq_notify(adapter, rxq->id, posted);
  914. } else if (atomic_read(&rxq->used) == 0) {
  915. /* Let be_worker replenish when memory is available */
  916. adapter->rx_post_starved = true;
  917. }
  918. }
  919. static struct be_eth_tx_compl *be_tx_compl_get(struct be_queue_info *tx_cq)
  920. {
  921. struct be_eth_tx_compl *txcp = queue_tail_node(tx_cq);
  922. if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0)
  923. return NULL;
  924. rmb();
  925. be_dws_le_to_cpu(txcp, sizeof(*txcp));
  926. txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0;
  927. queue_tail_inc(tx_cq);
  928. return txcp;
  929. }
  930. static void be_tx_compl_process(struct be_adapter *adapter, u16 last_index)
  931. {
  932. struct be_queue_info *txq = &adapter->tx_obj.q;
  933. struct be_eth_wrb *wrb;
  934. struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
  935. struct sk_buff *sent_skb;
  936. u16 cur_index, num_wrbs = 1; /* account for hdr wrb */
  937. bool unmap_skb_hdr = true;
  938. sent_skb = sent_skbs[txq->tail];
  939. BUG_ON(!sent_skb);
  940. sent_skbs[txq->tail] = NULL;
  941. /* skip header wrb */
  942. queue_tail_inc(txq);
  943. do {
  944. cur_index = txq->tail;
  945. wrb = queue_tail_node(txq);
  946. unmap_tx_frag(adapter->pdev, wrb, (unmap_skb_hdr &&
  947. skb_headlen(sent_skb)));
  948. unmap_skb_hdr = false;
  949. num_wrbs++;
  950. queue_tail_inc(txq);
  951. } while (cur_index != last_index);
  952. atomic_sub(num_wrbs, &txq->used);
  953. kfree_skb(sent_skb);
  954. }
  955. static inline struct be_eq_entry *event_get(struct be_eq_obj *eq_obj)
  956. {
  957. struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
  958. if (!eqe->evt)
  959. return NULL;
  960. rmb();
  961. eqe->evt = le32_to_cpu(eqe->evt);
  962. queue_tail_inc(&eq_obj->q);
  963. return eqe;
  964. }
  965. static int event_handle(struct be_adapter *adapter,
  966. struct be_eq_obj *eq_obj)
  967. {
  968. struct be_eq_entry *eqe;
  969. u16 num = 0;
  970. while ((eqe = event_get(eq_obj)) != NULL) {
  971. eqe->evt = 0;
  972. num++;
  973. }
  974. /* Deal with any spurious interrupts that come
  975. * without events
  976. */
  977. be_eq_notify(adapter, eq_obj->q.id, true, true, num);
  978. if (num)
  979. napi_schedule(&eq_obj->napi);
  980. return num;
  981. }
  982. /* Just read and notify events without processing them.
  983. * Used at the time of destroying event queues */
  984. static void be_eq_clean(struct be_adapter *adapter,
  985. struct be_eq_obj *eq_obj)
  986. {
  987. struct be_eq_entry *eqe;
  988. u16 num = 0;
  989. while ((eqe = event_get(eq_obj)) != NULL) {
  990. eqe->evt = 0;
  991. num++;
  992. }
  993. if (num)
  994. be_eq_notify(adapter, eq_obj->q.id, false, true, num);
  995. }
  996. static void be_rx_q_clean(struct be_adapter *adapter)
  997. {
  998. struct be_rx_page_info *page_info;
  999. struct be_queue_info *rxq = &adapter->rx_obj.q;
  1000. struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
  1001. struct be_eth_rx_compl *rxcp;
  1002. u16 tail;
  1003. /* First cleanup pending rx completions */
  1004. while ((rxcp = be_rx_compl_get(adapter)) != NULL) {
  1005. be_rx_compl_discard(adapter, rxcp);
  1006. be_rx_compl_reset(rxcp);
  1007. be_cq_notify(adapter, rx_cq->id, true, 1);
  1008. }
  1009. /* Then free posted rx buffer that were not used */
  1010. tail = (rxq->head + rxq->len - atomic_read(&rxq->used)) % rxq->len;
  1011. for (; atomic_read(&rxq->used) > 0; index_inc(&tail, rxq->len)) {
  1012. page_info = get_rx_page_info(adapter, tail);
  1013. put_page(page_info->page);
  1014. memset(page_info, 0, sizeof(*page_info));
  1015. }
  1016. BUG_ON(atomic_read(&rxq->used));
  1017. }
  1018. static void be_tx_compl_clean(struct be_adapter *adapter)
  1019. {
  1020. struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
  1021. struct be_queue_info *txq = &adapter->tx_obj.q;
  1022. struct be_eth_tx_compl *txcp;
  1023. u16 end_idx, cmpl = 0, timeo = 0;
  1024. struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
  1025. struct sk_buff *sent_skb;
  1026. bool dummy_wrb;
  1027. /* Wait for a max of 200ms for all the tx-completions to arrive. */
  1028. do {
  1029. while ((txcp = be_tx_compl_get(tx_cq))) {
  1030. end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
  1031. wrb_index, txcp);
  1032. be_tx_compl_process(adapter, end_idx);
  1033. cmpl++;
  1034. }
  1035. if (cmpl) {
  1036. be_cq_notify(adapter, tx_cq->id, false, cmpl);
  1037. cmpl = 0;
  1038. }
  1039. if (atomic_read(&txq->used) == 0 || ++timeo > 200)
  1040. break;
  1041. mdelay(1);
  1042. } while (true);
  1043. if (atomic_read(&txq->used))
  1044. dev_err(&adapter->pdev->dev, "%d pending tx-completions\n",
  1045. atomic_read(&txq->used));
  1046. /* free posted tx for which compls will never arrive */
  1047. while (atomic_read(&txq->used)) {
  1048. sent_skb = sent_skbs[txq->tail];
  1049. end_idx = txq->tail;
  1050. index_adv(&end_idx,
  1051. wrb_cnt_for_skb(sent_skb, &dummy_wrb) - 1, txq->len);
  1052. be_tx_compl_process(adapter, end_idx);
  1053. }
  1054. }
  1055. static void be_mcc_queues_destroy(struct be_adapter *adapter)
  1056. {
  1057. struct be_queue_info *q;
  1058. q = &adapter->mcc_obj.q;
  1059. if (q->created)
  1060. be_cmd_q_destroy(adapter, q, QTYPE_MCCQ);
  1061. be_queue_free(adapter, q);
  1062. q = &adapter->mcc_obj.cq;
  1063. if (q->created)
  1064. be_cmd_q_destroy(adapter, q, QTYPE_CQ);
  1065. be_queue_free(adapter, q);
  1066. }
  1067. /* Must be called only after TX qs are created as MCC shares TX EQ */
  1068. static int be_mcc_queues_create(struct be_adapter *adapter)
  1069. {
  1070. struct be_queue_info *q, *cq;
  1071. /* Alloc MCC compl queue */
  1072. cq = &adapter->mcc_obj.cq;
  1073. if (be_queue_alloc(adapter, cq, MCC_CQ_LEN,
  1074. sizeof(struct be_mcc_compl)))
  1075. goto err;
  1076. /* Ask BE to create MCC compl queue; share TX's eq */
  1077. if (be_cmd_cq_create(adapter, cq, &adapter->tx_eq.q, false, true, 0))
  1078. goto mcc_cq_free;
  1079. /* Alloc MCC queue */
  1080. q = &adapter->mcc_obj.q;
  1081. if (be_queue_alloc(adapter, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
  1082. goto mcc_cq_destroy;
  1083. /* Ask BE to create MCC queue */
  1084. if (be_cmd_mccq_create(adapter, q, cq))
  1085. goto mcc_q_free;
  1086. return 0;
  1087. mcc_q_free:
  1088. be_queue_free(adapter, q);
  1089. mcc_cq_destroy:
  1090. be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
  1091. mcc_cq_free:
  1092. be_queue_free(adapter, cq);
  1093. err:
  1094. return -1;
  1095. }
  1096. static void be_tx_queues_destroy(struct be_adapter *adapter)
  1097. {
  1098. struct be_queue_info *q;
  1099. q = &adapter->tx_obj.q;
  1100. if (q->created)
  1101. be_cmd_q_destroy(adapter, q, QTYPE_TXQ);
  1102. be_queue_free(adapter, q);
  1103. q = &adapter->tx_obj.cq;
  1104. if (q->created)
  1105. be_cmd_q_destroy(adapter, q, QTYPE_CQ);
  1106. be_queue_free(adapter, q);
  1107. /* Clear any residual events */
  1108. be_eq_clean(adapter, &adapter->tx_eq);
  1109. q = &adapter->tx_eq.q;
  1110. if (q->created)
  1111. be_cmd_q_destroy(adapter, q, QTYPE_EQ);
  1112. be_queue_free(adapter, q);
  1113. }
  1114. static int be_tx_queues_create(struct be_adapter *adapter)
  1115. {
  1116. struct be_queue_info *eq, *q, *cq;
  1117. adapter->tx_eq.max_eqd = 0;
  1118. adapter->tx_eq.min_eqd = 0;
  1119. adapter->tx_eq.cur_eqd = 96;
  1120. adapter->tx_eq.enable_aic = false;
  1121. /* Alloc Tx Event queue */
  1122. eq = &adapter->tx_eq.q;
  1123. if (be_queue_alloc(adapter, eq, EVNT_Q_LEN, sizeof(struct be_eq_entry)))
  1124. return -1;
  1125. /* Ask BE to create Tx Event queue */
  1126. if (be_cmd_eq_create(adapter, eq, adapter->tx_eq.cur_eqd))
  1127. goto tx_eq_free;
  1128. adapter->base_eq_id = adapter->tx_eq.q.id;
  1129. /* Alloc TX eth compl queue */
  1130. cq = &adapter->tx_obj.cq;
  1131. if (be_queue_alloc(adapter, cq, TX_CQ_LEN,
  1132. sizeof(struct be_eth_tx_compl)))
  1133. goto tx_eq_destroy;
  1134. /* Ask BE to create Tx eth compl queue */
  1135. if (be_cmd_cq_create(adapter, cq, eq, false, false, 3))
  1136. goto tx_cq_free;
  1137. /* Alloc TX eth queue */
  1138. q = &adapter->tx_obj.q;
  1139. if (be_queue_alloc(adapter, q, TX_Q_LEN, sizeof(struct be_eth_wrb)))
  1140. goto tx_cq_destroy;
  1141. /* Ask BE to create Tx eth queue */
  1142. if (be_cmd_txq_create(adapter, q, cq))
  1143. goto tx_q_free;
  1144. return 0;
  1145. tx_q_free:
  1146. be_queue_free(adapter, q);
  1147. tx_cq_destroy:
  1148. be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
  1149. tx_cq_free:
  1150. be_queue_free(adapter, cq);
  1151. tx_eq_destroy:
  1152. be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
  1153. tx_eq_free:
  1154. be_queue_free(adapter, eq);
  1155. return -1;
  1156. }
  1157. static void be_rx_queues_destroy(struct be_adapter *adapter)
  1158. {
  1159. struct be_queue_info *q;
  1160. q = &adapter->rx_obj.q;
  1161. if (q->created) {
  1162. be_cmd_q_destroy(adapter, q, QTYPE_RXQ);
  1163. /* After the rxq is invalidated, wait for a grace time
  1164. * of 1ms for all dma to end and the flush compl to arrive
  1165. */
  1166. mdelay(1);
  1167. be_rx_q_clean(adapter);
  1168. }
  1169. be_queue_free(adapter, q);
  1170. q = &adapter->rx_obj.cq;
  1171. if (q->created)
  1172. be_cmd_q_destroy(adapter, q, QTYPE_CQ);
  1173. be_queue_free(adapter, q);
  1174. /* Clear any residual events */
  1175. be_eq_clean(adapter, &adapter->rx_eq);
  1176. q = &adapter->rx_eq.q;
  1177. if (q->created)
  1178. be_cmd_q_destroy(adapter, q, QTYPE_EQ);
  1179. be_queue_free(adapter, q);
  1180. }
  1181. static int be_rx_queues_create(struct be_adapter *adapter)
  1182. {
  1183. struct be_queue_info *eq, *q, *cq;
  1184. int rc;
  1185. adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE;
  1186. adapter->rx_eq.max_eqd = BE_MAX_EQD;
  1187. adapter->rx_eq.min_eqd = 0;
  1188. adapter->rx_eq.cur_eqd = 0;
  1189. adapter->rx_eq.enable_aic = true;
  1190. /* Alloc Rx Event queue */
  1191. eq = &adapter->rx_eq.q;
  1192. rc = be_queue_alloc(adapter, eq, EVNT_Q_LEN,
  1193. sizeof(struct be_eq_entry));
  1194. if (rc)
  1195. return rc;
  1196. /* Ask BE to create Rx Event queue */
  1197. rc = be_cmd_eq_create(adapter, eq, adapter->rx_eq.cur_eqd);
  1198. if (rc)
  1199. goto rx_eq_free;
  1200. /* Alloc RX eth compl queue */
  1201. cq = &adapter->rx_obj.cq;
  1202. rc = be_queue_alloc(adapter, cq, RX_CQ_LEN,
  1203. sizeof(struct be_eth_rx_compl));
  1204. if (rc)
  1205. goto rx_eq_destroy;
  1206. /* Ask BE to create Rx eth compl queue */
  1207. rc = be_cmd_cq_create(adapter, cq, eq, false, false, 3);
  1208. if (rc)
  1209. goto rx_cq_free;
  1210. /* Alloc RX eth queue */
  1211. q = &adapter->rx_obj.q;
  1212. rc = be_queue_alloc(adapter, q, RX_Q_LEN, sizeof(struct be_eth_rx_d));
  1213. if (rc)
  1214. goto rx_cq_destroy;
  1215. /* Ask BE to create Rx eth queue */
  1216. rc = be_cmd_rxq_create(adapter, q, cq->id, rx_frag_size,
  1217. BE_MAX_JUMBO_FRAME_SIZE, adapter->if_handle, false);
  1218. if (rc)
  1219. goto rx_q_free;
  1220. return 0;
  1221. rx_q_free:
  1222. be_queue_free(adapter, q);
  1223. rx_cq_destroy:
  1224. be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
  1225. rx_cq_free:
  1226. be_queue_free(adapter, cq);
  1227. rx_eq_destroy:
  1228. be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
  1229. rx_eq_free:
  1230. be_queue_free(adapter, eq);
  1231. return rc;
  1232. }
  1233. /* There are 8 evt ids per func. Retruns the evt id's bit number */
  1234. static inline int be_evt_bit_get(struct be_adapter *adapter, u32 eq_id)
  1235. {
  1236. return eq_id - adapter->base_eq_id;
  1237. }
  1238. static irqreturn_t be_intx(int irq, void *dev)
  1239. {
  1240. struct be_adapter *adapter = dev;
  1241. int isr;
  1242. isr = ioread32(adapter->csr + CEV_ISR0_OFFSET +
  1243. (adapter->tx_eq.q.id/ 8) * CEV_ISR_SIZE);
  1244. if (!isr)
  1245. return IRQ_NONE;
  1246. event_handle(adapter, &adapter->tx_eq);
  1247. event_handle(adapter, &adapter->rx_eq);
  1248. return IRQ_HANDLED;
  1249. }
  1250. static irqreturn_t be_msix_rx(int irq, void *dev)
  1251. {
  1252. struct be_adapter *adapter = dev;
  1253. event_handle(adapter, &adapter->rx_eq);
  1254. return IRQ_HANDLED;
  1255. }
  1256. static irqreturn_t be_msix_tx_mcc(int irq, void *dev)
  1257. {
  1258. struct be_adapter *adapter = dev;
  1259. event_handle(adapter, &adapter->tx_eq);
  1260. return IRQ_HANDLED;
  1261. }
  1262. static inline bool do_gro(struct be_adapter *adapter,
  1263. struct be_eth_rx_compl *rxcp)
  1264. {
  1265. int err = AMAP_GET_BITS(struct amap_eth_rx_compl, err, rxcp);
  1266. int tcp_frame = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
  1267. if (err)
  1268. drvr_stats(adapter)->be_rxcp_err++;
  1269. return (tcp_frame && !err) ? true : false;
  1270. }
  1271. int be_poll_rx(struct napi_struct *napi, int budget)
  1272. {
  1273. struct be_eq_obj *rx_eq = container_of(napi, struct be_eq_obj, napi);
  1274. struct be_adapter *adapter =
  1275. container_of(rx_eq, struct be_adapter, rx_eq);
  1276. struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
  1277. struct be_eth_rx_compl *rxcp;
  1278. u32 work_done;
  1279. adapter->stats.drvr_stats.be_rx_polls++;
  1280. for (work_done = 0; work_done < budget; work_done++) {
  1281. rxcp = be_rx_compl_get(adapter);
  1282. if (!rxcp)
  1283. break;
  1284. if (do_gro(adapter, rxcp))
  1285. be_rx_compl_process_gro(adapter, rxcp);
  1286. else
  1287. be_rx_compl_process(adapter, rxcp);
  1288. be_rx_compl_reset(rxcp);
  1289. }
  1290. /* Refill the queue */
  1291. if (atomic_read(&adapter->rx_obj.q.used) < RX_FRAGS_REFILL_WM)
  1292. be_post_rx_frags(adapter);
  1293. /* All consumed */
  1294. if (work_done < budget) {
  1295. napi_complete(napi);
  1296. be_cq_notify(adapter, rx_cq->id, true, work_done);
  1297. } else {
  1298. /* More to be consumed; continue with interrupts disabled */
  1299. be_cq_notify(adapter, rx_cq->id, false, work_done);
  1300. }
  1301. return work_done;
  1302. }
  1303. /* As TX and MCC share the same EQ check for both TX and MCC completions.
  1304. * For TX/MCC we don't honour budget; consume everything
  1305. */
  1306. static int be_poll_tx_mcc(struct napi_struct *napi, int budget)
  1307. {
  1308. struct be_eq_obj *tx_eq = container_of(napi, struct be_eq_obj, napi);
  1309. struct be_adapter *adapter =
  1310. container_of(tx_eq, struct be_adapter, tx_eq);
  1311. struct be_queue_info *txq = &adapter->tx_obj.q;
  1312. struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
  1313. struct be_eth_tx_compl *txcp;
  1314. int tx_compl = 0, mcc_compl, status = 0;
  1315. u16 end_idx;
  1316. while ((txcp = be_tx_compl_get(tx_cq))) {
  1317. end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
  1318. wrb_index, txcp);
  1319. be_tx_compl_process(adapter, end_idx);
  1320. tx_compl++;
  1321. }
  1322. mcc_compl = be_process_mcc(adapter, &status);
  1323. napi_complete(napi);
  1324. if (mcc_compl) {
  1325. struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
  1326. be_cq_notify(adapter, mcc_obj->cq.id, true, mcc_compl);
  1327. }
  1328. if (tx_compl) {
  1329. be_cq_notify(adapter, adapter->tx_obj.cq.id, true, tx_compl);
  1330. /* As Tx wrbs have been freed up, wake up netdev queue if
  1331. * it was stopped due to lack of tx wrbs.
  1332. */
  1333. if (netif_queue_stopped(adapter->netdev) &&
  1334. atomic_read(&txq->used) < txq->len / 2) {
  1335. netif_wake_queue(adapter->netdev);
  1336. }
  1337. drvr_stats(adapter)->be_tx_events++;
  1338. drvr_stats(adapter)->be_tx_compl += tx_compl;
  1339. }
  1340. return 1;
  1341. }
  1342. static void be_worker(struct work_struct *work)
  1343. {
  1344. struct be_adapter *adapter =
  1345. container_of(work, struct be_adapter, work.work);
  1346. be_cmd_get_stats(adapter, &adapter->stats.cmd);
  1347. /* Set EQ delay */
  1348. be_rx_eqd_update(adapter);
  1349. be_tx_rate_update(adapter);
  1350. be_rx_rate_update(adapter);
  1351. if (adapter->rx_post_starved) {
  1352. adapter->rx_post_starved = false;
  1353. be_post_rx_frags(adapter);
  1354. }
  1355. schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000));
  1356. }
  1357. static void be_msix_disable(struct be_adapter *adapter)
  1358. {
  1359. if (adapter->msix_enabled) {
  1360. pci_disable_msix(adapter->pdev);
  1361. adapter->msix_enabled = false;
  1362. }
  1363. }
  1364. static void be_msix_enable(struct be_adapter *adapter)
  1365. {
  1366. int i, status;
  1367. for (i = 0; i < BE_NUM_MSIX_VECTORS; i++)
  1368. adapter->msix_entries[i].entry = i;
  1369. status = pci_enable_msix(adapter->pdev, adapter->msix_entries,
  1370. BE_NUM_MSIX_VECTORS);
  1371. if (status == 0)
  1372. adapter->msix_enabled = true;
  1373. }
  1374. static void be_sriov_enable(struct be_adapter *adapter)
  1375. {
  1376. #ifdef CONFIG_PCI_IOV
  1377. int status;
  1378. be_check_sriov_fn_type(adapter);
  1379. if (be_physfn(adapter) && num_vfs) {
  1380. status = pci_enable_sriov(adapter->pdev, num_vfs);
  1381. adapter->sriov_enabled = status ? false : true;
  1382. }
  1383. #endif
  1384. }
  1385. static void be_sriov_disable(struct be_adapter *adapter)
  1386. {
  1387. #ifdef CONFIG_PCI_IOV
  1388. if (adapter->sriov_enabled) {
  1389. pci_disable_sriov(adapter->pdev);
  1390. adapter->sriov_enabled = false;
  1391. }
  1392. #endif
  1393. }
  1394. static inline int be_msix_vec_get(struct be_adapter *adapter, u32 eq_id)
  1395. {
  1396. return adapter->msix_entries[
  1397. be_evt_bit_get(adapter, eq_id)].vector;
  1398. }
  1399. static int be_request_irq(struct be_adapter *adapter,
  1400. struct be_eq_obj *eq_obj,
  1401. void *handler, char *desc)
  1402. {
  1403. struct net_device *netdev = adapter->netdev;
  1404. int vec;
  1405. sprintf(eq_obj->desc, "%s-%s", netdev->name, desc);
  1406. vec = be_msix_vec_get(adapter, eq_obj->q.id);
  1407. return request_irq(vec, handler, 0, eq_obj->desc, adapter);
  1408. }
  1409. static void be_free_irq(struct be_adapter *adapter, struct be_eq_obj *eq_obj)
  1410. {
  1411. int vec = be_msix_vec_get(adapter, eq_obj->q.id);
  1412. free_irq(vec, adapter);
  1413. }
  1414. static int be_msix_register(struct be_adapter *adapter)
  1415. {
  1416. int status;
  1417. status = be_request_irq(adapter, &adapter->tx_eq, be_msix_tx_mcc, "tx");
  1418. if (status)
  1419. goto err;
  1420. status = be_request_irq(adapter, &adapter->rx_eq, be_msix_rx, "rx");
  1421. if (status)
  1422. goto free_tx_irq;
  1423. return 0;
  1424. free_tx_irq:
  1425. be_free_irq(adapter, &adapter->tx_eq);
  1426. err:
  1427. dev_warn(&adapter->pdev->dev,
  1428. "MSIX Request IRQ failed - err %d\n", status);
  1429. pci_disable_msix(adapter->pdev);
  1430. adapter->msix_enabled = false;
  1431. return status;
  1432. }
  1433. static int be_irq_register(struct be_adapter *adapter)
  1434. {
  1435. struct net_device *netdev = adapter->netdev;
  1436. int status;
  1437. if (adapter->msix_enabled) {
  1438. status = be_msix_register(adapter);
  1439. if (status == 0)
  1440. goto done;
  1441. /* INTx is not supported for VF */
  1442. if (!be_physfn(adapter))
  1443. return status;
  1444. }
  1445. /* INTx */
  1446. netdev->irq = adapter->pdev->irq;
  1447. status = request_irq(netdev->irq, be_intx, IRQF_SHARED, netdev->name,
  1448. adapter);
  1449. if (status) {
  1450. dev_err(&adapter->pdev->dev,
  1451. "INTx request IRQ failed - err %d\n", status);
  1452. return status;
  1453. }
  1454. done:
  1455. adapter->isr_registered = true;
  1456. return 0;
  1457. }
  1458. static void be_irq_unregister(struct be_adapter *adapter)
  1459. {
  1460. struct net_device *netdev = adapter->netdev;
  1461. if (!adapter->isr_registered)
  1462. return;
  1463. /* INTx */
  1464. if (!adapter->msix_enabled) {
  1465. free_irq(netdev->irq, adapter);
  1466. goto done;
  1467. }
  1468. /* MSIx */
  1469. be_free_irq(adapter, &adapter->tx_eq);
  1470. be_free_irq(adapter, &adapter->rx_eq);
  1471. done:
  1472. adapter->isr_registered = false;
  1473. }
  1474. static int be_close(struct net_device *netdev)
  1475. {
  1476. struct be_adapter *adapter = netdev_priv(netdev);
  1477. struct be_eq_obj *rx_eq = &adapter->rx_eq;
  1478. struct be_eq_obj *tx_eq = &adapter->tx_eq;
  1479. int vec;
  1480. cancel_delayed_work_sync(&adapter->work);
  1481. be_async_mcc_disable(adapter);
  1482. netif_stop_queue(netdev);
  1483. netif_carrier_off(netdev);
  1484. adapter->link_up = false;
  1485. be_intr_set(adapter, false);
  1486. if (adapter->msix_enabled) {
  1487. vec = be_msix_vec_get(adapter, tx_eq->q.id);
  1488. synchronize_irq(vec);
  1489. vec = be_msix_vec_get(adapter, rx_eq->q.id);
  1490. synchronize_irq(vec);
  1491. } else {
  1492. synchronize_irq(netdev->irq);
  1493. }
  1494. be_irq_unregister(adapter);
  1495. napi_disable(&rx_eq->napi);
  1496. napi_disable(&tx_eq->napi);
  1497. /* Wait for all pending tx completions to arrive so that
  1498. * all tx skbs are freed.
  1499. */
  1500. be_tx_compl_clean(adapter);
  1501. return 0;
  1502. }
  1503. static int be_open(struct net_device *netdev)
  1504. {
  1505. struct be_adapter *adapter = netdev_priv(netdev);
  1506. struct be_eq_obj *rx_eq = &adapter->rx_eq;
  1507. struct be_eq_obj *tx_eq = &adapter->tx_eq;
  1508. bool link_up;
  1509. int status;
  1510. u8 mac_speed;
  1511. u16 link_speed;
  1512. /* First time posting */
  1513. be_post_rx_frags(adapter);
  1514. napi_enable(&rx_eq->napi);
  1515. napi_enable(&tx_eq->napi);
  1516. be_irq_register(adapter);
  1517. be_intr_set(adapter, true);
  1518. /* The evt queues are created in unarmed state; arm them */
  1519. be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
  1520. be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
  1521. /* Rx compl queue may be in unarmed state; rearm it */
  1522. be_cq_notify(adapter, adapter->rx_obj.cq.id, true, 0);
  1523. /* Now that interrupts are on we can process async mcc */
  1524. be_async_mcc_enable(adapter);
  1525. schedule_delayed_work(&adapter->work, msecs_to_jiffies(100));
  1526. status = be_cmd_link_status_query(adapter, &link_up, &mac_speed,
  1527. &link_speed);
  1528. if (status)
  1529. goto err;
  1530. be_link_status_update(adapter, link_up);
  1531. if (be_physfn(adapter)) {
  1532. status = be_vid_config(adapter);
  1533. if (status)
  1534. goto err;
  1535. status = be_cmd_set_flow_control(adapter,
  1536. adapter->tx_fc, adapter->rx_fc);
  1537. if (status)
  1538. goto err;
  1539. }
  1540. return 0;
  1541. err:
  1542. be_close(adapter->netdev);
  1543. return -EIO;
  1544. }
  1545. static int be_setup_wol(struct be_adapter *adapter, bool enable)
  1546. {
  1547. struct be_dma_mem cmd;
  1548. int status = 0;
  1549. u8 mac[ETH_ALEN];
  1550. memset(mac, 0, ETH_ALEN);
  1551. cmd.size = sizeof(struct be_cmd_req_acpi_wol_magic_config);
  1552. cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
  1553. if (cmd.va == NULL)
  1554. return -1;
  1555. memset(cmd.va, 0, cmd.size);
  1556. if (enable) {
  1557. status = pci_write_config_dword(adapter->pdev,
  1558. PCICFG_PM_CONTROL_OFFSET, PCICFG_PM_CONTROL_MASK);
  1559. if (status) {
  1560. dev_err(&adapter->pdev->dev,
  1561. "Could not enable Wake-on-lan\n");
  1562. pci_free_consistent(adapter->pdev, cmd.size, cmd.va,
  1563. cmd.dma);
  1564. return status;
  1565. }
  1566. status = be_cmd_enable_magic_wol(adapter,
  1567. adapter->netdev->dev_addr, &cmd);
  1568. pci_enable_wake(adapter->pdev, PCI_D3hot, 1);
  1569. pci_enable_wake(adapter->pdev, PCI_D3cold, 1);
  1570. } else {
  1571. status = be_cmd_enable_magic_wol(adapter, mac, &cmd);
  1572. pci_enable_wake(adapter->pdev, PCI_D3hot, 0);
  1573. pci_enable_wake(adapter->pdev, PCI_D3cold, 0);
  1574. }
  1575. pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
  1576. return status;
  1577. }
  1578. static int be_setup(struct be_adapter *adapter)
  1579. {
  1580. struct net_device *netdev = adapter->netdev;
  1581. u32 cap_flags, en_flags, vf = 0;
  1582. int status;
  1583. u8 mac[ETH_ALEN];
  1584. cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST;
  1585. if (be_physfn(adapter)) {
  1586. cap_flags |= BE_IF_FLAGS_MCAST_PROMISCUOUS |
  1587. BE_IF_FLAGS_PROMISCUOUS |
  1588. BE_IF_FLAGS_PASS_L3L4_ERRORS;
  1589. en_flags |= BE_IF_FLAGS_PASS_L3L4_ERRORS;
  1590. }
  1591. status = be_cmd_if_create(adapter, cap_flags, en_flags,
  1592. netdev->dev_addr, false/* pmac_invalid */,
  1593. &adapter->if_handle, &adapter->pmac_id, 0);
  1594. if (status != 0)
  1595. goto do_none;
  1596. if (be_physfn(adapter)) {
  1597. while (vf < num_vfs) {
  1598. cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED
  1599. | BE_IF_FLAGS_BROADCAST;
  1600. status = be_cmd_if_create(adapter, cap_flags, en_flags,
  1601. mac, true,
  1602. &adapter->vf_cfg[vf].vf_if_handle,
  1603. NULL, vf+1);
  1604. if (status) {
  1605. dev_err(&adapter->pdev->dev,
  1606. "Interface Create failed for VF %d\n", vf);
  1607. goto if_destroy;
  1608. }
  1609. adapter->vf_cfg[vf].vf_pmac_id = BE_INVALID_PMAC_ID;
  1610. vf++;
  1611. }
  1612. } else if (!be_physfn(adapter)) {
  1613. status = be_cmd_mac_addr_query(adapter, mac,
  1614. MAC_ADDRESS_TYPE_NETWORK, false, adapter->if_handle);
  1615. if (!status) {
  1616. memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
  1617. memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
  1618. }
  1619. }
  1620. status = be_tx_queues_create(adapter);
  1621. if (status != 0)
  1622. goto if_destroy;
  1623. status = be_rx_queues_create(adapter);
  1624. if (status != 0)
  1625. goto tx_qs_destroy;
  1626. status = be_mcc_queues_create(adapter);
  1627. if (status != 0)
  1628. goto rx_qs_destroy;
  1629. adapter->link_speed = -1;
  1630. return 0;
  1631. rx_qs_destroy:
  1632. be_rx_queues_destroy(adapter);
  1633. tx_qs_destroy:
  1634. be_tx_queues_destroy(adapter);
  1635. if_destroy:
  1636. for (vf = 0; vf < num_vfs; vf++)
  1637. if (adapter->vf_cfg[vf].vf_if_handle)
  1638. be_cmd_if_destroy(adapter,
  1639. adapter->vf_cfg[vf].vf_if_handle);
  1640. be_cmd_if_destroy(adapter, adapter->if_handle);
  1641. do_none:
  1642. return status;
  1643. }
  1644. static int be_clear(struct be_adapter *adapter)
  1645. {
  1646. be_mcc_queues_destroy(adapter);
  1647. be_rx_queues_destroy(adapter);
  1648. be_tx_queues_destroy(adapter);
  1649. be_cmd_if_destroy(adapter, adapter->if_handle);
  1650. /* tell fw we're done with firing cmds */
  1651. be_cmd_fw_clean(adapter);
  1652. return 0;
  1653. }
  1654. #define FW_FILE_HDR_SIGN "ServerEngines Corp. "
  1655. char flash_cookie[2][16] = {"*** SE FLAS",
  1656. "H DIRECTORY *** "};
  1657. static bool be_flash_redboot(struct be_adapter *adapter,
  1658. const u8 *p, u32 img_start, int image_size,
  1659. int hdr_size)
  1660. {
  1661. u32 crc_offset;
  1662. u8 flashed_crc[4];
  1663. int status;
  1664. crc_offset = hdr_size + img_start + image_size - 4;
  1665. p += crc_offset;
  1666. status = be_cmd_get_flash_crc(adapter, flashed_crc,
  1667. (image_size - 4));
  1668. if (status) {
  1669. dev_err(&adapter->pdev->dev,
  1670. "could not get crc from flash, not flashing redboot\n");
  1671. return false;
  1672. }
  1673. /*update redboot only if crc does not match*/
  1674. if (!memcmp(flashed_crc, p, 4))
  1675. return false;
  1676. else
  1677. return true;
  1678. }
  1679. static int be_flash_data(struct be_adapter *adapter,
  1680. const struct firmware *fw,
  1681. struct be_dma_mem *flash_cmd, int num_of_images)
  1682. {
  1683. int status = 0, i, filehdr_size = 0;
  1684. u32 total_bytes = 0, flash_op;
  1685. int num_bytes;
  1686. const u8 *p = fw->data;
  1687. struct be_cmd_write_flashrom *req = flash_cmd->va;
  1688. struct flash_comp *pflashcomp;
  1689. int num_comp;
  1690. struct flash_comp gen3_flash_types[9] = {
  1691. { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, IMG_TYPE_ISCSI_ACTIVE,
  1692. FLASH_IMAGE_MAX_SIZE_g3},
  1693. { FLASH_REDBOOT_START_g3, IMG_TYPE_REDBOOT,
  1694. FLASH_REDBOOT_IMAGE_MAX_SIZE_g3},
  1695. { FLASH_iSCSI_BIOS_START_g3, IMG_TYPE_BIOS,
  1696. FLASH_BIOS_IMAGE_MAX_SIZE_g3},
  1697. { FLASH_PXE_BIOS_START_g3, IMG_TYPE_PXE_BIOS,
  1698. FLASH_BIOS_IMAGE_MAX_SIZE_g3},
  1699. { FLASH_FCoE_BIOS_START_g3, IMG_TYPE_FCOE_BIOS,
  1700. FLASH_BIOS_IMAGE_MAX_SIZE_g3},
  1701. { FLASH_iSCSI_BACKUP_IMAGE_START_g3, IMG_TYPE_ISCSI_BACKUP,
  1702. FLASH_IMAGE_MAX_SIZE_g3},
  1703. { FLASH_FCoE_PRIMARY_IMAGE_START_g3, IMG_TYPE_FCOE_FW_ACTIVE,
  1704. FLASH_IMAGE_MAX_SIZE_g3},
  1705. { FLASH_FCoE_BACKUP_IMAGE_START_g3, IMG_TYPE_FCOE_FW_BACKUP,
  1706. FLASH_IMAGE_MAX_SIZE_g3},
  1707. { FLASH_NCSI_START_g3, IMG_TYPE_NCSI_FW,
  1708. FLASH_NCSI_IMAGE_MAX_SIZE_g3}
  1709. };
  1710. struct flash_comp gen2_flash_types[8] = {
  1711. { FLASH_iSCSI_PRIMARY_IMAGE_START_g2, IMG_TYPE_ISCSI_ACTIVE,
  1712. FLASH_IMAGE_MAX_SIZE_g2},
  1713. { FLASH_REDBOOT_START_g2, IMG_TYPE_REDBOOT,
  1714. FLASH_REDBOOT_IMAGE_MAX_SIZE_g2},
  1715. { FLASH_iSCSI_BIOS_START_g2, IMG_TYPE_BIOS,
  1716. FLASH_BIOS_IMAGE_MAX_SIZE_g2},
  1717. { FLASH_PXE_BIOS_START_g2, IMG_TYPE_PXE_BIOS,
  1718. FLASH_BIOS_IMAGE_MAX_SIZE_g2},
  1719. { FLASH_FCoE_BIOS_START_g2, IMG_TYPE_FCOE_BIOS,
  1720. FLASH_BIOS_IMAGE_MAX_SIZE_g2},
  1721. { FLASH_iSCSI_BACKUP_IMAGE_START_g2, IMG_TYPE_ISCSI_BACKUP,
  1722. FLASH_IMAGE_MAX_SIZE_g2},
  1723. { FLASH_FCoE_PRIMARY_IMAGE_START_g2, IMG_TYPE_FCOE_FW_ACTIVE,
  1724. FLASH_IMAGE_MAX_SIZE_g2},
  1725. { FLASH_FCoE_BACKUP_IMAGE_START_g2, IMG_TYPE_FCOE_FW_BACKUP,
  1726. FLASH_IMAGE_MAX_SIZE_g2}
  1727. };
  1728. if (adapter->generation == BE_GEN3) {
  1729. pflashcomp = gen3_flash_types;
  1730. filehdr_size = sizeof(struct flash_file_hdr_g3);
  1731. num_comp = 9;
  1732. } else {
  1733. pflashcomp = gen2_flash_types;
  1734. filehdr_size = sizeof(struct flash_file_hdr_g2);
  1735. num_comp = 8;
  1736. }
  1737. for (i = 0; i < num_comp; i++) {
  1738. if ((pflashcomp[i].optype == IMG_TYPE_NCSI_FW) &&
  1739. memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0)
  1740. continue;
  1741. if ((pflashcomp[i].optype == IMG_TYPE_REDBOOT) &&
  1742. (!be_flash_redboot(adapter, fw->data,
  1743. pflashcomp[i].offset, pflashcomp[i].size,
  1744. filehdr_size)))
  1745. continue;
  1746. p = fw->data;
  1747. p += filehdr_size + pflashcomp[i].offset
  1748. + (num_of_images * sizeof(struct image_hdr));
  1749. if (p + pflashcomp[i].size > fw->data + fw->size)
  1750. return -1;
  1751. total_bytes = pflashcomp[i].size;
  1752. while (total_bytes) {
  1753. if (total_bytes > 32*1024)
  1754. num_bytes = 32*1024;
  1755. else
  1756. num_bytes = total_bytes;
  1757. total_bytes -= num_bytes;
  1758. if (!total_bytes)
  1759. flash_op = FLASHROM_OPER_FLASH;
  1760. else
  1761. flash_op = FLASHROM_OPER_SAVE;
  1762. memcpy(req->params.data_buf, p, num_bytes);
  1763. p += num_bytes;
  1764. status = be_cmd_write_flashrom(adapter, flash_cmd,
  1765. pflashcomp[i].optype, flash_op, num_bytes);
  1766. if (status) {
  1767. dev_err(&adapter->pdev->dev,
  1768. "cmd to write to flash rom failed.\n");
  1769. return -1;
  1770. }
  1771. yield();
  1772. }
  1773. }
  1774. return 0;
  1775. }
  1776. static int get_ufigen_type(struct flash_file_hdr_g2 *fhdr)
  1777. {
  1778. if (fhdr == NULL)
  1779. return 0;
  1780. if (fhdr->build[0] == '3')
  1781. return BE_GEN3;
  1782. else if (fhdr->build[0] == '2')
  1783. return BE_GEN2;
  1784. else
  1785. return 0;
  1786. }
  1787. int be_load_fw(struct be_adapter *adapter, u8 *func)
  1788. {
  1789. char fw_file[ETHTOOL_FLASH_MAX_FILENAME];
  1790. const struct firmware *fw;
  1791. struct flash_file_hdr_g2 *fhdr;
  1792. struct flash_file_hdr_g3 *fhdr3;
  1793. struct image_hdr *img_hdr_ptr = NULL;
  1794. struct be_dma_mem flash_cmd;
  1795. int status, i = 0, num_imgs = 0;
  1796. const u8 *p;
  1797. strcpy(fw_file, func);
  1798. status = request_firmware(&fw, fw_file, &adapter->pdev->dev);
  1799. if (status)
  1800. goto fw_exit;
  1801. p = fw->data;
  1802. fhdr = (struct flash_file_hdr_g2 *) p;
  1803. dev_info(&adapter->pdev->dev, "Flashing firmware file %s\n", fw_file);
  1804. flash_cmd.size = sizeof(struct be_cmd_write_flashrom) + 32*1024;
  1805. flash_cmd.va = pci_alloc_consistent(adapter->pdev, flash_cmd.size,
  1806. &flash_cmd.dma);
  1807. if (!flash_cmd.va) {
  1808. status = -ENOMEM;
  1809. dev_err(&adapter->pdev->dev,
  1810. "Memory allocation failure while flashing\n");
  1811. goto fw_exit;
  1812. }
  1813. if ((adapter->generation == BE_GEN3) &&
  1814. (get_ufigen_type(fhdr) == BE_GEN3)) {
  1815. fhdr3 = (struct flash_file_hdr_g3 *) fw->data;
  1816. num_imgs = le32_to_cpu(fhdr3->num_imgs);
  1817. for (i = 0; i < num_imgs; i++) {
  1818. img_hdr_ptr = (struct image_hdr *) (fw->data +
  1819. (sizeof(struct flash_file_hdr_g3) +
  1820. i * sizeof(struct image_hdr)));
  1821. if (le32_to_cpu(img_hdr_ptr->imageid) == 1)
  1822. status = be_flash_data(adapter, fw, &flash_cmd,
  1823. num_imgs);
  1824. }
  1825. } else if ((adapter->generation == BE_GEN2) &&
  1826. (get_ufigen_type(fhdr) == BE_GEN2)) {
  1827. status = be_flash_data(adapter, fw, &flash_cmd, 0);
  1828. } else {
  1829. dev_err(&adapter->pdev->dev,
  1830. "UFI and Interface are not compatible for flashing\n");
  1831. status = -1;
  1832. }
  1833. pci_free_consistent(adapter->pdev, flash_cmd.size, flash_cmd.va,
  1834. flash_cmd.dma);
  1835. if (status) {
  1836. dev_err(&adapter->pdev->dev, "Firmware load error\n");
  1837. goto fw_exit;
  1838. }
  1839. dev_info(&adapter->pdev->dev, "Firmware flashed successfully\n");
  1840. fw_exit:
  1841. release_firmware(fw);
  1842. return status;
  1843. }
  1844. static struct net_device_ops be_netdev_ops = {
  1845. .ndo_open = be_open,
  1846. .ndo_stop = be_close,
  1847. .ndo_start_xmit = be_xmit,
  1848. .ndo_get_stats = be_get_stats,
  1849. .ndo_set_rx_mode = be_set_multicast_list,
  1850. .ndo_set_mac_address = be_mac_addr_set,
  1851. .ndo_change_mtu = be_change_mtu,
  1852. .ndo_validate_addr = eth_validate_addr,
  1853. .ndo_vlan_rx_register = be_vlan_register,
  1854. .ndo_vlan_rx_add_vid = be_vlan_add_vid,
  1855. .ndo_vlan_rx_kill_vid = be_vlan_rem_vid,
  1856. .ndo_set_vf_mac = be_set_vf_mac,
  1857. .ndo_get_vf_config = be_get_vf_config
  1858. };
  1859. static void be_netdev_init(struct net_device *netdev)
  1860. {
  1861. struct be_adapter *adapter = netdev_priv(netdev);
  1862. netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO |
  1863. NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER | NETIF_F_HW_CSUM |
  1864. NETIF_F_GRO | NETIF_F_TSO6;
  1865. netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_HW_CSUM;
  1866. netdev->flags |= IFF_MULTICAST;
  1867. adapter->rx_csum = true;
  1868. /* Default settings for Rx and Tx flow control */
  1869. adapter->rx_fc = true;
  1870. adapter->tx_fc = true;
  1871. netif_set_gso_max_size(netdev, 65535);
  1872. BE_SET_NETDEV_OPS(netdev, &be_netdev_ops);
  1873. SET_ETHTOOL_OPS(netdev, &be_ethtool_ops);
  1874. netif_napi_add(netdev, &adapter->rx_eq.napi, be_poll_rx,
  1875. BE_NAPI_WEIGHT);
  1876. netif_napi_add(netdev, &adapter->tx_eq.napi, be_poll_tx_mcc,
  1877. BE_NAPI_WEIGHT);
  1878. netif_carrier_off(netdev);
  1879. netif_stop_queue(netdev);
  1880. }
  1881. static void be_unmap_pci_bars(struct be_adapter *adapter)
  1882. {
  1883. if (adapter->csr)
  1884. iounmap(adapter->csr);
  1885. if (adapter->db)
  1886. iounmap(adapter->db);
  1887. if (adapter->pcicfg && be_physfn(adapter))
  1888. iounmap(adapter->pcicfg);
  1889. }
  1890. static int be_map_pci_bars(struct be_adapter *adapter)
  1891. {
  1892. u8 __iomem *addr;
  1893. int pcicfg_reg, db_reg;
  1894. if (be_physfn(adapter)) {
  1895. addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2),
  1896. pci_resource_len(adapter->pdev, 2));
  1897. if (addr == NULL)
  1898. return -ENOMEM;
  1899. adapter->csr = addr;
  1900. }
  1901. if (adapter->generation == BE_GEN2) {
  1902. pcicfg_reg = 1;
  1903. db_reg = 4;
  1904. } else {
  1905. pcicfg_reg = 0;
  1906. if (be_physfn(adapter))
  1907. db_reg = 4;
  1908. else
  1909. db_reg = 0;
  1910. }
  1911. addr = ioremap_nocache(pci_resource_start(adapter->pdev, db_reg),
  1912. pci_resource_len(adapter->pdev, db_reg));
  1913. if (addr == NULL)
  1914. goto pci_map_err;
  1915. adapter->db = addr;
  1916. if (be_physfn(adapter)) {
  1917. addr = ioremap_nocache(
  1918. pci_resource_start(adapter->pdev, pcicfg_reg),
  1919. pci_resource_len(adapter->pdev, pcicfg_reg));
  1920. if (addr == NULL)
  1921. goto pci_map_err;
  1922. adapter->pcicfg = addr;
  1923. } else
  1924. adapter->pcicfg = adapter->db + SRIOV_VF_PCICFG_OFFSET;
  1925. return 0;
  1926. pci_map_err:
  1927. be_unmap_pci_bars(adapter);
  1928. return -ENOMEM;
  1929. }
  1930. static void be_ctrl_cleanup(struct be_adapter *adapter)
  1931. {
  1932. struct be_dma_mem *mem = &adapter->mbox_mem_alloced;
  1933. be_unmap_pci_bars(adapter);
  1934. if (mem->va)
  1935. pci_free_consistent(adapter->pdev, mem->size,
  1936. mem->va, mem->dma);
  1937. mem = &adapter->mc_cmd_mem;
  1938. if (mem->va)
  1939. pci_free_consistent(adapter->pdev, mem->size,
  1940. mem->va, mem->dma);
  1941. }
  1942. static int be_ctrl_init(struct be_adapter *adapter)
  1943. {
  1944. struct be_dma_mem *mbox_mem_alloc = &adapter->mbox_mem_alloced;
  1945. struct be_dma_mem *mbox_mem_align = &adapter->mbox_mem;
  1946. struct be_dma_mem *mc_cmd_mem = &adapter->mc_cmd_mem;
  1947. int status;
  1948. status = be_map_pci_bars(adapter);
  1949. if (status)
  1950. goto done;
  1951. mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
  1952. mbox_mem_alloc->va = pci_alloc_consistent(adapter->pdev,
  1953. mbox_mem_alloc->size, &mbox_mem_alloc->dma);
  1954. if (!mbox_mem_alloc->va) {
  1955. status = -ENOMEM;
  1956. goto unmap_pci_bars;
  1957. }
  1958. mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
  1959. mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
  1960. mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
  1961. memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
  1962. mc_cmd_mem->size = sizeof(struct be_cmd_req_mcast_mac_config);
  1963. mc_cmd_mem->va = pci_alloc_consistent(adapter->pdev, mc_cmd_mem->size,
  1964. &mc_cmd_mem->dma);
  1965. if (mc_cmd_mem->va == NULL) {
  1966. status = -ENOMEM;
  1967. goto free_mbox;
  1968. }
  1969. memset(mc_cmd_mem->va, 0, mc_cmd_mem->size);
  1970. spin_lock_init(&adapter->mbox_lock);
  1971. spin_lock_init(&adapter->mcc_lock);
  1972. spin_lock_init(&adapter->mcc_cq_lock);
  1973. init_completion(&adapter->flash_compl);
  1974. pci_save_state(adapter->pdev);
  1975. return 0;
  1976. free_mbox:
  1977. pci_free_consistent(adapter->pdev, mbox_mem_alloc->size,
  1978. mbox_mem_alloc->va, mbox_mem_alloc->dma);
  1979. unmap_pci_bars:
  1980. be_unmap_pci_bars(adapter);
  1981. done:
  1982. return status;
  1983. }
  1984. static void be_stats_cleanup(struct be_adapter *adapter)
  1985. {
  1986. struct be_stats_obj *stats = &adapter->stats;
  1987. struct be_dma_mem *cmd = &stats->cmd;
  1988. if (cmd->va)
  1989. pci_free_consistent(adapter->pdev, cmd->size,
  1990. cmd->va, cmd->dma);
  1991. }
  1992. static int be_stats_init(struct be_adapter *adapter)
  1993. {
  1994. struct be_stats_obj *stats = &adapter->stats;
  1995. struct be_dma_mem *cmd = &stats->cmd;
  1996. cmd->size = sizeof(struct be_cmd_req_get_stats);
  1997. cmd->va = pci_alloc_consistent(adapter->pdev, cmd->size, &cmd->dma);
  1998. if (cmd->va == NULL)
  1999. return -1;
  2000. memset(cmd->va, 0, cmd->size);
  2001. return 0;
  2002. }
  2003. static void __devexit be_remove(struct pci_dev *pdev)
  2004. {
  2005. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2006. if (!adapter)
  2007. return;
  2008. unregister_netdev(adapter->netdev);
  2009. be_clear(adapter);
  2010. be_stats_cleanup(adapter);
  2011. be_ctrl_cleanup(adapter);
  2012. be_sriov_disable(adapter);
  2013. be_msix_disable(adapter);
  2014. pci_set_drvdata(pdev, NULL);
  2015. pci_release_regions(pdev);
  2016. pci_disable_device(pdev);
  2017. free_netdev(adapter->netdev);
  2018. }
  2019. static int be_get_config(struct be_adapter *adapter)
  2020. {
  2021. int status;
  2022. u8 mac[ETH_ALEN];
  2023. status = be_cmd_get_fw_ver(adapter, adapter->fw_ver);
  2024. if (status)
  2025. return status;
  2026. status = be_cmd_query_fw_cfg(adapter,
  2027. &adapter->port_num, &adapter->cap);
  2028. if (status)
  2029. return status;
  2030. memset(mac, 0, ETH_ALEN);
  2031. if (be_physfn(adapter)) {
  2032. status = be_cmd_mac_addr_query(adapter, mac,
  2033. MAC_ADDRESS_TYPE_NETWORK, true /*permanent */, 0);
  2034. if (status)
  2035. return status;
  2036. if (!is_valid_ether_addr(mac))
  2037. return -EADDRNOTAVAIL;
  2038. memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
  2039. memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
  2040. }
  2041. if (adapter->cap & 0x400)
  2042. adapter->max_vlans = BE_NUM_VLANS_SUPPORTED/4;
  2043. else
  2044. adapter->max_vlans = BE_NUM_VLANS_SUPPORTED;
  2045. return 0;
  2046. }
  2047. static int __devinit be_probe(struct pci_dev *pdev,
  2048. const struct pci_device_id *pdev_id)
  2049. {
  2050. int status = 0;
  2051. struct be_adapter *adapter;
  2052. struct net_device *netdev;
  2053. status = pci_enable_device(pdev);
  2054. if (status)
  2055. goto do_none;
  2056. status = pci_request_regions(pdev, DRV_NAME);
  2057. if (status)
  2058. goto disable_dev;
  2059. pci_set_master(pdev);
  2060. netdev = alloc_etherdev(sizeof(struct be_adapter));
  2061. if (netdev == NULL) {
  2062. status = -ENOMEM;
  2063. goto rel_reg;
  2064. }
  2065. adapter = netdev_priv(netdev);
  2066. switch (pdev->device) {
  2067. case BE_DEVICE_ID1:
  2068. case OC_DEVICE_ID1:
  2069. adapter->generation = BE_GEN2;
  2070. break;
  2071. case BE_DEVICE_ID2:
  2072. case OC_DEVICE_ID2:
  2073. adapter->generation = BE_GEN3;
  2074. break;
  2075. default:
  2076. adapter->generation = 0;
  2077. }
  2078. adapter->pdev = pdev;
  2079. pci_set_drvdata(pdev, adapter);
  2080. adapter->netdev = netdev;
  2081. be_netdev_init(netdev);
  2082. SET_NETDEV_DEV(netdev, &pdev->dev);
  2083. be_msix_enable(adapter);
  2084. status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  2085. if (!status) {
  2086. netdev->features |= NETIF_F_HIGHDMA;
  2087. } else {
  2088. status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2089. if (status) {
  2090. dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
  2091. goto free_netdev;
  2092. }
  2093. }
  2094. be_sriov_enable(adapter);
  2095. status = be_ctrl_init(adapter);
  2096. if (status)
  2097. goto free_netdev;
  2098. /* sync up with fw's ready state */
  2099. if (be_physfn(adapter)) {
  2100. status = be_cmd_POST(adapter);
  2101. if (status)
  2102. goto ctrl_clean;
  2103. }
  2104. /* tell fw we're ready to fire cmds */
  2105. status = be_cmd_fw_init(adapter);
  2106. if (status)
  2107. goto ctrl_clean;
  2108. if (be_physfn(adapter)) {
  2109. status = be_cmd_reset_function(adapter);
  2110. if (status)
  2111. goto ctrl_clean;
  2112. }
  2113. status = be_stats_init(adapter);
  2114. if (status)
  2115. goto ctrl_clean;
  2116. status = be_get_config(adapter);
  2117. if (status)
  2118. goto stats_clean;
  2119. INIT_DELAYED_WORK(&adapter->work, be_worker);
  2120. status = be_setup(adapter);
  2121. if (status)
  2122. goto stats_clean;
  2123. status = register_netdev(netdev);
  2124. if (status != 0)
  2125. goto unsetup;
  2126. dev_info(&pdev->dev, "%s port %d\n", nic_name(pdev), adapter->port_num);
  2127. return 0;
  2128. unsetup:
  2129. be_clear(adapter);
  2130. stats_clean:
  2131. be_stats_cleanup(adapter);
  2132. ctrl_clean:
  2133. be_ctrl_cleanup(adapter);
  2134. free_netdev:
  2135. be_msix_disable(adapter);
  2136. be_sriov_disable(adapter);
  2137. free_netdev(adapter->netdev);
  2138. pci_set_drvdata(pdev, NULL);
  2139. rel_reg:
  2140. pci_release_regions(pdev);
  2141. disable_dev:
  2142. pci_disable_device(pdev);
  2143. do_none:
  2144. dev_err(&pdev->dev, "%s initialization failed\n", nic_name(pdev));
  2145. return status;
  2146. }
  2147. static int be_suspend(struct pci_dev *pdev, pm_message_t state)
  2148. {
  2149. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2150. struct net_device *netdev = adapter->netdev;
  2151. if (adapter->wol)
  2152. be_setup_wol(adapter, true);
  2153. netif_device_detach(netdev);
  2154. if (netif_running(netdev)) {
  2155. rtnl_lock();
  2156. be_close(netdev);
  2157. rtnl_unlock();
  2158. }
  2159. be_cmd_get_flow_control(adapter, &adapter->tx_fc, &adapter->rx_fc);
  2160. be_clear(adapter);
  2161. pci_save_state(pdev);
  2162. pci_disable_device(pdev);
  2163. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  2164. return 0;
  2165. }
  2166. static int be_resume(struct pci_dev *pdev)
  2167. {
  2168. int status = 0;
  2169. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2170. struct net_device *netdev = adapter->netdev;
  2171. netif_device_detach(netdev);
  2172. status = pci_enable_device(pdev);
  2173. if (status)
  2174. return status;
  2175. pci_set_power_state(pdev, 0);
  2176. pci_restore_state(pdev);
  2177. /* tell fw we're ready to fire cmds */
  2178. status = be_cmd_fw_init(adapter);
  2179. if (status)
  2180. return status;
  2181. be_setup(adapter);
  2182. if (netif_running(netdev)) {
  2183. rtnl_lock();
  2184. be_open(netdev);
  2185. rtnl_unlock();
  2186. }
  2187. netif_device_attach(netdev);
  2188. if (adapter->wol)
  2189. be_setup_wol(adapter, false);
  2190. return 0;
  2191. }
  2192. /*
  2193. * An FLR will stop BE from DMAing any data.
  2194. */
  2195. static void be_shutdown(struct pci_dev *pdev)
  2196. {
  2197. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2198. struct net_device *netdev = adapter->netdev;
  2199. netif_device_detach(netdev);
  2200. be_cmd_reset_function(adapter);
  2201. if (adapter->wol)
  2202. be_setup_wol(adapter, true);
  2203. pci_disable_device(pdev);
  2204. }
  2205. static pci_ers_result_t be_eeh_err_detected(struct pci_dev *pdev,
  2206. pci_channel_state_t state)
  2207. {
  2208. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2209. struct net_device *netdev = adapter->netdev;
  2210. dev_err(&adapter->pdev->dev, "EEH error detected\n");
  2211. adapter->eeh_err = true;
  2212. netif_device_detach(netdev);
  2213. if (netif_running(netdev)) {
  2214. rtnl_lock();
  2215. be_close(netdev);
  2216. rtnl_unlock();
  2217. }
  2218. be_clear(adapter);
  2219. if (state == pci_channel_io_perm_failure)
  2220. return PCI_ERS_RESULT_DISCONNECT;
  2221. pci_disable_device(pdev);
  2222. return PCI_ERS_RESULT_NEED_RESET;
  2223. }
  2224. static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
  2225. {
  2226. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2227. int status;
  2228. dev_info(&adapter->pdev->dev, "EEH reset\n");
  2229. adapter->eeh_err = false;
  2230. status = pci_enable_device(pdev);
  2231. if (status)
  2232. return PCI_ERS_RESULT_DISCONNECT;
  2233. pci_set_master(pdev);
  2234. pci_set_power_state(pdev, 0);
  2235. pci_restore_state(pdev);
  2236. /* Check if card is ok and fw is ready */
  2237. status = be_cmd_POST(adapter);
  2238. if (status)
  2239. return PCI_ERS_RESULT_DISCONNECT;
  2240. return PCI_ERS_RESULT_RECOVERED;
  2241. }
  2242. static void be_eeh_resume(struct pci_dev *pdev)
  2243. {
  2244. int status = 0;
  2245. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2246. struct net_device *netdev = adapter->netdev;
  2247. dev_info(&adapter->pdev->dev, "EEH resume\n");
  2248. pci_save_state(pdev);
  2249. /* tell fw we're ready to fire cmds */
  2250. status = be_cmd_fw_init(adapter);
  2251. if (status)
  2252. goto err;
  2253. status = be_setup(adapter);
  2254. if (status)
  2255. goto err;
  2256. if (netif_running(netdev)) {
  2257. status = be_open(netdev);
  2258. if (status)
  2259. goto err;
  2260. }
  2261. netif_device_attach(netdev);
  2262. return;
  2263. err:
  2264. dev_err(&adapter->pdev->dev, "EEH resume failed\n");
  2265. }
  2266. static struct pci_error_handlers be_eeh_handlers = {
  2267. .error_detected = be_eeh_err_detected,
  2268. .slot_reset = be_eeh_reset,
  2269. .resume = be_eeh_resume,
  2270. };
  2271. static struct pci_driver be_driver = {
  2272. .name = DRV_NAME,
  2273. .id_table = be_dev_ids,
  2274. .probe = be_probe,
  2275. .remove = be_remove,
  2276. .suspend = be_suspend,
  2277. .resume = be_resume,
  2278. .shutdown = be_shutdown,
  2279. .err_handler = &be_eeh_handlers
  2280. };
  2281. static int __init be_init_module(void)
  2282. {
  2283. if (rx_frag_size != 8192 && rx_frag_size != 4096 &&
  2284. rx_frag_size != 2048) {
  2285. printk(KERN_WARNING DRV_NAME
  2286. " : Module param rx_frag_size must be 2048/4096/8192."
  2287. " Using 2048\n");
  2288. rx_frag_size = 2048;
  2289. }
  2290. if (num_vfs > 32) {
  2291. printk(KERN_WARNING DRV_NAME
  2292. " : Module param num_vfs must not be greater than 32."
  2293. "Using 32\n");
  2294. num_vfs = 32;
  2295. }
  2296. return pci_register_driver(&be_driver);
  2297. }
  2298. module_init(be_init_module);
  2299. static void __exit be_exit_module(void)
  2300. {
  2301. pci_unregister_driver(&be_driver);
  2302. }
  2303. module_exit(be_exit_module);