setup.c 14 KB

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  1. /*
  2. * Copyright (C) 2009 Renesas Solutions Corp.
  3. *
  4. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/init.h>
  11. #include <linux/device.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/mtd/physmap.h>
  14. #include <linux/gpio.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/io.h>
  17. #include <linux/delay.h>
  18. #include <linux/usb/r8a66597.h>
  19. #include <linux/i2c.h>
  20. #include <video/sh_mobile_lcdc.h>
  21. #include <media/sh_mobile_ceu.h>
  22. #include <asm/heartbeat.h>
  23. #include <asm/sh_eth.h>
  24. #include <cpu/sh7724.h>
  25. /*
  26. * Address Interface BusWidth
  27. *-----------------------------------------
  28. * 0x0000_0000 uboot 16bit
  29. * 0x0004_0000 Linux romImage 16bit
  30. * 0x0014_0000 MTD for Linux 16bit
  31. * 0x0400_0000 Internal I/O 16/32bit
  32. * 0x0800_0000 DRAM 32bit
  33. * 0x1800_0000 MFI 16bit
  34. */
  35. /* Heartbeat */
  36. static unsigned char led_pos[] = { 0, 1, 2, 3 };
  37. static struct heartbeat_data heartbeat_data = {
  38. .regsize = 8,
  39. .nr_bits = 4,
  40. .bit_pos = led_pos,
  41. };
  42. static struct resource heartbeat_resources[] = {
  43. [0] = {
  44. .start = 0xA405012C, /* PTG */
  45. .end = 0xA405012E - 1,
  46. .flags = IORESOURCE_MEM,
  47. },
  48. };
  49. static struct platform_device heartbeat_device = {
  50. .name = "heartbeat",
  51. .id = -1,
  52. .dev = {
  53. .platform_data = &heartbeat_data,
  54. },
  55. .num_resources = ARRAY_SIZE(heartbeat_resources),
  56. .resource = heartbeat_resources,
  57. };
  58. /* MTD */
  59. static struct mtd_partition nor_flash_partitions[] = {
  60. {
  61. .name = "boot loader",
  62. .offset = 0,
  63. .size = (5 * 1024 * 1024),
  64. .mask_flags = MTD_CAP_ROM,
  65. }, {
  66. .name = "free-area",
  67. .offset = MTDPART_OFS_APPEND,
  68. .size = MTDPART_SIZ_FULL,
  69. },
  70. };
  71. static struct physmap_flash_data nor_flash_data = {
  72. .width = 2,
  73. .parts = nor_flash_partitions,
  74. .nr_parts = ARRAY_SIZE(nor_flash_partitions),
  75. };
  76. static struct resource nor_flash_resources[] = {
  77. [0] = {
  78. .name = "NOR Flash",
  79. .start = 0x00000000,
  80. .end = 0x03ffffff,
  81. .flags = IORESOURCE_MEM,
  82. }
  83. };
  84. static struct platform_device nor_flash_device = {
  85. .name = "physmap-flash",
  86. .resource = nor_flash_resources,
  87. .num_resources = ARRAY_SIZE(nor_flash_resources),
  88. .dev = {
  89. .platform_data = &nor_flash_data,
  90. },
  91. };
  92. /* SH Eth */
  93. #define SH_ETH_ADDR (0xA4600000)
  94. #define SH_ETH_MAHR (SH_ETH_ADDR + 0x1C0)
  95. #define SH_ETH_MALR (SH_ETH_ADDR + 0x1C8)
  96. static struct resource sh_eth_resources[] = {
  97. [0] = {
  98. .start = SH_ETH_ADDR,
  99. .end = SH_ETH_ADDR + 0x1FC,
  100. .flags = IORESOURCE_MEM,
  101. },
  102. [1] = {
  103. .start = 91,
  104. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  105. },
  106. };
  107. struct sh_eth_plat_data sh_eth_plat = {
  108. .phy = 0x1f, /* SMSC LAN8700 */
  109. .edmac_endian = EDMAC_LITTLE_ENDIAN,
  110. };
  111. static struct platform_device sh_eth_device = {
  112. .name = "sh-eth",
  113. .id = 0,
  114. .dev = {
  115. .platform_data = &sh_eth_plat,
  116. },
  117. .num_resources = ARRAY_SIZE(sh_eth_resources),
  118. .resource = sh_eth_resources,
  119. };
  120. /* USB0 host */
  121. void usb0_port_power(int port, int power)
  122. {
  123. gpio_set_value(GPIO_PTB4, power);
  124. }
  125. static struct r8a66597_platdata usb0_host_data = {
  126. .on_chip = 1,
  127. .port_power = usb0_port_power,
  128. };
  129. static struct resource usb0_host_resources[] = {
  130. [0] = {
  131. .start = 0xa4d80000,
  132. .end = 0xa4d80124 - 1,
  133. .flags = IORESOURCE_MEM,
  134. },
  135. [1] = {
  136. .start = 65,
  137. .end = 65,
  138. .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
  139. },
  140. };
  141. static struct platform_device usb0_host_device = {
  142. .name = "r8a66597_hcd",
  143. .id = 0,
  144. .dev = {
  145. .dma_mask = NULL, /* not use dma */
  146. .coherent_dma_mask = 0xffffffff,
  147. .platform_data = &usb0_host_data,
  148. },
  149. .num_resources = ARRAY_SIZE(usb0_host_resources),
  150. .resource = usb0_host_resources,
  151. };
  152. /*
  153. * USB1
  154. *
  155. * CN5 can use both host/function,
  156. * and we can determine it by checking PTB[3]
  157. *
  158. * This time only USB1 host is supported.
  159. */
  160. void usb1_port_power(int port, int power)
  161. {
  162. if (!gpio_get_value(GPIO_PTB3)) {
  163. printk(KERN_ERR "USB1 function is not supported\n");
  164. return;
  165. }
  166. gpio_set_value(GPIO_PTB5, power);
  167. }
  168. static struct r8a66597_platdata usb1_host_data = {
  169. .on_chip = 1,
  170. .port_power = usb1_port_power,
  171. };
  172. static struct resource usb1_host_resources[] = {
  173. [0] = {
  174. .start = 0xa4d90000,
  175. .end = 0xa4d90124 - 1,
  176. .flags = IORESOURCE_MEM,
  177. },
  178. [1] = {
  179. .start = 66,
  180. .end = 66,
  181. .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
  182. },
  183. };
  184. static struct platform_device usb1_host_device = {
  185. .name = "r8a66597_hcd",
  186. .id = 1,
  187. .dev = {
  188. .dma_mask = NULL, /* not use dma */
  189. .coherent_dma_mask = 0xffffffff,
  190. .platform_data = &usb1_host_data,
  191. },
  192. .num_resources = ARRAY_SIZE(usb1_host_resources),
  193. .resource = usb1_host_resources,
  194. };
  195. /* LCDC */
  196. static struct sh_mobile_lcdc_info lcdc_info = {
  197. .ch[0] = {
  198. .interface_type = RGB18,
  199. .chan = LCDC_CHAN_MAINLCD,
  200. .bpp = 16,
  201. .lcd_cfg = {
  202. .sync = 0, /* hsync and vsync are active low */
  203. },
  204. .lcd_size_cfg = { /* 7.0 inch */
  205. .width = 152,
  206. .height = 91,
  207. },
  208. .board_cfg = {
  209. },
  210. }
  211. };
  212. static struct resource lcdc_resources[] = {
  213. [0] = {
  214. .name = "LCDC",
  215. .start = 0xfe940000,
  216. .end = 0xfe941fff,
  217. .flags = IORESOURCE_MEM,
  218. },
  219. [1] = {
  220. .start = 106,
  221. .flags = IORESOURCE_IRQ,
  222. },
  223. };
  224. static struct platform_device lcdc_device = {
  225. .name = "sh_mobile_lcdc_fb",
  226. .num_resources = ARRAY_SIZE(lcdc_resources),
  227. .resource = lcdc_resources,
  228. .dev = {
  229. .platform_data = &lcdc_info,
  230. },
  231. .archdata = {
  232. .hwblk_id = HWBLK_LCDC,
  233. },
  234. };
  235. /* CEU0 */
  236. static struct sh_mobile_ceu_info sh_mobile_ceu0_info = {
  237. .flags = SH_CEU_FLAG_USE_8BIT_BUS,
  238. };
  239. static struct resource ceu0_resources[] = {
  240. [0] = {
  241. .name = "CEU0",
  242. .start = 0xfe910000,
  243. .end = 0xfe91009f,
  244. .flags = IORESOURCE_MEM,
  245. },
  246. [1] = {
  247. .start = 52,
  248. .flags = IORESOURCE_IRQ,
  249. },
  250. [2] = {
  251. /* place holder for contiguous memory */
  252. },
  253. };
  254. static struct platform_device ceu0_device = {
  255. .name = "sh_mobile_ceu",
  256. .id = 0, /* "ceu0" clock */
  257. .num_resources = ARRAY_SIZE(ceu0_resources),
  258. .resource = ceu0_resources,
  259. .dev = {
  260. .platform_data = &sh_mobile_ceu0_info,
  261. },
  262. .archdata = {
  263. .hwblk_id = HWBLK_CEU0,
  264. },
  265. };
  266. /* CEU1 */
  267. static struct sh_mobile_ceu_info sh_mobile_ceu1_info = {
  268. .flags = SH_CEU_FLAG_USE_8BIT_BUS,
  269. };
  270. static struct resource ceu1_resources[] = {
  271. [0] = {
  272. .name = "CEU1",
  273. .start = 0xfe914000,
  274. .end = 0xfe91409f,
  275. .flags = IORESOURCE_MEM,
  276. },
  277. [1] = {
  278. .start = 63,
  279. .flags = IORESOURCE_IRQ,
  280. },
  281. [2] = {
  282. /* place holder for contiguous memory */
  283. },
  284. };
  285. static struct platform_device ceu1_device = {
  286. .name = "sh_mobile_ceu",
  287. .id = 1, /* "ceu1" clock */
  288. .num_resources = ARRAY_SIZE(ceu1_resources),
  289. .resource = ceu1_resources,
  290. .dev = {
  291. .platform_data = &sh_mobile_ceu1_info,
  292. },
  293. .archdata = {
  294. .hwblk_id = HWBLK_CEU1,
  295. },
  296. };
  297. /* I2C device */
  298. static struct i2c_board_info i2c1_devices[] = {
  299. {
  300. I2C_BOARD_INFO("r2025sd", 0x32),
  301. },
  302. };
  303. static struct platform_device *ecovec_devices[] __initdata = {
  304. &heartbeat_device,
  305. &nor_flash_device,
  306. &sh_eth_device,
  307. &usb0_host_device,
  308. &usb1_host_device, /* USB1 host support */
  309. &lcdc_device,
  310. &ceu0_device,
  311. &ceu1_device,
  312. };
  313. #define EEPROM_ADDR 0x50
  314. static u8 mac_read(struct i2c_adapter *a, u8 command)
  315. {
  316. struct i2c_msg msg[2];
  317. u8 buf;
  318. int ret;
  319. msg[0].addr = EEPROM_ADDR;
  320. msg[0].flags = 0;
  321. msg[0].len = 1;
  322. msg[0].buf = &command;
  323. msg[1].addr = EEPROM_ADDR;
  324. msg[1].flags = I2C_M_RD;
  325. msg[1].len = 1;
  326. msg[1].buf = &buf;
  327. ret = i2c_transfer(a, msg, 2);
  328. if (ret < 0) {
  329. printk(KERN_ERR "error %d\n", ret);
  330. buf = 0xff;
  331. }
  332. return buf;
  333. }
  334. #define MAC_LEN 6
  335. static void __init sh_eth_init(void)
  336. {
  337. struct i2c_adapter *a = i2c_get_adapter(1);
  338. struct clk *eth_clk;
  339. u8 mac[MAC_LEN];
  340. int i;
  341. if (!a) {
  342. pr_err("can not get I2C 1\n");
  343. return;
  344. }
  345. eth_clk = clk_get(NULL, "eth0");
  346. if (!eth_clk) {
  347. pr_err("can not get eth0 clk\n");
  348. return;
  349. }
  350. /* read MAC address frome EEPROM */
  351. for (i = 0; i < MAC_LEN; i++) {
  352. mac[i] = mac_read(a, 0x10 + i);
  353. msleep(10);
  354. }
  355. /* clock enable */
  356. clk_enable(eth_clk);
  357. /* reset sh-eth */
  358. ctrl_outl(0x1, SH_ETH_ADDR + 0x0);
  359. /* set MAC addr */
  360. ctrl_outl((mac[0] << 24) |
  361. (mac[1] << 16) |
  362. (mac[2] << 8) |
  363. (mac[3] << 0), SH_ETH_MAHR);
  364. ctrl_outl((mac[4] << 8) |
  365. (mac[5] << 0), SH_ETH_MALR);
  366. clk_put(eth_clk);
  367. }
  368. #define PORT_HIZA 0xA4050158
  369. #define IODRIVEA 0xA405018A
  370. static int __init arch_setup(void)
  371. {
  372. /* enable SCIFA0 */
  373. gpio_request(GPIO_FN_SCIF0_TXD, NULL);
  374. gpio_request(GPIO_FN_SCIF0_RXD, NULL);
  375. /* enable debug LED */
  376. gpio_request(GPIO_PTG0, NULL);
  377. gpio_request(GPIO_PTG1, NULL);
  378. gpio_request(GPIO_PTG2, NULL);
  379. gpio_request(GPIO_PTG3, NULL);
  380. gpio_direction_output(GPIO_PTG0, 0);
  381. gpio_direction_output(GPIO_PTG1, 0);
  382. gpio_direction_output(GPIO_PTG2, 0);
  383. gpio_direction_output(GPIO_PTG3, 0);
  384. ctrl_outw((ctrl_inw(PORT_HIZA) & ~(0x1 << 1)) , PORT_HIZA);
  385. /* enable SH-Eth */
  386. gpio_request(GPIO_PTA1, NULL);
  387. gpio_direction_output(GPIO_PTA1, 1);
  388. mdelay(20);
  389. gpio_request(GPIO_FN_RMII_RXD0, NULL);
  390. gpio_request(GPIO_FN_RMII_RXD1, NULL);
  391. gpio_request(GPIO_FN_RMII_TXD0, NULL);
  392. gpio_request(GPIO_FN_RMII_TXD1, NULL);
  393. gpio_request(GPIO_FN_RMII_REF_CLK, NULL);
  394. gpio_request(GPIO_FN_RMII_TX_EN, NULL);
  395. gpio_request(GPIO_FN_RMII_RX_ER, NULL);
  396. gpio_request(GPIO_FN_RMII_CRS_DV, NULL);
  397. gpio_request(GPIO_FN_MDIO, NULL);
  398. gpio_request(GPIO_FN_MDC, NULL);
  399. gpio_request(GPIO_FN_LNKSTA, NULL);
  400. /* enable USB */
  401. ctrl_outw(0x0000, 0xA4D80000);
  402. gpio_request(GPIO_PTB3, NULL);
  403. gpio_request(GPIO_PTB4, NULL);
  404. gpio_request(GPIO_PTB5, NULL);
  405. gpio_direction_input(GPIO_PTB3);
  406. gpio_direction_output(GPIO_PTB4, 0);
  407. gpio_direction_output(GPIO_PTB5, 0);
  408. ctrl_outw(0x0600, 0xa40501d4);
  409. ctrl_outw(0x0600, 0xa4050192);
  410. /* enable LCDC */
  411. gpio_request(GPIO_FN_LCDD23, NULL);
  412. gpio_request(GPIO_FN_LCDD22, NULL);
  413. gpio_request(GPIO_FN_LCDD21, NULL);
  414. gpio_request(GPIO_FN_LCDD20, NULL);
  415. gpio_request(GPIO_FN_LCDD19, NULL);
  416. gpio_request(GPIO_FN_LCDD18, NULL);
  417. gpio_request(GPIO_FN_LCDD17, NULL);
  418. gpio_request(GPIO_FN_LCDD16, NULL);
  419. gpio_request(GPIO_FN_LCDD15, NULL);
  420. gpio_request(GPIO_FN_LCDD14, NULL);
  421. gpio_request(GPIO_FN_LCDD13, NULL);
  422. gpio_request(GPIO_FN_LCDD12, NULL);
  423. gpio_request(GPIO_FN_LCDD11, NULL);
  424. gpio_request(GPIO_FN_LCDD10, NULL);
  425. gpio_request(GPIO_FN_LCDD9, NULL);
  426. gpio_request(GPIO_FN_LCDD8, NULL);
  427. gpio_request(GPIO_FN_LCDD7, NULL);
  428. gpio_request(GPIO_FN_LCDD6, NULL);
  429. gpio_request(GPIO_FN_LCDD5, NULL);
  430. gpio_request(GPIO_FN_LCDD4, NULL);
  431. gpio_request(GPIO_FN_LCDD3, NULL);
  432. gpio_request(GPIO_FN_LCDD2, NULL);
  433. gpio_request(GPIO_FN_LCDD1, NULL);
  434. gpio_request(GPIO_FN_LCDD0, NULL);
  435. gpio_request(GPIO_FN_LCDDISP, NULL);
  436. gpio_request(GPIO_FN_LCDHSYN, NULL);
  437. gpio_request(GPIO_FN_LCDDCK, NULL);
  438. gpio_request(GPIO_FN_LCDVSYN, NULL);
  439. gpio_request(GPIO_FN_LCDDON, NULL);
  440. gpio_request(GPIO_FN_LCDLCLK, NULL);
  441. ctrl_outw((ctrl_inw(PORT_HIZA) & ~0x0001), PORT_HIZA);
  442. gpio_request(GPIO_PTE6, NULL);
  443. gpio_request(GPIO_PTU1, NULL);
  444. gpio_request(GPIO_PTR1, NULL);
  445. gpio_request(GPIO_PTA2, NULL);
  446. gpio_direction_input(GPIO_PTE6);
  447. gpio_direction_output(GPIO_PTU1, 0);
  448. gpio_direction_output(GPIO_PTR1, 0);
  449. gpio_direction_output(GPIO_PTA2, 0);
  450. /* I/O buffer drive ability is low */
  451. ctrl_outw((ctrl_inw(IODRIVEA) & ~0x00c0) | 0x0040 , IODRIVEA);
  452. if (gpio_get_value(GPIO_PTE6)) {
  453. /* DVI */
  454. lcdc_info.clock_source = LCDC_CLK_EXTERNAL;
  455. lcdc_info.ch[0].clock_divider = 1,
  456. lcdc_info.ch[0].lcd_cfg.name = "DVI";
  457. lcdc_info.ch[0].lcd_cfg.xres = 1280;
  458. lcdc_info.ch[0].lcd_cfg.yres = 720;
  459. lcdc_info.ch[0].lcd_cfg.left_margin = 220;
  460. lcdc_info.ch[0].lcd_cfg.right_margin = 110;
  461. lcdc_info.ch[0].lcd_cfg.hsync_len = 40;
  462. lcdc_info.ch[0].lcd_cfg.upper_margin = 20;
  463. lcdc_info.ch[0].lcd_cfg.lower_margin = 5;
  464. lcdc_info.ch[0].lcd_cfg.vsync_len = 5;
  465. gpio_set_value(GPIO_PTA2, 1);
  466. gpio_set_value(GPIO_PTU1, 1);
  467. } else {
  468. /* Panel */
  469. lcdc_info.clock_source = LCDC_CLK_PERIPHERAL;
  470. lcdc_info.ch[0].clock_divider = 2,
  471. lcdc_info.ch[0].lcd_cfg.name = "Panel";
  472. lcdc_info.ch[0].lcd_cfg.xres = 800;
  473. lcdc_info.ch[0].lcd_cfg.yres = 480;
  474. lcdc_info.ch[0].lcd_cfg.left_margin = 220;
  475. lcdc_info.ch[0].lcd_cfg.right_margin = 110;
  476. lcdc_info.ch[0].lcd_cfg.hsync_len = 70;
  477. lcdc_info.ch[0].lcd_cfg.upper_margin = 20;
  478. lcdc_info.ch[0].lcd_cfg.lower_margin = 5;
  479. lcdc_info.ch[0].lcd_cfg.vsync_len = 5;
  480. gpio_set_value(GPIO_PTR1, 1);
  481. /* FIXME
  482. *
  483. * LCDDON control is needed for Panel,
  484. * but current sh_mobile_lcdc driver doesn't control it.
  485. * It is temporary correspondence
  486. */
  487. gpio_request(GPIO_PTF4, NULL);
  488. gpio_direction_output(GPIO_PTF4, 1);
  489. }
  490. /* enable CEU0 */
  491. gpio_request(GPIO_FN_VIO0_D15, NULL);
  492. gpio_request(GPIO_FN_VIO0_D14, NULL);
  493. gpio_request(GPIO_FN_VIO0_D13, NULL);
  494. gpio_request(GPIO_FN_VIO0_D12, NULL);
  495. gpio_request(GPIO_FN_VIO0_D11, NULL);
  496. gpio_request(GPIO_FN_VIO0_D10, NULL);
  497. gpio_request(GPIO_FN_VIO0_D9, NULL);
  498. gpio_request(GPIO_FN_VIO0_D8, NULL);
  499. gpio_request(GPIO_FN_VIO0_D7, NULL);
  500. gpio_request(GPIO_FN_VIO0_D6, NULL);
  501. gpio_request(GPIO_FN_VIO0_D5, NULL);
  502. gpio_request(GPIO_FN_VIO0_D4, NULL);
  503. gpio_request(GPIO_FN_VIO0_D3, NULL);
  504. gpio_request(GPIO_FN_VIO0_D2, NULL);
  505. gpio_request(GPIO_FN_VIO0_D1, NULL);
  506. gpio_request(GPIO_FN_VIO0_D0, NULL);
  507. gpio_request(GPIO_FN_VIO0_VD, NULL);
  508. gpio_request(GPIO_FN_VIO0_CLK, NULL);
  509. gpio_request(GPIO_FN_VIO0_FLD, NULL);
  510. gpio_request(GPIO_FN_VIO0_HD, NULL);
  511. platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20);
  512. /* enable CEU1 */
  513. gpio_request(GPIO_FN_VIO1_D7, NULL);
  514. gpio_request(GPIO_FN_VIO1_D6, NULL);
  515. gpio_request(GPIO_FN_VIO1_D5, NULL);
  516. gpio_request(GPIO_FN_VIO1_D4, NULL);
  517. gpio_request(GPIO_FN_VIO1_D3, NULL);
  518. gpio_request(GPIO_FN_VIO1_D2, NULL);
  519. gpio_request(GPIO_FN_VIO1_D1, NULL);
  520. gpio_request(GPIO_FN_VIO1_D0, NULL);
  521. gpio_request(GPIO_FN_VIO1_FLD, NULL);
  522. gpio_request(GPIO_FN_VIO1_HD, NULL);
  523. gpio_request(GPIO_FN_VIO1_VD, NULL);
  524. gpio_request(GPIO_FN_VIO1_CLK, NULL);
  525. platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20);
  526. /* enable I2C device */
  527. i2c_register_board_info(1, i2c1_devices,
  528. ARRAY_SIZE(i2c1_devices));
  529. return platform_add_devices(ecovec_devices,
  530. ARRAY_SIZE(ecovec_devices));
  531. }
  532. arch_initcall(arch_setup);
  533. static int __init devices_setup(void)
  534. {
  535. sh_eth_init();
  536. return 0;
  537. }
  538. device_initcall(devices_setup);
  539. static struct sh_machine_vector mv_ecovec __initmv = {
  540. .mv_name = "R0P7724 (EcoVec)",
  541. };