dice.c 29 KB

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  1. /*
  2. * TC Applied Technologies Digital Interface Communications Engine driver
  3. *
  4. * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
  5. * Licensed under the terms of the GNU General Public License, version 2.
  6. */
  7. #include <linux/compat.h>
  8. #include <linux/completion.h>
  9. #include <linux/delay.h>
  10. #include <linux/device.h>
  11. #include <linux/firewire.h>
  12. #include <linux/firewire-constants.h>
  13. #include <linux/jiffies.h>
  14. #include <linux/module.h>
  15. #include <linux/mod_devicetable.h>
  16. #include <linux/mutex.h>
  17. #include <linux/slab.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/wait.h>
  20. #include <sound/control.h>
  21. #include <sound/core.h>
  22. #include <sound/firewire.h>
  23. #include <sound/hwdep.h>
  24. #include <sound/initval.h>
  25. #include <sound/pcm.h>
  26. #include <sound/pcm_params.h>
  27. #include "amdtp.h"
  28. #include "iso-resources.h"
  29. #include "lib.h"
  30. #include "dice-interface.h"
  31. struct dice {
  32. struct snd_card *card;
  33. struct fw_unit *unit;
  34. spinlock_t lock;
  35. struct mutex mutex;
  36. unsigned int global_offset;
  37. unsigned int rx_offset;
  38. unsigned int clock_caps;
  39. unsigned int rx_channels[3];
  40. unsigned int rx_midi_ports[3];
  41. struct fw_address_handler notification_handler;
  42. int owner_generation;
  43. int dev_lock_count; /* > 0 driver, < 0 userspace */
  44. bool dev_lock_changed;
  45. bool global_enabled;
  46. struct completion clock_accepted;
  47. wait_queue_head_t hwdep_wait;
  48. u32 notification_bits;
  49. struct fw_iso_resources resources;
  50. struct amdtp_out_stream stream;
  51. };
  52. MODULE_DESCRIPTION("DICE driver");
  53. MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
  54. MODULE_LICENSE("GPL v2");
  55. static const unsigned int dice_rates[] = {
  56. /* mode 0 */
  57. [0] = 32000,
  58. [1] = 44100,
  59. [2] = 48000,
  60. /* mode 1 */
  61. [3] = 88200,
  62. [4] = 96000,
  63. /* mode 2 */
  64. [5] = 176400,
  65. [6] = 192000,
  66. };
  67. static unsigned int rate_to_index(unsigned int rate)
  68. {
  69. unsigned int i;
  70. for (i = 0; i < ARRAY_SIZE(dice_rates); ++i)
  71. if (dice_rates[i] == rate)
  72. return i;
  73. return 0;
  74. }
  75. static unsigned int rate_index_to_mode(unsigned int rate_index)
  76. {
  77. return ((int)rate_index - 1) / 2;
  78. }
  79. static void dice_lock_changed(struct dice *dice)
  80. {
  81. dice->dev_lock_changed = true;
  82. wake_up(&dice->hwdep_wait);
  83. }
  84. static int dice_try_lock(struct dice *dice)
  85. {
  86. int err;
  87. spin_lock_irq(&dice->lock);
  88. if (dice->dev_lock_count < 0) {
  89. err = -EBUSY;
  90. goto out;
  91. }
  92. if (dice->dev_lock_count++ == 0)
  93. dice_lock_changed(dice);
  94. err = 0;
  95. out:
  96. spin_unlock_irq(&dice->lock);
  97. return err;
  98. }
  99. static void dice_unlock(struct dice *dice)
  100. {
  101. spin_lock_irq(&dice->lock);
  102. if (WARN_ON(dice->dev_lock_count <= 0))
  103. goto out;
  104. if (--dice->dev_lock_count == 0)
  105. dice_lock_changed(dice);
  106. out:
  107. spin_unlock_irq(&dice->lock);
  108. }
  109. static inline u64 global_address(struct dice *dice, unsigned int offset)
  110. {
  111. return DICE_PRIVATE_SPACE + dice->global_offset + offset;
  112. }
  113. // TODO: rx index
  114. static inline u64 rx_address(struct dice *dice, unsigned int offset)
  115. {
  116. return DICE_PRIVATE_SPACE + dice->rx_offset + offset;
  117. }
  118. static int dice_owner_set(struct dice *dice)
  119. {
  120. struct fw_device *device = fw_parent_device(dice->unit);
  121. __be64 *buffer;
  122. int err, errors = 0;
  123. buffer = kmalloc(2 * 8, GFP_KERNEL);
  124. if (!buffer)
  125. return -ENOMEM;
  126. for (;;) {
  127. buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
  128. buffer[1] = cpu_to_be64(
  129. ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
  130. dice->notification_handler.offset);
  131. dice->owner_generation = device->generation;
  132. smp_rmb(); /* node_id vs. generation */
  133. err = snd_fw_transaction(dice->unit,
  134. TCODE_LOCK_COMPARE_SWAP,
  135. global_address(dice, GLOBAL_OWNER),
  136. buffer, 2 * 8,
  137. FW_FIXED_GENERATION |
  138. dice->owner_generation);
  139. if (err == 0) {
  140. if (buffer[0] != cpu_to_be64(OWNER_NO_OWNER)) {
  141. dev_err(&dice->unit->device,
  142. "device is already in use\n");
  143. err = -EBUSY;
  144. }
  145. break;
  146. }
  147. if (err != -EAGAIN || ++errors >= 3)
  148. break;
  149. msleep(20);
  150. }
  151. kfree(buffer);
  152. return err;
  153. }
  154. static int dice_owner_update(struct dice *dice)
  155. {
  156. struct fw_device *device = fw_parent_device(dice->unit);
  157. __be64 *buffer;
  158. int err;
  159. if (dice->owner_generation == -1)
  160. return 0;
  161. buffer = kmalloc(2 * 8, GFP_KERNEL);
  162. if (!buffer)
  163. return -ENOMEM;
  164. buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
  165. buffer[1] = cpu_to_be64(
  166. ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
  167. dice->notification_handler.offset);
  168. dice->owner_generation = device->generation;
  169. smp_rmb(); /* node_id vs. generation */
  170. err = snd_fw_transaction(dice->unit, TCODE_LOCK_COMPARE_SWAP,
  171. global_address(dice, GLOBAL_OWNER),
  172. buffer, 2 * 8,
  173. FW_FIXED_GENERATION | dice->owner_generation);
  174. if (err == 0) {
  175. if (buffer[0] != cpu_to_be64(OWNER_NO_OWNER)) {
  176. dev_err(&dice->unit->device,
  177. "device is already in use\n");
  178. err = -EBUSY;
  179. }
  180. } else if (err == -EAGAIN) {
  181. err = 0; /* try again later */
  182. }
  183. kfree(buffer);
  184. if (err < 0)
  185. dice->owner_generation = -1;
  186. return err;
  187. }
  188. static void dice_owner_clear(struct dice *dice)
  189. {
  190. struct fw_device *device = fw_parent_device(dice->unit);
  191. __be64 *buffer;
  192. buffer = kmalloc(2 * 8, GFP_KERNEL);
  193. if (!buffer)
  194. return;
  195. buffer[0] = cpu_to_be64(
  196. ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
  197. dice->notification_handler.offset);
  198. buffer[1] = cpu_to_be64(OWNER_NO_OWNER);
  199. snd_fw_transaction(dice->unit, TCODE_LOCK_COMPARE_SWAP,
  200. global_address(dice, GLOBAL_OWNER),
  201. buffer, 2 * 8, FW_QUIET |
  202. FW_FIXED_GENERATION | dice->owner_generation);
  203. kfree(buffer);
  204. dice->owner_generation = -1;
  205. }
  206. static int dice_enable_set(struct dice *dice)
  207. {
  208. __be32 value;
  209. int err;
  210. value = cpu_to_be32(1);
  211. err = snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
  212. global_address(dice, GLOBAL_ENABLE),
  213. &value, 4,
  214. FW_FIXED_GENERATION | dice->owner_generation);
  215. if (err < 0)
  216. return err;
  217. dice->global_enabled = true;
  218. return 0;
  219. }
  220. static void dice_enable_clear(struct dice *dice)
  221. {
  222. __be32 value;
  223. if (!dice->global_enabled)
  224. return;
  225. value = 0;
  226. snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
  227. global_address(dice, GLOBAL_ENABLE),
  228. &value, 4, FW_QUIET |
  229. FW_FIXED_GENERATION | dice->owner_generation);
  230. dice->global_enabled = false;
  231. }
  232. static void dice_notification(struct fw_card *card, struct fw_request *request,
  233. int tcode, int destination, int source,
  234. int generation, unsigned long long offset,
  235. void *data, size_t length, void *callback_data)
  236. {
  237. struct dice *dice = callback_data;
  238. u32 bits;
  239. unsigned long flags;
  240. if (tcode != TCODE_WRITE_QUADLET_REQUEST) {
  241. fw_send_response(card, request, RCODE_TYPE_ERROR);
  242. return;
  243. }
  244. if ((offset & 3) != 0) {
  245. fw_send_response(card, request, RCODE_ADDRESS_ERROR);
  246. return;
  247. }
  248. bits = be32_to_cpup(data);
  249. spin_lock_irqsave(&dice->lock, flags);
  250. dice->notification_bits |= bits;
  251. spin_unlock_irqrestore(&dice->lock, flags);
  252. fw_send_response(card, request, RCODE_COMPLETE);
  253. if (bits & NOTIFY_CLOCK_ACCEPTED)
  254. complete(&dice->clock_accepted);
  255. wake_up(&dice->hwdep_wait);
  256. }
  257. static int dice_rate_constraint(struct snd_pcm_hw_params *params,
  258. struct snd_pcm_hw_rule *rule)
  259. {
  260. struct dice *dice = rule->private;
  261. const struct snd_interval *channels =
  262. hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_CHANNELS);
  263. struct snd_interval *rate =
  264. hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
  265. struct snd_interval allowed_rates = {
  266. .min = UINT_MAX, .max = 0, .integer = 1
  267. };
  268. unsigned int i, mode;
  269. for (i = 0; i < ARRAY_SIZE(dice_rates); ++i) {
  270. mode = rate_index_to_mode(i);
  271. if ((dice->clock_caps & (1 << i)) &&
  272. snd_interval_test(channels, dice->rx_channels[mode])) {
  273. allowed_rates.min = min(allowed_rates.min,
  274. dice_rates[i]);
  275. allowed_rates.max = max(allowed_rates.max,
  276. dice_rates[i]);
  277. }
  278. }
  279. return snd_interval_refine(rate, &allowed_rates);
  280. }
  281. static int dice_channels_constraint(struct snd_pcm_hw_params *params,
  282. struct snd_pcm_hw_rule *rule)
  283. {
  284. struct dice *dice = rule->private;
  285. const struct snd_interval *rate =
  286. hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_RATE);
  287. struct snd_interval *channels =
  288. hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
  289. struct snd_interval allowed_channels = {
  290. .min = UINT_MAX, .max = 0, .integer = 1
  291. };
  292. unsigned int i, mode;
  293. for (i = 0; i < ARRAY_SIZE(dice_rates); ++i)
  294. if ((dice->clock_caps & (1 << i)) &&
  295. snd_interval_test(rate, dice_rates[i])) {
  296. mode = rate_index_to_mode(i);
  297. allowed_channels.min = min(allowed_channels.min,
  298. dice->rx_channels[mode]);
  299. allowed_channels.max = max(allowed_channels.max,
  300. dice->rx_channels[mode]);
  301. }
  302. return snd_interval_refine(channels, &allowed_channels);
  303. }
  304. static int dice_open(struct snd_pcm_substream *substream)
  305. {
  306. static const struct snd_pcm_hardware hardware = {
  307. .info = SNDRV_PCM_INFO_MMAP |
  308. SNDRV_PCM_INFO_MMAP_VALID |
  309. SNDRV_PCM_INFO_BATCH |
  310. SNDRV_PCM_INFO_INTERLEAVED |
  311. SNDRV_PCM_INFO_BLOCK_TRANSFER,
  312. .formats = AMDTP_OUT_PCM_FORMAT_BITS,
  313. .channels_min = UINT_MAX,
  314. .channels_max = 0,
  315. .buffer_bytes_max = 16 * 1024 * 1024,
  316. .period_bytes_min = 1,
  317. .period_bytes_max = UINT_MAX,
  318. .periods_min = 1,
  319. .periods_max = UINT_MAX,
  320. };
  321. struct dice *dice = substream->private_data;
  322. struct snd_pcm_runtime *runtime = substream->runtime;
  323. unsigned int i;
  324. int err;
  325. err = dice_try_lock(dice);
  326. if (err < 0)
  327. goto error;
  328. runtime->hw = hardware;
  329. for (i = 0; i < ARRAY_SIZE(dice_rates); ++i)
  330. if (dice->clock_caps & (1 << i))
  331. runtime->hw.rates |=
  332. snd_pcm_rate_to_rate_bit(dice_rates[i]);
  333. snd_pcm_limit_hw_rates(runtime);
  334. for (i = 0; i < 3; ++i)
  335. if (dice->rx_channels[i]) {
  336. runtime->hw.channels_min = min(runtime->hw.channels_min,
  337. dice->rx_channels[i]);
  338. runtime->hw.channels_max = max(runtime->hw.channels_max,
  339. dice->rx_channels[i]);
  340. }
  341. err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  342. dice_rate_constraint, dice,
  343. SNDRV_PCM_HW_PARAM_CHANNELS, -1);
  344. if (err < 0)
  345. goto err_lock;
  346. err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
  347. dice_channels_constraint, dice,
  348. SNDRV_PCM_HW_PARAM_RATE, -1);
  349. if (err < 0)
  350. goto err_lock;
  351. err = snd_pcm_hw_constraint_step(runtime, 0,
  352. SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 32);
  353. if (err < 0)
  354. goto err_lock;
  355. err = snd_pcm_hw_constraint_step(runtime, 0,
  356. SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 32);
  357. if (err < 0)
  358. goto err_lock;
  359. err = snd_pcm_hw_constraint_minmax(runtime,
  360. SNDRV_PCM_HW_PARAM_PERIOD_TIME,
  361. 5000, UINT_MAX);
  362. if (err < 0)
  363. goto err_lock;
  364. err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  365. if (err < 0)
  366. goto err_lock;
  367. return 0;
  368. err_lock:
  369. dice_unlock(dice);
  370. error:
  371. return err;
  372. }
  373. static int dice_close(struct snd_pcm_substream *substream)
  374. {
  375. struct dice *dice = substream->private_data;
  376. dice_unlock(dice);
  377. return 0;
  378. }
  379. static int dice_stream_start_packets(struct dice *dice)
  380. {
  381. int err;
  382. if (amdtp_out_stream_running(&dice->stream))
  383. return 0;
  384. err = amdtp_out_stream_start(&dice->stream, dice->resources.channel,
  385. fw_parent_device(dice->unit)->max_speed);
  386. if (err < 0)
  387. return err;
  388. err = dice_enable_set(dice);
  389. if (err < 0) {
  390. amdtp_out_stream_stop(&dice->stream);
  391. return err;
  392. }
  393. return 0;
  394. }
  395. static int dice_stream_start(struct dice *dice)
  396. {
  397. __be32 channel;
  398. int err;
  399. if (!dice->resources.allocated) {
  400. err = fw_iso_resources_allocate(&dice->resources,
  401. amdtp_out_stream_get_max_payload(&dice->stream),
  402. fw_parent_device(dice->unit)->max_speed);
  403. if (err < 0)
  404. goto error;
  405. channel = cpu_to_be32(dice->resources.channel);
  406. err = snd_fw_transaction(dice->unit,
  407. TCODE_WRITE_QUADLET_REQUEST,
  408. rx_address(dice, RX_ISOCHRONOUS),
  409. &channel, 4, 0);
  410. if (err < 0)
  411. goto err_resources;
  412. }
  413. err = dice_stream_start_packets(dice);
  414. if (err < 0)
  415. goto err_rx_channel;
  416. return 0;
  417. err_rx_channel:
  418. channel = cpu_to_be32((u32)-1);
  419. snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
  420. rx_address(dice, RX_ISOCHRONOUS), &channel, 4, 0);
  421. err_resources:
  422. fw_iso_resources_free(&dice->resources);
  423. error:
  424. return err;
  425. }
  426. static void dice_stream_stop_packets(struct dice *dice)
  427. {
  428. if (amdtp_out_stream_running(&dice->stream)) {
  429. dice_enable_clear(dice);
  430. amdtp_out_stream_stop(&dice->stream);
  431. }
  432. }
  433. static void dice_stream_stop(struct dice *dice)
  434. {
  435. __be32 channel;
  436. dice_stream_stop_packets(dice);
  437. if (!dice->resources.allocated)
  438. return;
  439. channel = cpu_to_be32((u32)-1);
  440. snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
  441. rx_address(dice, RX_ISOCHRONOUS), &channel, 4, 0);
  442. fw_iso_resources_free(&dice->resources);
  443. }
  444. static int dice_change_rate(struct dice *dice, unsigned int clock_rate)
  445. {
  446. __be32 value;
  447. int err;
  448. INIT_COMPLETION(dice->clock_accepted);
  449. value = cpu_to_be32(clock_rate | CLOCK_SOURCE_ARX1);
  450. err = snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
  451. global_address(dice, GLOBAL_CLOCK_SELECT),
  452. &value, 4, 0);
  453. if (err < 0)
  454. return err;
  455. if (!wait_for_completion_timeout(&dice->clock_accepted,
  456. msecs_to_jiffies(100)))
  457. dev_warn(&dice->unit->device, "clock change timed out\n");
  458. return 0;
  459. }
  460. static int dice_hw_params(struct snd_pcm_substream *substream,
  461. struct snd_pcm_hw_params *hw_params)
  462. {
  463. struct dice *dice = substream->private_data;
  464. unsigned int rate_index, mode;
  465. int err;
  466. mutex_lock(&dice->mutex);
  467. dice_stream_stop(dice);
  468. mutex_unlock(&dice->mutex);
  469. err = snd_pcm_lib_alloc_vmalloc_buffer(substream,
  470. params_buffer_bytes(hw_params));
  471. if (err < 0)
  472. return err;
  473. rate_index = rate_to_index(params_rate(hw_params));
  474. err = dice_change_rate(dice, rate_index << CLOCK_RATE_SHIFT);
  475. if (err < 0)
  476. return err;
  477. mode = rate_index_to_mode(rate_index);
  478. amdtp_out_stream_set_parameters(&dice->stream,
  479. params_rate(hw_params),
  480. params_channels(hw_params),
  481. dice->rx_midi_ports[mode]);
  482. amdtp_out_stream_set_pcm_format(&dice->stream,
  483. params_format(hw_params));
  484. return 0;
  485. }
  486. static int dice_hw_free(struct snd_pcm_substream *substream)
  487. {
  488. struct dice *dice = substream->private_data;
  489. mutex_lock(&dice->mutex);
  490. dice_stream_stop(dice);
  491. mutex_unlock(&dice->mutex);
  492. return snd_pcm_lib_free_vmalloc_buffer(substream);
  493. }
  494. static int dice_prepare(struct snd_pcm_substream *substream)
  495. {
  496. struct dice *dice = substream->private_data;
  497. int err;
  498. mutex_lock(&dice->mutex);
  499. if (amdtp_out_streaming_error(&dice->stream))
  500. dice_stream_stop_packets(dice);
  501. err = dice_stream_start(dice);
  502. if (err < 0) {
  503. mutex_unlock(&dice->mutex);
  504. return err;
  505. }
  506. mutex_unlock(&dice->mutex);
  507. amdtp_out_stream_pcm_prepare(&dice->stream);
  508. return 0;
  509. }
  510. static int dice_trigger(struct snd_pcm_substream *substream, int cmd)
  511. {
  512. struct dice *dice = substream->private_data;
  513. struct snd_pcm_substream *pcm;
  514. switch (cmd) {
  515. case SNDRV_PCM_TRIGGER_START:
  516. pcm = substream;
  517. break;
  518. case SNDRV_PCM_TRIGGER_STOP:
  519. pcm = NULL;
  520. break;
  521. default:
  522. return -EINVAL;
  523. }
  524. amdtp_out_stream_pcm_trigger(&dice->stream, pcm);
  525. return 0;
  526. }
  527. static snd_pcm_uframes_t dice_pointer(struct snd_pcm_substream *substream)
  528. {
  529. struct dice *dice = substream->private_data;
  530. return amdtp_out_stream_pcm_pointer(&dice->stream);
  531. }
  532. static int dice_create_pcm(struct dice *dice)
  533. {
  534. static struct snd_pcm_ops ops = {
  535. .open = dice_open,
  536. .close = dice_close,
  537. .ioctl = snd_pcm_lib_ioctl,
  538. .hw_params = dice_hw_params,
  539. .hw_free = dice_hw_free,
  540. .prepare = dice_prepare,
  541. .trigger = dice_trigger,
  542. .pointer = dice_pointer,
  543. .page = snd_pcm_lib_get_vmalloc_page,
  544. .mmap = snd_pcm_lib_mmap_vmalloc,
  545. };
  546. struct snd_pcm *pcm;
  547. int err;
  548. err = snd_pcm_new(dice->card, "DICE", 0, 1, 0, &pcm);
  549. if (err < 0)
  550. return err;
  551. pcm->private_data = dice;
  552. strcpy(pcm->name, dice->card->shortname);
  553. pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->ops = &ops;
  554. return 0;
  555. }
  556. static long dice_hwdep_read(struct snd_hwdep *hwdep, char __user *buf,
  557. long count, loff_t *offset)
  558. {
  559. struct dice *dice = hwdep->private_data;
  560. DEFINE_WAIT(wait);
  561. union snd_firewire_event event;
  562. spin_lock_irq(&dice->lock);
  563. while (!dice->dev_lock_changed && dice->notification_bits == 0) {
  564. prepare_to_wait(&dice->hwdep_wait, &wait, TASK_INTERRUPTIBLE);
  565. spin_unlock_irq(&dice->lock);
  566. schedule();
  567. finish_wait(&dice->hwdep_wait, &wait);
  568. if (signal_pending(current))
  569. return -ERESTARTSYS;
  570. spin_lock_irq(&dice->lock);
  571. }
  572. memset(&event, 0, sizeof(event));
  573. if (dice->dev_lock_changed) {
  574. event.lock_status.type = SNDRV_FIREWIRE_EVENT_LOCK_STATUS;
  575. event.lock_status.status = dice->dev_lock_count > 0;
  576. dice->dev_lock_changed = false;
  577. count = min(count, (long)sizeof(event.lock_status));
  578. } else {
  579. event.dice_notification.type = SNDRV_FIREWIRE_EVENT_DICE_NOTIFICATION;
  580. event.dice_notification.notification = dice->notification_bits;
  581. dice->notification_bits = 0;
  582. count = min(count, (long)sizeof(event.dice_notification));
  583. }
  584. spin_unlock_irq(&dice->lock);
  585. if (copy_to_user(buf, &event, count))
  586. return -EFAULT;
  587. return count;
  588. }
  589. static unsigned int dice_hwdep_poll(struct snd_hwdep *hwdep, struct file *file,
  590. poll_table *wait)
  591. {
  592. struct dice *dice = hwdep->private_data;
  593. unsigned int events;
  594. poll_wait(file, &dice->hwdep_wait, wait);
  595. spin_lock_irq(&dice->lock);
  596. if (dice->dev_lock_changed || dice->notification_bits != 0)
  597. events = POLLIN | POLLRDNORM;
  598. else
  599. events = 0;
  600. spin_unlock_irq(&dice->lock);
  601. return events;
  602. }
  603. static int dice_hwdep_get_info(struct dice *dice, void __user *arg)
  604. {
  605. struct fw_device *dev = fw_parent_device(dice->unit);
  606. struct snd_firewire_get_info info;
  607. memset(&info, 0, sizeof(info));
  608. info.type = SNDRV_FIREWIRE_TYPE_DICE;
  609. info.card = dev->card->index;
  610. *(__be32 *)&info.guid[0] = cpu_to_be32(dev->config_rom[3]);
  611. *(__be32 *)&info.guid[4] = cpu_to_be32(dev->config_rom[4]);
  612. strlcpy(info.device_name, dev_name(&dev->device),
  613. sizeof(info.device_name));
  614. if (copy_to_user(arg, &info, sizeof(info)))
  615. return -EFAULT;
  616. return 0;
  617. }
  618. static int dice_hwdep_lock(struct dice *dice)
  619. {
  620. int err;
  621. spin_lock_irq(&dice->lock);
  622. if (dice->dev_lock_count == 0) {
  623. dice->dev_lock_count = -1;
  624. err = 0;
  625. } else {
  626. err = -EBUSY;
  627. }
  628. spin_unlock_irq(&dice->lock);
  629. return err;
  630. }
  631. static int dice_hwdep_unlock(struct dice *dice)
  632. {
  633. int err;
  634. spin_lock_irq(&dice->lock);
  635. if (dice->dev_lock_count == -1) {
  636. dice->dev_lock_count = 0;
  637. err = 0;
  638. } else {
  639. err = -EBADFD;
  640. }
  641. spin_unlock_irq(&dice->lock);
  642. return err;
  643. }
  644. static int dice_hwdep_release(struct snd_hwdep *hwdep, struct file *file)
  645. {
  646. struct dice *dice = hwdep->private_data;
  647. spin_lock_irq(&dice->lock);
  648. if (dice->dev_lock_count == -1)
  649. dice->dev_lock_count = 0;
  650. spin_unlock_irq(&dice->lock);
  651. return 0;
  652. }
  653. static int dice_hwdep_ioctl(struct snd_hwdep *hwdep, struct file *file,
  654. unsigned int cmd, unsigned long arg)
  655. {
  656. struct dice *dice = hwdep->private_data;
  657. switch (cmd) {
  658. case SNDRV_FIREWIRE_IOCTL_GET_INFO:
  659. return dice_hwdep_get_info(dice, (void __user *)arg);
  660. case SNDRV_FIREWIRE_IOCTL_LOCK:
  661. return dice_hwdep_lock(dice);
  662. case SNDRV_FIREWIRE_IOCTL_UNLOCK:
  663. return dice_hwdep_unlock(dice);
  664. default:
  665. return -ENOIOCTLCMD;
  666. }
  667. }
  668. #ifdef CONFIG_COMPAT
  669. static int dice_hwdep_compat_ioctl(struct snd_hwdep *hwdep, struct file *file,
  670. unsigned int cmd, unsigned long arg)
  671. {
  672. return dice_hwdep_ioctl(hwdep, file, cmd,
  673. (unsigned long)compat_ptr(arg));
  674. }
  675. #else
  676. #define dice_hwdep_compat_ioctl NULL
  677. #endif
  678. static int dice_create_hwdep(struct dice *dice)
  679. {
  680. static const struct snd_hwdep_ops ops = {
  681. .read = dice_hwdep_read,
  682. .release = dice_hwdep_release,
  683. .poll = dice_hwdep_poll,
  684. .ioctl = dice_hwdep_ioctl,
  685. .ioctl_compat = dice_hwdep_compat_ioctl,
  686. };
  687. struct snd_hwdep *hwdep;
  688. int err;
  689. err = snd_hwdep_new(dice->card, "DICE", 0, &hwdep);
  690. if (err < 0)
  691. return err;
  692. strcpy(hwdep->name, "DICE");
  693. hwdep->iface = SNDRV_HWDEP_IFACE_FW_DICE;
  694. hwdep->ops = ops;
  695. hwdep->private_data = dice;
  696. hwdep->exclusive = true;
  697. return 0;
  698. }
  699. static void dice_card_free(struct snd_card *card)
  700. {
  701. struct dice *dice = card->private_data;
  702. amdtp_out_stream_destroy(&dice->stream);
  703. fw_core_remove_address_handler(&dice->notification_handler);
  704. mutex_destroy(&dice->mutex);
  705. }
  706. #define DICE_CATEGORY_ID 0x04
  707. static int dice_interface_check(struct fw_unit *unit)
  708. {
  709. static const int min_values[10] = {
  710. 10, 0x64 / 4,
  711. 10, 0x18 / 4,
  712. 10, 0x18 / 4,
  713. 0, 0,
  714. 0, 0,
  715. };
  716. struct fw_device *device = fw_parent_device(unit);
  717. struct fw_csr_iterator it;
  718. int key, value, vendor = -1, model = -1, err;
  719. unsigned int i;
  720. __be32 pointers[ARRAY_SIZE(min_values)];
  721. __be32 version;
  722. /*
  723. * Check that GUID and unit directory are constructed according to DICE
  724. * rules, i.e., that the specifier ID is the GUID's OUI, and that the
  725. * GUID chip ID consists of the 8-bit DICE category ID, the 10-bit
  726. * product ID, and a 22-bit serial number.
  727. */
  728. fw_csr_iterator_init(&it, unit->directory);
  729. while (fw_csr_iterator_next(&it, &key, &value)) {
  730. switch (key) {
  731. case CSR_SPECIFIER_ID:
  732. vendor = value;
  733. break;
  734. case CSR_MODEL:
  735. model = value;
  736. break;
  737. }
  738. }
  739. if (device->config_rom[3] != ((vendor << 8) | DICE_CATEGORY_ID) ||
  740. device->config_rom[4] >> 22 != model)
  741. return -ENODEV;
  742. /*
  743. * Check that the sub address spaces exist and are located inside the
  744. * private address space. The minimum values are chosen so that all
  745. * minimally required registers are included.
  746. */
  747. err = snd_fw_transaction(unit, TCODE_READ_BLOCK_REQUEST,
  748. DICE_PRIVATE_SPACE,
  749. pointers, sizeof(pointers), 0);
  750. if (err < 0)
  751. return -ENODEV;
  752. for (i = 0; i < ARRAY_SIZE(pointers); ++i) {
  753. value = be32_to_cpu(pointers[i]);
  754. if (value < min_values[i] || value >= 0x40000)
  755. return -ENODEV;
  756. }
  757. /*
  758. * Check that the implemented DICE driver specification major version
  759. * number matches.
  760. */
  761. err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
  762. DICE_PRIVATE_SPACE +
  763. be32_to_cpu(pointers[0]) * 4 + GLOBAL_VERSION,
  764. &version, 4, 0);
  765. if (err < 0)
  766. return -ENODEV;
  767. if ((version & cpu_to_be32(0xff000000)) != cpu_to_be32(0x01000000)) {
  768. dev_err(&unit->device,
  769. "unknown DICE version: 0x%08x\n", be32_to_cpu(version));
  770. return -ENODEV;
  771. }
  772. return 0;
  773. }
  774. static int highest_supported_mode_rate(struct dice *dice, unsigned int mode)
  775. {
  776. int i;
  777. for (i = ARRAY_SIZE(dice_rates) - 1; i >= 0; --i)
  778. if ((dice->clock_caps & (1 << i)) &&
  779. rate_index_to_mode(i) == mode)
  780. return i;
  781. return -1;
  782. }
  783. static int dice_read_mode_params(struct dice *dice, unsigned int mode)
  784. {
  785. __be32 values[2];
  786. int rate_index, err;
  787. rate_index = highest_supported_mode_rate(dice, mode);
  788. if (rate_index < 0) {
  789. dice->rx_channels[mode] = 0;
  790. dice->rx_midi_ports[mode] = 0;
  791. return 0;
  792. }
  793. err = dice_change_rate(dice, rate_index << CLOCK_RATE_SHIFT);
  794. if (err < 0)
  795. return err;
  796. err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
  797. rx_address(dice, RX_NUMBER_AUDIO),
  798. values, 2 * 4, 0);
  799. if (err < 0)
  800. return err;
  801. dice->rx_channels[mode] = be32_to_cpu(values[0]);
  802. dice->rx_midi_ports[mode] = be32_to_cpu(values[1]);
  803. return 0;
  804. }
  805. static int dice_read_params(struct dice *dice)
  806. {
  807. __be32 pointers[6];
  808. __be32 value;
  809. int mode, err;
  810. err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
  811. DICE_PRIVATE_SPACE,
  812. pointers, sizeof(pointers), 0);
  813. if (err < 0)
  814. return err;
  815. dice->global_offset = be32_to_cpu(pointers[0]) * 4;
  816. dice->rx_offset = be32_to_cpu(pointers[4]) * 4;
  817. /* some very old firmwares don't tell about their clock support */
  818. if (be32_to_cpu(pointers[1]) * 4 >= GLOBAL_CLOCK_CAPABILITIES + 4) {
  819. err = snd_fw_transaction(
  820. dice->unit, TCODE_READ_QUADLET_REQUEST,
  821. global_address(dice, GLOBAL_CLOCK_CAPABILITIES),
  822. &value, 4, 0);
  823. if (err < 0)
  824. return err;
  825. dice->clock_caps = be32_to_cpu(value);
  826. } else {
  827. /* this should be supported by any device */
  828. dice->clock_caps = CLOCK_CAP_RATE_44100 |
  829. CLOCK_CAP_RATE_48000 |
  830. CLOCK_CAP_SOURCE_ARX1 |
  831. CLOCK_CAP_SOURCE_INTERNAL;
  832. }
  833. for (mode = 2; mode >= 0; --mode) {
  834. err = dice_read_mode_params(dice, mode);
  835. if (err < 0)
  836. return err;
  837. }
  838. return 0;
  839. }
  840. static void dice_card_strings(struct dice *dice)
  841. {
  842. struct snd_card *card = dice->card;
  843. struct fw_device *dev = fw_parent_device(dice->unit);
  844. char vendor[32], model[32];
  845. unsigned int i;
  846. int err;
  847. strcpy(card->driver, "DICE");
  848. strcpy(card->shortname, "DICE");
  849. BUILD_BUG_ON(NICK_NAME_SIZE < sizeof(card->shortname));
  850. err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
  851. global_address(dice, GLOBAL_NICK_NAME),
  852. card->shortname, sizeof(card->shortname), 0);
  853. if (err >= 0) {
  854. /* DICE strings are returned in "always-wrong" endianness */
  855. BUILD_BUG_ON(sizeof(card->shortname) % 4 != 0);
  856. for (i = 0; i < sizeof(card->shortname); i += 4)
  857. swab32s((u32 *)&card->shortname[i]);
  858. card->shortname[sizeof(card->shortname) - 1] = '\0';
  859. }
  860. strcpy(vendor, "?");
  861. fw_csr_string(dev->config_rom + 5, CSR_VENDOR, vendor, sizeof(vendor));
  862. strcpy(model, "?");
  863. fw_csr_string(dice->unit->directory, CSR_MODEL, model, sizeof(model));
  864. snprintf(card->longname, sizeof(card->longname),
  865. "%s %s (serial %u) at %s, S%d",
  866. vendor, model, dev->config_rom[4] & 0x3fffff,
  867. dev_name(&dice->unit->device), 100 << dev->max_speed);
  868. strcpy(card->mixername, "DICE");
  869. }
  870. static int dice_probe(struct fw_unit *unit, const struct ieee1394_device_id *id)
  871. {
  872. struct snd_card *card;
  873. struct dice *dice;
  874. __be32 clock_sel;
  875. int err;
  876. err = dice_interface_check(unit);
  877. if (err < 0)
  878. return err;
  879. err = snd_card_create(-1, NULL, THIS_MODULE, sizeof(*dice), &card);
  880. if (err < 0)
  881. return err;
  882. snd_card_set_dev(card, &unit->device);
  883. dice = card->private_data;
  884. dice->card = card;
  885. spin_lock_init(&dice->lock);
  886. mutex_init(&dice->mutex);
  887. dice->unit = unit;
  888. init_completion(&dice->clock_accepted);
  889. init_waitqueue_head(&dice->hwdep_wait);
  890. dice->notification_handler.length = 4;
  891. dice->notification_handler.address_callback = dice_notification;
  892. dice->notification_handler.callback_data = dice;
  893. err = fw_core_add_address_handler(&dice->notification_handler,
  894. &fw_high_memory_region);
  895. if (err < 0)
  896. goto err_mutex;
  897. err = dice_owner_set(dice);
  898. if (err < 0)
  899. goto err_notification_handler;
  900. err = dice_read_params(dice);
  901. if (err < 0)
  902. goto err_owner;
  903. err = fw_iso_resources_init(&dice->resources, unit);
  904. if (err < 0)
  905. goto err_owner;
  906. dice->resources.channels_mask = 0x00000000ffffffffuLL;
  907. err = amdtp_out_stream_init(&dice->stream, unit,
  908. CIP_BLOCKING | CIP_HI_DUALWIRE);
  909. if (err < 0)
  910. goto err_resources;
  911. card->private_free = dice_card_free;
  912. dice_card_strings(dice);
  913. err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
  914. global_address(dice, GLOBAL_CLOCK_SELECT),
  915. &clock_sel, 4, 0);
  916. if (err < 0)
  917. goto error;
  918. clock_sel &= cpu_to_be32(~CLOCK_SOURCE_MASK);
  919. clock_sel |= cpu_to_be32(CLOCK_SOURCE_ARX1);
  920. err = snd_fw_transaction(unit, TCODE_WRITE_QUADLET_REQUEST,
  921. global_address(dice, GLOBAL_CLOCK_SELECT),
  922. &clock_sel, 4, 0);
  923. if (err < 0)
  924. goto error;
  925. err = dice_create_pcm(dice);
  926. if (err < 0)
  927. goto error;
  928. err = dice_create_hwdep(dice);
  929. if (err < 0)
  930. goto error;
  931. err = snd_card_register(card);
  932. if (err < 0)
  933. goto error;
  934. dev_set_drvdata(&unit->device, dice);
  935. return 0;
  936. err_resources:
  937. fw_iso_resources_destroy(&dice->resources);
  938. err_owner:
  939. dice_owner_clear(dice);
  940. err_notification_handler:
  941. fw_core_remove_address_handler(&dice->notification_handler);
  942. err_mutex:
  943. mutex_destroy(&dice->mutex);
  944. error:
  945. snd_card_free(card);
  946. return err;
  947. }
  948. static void dice_remove(struct fw_unit *unit)
  949. {
  950. struct dice *dice = dev_get_drvdata(&unit->device);
  951. amdtp_out_stream_pcm_abort(&dice->stream);
  952. snd_card_disconnect(dice->card);
  953. mutex_lock(&dice->mutex);
  954. dice_stream_stop(dice);
  955. dice_owner_clear(dice);
  956. mutex_unlock(&dice->mutex);
  957. snd_card_free_when_closed(dice->card);
  958. }
  959. static void dice_bus_reset(struct fw_unit *unit)
  960. {
  961. struct dice *dice = dev_get_drvdata(&unit->device);
  962. /*
  963. * On a bus reset, the DICE firmware disables streaming and then goes
  964. * off contemplating its own navel for hundreds of milliseconds before
  965. * it can react to any of our attempts to reenable streaming. This
  966. * means that we lose synchronization anyway, so we force our streams
  967. * to stop so that the application can restart them in an orderly
  968. * manner.
  969. */
  970. amdtp_out_stream_pcm_abort(&dice->stream);
  971. mutex_lock(&dice->mutex);
  972. dice->global_enabled = false;
  973. dice_stream_stop_packets(dice);
  974. dice_owner_update(dice);
  975. fw_iso_resources_update(&dice->resources);
  976. mutex_unlock(&dice->mutex);
  977. }
  978. #define DICE_INTERFACE 0x000001
  979. static const struct ieee1394_device_id dice_id_table[] = {
  980. {
  981. .match_flags = IEEE1394_MATCH_VERSION,
  982. .version = DICE_INTERFACE,
  983. },
  984. { }
  985. };
  986. MODULE_DEVICE_TABLE(ieee1394, dice_id_table);
  987. static struct fw_driver dice_driver = {
  988. .driver = {
  989. .owner = THIS_MODULE,
  990. .name = KBUILD_MODNAME,
  991. .bus = &fw_bus_type,
  992. },
  993. .probe = dice_probe,
  994. .update = dice_bus_reset,
  995. .remove = dice_remove,
  996. .id_table = dice_id_table,
  997. };
  998. static int __init alsa_dice_init(void)
  999. {
  1000. return driver_register(&dice_driver.driver);
  1001. }
  1002. static void __exit alsa_dice_exit(void)
  1003. {
  1004. driver_unregister(&dice_driver.driver);
  1005. }
  1006. module_init(alsa_dice_init);
  1007. module_exit(alsa_dice_exit);