apic_numachip.c 6.5 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Numascale NumaConnect-Specific APIC Code
  7. *
  8. * Copyright (C) 2011 Numascale AS. All rights reserved.
  9. *
  10. * Send feedback to <support@numascale.com>
  11. *
  12. */
  13. #include <linux/errno.h>
  14. #include <linux/threads.h>
  15. #include <linux/cpumask.h>
  16. #include <linux/string.h>
  17. #include <linux/kernel.h>
  18. #include <linux/module.h>
  19. #include <linux/ctype.h>
  20. #include <linux/init.h>
  21. #include <linux/hardirq.h>
  22. #include <linux/delay.h>
  23. #include <asm/numachip/numachip_csr.h>
  24. #include <asm/smp.h>
  25. #include <asm/apic.h>
  26. #include <asm/ipi.h>
  27. #include <asm/apic_flat_64.h>
  28. static int numachip_system __read_mostly;
  29. static struct apic apic_numachip __read_mostly;
  30. static unsigned int get_apic_id(unsigned long x)
  31. {
  32. unsigned long value;
  33. unsigned int id;
  34. rdmsrl(MSR_FAM10H_NODE_ID, value);
  35. id = ((x >> 24) & 0xffU) | ((value << 2) & 0x3f00U);
  36. return id;
  37. }
  38. static unsigned long set_apic_id(unsigned int id)
  39. {
  40. unsigned long x;
  41. x = ((id & 0xffU) << 24);
  42. return x;
  43. }
  44. static unsigned int read_xapic_id(void)
  45. {
  46. return get_apic_id(apic_read(APIC_ID));
  47. }
  48. static int numachip_apic_id_valid(int apicid)
  49. {
  50. /* Trust what bootloader passes in MADT */
  51. return 1;
  52. }
  53. static int numachip_apic_id_registered(void)
  54. {
  55. return physid_isset(read_xapic_id(), phys_cpu_present_map);
  56. }
  57. static int numachip_phys_pkg_id(int initial_apic_id, int index_msb)
  58. {
  59. return initial_apic_id >> index_msb;
  60. }
  61. static void numachip_vector_allocation_domain(int cpu, struct cpumask *retmask)
  62. {
  63. cpumask_clear(retmask);
  64. cpumask_set_cpu(cpu, retmask);
  65. }
  66. static int __cpuinit numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip)
  67. {
  68. union numachip_csr_g3_ext_irq_gen int_gen;
  69. int_gen.s._destination_apic_id = phys_apicid;
  70. int_gen.s._vector = 0;
  71. int_gen.s._msgtype = APIC_DM_INIT >> 8;
  72. int_gen.s._index = 0;
  73. write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);
  74. int_gen.s._msgtype = APIC_DM_STARTUP >> 8;
  75. int_gen.s._vector = start_rip >> 12;
  76. write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);
  77. atomic_set(&init_deasserted, 1);
  78. return 0;
  79. }
  80. static void numachip_send_IPI_one(int cpu, int vector)
  81. {
  82. union numachip_csr_g3_ext_irq_gen int_gen;
  83. int apicid = per_cpu(x86_cpu_to_apicid, cpu);
  84. int_gen.s._destination_apic_id = apicid;
  85. int_gen.s._vector = vector;
  86. int_gen.s._msgtype = (vector == NMI_VECTOR ? APIC_DM_NMI : APIC_DM_FIXED) >> 8;
  87. int_gen.s._index = 0;
  88. write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);
  89. }
  90. static void numachip_send_IPI_mask(const struct cpumask *mask, int vector)
  91. {
  92. unsigned int cpu;
  93. for_each_cpu(cpu, mask)
  94. numachip_send_IPI_one(cpu, vector);
  95. }
  96. static void numachip_send_IPI_mask_allbutself(const struct cpumask *mask,
  97. int vector)
  98. {
  99. unsigned int this_cpu = smp_processor_id();
  100. unsigned int cpu;
  101. for_each_cpu(cpu, mask) {
  102. if (cpu != this_cpu)
  103. numachip_send_IPI_one(cpu, vector);
  104. }
  105. }
  106. static void numachip_send_IPI_allbutself(int vector)
  107. {
  108. unsigned int this_cpu = smp_processor_id();
  109. unsigned int cpu;
  110. for_each_online_cpu(cpu) {
  111. if (cpu != this_cpu)
  112. numachip_send_IPI_one(cpu, vector);
  113. }
  114. }
  115. static void numachip_send_IPI_all(int vector)
  116. {
  117. numachip_send_IPI_mask(cpu_online_mask, vector);
  118. }
  119. static void numachip_send_IPI_self(int vector)
  120. {
  121. __default_send_IPI_shortcut(APIC_DEST_SELF, vector, APIC_DEST_PHYSICAL);
  122. }
  123. static int __init numachip_probe(void)
  124. {
  125. return apic == &apic_numachip;
  126. }
  127. static void __init map_csrs(void)
  128. {
  129. printk(KERN_INFO "NumaChip: Mapping local CSR space (%016llx - %016llx)\n",
  130. NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_BASE + NUMACHIP_LCSR_SIZE - 1);
  131. init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE);
  132. printk(KERN_INFO "NumaChip: Mapping global CSR space (%016llx - %016llx)\n",
  133. NUMACHIP_GCSR_BASE, NUMACHIP_GCSR_BASE + NUMACHIP_GCSR_SIZE - 1);
  134. init_extra_mapping_uc(NUMACHIP_GCSR_BASE, NUMACHIP_GCSR_SIZE);
  135. }
  136. static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
  137. {
  138. if (c->phys_proc_id != node) {
  139. c->phys_proc_id = node;
  140. per_cpu(cpu_llc_id, smp_processor_id()) = node;
  141. }
  142. }
  143. static int __init numachip_system_init(void)
  144. {
  145. unsigned int val;
  146. if (!numachip_system)
  147. return 0;
  148. x86_cpuinit.fixup_cpu_id = fixup_cpu_id;
  149. map_csrs();
  150. val = read_lcsr(CSR_G0_NODE_IDS);
  151. printk(KERN_INFO "NumaChip: Local NodeID = %08x\n", val);
  152. return 0;
  153. }
  154. early_initcall(numachip_system_init);
  155. static int numachip_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  156. {
  157. if (!strncmp(oem_id, "NUMASC", 6)) {
  158. numachip_system = 1;
  159. return 1;
  160. }
  161. return 0;
  162. }
  163. static struct apic apic_numachip __refconst = {
  164. .name = "NumaConnect system",
  165. .probe = numachip_probe,
  166. .acpi_madt_oem_check = numachip_acpi_madt_oem_check,
  167. .apic_id_valid = numachip_apic_id_valid,
  168. .apic_id_registered = numachip_apic_id_registered,
  169. .irq_delivery_mode = dest_Fixed,
  170. .irq_dest_mode = 0, /* physical */
  171. .target_cpus = online_target_cpus,
  172. .disable_esr = 0,
  173. .dest_logical = 0,
  174. .check_apicid_used = NULL,
  175. .check_apicid_present = NULL,
  176. .vector_allocation_domain = numachip_vector_allocation_domain,
  177. .init_apic_ldr = flat_init_apic_ldr,
  178. .ioapic_phys_id_map = NULL,
  179. .setup_apic_routing = NULL,
  180. .multi_timer_check = NULL,
  181. .cpu_present_to_apicid = default_cpu_present_to_apicid,
  182. .apicid_to_cpu_present = NULL,
  183. .setup_portio_remap = NULL,
  184. .check_phys_apicid_present = default_check_phys_apicid_present,
  185. .enable_apic_mode = NULL,
  186. .phys_pkg_id = numachip_phys_pkg_id,
  187. .mps_oem_check = NULL,
  188. .get_apic_id = get_apic_id,
  189. .set_apic_id = set_apic_id,
  190. .apic_id_mask = 0xffU << 24,
  191. .cpu_mask_to_apicid = default_cpu_mask_to_apicid,
  192. .cpu_mask_to_apicid_and = default_cpu_mask_to_apicid_and,
  193. .send_IPI_mask = numachip_send_IPI_mask,
  194. .send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself,
  195. .send_IPI_allbutself = numachip_send_IPI_allbutself,
  196. .send_IPI_all = numachip_send_IPI_all,
  197. .send_IPI_self = numachip_send_IPI_self,
  198. .wakeup_secondary_cpu = numachip_wakeup_secondary,
  199. .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
  200. .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
  201. .wait_for_init_deassert = NULL,
  202. .smp_callin_clear_local_apic = NULL,
  203. .inquire_remote_apic = NULL, /* REMRD not supported */
  204. .read = native_apic_mem_read,
  205. .write = native_apic_mem_write,
  206. .eoi_write = native_apic_mem_write,
  207. .icr_read = native_apic_icr_read,
  208. .icr_write = native_apic_icr_write,
  209. .wait_icr_idle = native_apic_wait_icr_idle,
  210. .safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
  211. };
  212. apic_driver(apic_numachip);