iwl-4965.c 100 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520
  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  23. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24. *
  25. *****************************************************************************/
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/version.h>
  29. #include <linux/init.h>
  30. #include <linux/pci.h>
  31. #include <linux/dma-mapping.h>
  32. #include <linux/delay.h>
  33. #include <linux/skbuff.h>
  34. #include <linux/netdevice.h>
  35. #include <linux/wireless.h>
  36. #include <net/mac80211.h>
  37. #include <linux/etherdevice.h>
  38. #include <asm/unaligned.h>
  39. #include "iwl-eeprom.h"
  40. #include "iwl-dev.h"
  41. #include "iwl-core.h"
  42. #include "iwl-io.h"
  43. #include "iwl-helpers.h"
  44. #include "iwl-calib.h"
  45. #include "iwl-sta.h"
  46. static int iwl4965_send_tx_power(struct iwl_priv *priv);
  47. /* module parameters */
  48. static struct iwl_mod_params iwl4965_mod_params = {
  49. .num_of_queues = IWL49_NUM_QUEUES,
  50. .enable_qos = 1,
  51. .amsdu_size_8K = 1,
  52. .restart_fw = 1,
  53. /* the rest are 0 by default */
  54. };
  55. /* check contents of special bootstrap uCode SRAM */
  56. static int iwl4965_verify_bsm(struct iwl_priv *priv)
  57. {
  58. __le32 *image = priv->ucode_boot.v_addr;
  59. u32 len = priv->ucode_boot.len;
  60. u32 reg;
  61. u32 val;
  62. IWL_DEBUG_INFO("Begin verify bsm\n");
  63. /* verify BSM SRAM contents */
  64. val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
  65. for (reg = BSM_SRAM_LOWER_BOUND;
  66. reg < BSM_SRAM_LOWER_BOUND + len;
  67. reg += sizeof(u32), image++) {
  68. val = iwl_read_prph(priv, reg);
  69. if (val != le32_to_cpu(*image)) {
  70. IWL_ERROR("BSM uCode verification failed at "
  71. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  72. BSM_SRAM_LOWER_BOUND,
  73. reg - BSM_SRAM_LOWER_BOUND, len,
  74. val, le32_to_cpu(*image));
  75. return -EIO;
  76. }
  77. }
  78. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  79. return 0;
  80. }
  81. /**
  82. * iwl4965_load_bsm - Load bootstrap instructions
  83. *
  84. * BSM operation:
  85. *
  86. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  87. * in special SRAM that does not power down during RFKILL. When powering back
  88. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  89. * the bootstrap program into the on-board processor, and starts it.
  90. *
  91. * The bootstrap program loads (via DMA) instructions and data for a new
  92. * program from host DRAM locations indicated by the host driver in the
  93. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  94. * automatically.
  95. *
  96. * When initializing the NIC, the host driver points the BSM to the
  97. * "initialize" uCode image. This uCode sets up some internal data, then
  98. * notifies host via "initialize alive" that it is complete.
  99. *
  100. * The host then replaces the BSM_DRAM_* pointer values to point to the
  101. * normal runtime uCode instructions and a backup uCode data cache buffer
  102. * (filled initially with starting data values for the on-board processor),
  103. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  104. * which begins normal operation.
  105. *
  106. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  107. * the backup data cache in DRAM before SRAM is powered down.
  108. *
  109. * When powering back up, the BSM loads the bootstrap program. This reloads
  110. * the runtime uCode instructions and the backup data cache into SRAM,
  111. * and re-launches the runtime uCode from where it left off.
  112. */
  113. static int iwl4965_load_bsm(struct iwl_priv *priv)
  114. {
  115. __le32 *image = priv->ucode_boot.v_addr;
  116. u32 len = priv->ucode_boot.len;
  117. dma_addr_t pinst;
  118. dma_addr_t pdata;
  119. u32 inst_len;
  120. u32 data_len;
  121. int i;
  122. u32 done;
  123. u32 reg_offset;
  124. int ret;
  125. IWL_DEBUG_INFO("Begin load bsm\n");
  126. priv->ucode_type = UCODE_RT;
  127. /* make sure bootstrap program is no larger than BSM's SRAM size */
  128. if (len > IWL_MAX_BSM_SIZE)
  129. return -EINVAL;
  130. /* Tell bootstrap uCode where to find the "Initialize" uCode
  131. * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
  132. * NOTE: iwl_init_alive_start() will replace these values,
  133. * after the "initialize" uCode has run, to point to
  134. * runtime/protocol instructions and backup data cache.
  135. */
  136. pinst = priv->ucode_init.p_addr >> 4;
  137. pdata = priv->ucode_init_data.p_addr >> 4;
  138. inst_len = priv->ucode_init.len;
  139. data_len = priv->ucode_init_data.len;
  140. ret = iwl_grab_nic_access(priv);
  141. if (ret)
  142. return ret;
  143. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  144. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  145. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  146. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  147. /* Fill BSM memory with bootstrap instructions */
  148. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  149. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  150. reg_offset += sizeof(u32), image++)
  151. _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
  152. ret = iwl4965_verify_bsm(priv);
  153. if (ret) {
  154. iwl_release_nic_access(priv);
  155. return ret;
  156. }
  157. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  158. iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  159. iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
  160. iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  161. /* Load bootstrap code into instruction SRAM now,
  162. * to prepare to load "initialize" uCode */
  163. iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
  164. /* Wait for load of bootstrap uCode to finish */
  165. for (i = 0; i < 100; i++) {
  166. done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
  167. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  168. break;
  169. udelay(10);
  170. }
  171. if (i < 100)
  172. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  173. else {
  174. IWL_ERROR("BSM write did not complete!\n");
  175. return -EIO;
  176. }
  177. /* Enable future boot loads whenever power management unit triggers it
  178. * (e.g. when powering back up after power-save shutdown) */
  179. iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
  180. iwl_release_nic_access(priv);
  181. return 0;
  182. }
  183. /**
  184. * iwl4965_set_ucode_ptrs - Set uCode address location
  185. *
  186. * Tell initialization uCode where to find runtime uCode.
  187. *
  188. * BSM registers initially contain pointers to initialization uCode.
  189. * We need to replace them to load runtime uCode inst and data,
  190. * and to save runtime data when powering down.
  191. */
  192. static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
  193. {
  194. dma_addr_t pinst;
  195. dma_addr_t pdata;
  196. unsigned long flags;
  197. int ret = 0;
  198. /* bits 35:4 for 4965 */
  199. pinst = priv->ucode_code.p_addr >> 4;
  200. pdata = priv->ucode_data_backup.p_addr >> 4;
  201. spin_lock_irqsave(&priv->lock, flags);
  202. ret = iwl_grab_nic_access(priv);
  203. if (ret) {
  204. spin_unlock_irqrestore(&priv->lock, flags);
  205. return ret;
  206. }
  207. /* Tell bootstrap uCode where to find image to load */
  208. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  209. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  210. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  211. priv->ucode_data.len);
  212. /* Inst bytecount must be last to set up, bit 31 signals uCode
  213. * that all new ptr/size info is in place */
  214. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  215. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  216. iwl_release_nic_access(priv);
  217. spin_unlock_irqrestore(&priv->lock, flags);
  218. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  219. return ret;
  220. }
  221. /**
  222. * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
  223. *
  224. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  225. *
  226. * The 4965 "initialize" ALIVE reply contains calibration data for:
  227. * Voltage, temperature, and MIMO tx gain correction, now stored in priv
  228. * (3945 does not contain this data).
  229. *
  230. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  231. */
  232. static void iwl4965_init_alive_start(struct iwl_priv *priv)
  233. {
  234. /* Check alive response for "valid" sign from uCode */
  235. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  236. /* We had an error bringing up the hardware, so take it
  237. * all the way back down so we can try again */
  238. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  239. goto restart;
  240. }
  241. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  242. * This is a paranoid check, because we would not have gotten the
  243. * "initialize" alive if code weren't properly loaded. */
  244. if (iwl_verify_ucode(priv)) {
  245. /* Runtime instruction load was bad;
  246. * take it all the way back down so we can try again */
  247. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  248. goto restart;
  249. }
  250. /* Calculate temperature */
  251. priv->temperature = iwl4965_get_temperature(priv);
  252. /* Send pointers to protocol/runtime uCode image ... init code will
  253. * load and launch runtime uCode, which will send us another "Alive"
  254. * notification. */
  255. IWL_DEBUG_INFO("Initialization Alive received.\n");
  256. if (iwl4965_set_ucode_ptrs(priv)) {
  257. /* Runtime instruction load won't happen;
  258. * take it all the way back down so we can try again */
  259. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  260. goto restart;
  261. }
  262. return;
  263. restart:
  264. queue_work(priv->workqueue, &priv->restart);
  265. }
  266. static int is_fat_channel(__le32 rxon_flags)
  267. {
  268. return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
  269. (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
  270. }
  271. int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
  272. {
  273. int idx = 0;
  274. /* 4965 HT rate format */
  275. if (rate_n_flags & RATE_MCS_HT_MSK) {
  276. idx = (rate_n_flags & 0xff);
  277. if (idx >= IWL_RATE_MIMO2_6M_PLCP)
  278. idx = idx - IWL_RATE_MIMO2_6M_PLCP;
  279. idx += IWL_FIRST_OFDM_RATE;
  280. /* skip 9M not supported in ht*/
  281. if (idx >= IWL_RATE_9M_INDEX)
  282. idx += 1;
  283. if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
  284. return idx;
  285. /* 4965 legacy rate format, search for match in table */
  286. } else {
  287. for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
  288. if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
  289. return idx;
  290. }
  291. return -1;
  292. }
  293. /**
  294. * translate ucode response to mac80211 tx status control values
  295. */
  296. void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
  297. struct ieee80211_tx_info *control)
  298. {
  299. int rate_index;
  300. control->antenna_sel_tx =
  301. ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
  302. if (rate_n_flags & RATE_MCS_HT_MSK)
  303. control->flags |= IEEE80211_TX_CTL_OFDM_HT;
  304. if (rate_n_flags & RATE_MCS_GF_MSK)
  305. control->flags |= IEEE80211_TX_CTL_GREEN_FIELD;
  306. if (rate_n_flags & RATE_MCS_FAT_MSK)
  307. control->flags |= IEEE80211_TX_CTL_40_MHZ_WIDTH;
  308. if (rate_n_flags & RATE_MCS_DUP_MSK)
  309. control->flags |= IEEE80211_TX_CTL_DUP_DATA;
  310. if (rate_n_flags & RATE_MCS_SGI_MSK)
  311. control->flags |= IEEE80211_TX_CTL_SHORT_GI;
  312. rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
  313. if (control->band == IEEE80211_BAND_5GHZ)
  314. rate_index -= IWL_FIRST_OFDM_RATE;
  315. control->tx_rate_idx = rate_index;
  316. }
  317. /*
  318. * EEPROM handlers
  319. */
  320. static int iwl4965_eeprom_check_version(struct iwl_priv *priv)
  321. {
  322. u16 eeprom_ver;
  323. u16 calib_ver;
  324. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  325. calib_ver = iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
  326. if (eeprom_ver < EEPROM_4965_EEPROM_VERSION ||
  327. calib_ver < EEPROM_4965_TX_POWER_VERSION)
  328. goto err;
  329. return 0;
  330. err:
  331. IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
  332. eeprom_ver, EEPROM_4965_EEPROM_VERSION,
  333. calib_ver, EEPROM_4965_TX_POWER_VERSION);
  334. return -EINVAL;
  335. }
  336. int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  337. {
  338. int ret;
  339. unsigned long flags;
  340. spin_lock_irqsave(&priv->lock, flags);
  341. ret = iwl_grab_nic_access(priv);
  342. if (ret) {
  343. spin_unlock_irqrestore(&priv->lock, flags);
  344. return ret;
  345. }
  346. if (src == IWL_PWR_SRC_VAUX) {
  347. u32 val;
  348. ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
  349. &val);
  350. if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
  351. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  352. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  353. ~APMG_PS_CTRL_MSK_PWR_SRC);
  354. }
  355. } else {
  356. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  357. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  358. ~APMG_PS_CTRL_MSK_PWR_SRC);
  359. }
  360. iwl_release_nic_access(priv);
  361. spin_unlock_irqrestore(&priv->lock, flags);
  362. return ret;
  363. }
  364. /*
  365. * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask
  366. * must be called under priv->lock and mac access
  367. */
  368. static void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask)
  369. {
  370. iwl_write_prph(priv, IWL49_SCD_TXFACT, mask);
  371. }
  372. static int iwl4965_apm_init(struct iwl_priv *priv)
  373. {
  374. int ret = 0;
  375. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  376. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  377. /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
  378. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  379. CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
  380. /* set "initialization complete" bit to move adapter
  381. * D0U* --> D0A* state */
  382. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  383. /* wait for clock stabilization */
  384. ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
  385. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  386. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  387. if (ret < 0) {
  388. IWL_DEBUG_INFO("Failed to init the card\n");
  389. goto out;
  390. }
  391. ret = iwl_grab_nic_access(priv);
  392. if (ret)
  393. goto out;
  394. /* enable DMA */
  395. iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
  396. APMG_CLK_VAL_BSM_CLK_RQT);
  397. udelay(20);
  398. /* disable L1-Active */
  399. iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  400. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  401. iwl_release_nic_access(priv);
  402. out:
  403. return ret;
  404. }
  405. static void iwl4965_nic_config(struct iwl_priv *priv)
  406. {
  407. unsigned long flags;
  408. u32 val;
  409. u16 radio_cfg;
  410. u8 val_link;
  411. spin_lock_irqsave(&priv->lock, flags);
  412. if ((priv->rev_id & 0x80) == 0x80 && (priv->rev_id & 0x7f) < 8) {
  413. pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
  414. /* Enable No Snoop field */
  415. pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
  416. val & ~(1 << 11));
  417. }
  418. pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
  419. /* L1 is enabled by BIOS */
  420. if ((val_link & PCI_LINK_VAL_L1_EN) == PCI_LINK_VAL_L1_EN)
  421. /* diable L0S disabled L1A enabled */
  422. iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
  423. else
  424. /* L0S enabled L1A disabled */
  425. iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
  426. radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
  427. /* write radio config values to register */
  428. if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
  429. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  430. EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
  431. EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
  432. EEPROM_RF_CFG_DASH_MSK(radio_cfg));
  433. /* set CSR_HW_CONFIG_REG for uCode use */
  434. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  435. CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
  436. CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
  437. priv->calib_info = (struct iwl_eeprom_calib_info *)
  438. iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
  439. spin_unlock_irqrestore(&priv->lock, flags);
  440. }
  441. static int iwl4965_apm_stop_master(struct iwl_priv *priv)
  442. {
  443. int ret = 0;
  444. unsigned long flags;
  445. spin_lock_irqsave(&priv->lock, flags);
  446. /* set stop master bit */
  447. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  448. ret = iwl_poll_bit(priv, CSR_RESET,
  449. CSR_RESET_REG_FLAG_MASTER_DISABLED,
  450. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  451. if (ret < 0)
  452. goto out;
  453. out:
  454. spin_unlock_irqrestore(&priv->lock, flags);
  455. IWL_DEBUG_INFO("stop master\n");
  456. return ret;
  457. }
  458. static void iwl4965_apm_stop(struct iwl_priv *priv)
  459. {
  460. unsigned long flags;
  461. iwl4965_apm_stop_master(priv);
  462. spin_lock_irqsave(&priv->lock, flags);
  463. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  464. udelay(10);
  465. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  466. spin_unlock_irqrestore(&priv->lock, flags);
  467. }
  468. static int iwl4965_apm_reset(struct iwl_priv *priv)
  469. {
  470. int ret = 0;
  471. unsigned long flags;
  472. iwl4965_apm_stop_master(priv);
  473. spin_lock_irqsave(&priv->lock, flags);
  474. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  475. udelay(10);
  476. /* FIXME: put here L1A -L0S w/a */
  477. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  478. ret = iwl_poll_bit(priv, CSR_RESET,
  479. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  480. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
  481. if (ret)
  482. goto out;
  483. udelay(10);
  484. ret = iwl_grab_nic_access(priv);
  485. if (ret)
  486. goto out;
  487. /* Enable DMA and BSM Clock */
  488. iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT |
  489. APMG_CLK_VAL_BSM_CLK_RQT);
  490. udelay(10);
  491. /* disable L1A */
  492. iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  493. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  494. iwl_release_nic_access(priv);
  495. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  496. wake_up_interruptible(&priv->wait_command_queue);
  497. out:
  498. spin_unlock_irqrestore(&priv->lock, flags);
  499. return ret;
  500. }
  501. #define REG_RECALIB_PERIOD (60)
  502. void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
  503. {
  504. struct iwl4965_ct_kill_config cmd;
  505. unsigned long flags;
  506. int ret = 0;
  507. spin_lock_irqsave(&priv->lock, flags);
  508. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  509. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  510. spin_unlock_irqrestore(&priv->lock, flags);
  511. cmd.critical_temperature_R =
  512. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  513. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  514. sizeof(cmd), &cmd);
  515. if (ret)
  516. IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
  517. else
  518. IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
  519. "critical temperature is %d\n",
  520. cmd.critical_temperature_R);
  521. }
  522. /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
  523. * Called after every association, but this runs only once!
  524. * ... once chain noise is calibrated the first time, it's good forever. */
  525. static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
  526. {
  527. struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
  528. if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
  529. struct iwl4965_calibration_cmd cmd;
  530. memset(&cmd, 0, sizeof(cmd));
  531. cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
  532. cmd.diff_gain_a = 0;
  533. cmd.diff_gain_b = 0;
  534. cmd.diff_gain_c = 0;
  535. if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
  536. sizeof(cmd), &cmd))
  537. IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
  538. data->state = IWL_CHAIN_NOISE_ACCUMULATE;
  539. IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
  540. }
  541. }
  542. static void iwl4965_gain_computation(struct iwl_priv *priv,
  543. u32 *average_noise,
  544. u16 min_average_noise_antenna_i,
  545. u32 min_average_noise)
  546. {
  547. int i, ret;
  548. struct iwl_chain_noise_data *data = &priv->chain_noise_data;
  549. data->delta_gain_code[min_average_noise_antenna_i] = 0;
  550. for (i = 0; i < NUM_RX_CHAINS; i++) {
  551. s32 delta_g = 0;
  552. if (!(data->disconn_array[i]) &&
  553. (data->delta_gain_code[i] ==
  554. CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
  555. delta_g = average_noise[i] - min_average_noise;
  556. data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
  557. data->delta_gain_code[i] =
  558. min(data->delta_gain_code[i],
  559. (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
  560. data->delta_gain_code[i] =
  561. (data->delta_gain_code[i] | (1 << 2));
  562. } else {
  563. data->delta_gain_code[i] = 0;
  564. }
  565. }
  566. IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
  567. data->delta_gain_code[0],
  568. data->delta_gain_code[1],
  569. data->delta_gain_code[2]);
  570. /* Differential gain gets sent to uCode only once */
  571. if (!data->radio_write) {
  572. struct iwl4965_calibration_cmd cmd;
  573. data->radio_write = 1;
  574. memset(&cmd, 0, sizeof(cmd));
  575. cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
  576. cmd.diff_gain_a = data->delta_gain_code[0];
  577. cmd.diff_gain_b = data->delta_gain_code[1];
  578. cmd.diff_gain_c = data->delta_gain_code[2];
  579. ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
  580. sizeof(cmd), &cmd);
  581. if (ret)
  582. IWL_DEBUG_CALIB("fail sending cmd "
  583. "REPLY_PHY_CALIBRATION_CMD \n");
  584. /* TODO we might want recalculate
  585. * rx_chain in rxon cmd */
  586. /* Mark so we run this algo only once! */
  587. data->state = IWL_CHAIN_NOISE_CALIBRATED;
  588. }
  589. data->chain_noise_a = 0;
  590. data->chain_noise_b = 0;
  591. data->chain_noise_c = 0;
  592. data->chain_signal_a = 0;
  593. data->chain_signal_b = 0;
  594. data->chain_signal_c = 0;
  595. data->beacon_count = 0;
  596. }
  597. static void iwl4965_bg_txpower_work(struct work_struct *work)
  598. {
  599. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  600. txpower_work);
  601. /* If a scan happened to start before we got here
  602. * then just return; the statistics notification will
  603. * kick off another scheduled work to compensate for
  604. * any temperature delta we missed here. */
  605. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  606. test_bit(STATUS_SCANNING, &priv->status))
  607. return;
  608. mutex_lock(&priv->mutex);
  609. /* Regardless of if we are assocaited, we must reconfigure the
  610. * TX power since frames can be sent on non-radar channels while
  611. * not associated */
  612. iwl4965_send_tx_power(priv);
  613. /* Update last_temperature to keep is_calib_needed from running
  614. * when it isn't needed... */
  615. priv->last_temperature = priv->temperature;
  616. mutex_unlock(&priv->mutex);
  617. }
  618. /*
  619. * Acquire priv->lock before calling this function !
  620. */
  621. static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
  622. {
  623. iwl_write_direct32(priv, HBUS_TARG_WRPTR,
  624. (index & 0xff) | (txq_id << 8));
  625. iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
  626. }
  627. /**
  628. * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
  629. * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
  630. * @scd_retry: (1) Indicates queue will be used in aggregation mode
  631. *
  632. * NOTE: Acquire priv->lock before calling this function !
  633. */
  634. static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
  635. struct iwl_tx_queue *txq,
  636. int tx_fifo_id, int scd_retry)
  637. {
  638. int txq_id = txq->q.id;
  639. /* Find out whether to activate Tx queue */
  640. int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
  641. /* Set up and activate */
  642. iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
  643. (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
  644. (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
  645. (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
  646. (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
  647. IWL49_SCD_QUEUE_STTS_REG_MSK);
  648. txq->sched_retry = scd_retry;
  649. IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
  650. active ? "Activate" : "Deactivate",
  651. scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
  652. }
  653. static const u16 default_queue_to_tx_fifo[] = {
  654. IWL_TX_FIFO_AC3,
  655. IWL_TX_FIFO_AC2,
  656. IWL_TX_FIFO_AC1,
  657. IWL_TX_FIFO_AC0,
  658. IWL49_CMD_FIFO_NUM,
  659. IWL_TX_FIFO_HCCA_1,
  660. IWL_TX_FIFO_HCCA_2
  661. };
  662. int iwl4965_alive_notify(struct iwl_priv *priv)
  663. {
  664. u32 a;
  665. int i = 0;
  666. unsigned long flags;
  667. int ret;
  668. spin_lock_irqsave(&priv->lock, flags);
  669. ret = iwl_grab_nic_access(priv);
  670. if (ret) {
  671. spin_unlock_irqrestore(&priv->lock, flags);
  672. return ret;
  673. }
  674. /* Clear 4965's internal Tx Scheduler data base */
  675. priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
  676. a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
  677. for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
  678. iwl_write_targ_mem(priv, a, 0);
  679. for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
  680. iwl_write_targ_mem(priv, a, 0);
  681. for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
  682. iwl_write_targ_mem(priv, a, 0);
  683. /* Tel 4965 where to find Tx byte count tables */
  684. iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
  685. (priv->shared_phys +
  686. offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
  687. /* Disable chain mode for all queues */
  688. iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
  689. /* Initialize each Tx queue (including the command queue) */
  690. for (i = 0; i < priv->hw_params.max_txq_num; i++) {
  691. /* TFD circular buffer read/write indexes */
  692. iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
  693. iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
  694. /* Max Tx Window size for Scheduler-ACK mode */
  695. iwl_write_targ_mem(priv, priv->scd_base_addr +
  696. IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
  697. (SCD_WIN_SIZE <<
  698. IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  699. IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  700. /* Frame limit */
  701. iwl_write_targ_mem(priv, priv->scd_base_addr +
  702. IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
  703. sizeof(u32),
  704. (SCD_FRAME_LIMIT <<
  705. IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
  706. IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  707. }
  708. iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
  709. (1 << priv->hw_params.max_txq_num) - 1);
  710. /* Activate all Tx DMA/FIFO channels */
  711. priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
  712. iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
  713. /* Map each Tx/cmd queue to its corresponding fifo */
  714. for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
  715. int ac = default_queue_to_tx_fifo[i];
  716. iwl_txq_ctx_activate(priv, i);
  717. iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
  718. }
  719. iwl_release_nic_access(priv);
  720. spin_unlock_irqrestore(&priv->lock, flags);
  721. return ret;
  722. }
  723. static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
  724. .min_nrg_cck = 97,
  725. .max_nrg_cck = 0,
  726. .auto_corr_min_ofdm = 85,
  727. .auto_corr_min_ofdm_mrc = 170,
  728. .auto_corr_min_ofdm_x1 = 105,
  729. .auto_corr_min_ofdm_mrc_x1 = 220,
  730. .auto_corr_max_ofdm = 120,
  731. .auto_corr_max_ofdm_mrc = 210,
  732. .auto_corr_max_ofdm_x1 = 140,
  733. .auto_corr_max_ofdm_mrc_x1 = 270,
  734. .auto_corr_min_cck = 125,
  735. .auto_corr_max_cck = 200,
  736. .auto_corr_min_cck_mrc = 200,
  737. .auto_corr_max_cck_mrc = 400,
  738. .nrg_th_cck = 100,
  739. .nrg_th_ofdm = 100,
  740. };
  741. /**
  742. * iwl4965_hw_set_hw_params
  743. *
  744. * Called when initializing driver
  745. */
  746. int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
  747. {
  748. if ((priv->cfg->mod_params->num_of_queues > IWL49_NUM_QUEUES) ||
  749. (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
  750. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  751. IWL_MIN_NUM_QUEUES, IWL49_NUM_QUEUES);
  752. return -EINVAL;
  753. }
  754. priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
  755. priv->hw_params.first_ampdu_q = IWL49_FIRST_AMPDU_QUEUE;
  756. priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
  757. priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
  758. priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
  759. if (priv->cfg->mod_params->amsdu_size_8K)
  760. priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
  761. else
  762. priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
  763. priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
  764. priv->hw_params.max_stations = IWL4965_STATION_COUNT;
  765. priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
  766. priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
  767. priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
  768. priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
  769. priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
  770. priv->hw_params.tx_chains_num = 2;
  771. priv->hw_params.rx_chains_num = 2;
  772. priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
  773. priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
  774. priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
  775. priv->hw_params.sens = &iwl4965_sensitivity;
  776. return 0;
  777. }
  778. /* set card power command */
  779. static int iwl4965_set_power(struct iwl_priv *priv,
  780. void *cmd)
  781. {
  782. int ret = 0;
  783. ret = iwl_send_cmd_pdu_async(priv, POWER_TABLE_CMD,
  784. sizeof(struct iwl4965_powertable_cmd),
  785. cmd, NULL);
  786. return ret;
  787. }
  788. static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
  789. {
  790. s32 sign = 1;
  791. if (num < 0) {
  792. sign = -sign;
  793. num = -num;
  794. }
  795. if (denom < 0) {
  796. sign = -sign;
  797. denom = -denom;
  798. }
  799. *res = 1;
  800. *res = ((num * 2 + denom) / (denom * 2)) * sign;
  801. return 1;
  802. }
  803. /**
  804. * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
  805. *
  806. * Determines power supply voltage compensation for txpower calculations.
  807. * Returns number of 1/2-dB steps to subtract from gain table index,
  808. * to compensate for difference between power supply voltage during
  809. * factory measurements, vs. current power supply voltage.
  810. *
  811. * Voltage indication is higher for lower voltage.
  812. * Lower voltage requires more gain (lower gain table index).
  813. */
  814. static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
  815. s32 current_voltage)
  816. {
  817. s32 comp = 0;
  818. if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
  819. (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
  820. return 0;
  821. iwl4965_math_div_round(current_voltage - eeprom_voltage,
  822. TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
  823. if (current_voltage > eeprom_voltage)
  824. comp *= 2;
  825. if ((comp < -2) || (comp > 2))
  826. comp = 0;
  827. return comp;
  828. }
  829. static s32 iwl4965_get_tx_atten_grp(u16 channel)
  830. {
  831. if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
  832. channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
  833. return CALIB_CH_GROUP_5;
  834. if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
  835. channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
  836. return CALIB_CH_GROUP_1;
  837. if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
  838. channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
  839. return CALIB_CH_GROUP_2;
  840. if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
  841. channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
  842. return CALIB_CH_GROUP_3;
  843. if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
  844. channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
  845. return CALIB_CH_GROUP_4;
  846. IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
  847. return -1;
  848. }
  849. static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
  850. {
  851. s32 b = -1;
  852. for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
  853. if (priv->calib_info->band_info[b].ch_from == 0)
  854. continue;
  855. if ((channel >= priv->calib_info->band_info[b].ch_from)
  856. && (channel <= priv->calib_info->band_info[b].ch_to))
  857. break;
  858. }
  859. return b;
  860. }
  861. static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
  862. {
  863. s32 val;
  864. if (x2 == x1)
  865. return y1;
  866. else {
  867. iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
  868. return val + y2;
  869. }
  870. }
  871. /**
  872. * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
  873. *
  874. * Interpolates factory measurements from the two sample channels within a
  875. * sub-band, to apply to channel of interest. Interpolation is proportional to
  876. * differences in channel frequencies, which is proportional to differences
  877. * in channel number.
  878. */
  879. static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
  880. struct iwl_eeprom_calib_ch_info *chan_info)
  881. {
  882. s32 s = -1;
  883. u32 c;
  884. u32 m;
  885. const struct iwl_eeprom_calib_measure *m1;
  886. const struct iwl_eeprom_calib_measure *m2;
  887. struct iwl_eeprom_calib_measure *omeas;
  888. u32 ch_i1;
  889. u32 ch_i2;
  890. s = iwl4965_get_sub_band(priv, channel);
  891. if (s >= EEPROM_TX_POWER_BANDS) {
  892. IWL_ERROR("Tx Power can not find channel %d ", channel);
  893. return -1;
  894. }
  895. ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
  896. ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
  897. chan_info->ch_num = (u8) channel;
  898. IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
  899. channel, s, ch_i1, ch_i2);
  900. for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
  901. for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
  902. m1 = &(priv->calib_info->band_info[s].ch1.
  903. measurements[c][m]);
  904. m2 = &(priv->calib_info->band_info[s].ch2.
  905. measurements[c][m]);
  906. omeas = &(chan_info->measurements[c][m]);
  907. omeas->actual_pow =
  908. (u8) iwl4965_interpolate_value(channel, ch_i1,
  909. m1->actual_pow,
  910. ch_i2,
  911. m2->actual_pow);
  912. omeas->gain_idx =
  913. (u8) iwl4965_interpolate_value(channel, ch_i1,
  914. m1->gain_idx, ch_i2,
  915. m2->gain_idx);
  916. omeas->temperature =
  917. (u8) iwl4965_interpolate_value(channel, ch_i1,
  918. m1->temperature,
  919. ch_i2,
  920. m2->temperature);
  921. omeas->pa_det =
  922. (s8) iwl4965_interpolate_value(channel, ch_i1,
  923. m1->pa_det, ch_i2,
  924. m2->pa_det);
  925. IWL_DEBUG_TXPOWER
  926. ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
  927. m1->actual_pow, m2->actual_pow, omeas->actual_pow);
  928. IWL_DEBUG_TXPOWER
  929. ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
  930. m1->gain_idx, m2->gain_idx, omeas->gain_idx);
  931. IWL_DEBUG_TXPOWER
  932. ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
  933. m1->pa_det, m2->pa_det, omeas->pa_det);
  934. IWL_DEBUG_TXPOWER
  935. ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
  936. m1->temperature, m2->temperature,
  937. omeas->temperature);
  938. }
  939. }
  940. return 0;
  941. }
  942. /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
  943. * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
  944. static s32 back_off_table[] = {
  945. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
  946. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
  947. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
  948. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
  949. 10 /* CCK */
  950. };
  951. /* Thermal compensation values for txpower for various frequency ranges ...
  952. * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
  953. static struct iwl4965_txpower_comp_entry {
  954. s32 degrees_per_05db_a;
  955. s32 degrees_per_05db_a_denom;
  956. } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
  957. {9, 2}, /* group 0 5.2, ch 34-43 */
  958. {4, 1}, /* group 1 5.2, ch 44-70 */
  959. {4, 1}, /* group 2 5.2, ch 71-124 */
  960. {4, 1}, /* group 3 5.2, ch 125-200 */
  961. {3, 1} /* group 4 2.4, ch all */
  962. };
  963. static s32 get_min_power_index(s32 rate_power_index, u32 band)
  964. {
  965. if (!band) {
  966. if ((rate_power_index & 7) <= 4)
  967. return MIN_TX_GAIN_INDEX_52GHZ_EXT;
  968. }
  969. return MIN_TX_GAIN_INDEX;
  970. }
  971. struct gain_entry {
  972. u8 dsp;
  973. u8 radio;
  974. };
  975. static const struct gain_entry gain_table[2][108] = {
  976. /* 5.2GHz power gain index table */
  977. {
  978. {123, 0x3F}, /* highest txpower */
  979. {117, 0x3F},
  980. {110, 0x3F},
  981. {104, 0x3F},
  982. {98, 0x3F},
  983. {110, 0x3E},
  984. {104, 0x3E},
  985. {98, 0x3E},
  986. {110, 0x3D},
  987. {104, 0x3D},
  988. {98, 0x3D},
  989. {110, 0x3C},
  990. {104, 0x3C},
  991. {98, 0x3C},
  992. {110, 0x3B},
  993. {104, 0x3B},
  994. {98, 0x3B},
  995. {110, 0x3A},
  996. {104, 0x3A},
  997. {98, 0x3A},
  998. {110, 0x39},
  999. {104, 0x39},
  1000. {98, 0x39},
  1001. {110, 0x38},
  1002. {104, 0x38},
  1003. {98, 0x38},
  1004. {110, 0x37},
  1005. {104, 0x37},
  1006. {98, 0x37},
  1007. {110, 0x36},
  1008. {104, 0x36},
  1009. {98, 0x36},
  1010. {110, 0x35},
  1011. {104, 0x35},
  1012. {98, 0x35},
  1013. {110, 0x34},
  1014. {104, 0x34},
  1015. {98, 0x34},
  1016. {110, 0x33},
  1017. {104, 0x33},
  1018. {98, 0x33},
  1019. {110, 0x32},
  1020. {104, 0x32},
  1021. {98, 0x32},
  1022. {110, 0x31},
  1023. {104, 0x31},
  1024. {98, 0x31},
  1025. {110, 0x30},
  1026. {104, 0x30},
  1027. {98, 0x30},
  1028. {110, 0x25},
  1029. {104, 0x25},
  1030. {98, 0x25},
  1031. {110, 0x24},
  1032. {104, 0x24},
  1033. {98, 0x24},
  1034. {110, 0x23},
  1035. {104, 0x23},
  1036. {98, 0x23},
  1037. {110, 0x22},
  1038. {104, 0x18},
  1039. {98, 0x18},
  1040. {110, 0x17},
  1041. {104, 0x17},
  1042. {98, 0x17},
  1043. {110, 0x16},
  1044. {104, 0x16},
  1045. {98, 0x16},
  1046. {110, 0x15},
  1047. {104, 0x15},
  1048. {98, 0x15},
  1049. {110, 0x14},
  1050. {104, 0x14},
  1051. {98, 0x14},
  1052. {110, 0x13},
  1053. {104, 0x13},
  1054. {98, 0x13},
  1055. {110, 0x12},
  1056. {104, 0x08},
  1057. {98, 0x08},
  1058. {110, 0x07},
  1059. {104, 0x07},
  1060. {98, 0x07},
  1061. {110, 0x06},
  1062. {104, 0x06},
  1063. {98, 0x06},
  1064. {110, 0x05},
  1065. {104, 0x05},
  1066. {98, 0x05},
  1067. {110, 0x04},
  1068. {104, 0x04},
  1069. {98, 0x04},
  1070. {110, 0x03},
  1071. {104, 0x03},
  1072. {98, 0x03},
  1073. {110, 0x02},
  1074. {104, 0x02},
  1075. {98, 0x02},
  1076. {110, 0x01},
  1077. {104, 0x01},
  1078. {98, 0x01},
  1079. {110, 0x00},
  1080. {104, 0x00},
  1081. {98, 0x00},
  1082. {93, 0x00},
  1083. {88, 0x00},
  1084. {83, 0x00},
  1085. {78, 0x00},
  1086. },
  1087. /* 2.4GHz power gain index table */
  1088. {
  1089. {110, 0x3f}, /* highest txpower */
  1090. {104, 0x3f},
  1091. {98, 0x3f},
  1092. {110, 0x3e},
  1093. {104, 0x3e},
  1094. {98, 0x3e},
  1095. {110, 0x3d},
  1096. {104, 0x3d},
  1097. {98, 0x3d},
  1098. {110, 0x3c},
  1099. {104, 0x3c},
  1100. {98, 0x3c},
  1101. {110, 0x3b},
  1102. {104, 0x3b},
  1103. {98, 0x3b},
  1104. {110, 0x3a},
  1105. {104, 0x3a},
  1106. {98, 0x3a},
  1107. {110, 0x39},
  1108. {104, 0x39},
  1109. {98, 0x39},
  1110. {110, 0x38},
  1111. {104, 0x38},
  1112. {98, 0x38},
  1113. {110, 0x37},
  1114. {104, 0x37},
  1115. {98, 0x37},
  1116. {110, 0x36},
  1117. {104, 0x36},
  1118. {98, 0x36},
  1119. {110, 0x35},
  1120. {104, 0x35},
  1121. {98, 0x35},
  1122. {110, 0x34},
  1123. {104, 0x34},
  1124. {98, 0x34},
  1125. {110, 0x33},
  1126. {104, 0x33},
  1127. {98, 0x33},
  1128. {110, 0x32},
  1129. {104, 0x32},
  1130. {98, 0x32},
  1131. {110, 0x31},
  1132. {104, 0x31},
  1133. {98, 0x31},
  1134. {110, 0x30},
  1135. {104, 0x30},
  1136. {98, 0x30},
  1137. {110, 0x6},
  1138. {104, 0x6},
  1139. {98, 0x6},
  1140. {110, 0x5},
  1141. {104, 0x5},
  1142. {98, 0x5},
  1143. {110, 0x4},
  1144. {104, 0x4},
  1145. {98, 0x4},
  1146. {110, 0x3},
  1147. {104, 0x3},
  1148. {98, 0x3},
  1149. {110, 0x2},
  1150. {104, 0x2},
  1151. {98, 0x2},
  1152. {110, 0x1},
  1153. {104, 0x1},
  1154. {98, 0x1},
  1155. {110, 0x0},
  1156. {104, 0x0},
  1157. {98, 0x0},
  1158. {97, 0},
  1159. {96, 0},
  1160. {95, 0},
  1161. {94, 0},
  1162. {93, 0},
  1163. {92, 0},
  1164. {91, 0},
  1165. {90, 0},
  1166. {89, 0},
  1167. {88, 0},
  1168. {87, 0},
  1169. {86, 0},
  1170. {85, 0},
  1171. {84, 0},
  1172. {83, 0},
  1173. {82, 0},
  1174. {81, 0},
  1175. {80, 0},
  1176. {79, 0},
  1177. {78, 0},
  1178. {77, 0},
  1179. {76, 0},
  1180. {75, 0},
  1181. {74, 0},
  1182. {73, 0},
  1183. {72, 0},
  1184. {71, 0},
  1185. {70, 0},
  1186. {69, 0},
  1187. {68, 0},
  1188. {67, 0},
  1189. {66, 0},
  1190. {65, 0},
  1191. {64, 0},
  1192. {63, 0},
  1193. {62, 0},
  1194. {61, 0},
  1195. {60, 0},
  1196. {59, 0},
  1197. }
  1198. };
  1199. static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
  1200. u8 is_fat, u8 ctrl_chan_high,
  1201. struct iwl4965_tx_power_db *tx_power_tbl)
  1202. {
  1203. u8 saturation_power;
  1204. s32 target_power;
  1205. s32 user_target_power;
  1206. s32 power_limit;
  1207. s32 current_temp;
  1208. s32 reg_limit;
  1209. s32 current_regulatory;
  1210. s32 txatten_grp = CALIB_CH_GROUP_MAX;
  1211. int i;
  1212. int c;
  1213. const struct iwl_channel_info *ch_info = NULL;
  1214. struct iwl_eeprom_calib_ch_info ch_eeprom_info;
  1215. const struct iwl_eeprom_calib_measure *measurement;
  1216. s16 voltage;
  1217. s32 init_voltage;
  1218. s32 voltage_compensation;
  1219. s32 degrees_per_05db_num;
  1220. s32 degrees_per_05db_denom;
  1221. s32 factory_temp;
  1222. s32 temperature_comp[2];
  1223. s32 factory_gain_index[2];
  1224. s32 factory_actual_pwr[2];
  1225. s32 power_index;
  1226. /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
  1227. * are used for indexing into txpower table) */
  1228. user_target_power = 2 * priv->tx_power_user_lmt;
  1229. /* Get current (RXON) channel, band, width */
  1230. IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
  1231. is_fat);
  1232. ch_info = iwl_get_channel_info(priv, priv->band, channel);
  1233. if (!is_channel_valid(ch_info))
  1234. return -EINVAL;
  1235. /* get txatten group, used to select 1) thermal txpower adjustment
  1236. * and 2) mimo txpower balance between Tx chains. */
  1237. txatten_grp = iwl4965_get_tx_atten_grp(channel);
  1238. if (txatten_grp < 0)
  1239. return -EINVAL;
  1240. IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
  1241. channel, txatten_grp);
  1242. if (is_fat) {
  1243. if (ctrl_chan_high)
  1244. channel -= 2;
  1245. else
  1246. channel += 2;
  1247. }
  1248. /* hardware txpower limits ...
  1249. * saturation (clipping distortion) txpowers are in half-dBm */
  1250. if (band)
  1251. saturation_power = priv->calib_info->saturation_power24;
  1252. else
  1253. saturation_power = priv->calib_info->saturation_power52;
  1254. if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
  1255. saturation_power > IWL_TX_POWER_SATURATION_MAX) {
  1256. if (band)
  1257. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
  1258. else
  1259. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
  1260. }
  1261. /* regulatory txpower limits ... reg_limit values are in half-dBm,
  1262. * max_power_avg values are in dBm, convert * 2 */
  1263. if (is_fat)
  1264. reg_limit = ch_info->fat_max_power_avg * 2;
  1265. else
  1266. reg_limit = ch_info->max_power_avg * 2;
  1267. if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
  1268. (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
  1269. if (band)
  1270. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
  1271. else
  1272. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
  1273. }
  1274. /* Interpolate txpower calibration values for this channel,
  1275. * based on factory calibration tests on spaced channels. */
  1276. iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
  1277. /* calculate tx gain adjustment based on power supply voltage */
  1278. voltage = priv->calib_info->voltage;
  1279. init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
  1280. voltage_compensation =
  1281. iwl4965_get_voltage_compensation(voltage, init_voltage);
  1282. IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
  1283. init_voltage,
  1284. voltage, voltage_compensation);
  1285. /* get current temperature (Celsius) */
  1286. current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
  1287. current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
  1288. current_temp = KELVIN_TO_CELSIUS(current_temp);
  1289. /* select thermal txpower adjustment params, based on channel group
  1290. * (same frequency group used for mimo txatten adjustment) */
  1291. degrees_per_05db_num =
  1292. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
  1293. degrees_per_05db_denom =
  1294. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
  1295. /* get per-chain txpower values from factory measurements */
  1296. for (c = 0; c < 2; c++) {
  1297. measurement = &ch_eeprom_info.measurements[c][1];
  1298. /* txgain adjustment (in half-dB steps) based on difference
  1299. * between factory and current temperature */
  1300. factory_temp = measurement->temperature;
  1301. iwl4965_math_div_round((current_temp - factory_temp) *
  1302. degrees_per_05db_denom,
  1303. degrees_per_05db_num,
  1304. &temperature_comp[c]);
  1305. factory_gain_index[c] = measurement->gain_idx;
  1306. factory_actual_pwr[c] = measurement->actual_pow;
  1307. IWL_DEBUG_TXPOWER("chain = %d\n", c);
  1308. IWL_DEBUG_TXPOWER("fctry tmp %d, "
  1309. "curr tmp %d, comp %d steps\n",
  1310. factory_temp, current_temp,
  1311. temperature_comp[c]);
  1312. IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
  1313. factory_gain_index[c],
  1314. factory_actual_pwr[c]);
  1315. }
  1316. /* for each of 33 bit-rates (including 1 for CCK) */
  1317. for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
  1318. u8 is_mimo_rate;
  1319. union iwl4965_tx_power_dual_stream tx_power;
  1320. /* for mimo, reduce each chain's txpower by half
  1321. * (3dB, 6 steps), so total output power is regulatory
  1322. * compliant. */
  1323. if (i & 0x8) {
  1324. current_regulatory = reg_limit -
  1325. IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
  1326. is_mimo_rate = 1;
  1327. } else {
  1328. current_regulatory = reg_limit;
  1329. is_mimo_rate = 0;
  1330. }
  1331. /* find txpower limit, either hardware or regulatory */
  1332. power_limit = saturation_power - back_off_table[i];
  1333. if (power_limit > current_regulatory)
  1334. power_limit = current_regulatory;
  1335. /* reduce user's txpower request if necessary
  1336. * for this rate on this channel */
  1337. target_power = user_target_power;
  1338. if (target_power > power_limit)
  1339. target_power = power_limit;
  1340. IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
  1341. i, saturation_power - back_off_table[i],
  1342. current_regulatory, user_target_power,
  1343. target_power);
  1344. /* for each of 2 Tx chains (radio transmitters) */
  1345. for (c = 0; c < 2; c++) {
  1346. s32 atten_value;
  1347. if (is_mimo_rate)
  1348. atten_value =
  1349. (s32)le32_to_cpu(priv->card_alive_init.
  1350. tx_atten[txatten_grp][c]);
  1351. else
  1352. atten_value = 0;
  1353. /* calculate index; higher index means lower txpower */
  1354. power_index = (u8) (factory_gain_index[c] -
  1355. (target_power -
  1356. factory_actual_pwr[c]) -
  1357. temperature_comp[c] -
  1358. voltage_compensation +
  1359. atten_value);
  1360. /* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
  1361. power_index); */
  1362. if (power_index < get_min_power_index(i, band))
  1363. power_index = get_min_power_index(i, band);
  1364. /* adjust 5 GHz index to support negative indexes */
  1365. if (!band)
  1366. power_index += 9;
  1367. /* CCK, rate 32, reduce txpower for CCK */
  1368. if (i == POWER_TABLE_CCK_ENTRY)
  1369. power_index +=
  1370. IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
  1371. /* stay within the table! */
  1372. if (power_index > 107) {
  1373. IWL_WARNING("txpower index %d > 107\n",
  1374. power_index);
  1375. power_index = 107;
  1376. }
  1377. if (power_index < 0) {
  1378. IWL_WARNING("txpower index %d < 0\n",
  1379. power_index);
  1380. power_index = 0;
  1381. }
  1382. /* fill txpower command for this rate/chain */
  1383. tx_power.s.radio_tx_gain[c] =
  1384. gain_table[band][power_index].radio;
  1385. tx_power.s.dsp_predis_atten[c] =
  1386. gain_table[band][power_index].dsp;
  1387. IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
  1388. "gain 0x%02x dsp %d\n",
  1389. c, atten_value, power_index,
  1390. tx_power.s.radio_tx_gain[c],
  1391. tx_power.s.dsp_predis_atten[c]);
  1392. }/* for each chain */
  1393. tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
  1394. }/* for each rate */
  1395. return 0;
  1396. }
  1397. /**
  1398. * iwl4965_send_tx_power - Configure the TXPOWER level user limit
  1399. *
  1400. * Uses the active RXON for channel, band, and characteristics (fat, high)
  1401. * The power limit is taken from priv->tx_power_user_lmt.
  1402. */
  1403. static int iwl4965_send_tx_power(struct iwl_priv *priv)
  1404. {
  1405. struct iwl4965_txpowertable_cmd cmd = { 0 };
  1406. int ret;
  1407. u8 band = 0;
  1408. u8 is_fat = 0;
  1409. u8 ctrl_chan_high = 0;
  1410. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1411. /* If this gets hit a lot, switch it to a BUG() and catch
  1412. * the stack trace to find out who is calling this during
  1413. * a scan. */
  1414. IWL_WARNING("TX Power requested while scanning!\n");
  1415. return -EAGAIN;
  1416. }
  1417. band = priv->band == IEEE80211_BAND_2GHZ;
  1418. is_fat = is_fat_channel(priv->active_rxon.flags);
  1419. if (is_fat &&
  1420. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  1421. ctrl_chan_high = 1;
  1422. cmd.band = band;
  1423. cmd.channel = priv->active_rxon.channel;
  1424. ret = iwl4965_fill_txpower_tbl(priv, band,
  1425. le16_to_cpu(priv->active_rxon.channel),
  1426. is_fat, ctrl_chan_high, &cmd.tx_power);
  1427. if (ret)
  1428. goto out;
  1429. ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
  1430. out:
  1431. return ret;
  1432. }
  1433. static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
  1434. {
  1435. int ret = 0;
  1436. struct iwl4965_rxon_assoc_cmd rxon_assoc;
  1437. const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
  1438. const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
  1439. if ((rxon1->flags == rxon2->flags) &&
  1440. (rxon1->filter_flags == rxon2->filter_flags) &&
  1441. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  1442. (rxon1->ofdm_ht_single_stream_basic_rates ==
  1443. rxon2->ofdm_ht_single_stream_basic_rates) &&
  1444. (rxon1->ofdm_ht_dual_stream_basic_rates ==
  1445. rxon2->ofdm_ht_dual_stream_basic_rates) &&
  1446. (rxon1->rx_chain == rxon2->rx_chain) &&
  1447. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  1448. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  1449. return 0;
  1450. }
  1451. rxon_assoc.flags = priv->staging_rxon.flags;
  1452. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  1453. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  1454. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  1455. rxon_assoc.reserved = 0;
  1456. rxon_assoc.ofdm_ht_single_stream_basic_rates =
  1457. priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
  1458. rxon_assoc.ofdm_ht_dual_stream_basic_rates =
  1459. priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
  1460. rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
  1461. ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
  1462. sizeof(rxon_assoc), &rxon_assoc, NULL);
  1463. if (ret)
  1464. return ret;
  1465. return ret;
  1466. }
  1467. int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
  1468. {
  1469. int rc;
  1470. u8 band = 0;
  1471. u8 is_fat = 0;
  1472. u8 ctrl_chan_high = 0;
  1473. struct iwl4965_channel_switch_cmd cmd = { 0 };
  1474. const struct iwl_channel_info *ch_info;
  1475. band = priv->band == IEEE80211_BAND_2GHZ;
  1476. ch_info = iwl_get_channel_info(priv, priv->band, channel);
  1477. is_fat = is_fat_channel(priv->staging_rxon.flags);
  1478. if (is_fat &&
  1479. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  1480. ctrl_chan_high = 1;
  1481. cmd.band = band;
  1482. cmd.expect_beacon = 0;
  1483. cmd.channel = cpu_to_le16(channel);
  1484. cmd.rxon_flags = priv->active_rxon.flags;
  1485. cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
  1486. cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
  1487. if (ch_info)
  1488. cmd.expect_beacon = is_channel_radar(ch_info);
  1489. else
  1490. cmd.expect_beacon = 1;
  1491. rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
  1492. ctrl_chan_high, &cmd.tx_power);
  1493. if (rc) {
  1494. IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
  1495. return rc;
  1496. }
  1497. rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
  1498. return rc;
  1499. }
  1500. static int iwl4965_shared_mem_rx_idx(struct iwl_priv *priv)
  1501. {
  1502. struct iwl4965_shared *s = priv->shared_virt;
  1503. return le32_to_cpu(s->rb_closed) & 0xFFF;
  1504. }
  1505. int iwl4965_hw_get_temperature(struct iwl_priv *priv)
  1506. {
  1507. return priv->temperature;
  1508. }
  1509. unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
  1510. struct iwl_frame *frame, u8 rate)
  1511. {
  1512. struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
  1513. unsigned int frame_size;
  1514. tx_beacon_cmd = &frame->u.beacon;
  1515. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  1516. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  1517. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  1518. frame_size = iwl4965_fill_beacon_frame(priv,
  1519. tx_beacon_cmd->frame,
  1520. iwl_bcast_addr,
  1521. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  1522. BUG_ON(frame_size > MAX_MPDU_SIZE);
  1523. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  1524. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  1525. tx_beacon_cmd->tx.rate_n_flags =
  1526. iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  1527. else
  1528. tx_beacon_cmd->tx.rate_n_flags =
  1529. iwl4965_hw_set_rate_n_flags(rate, 0);
  1530. tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
  1531. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
  1532. return (sizeof(*tx_beacon_cmd) + frame_size);
  1533. }
  1534. static int iwl4965_alloc_shared_mem(struct iwl_priv *priv)
  1535. {
  1536. priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
  1537. sizeof(struct iwl4965_shared),
  1538. &priv->shared_phys);
  1539. if (!priv->shared_virt)
  1540. return -ENOMEM;
  1541. memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
  1542. priv->rb_closed_offset = offsetof(struct iwl4965_shared, rb_closed);
  1543. return 0;
  1544. }
  1545. static void iwl4965_free_shared_mem(struct iwl_priv *priv)
  1546. {
  1547. if (priv->shared_virt)
  1548. pci_free_consistent(priv->pci_dev,
  1549. sizeof(struct iwl4965_shared),
  1550. priv->shared_virt,
  1551. priv->shared_phys);
  1552. }
  1553. /**
  1554. * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
  1555. */
  1556. static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
  1557. struct iwl_tx_queue *txq,
  1558. u16 byte_cnt)
  1559. {
  1560. int len;
  1561. int txq_id = txq->q.id;
  1562. struct iwl4965_shared *shared_data = priv->shared_virt;
  1563. len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
  1564. /* Set up byte count within first 256 entries */
  1565. IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
  1566. tfd_offset[txq->q.write_ptr], byte_cnt, len);
  1567. /* If within first 64 entries, duplicate at end */
  1568. if (txq->q.write_ptr < IWL49_MAX_WIN_SIZE)
  1569. IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
  1570. tfd_offset[IWL49_QUEUE_SIZE + txq->q.write_ptr],
  1571. byte_cnt, len);
  1572. }
  1573. /**
  1574. * sign_extend - Sign extend a value using specified bit as sign-bit
  1575. *
  1576. * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
  1577. * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
  1578. *
  1579. * @param oper value to sign extend
  1580. * @param index 0 based bit index (0<=index<32) to sign bit
  1581. */
  1582. static s32 sign_extend(u32 oper, int index)
  1583. {
  1584. u8 shift = 31 - index;
  1585. return (s32)(oper << shift) >> shift;
  1586. }
  1587. /**
  1588. * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
  1589. * @statistics: Provides the temperature reading from the uCode
  1590. *
  1591. * A return of <0 indicates bogus data in the statistics
  1592. */
  1593. int iwl4965_get_temperature(const struct iwl_priv *priv)
  1594. {
  1595. s32 temperature;
  1596. s32 vt;
  1597. s32 R1, R2, R3;
  1598. u32 R4;
  1599. if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
  1600. (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
  1601. IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
  1602. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
  1603. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
  1604. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
  1605. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
  1606. } else {
  1607. IWL_DEBUG_TEMP("Running temperature calibration\n");
  1608. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
  1609. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
  1610. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
  1611. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
  1612. }
  1613. /*
  1614. * Temperature is only 23 bits, so sign extend out to 32.
  1615. *
  1616. * NOTE If we haven't received a statistics notification yet
  1617. * with an updated temperature, use R4 provided to us in the
  1618. * "initialize" ALIVE response.
  1619. */
  1620. if (!test_bit(STATUS_TEMPERATURE, &priv->status))
  1621. vt = sign_extend(R4, 23);
  1622. else
  1623. vt = sign_extend(
  1624. le32_to_cpu(priv->statistics.general.temperature), 23);
  1625. IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
  1626. R1, R2, R3, vt);
  1627. if (R3 == R1) {
  1628. IWL_ERROR("Calibration conflict R1 == R3\n");
  1629. return -1;
  1630. }
  1631. /* Calculate temperature in degrees Kelvin, adjust by 97%.
  1632. * Add offset to center the adjustment around 0 degrees Centigrade. */
  1633. temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
  1634. temperature /= (R3 - R1);
  1635. temperature = (temperature * 97) / 100 +
  1636. TEMPERATURE_CALIB_KELVIN_OFFSET;
  1637. IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
  1638. KELVIN_TO_CELSIUS(temperature));
  1639. return temperature;
  1640. }
  1641. /* Adjust Txpower only if temperature variance is greater than threshold. */
  1642. #define IWL_TEMPERATURE_THRESHOLD 3
  1643. /**
  1644. * iwl4965_is_temp_calib_needed - determines if new calibration is needed
  1645. *
  1646. * If the temperature changed has changed sufficiently, then a recalibration
  1647. * is needed.
  1648. *
  1649. * Assumes caller will replace priv->last_temperature once calibration
  1650. * executed.
  1651. */
  1652. static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
  1653. {
  1654. int temp_diff;
  1655. if (!test_bit(STATUS_STATISTICS, &priv->status)) {
  1656. IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
  1657. return 0;
  1658. }
  1659. temp_diff = priv->temperature - priv->last_temperature;
  1660. /* get absolute value */
  1661. if (temp_diff < 0) {
  1662. IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
  1663. temp_diff = -temp_diff;
  1664. } else if (temp_diff == 0)
  1665. IWL_DEBUG_POWER("Same temp, \n");
  1666. else
  1667. IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
  1668. if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
  1669. IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
  1670. return 0;
  1671. }
  1672. IWL_DEBUG_POWER("Thermal txpower calib needed\n");
  1673. return 1;
  1674. }
  1675. /* Calculate noise level, based on measurements during network silence just
  1676. * before arriving beacon. This measurement can be done only if we know
  1677. * exactly when to expect beacons, therefore only when we're associated. */
  1678. static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
  1679. {
  1680. struct statistics_rx_non_phy *rx_info
  1681. = &(priv->statistics.rx.general);
  1682. int num_active_rx = 0;
  1683. int total_silence = 0;
  1684. int bcn_silence_a =
  1685. le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
  1686. int bcn_silence_b =
  1687. le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
  1688. int bcn_silence_c =
  1689. le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
  1690. if (bcn_silence_a) {
  1691. total_silence += bcn_silence_a;
  1692. num_active_rx++;
  1693. }
  1694. if (bcn_silence_b) {
  1695. total_silence += bcn_silence_b;
  1696. num_active_rx++;
  1697. }
  1698. if (bcn_silence_c) {
  1699. total_silence += bcn_silence_c;
  1700. num_active_rx++;
  1701. }
  1702. /* Average among active antennas */
  1703. if (num_active_rx)
  1704. priv->last_rx_noise = (total_silence / num_active_rx) - 107;
  1705. else
  1706. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  1707. IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
  1708. bcn_silence_a, bcn_silence_b, bcn_silence_c,
  1709. priv->last_rx_noise);
  1710. }
  1711. void iwl4965_hw_rx_statistics(struct iwl_priv *priv,
  1712. struct iwl_rx_mem_buffer *rxb)
  1713. {
  1714. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1715. int change;
  1716. s32 temp;
  1717. IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
  1718. (int)sizeof(priv->statistics), pkt->len);
  1719. change = ((priv->statistics.general.temperature !=
  1720. pkt->u.stats.general.temperature) ||
  1721. ((priv->statistics.flag &
  1722. STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
  1723. (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
  1724. memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
  1725. set_bit(STATUS_STATISTICS, &priv->status);
  1726. /* Reschedule the statistics timer to occur in
  1727. * REG_RECALIB_PERIOD seconds to ensure we get a
  1728. * thermal update even if the uCode doesn't give
  1729. * us one */
  1730. mod_timer(&priv->statistics_periodic, jiffies +
  1731. msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
  1732. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  1733. (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
  1734. iwl4965_rx_calc_noise(priv);
  1735. queue_work(priv->workqueue, &priv->run_time_calib_work);
  1736. }
  1737. iwl_leds_background(priv);
  1738. /* If the hardware hasn't reported a change in
  1739. * temperature then don't bother computing a
  1740. * calibrated temperature value */
  1741. if (!change)
  1742. return;
  1743. temp = iwl4965_get_temperature(priv);
  1744. if (temp < 0)
  1745. return;
  1746. if (priv->temperature != temp) {
  1747. if (priv->temperature)
  1748. IWL_DEBUG_TEMP("Temperature changed "
  1749. "from %dC to %dC\n",
  1750. KELVIN_TO_CELSIUS(priv->temperature),
  1751. KELVIN_TO_CELSIUS(temp));
  1752. else
  1753. IWL_DEBUG_TEMP("Temperature "
  1754. "initialized to %dC\n",
  1755. KELVIN_TO_CELSIUS(temp));
  1756. }
  1757. priv->temperature = temp;
  1758. set_bit(STATUS_TEMPERATURE, &priv->status);
  1759. if (!priv->disable_tx_power_cal &&
  1760. unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  1761. iwl4965_is_temp_calib_needed(priv))
  1762. queue_work(priv->workqueue, &priv->txpower_work);
  1763. }
  1764. static void iwl4965_add_radiotap(struct iwl_priv *priv,
  1765. struct sk_buff *skb,
  1766. struct iwl4965_rx_phy_res *rx_start,
  1767. struct ieee80211_rx_status *stats,
  1768. u32 ampdu_status)
  1769. {
  1770. s8 signal = stats->signal;
  1771. s8 noise = 0;
  1772. int rate = stats->rate_idx;
  1773. u64 tsf = stats->mactime;
  1774. __le16 antenna;
  1775. __le16 phy_flags_hw = rx_start->phy_flags;
  1776. struct iwl4965_rt_rx_hdr {
  1777. struct ieee80211_radiotap_header rt_hdr;
  1778. __le64 rt_tsf; /* TSF */
  1779. u8 rt_flags; /* radiotap packet flags */
  1780. u8 rt_rate; /* rate in 500kb/s */
  1781. __le16 rt_channelMHz; /* channel in MHz */
  1782. __le16 rt_chbitmask; /* channel bitfield */
  1783. s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
  1784. s8 rt_dbmnoise;
  1785. u8 rt_antenna; /* antenna number */
  1786. } __attribute__ ((packed)) *iwl4965_rt;
  1787. /* TODO: We won't have enough headroom for HT frames. Fix it later. */
  1788. if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
  1789. if (net_ratelimit())
  1790. printk(KERN_ERR "not enough headroom [%d] for "
  1791. "radiotap head [%zd]\n",
  1792. skb_headroom(skb), sizeof(*iwl4965_rt));
  1793. return;
  1794. }
  1795. /* put radiotap header in front of 802.11 header and data */
  1796. iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
  1797. /* initialise radiotap header */
  1798. iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
  1799. iwl4965_rt->rt_hdr.it_pad = 0;
  1800. /* total header + data */
  1801. put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
  1802. &iwl4965_rt->rt_hdr.it_len);
  1803. /* Indicate all the fields we add to the radiotap header */
  1804. put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
  1805. (1 << IEEE80211_RADIOTAP_FLAGS) |
  1806. (1 << IEEE80211_RADIOTAP_RATE) |
  1807. (1 << IEEE80211_RADIOTAP_CHANNEL) |
  1808. (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
  1809. (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
  1810. (1 << IEEE80211_RADIOTAP_ANTENNA)),
  1811. &iwl4965_rt->rt_hdr.it_present);
  1812. /* Zero the flags, we'll add to them as we go */
  1813. iwl4965_rt->rt_flags = 0;
  1814. put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
  1815. iwl4965_rt->rt_dbmsignal = signal;
  1816. iwl4965_rt->rt_dbmnoise = noise;
  1817. /* Convert the channel frequency and set the flags */
  1818. put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
  1819. if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
  1820. put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
  1821. IEEE80211_CHAN_5GHZ),
  1822. &iwl4965_rt->rt_chbitmask);
  1823. else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
  1824. put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
  1825. IEEE80211_CHAN_2GHZ),
  1826. &iwl4965_rt->rt_chbitmask);
  1827. else /* 802.11g */
  1828. put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
  1829. IEEE80211_CHAN_2GHZ),
  1830. &iwl4965_rt->rt_chbitmask);
  1831. if (rate == -1)
  1832. iwl4965_rt->rt_rate = 0;
  1833. else
  1834. iwl4965_rt->rt_rate = iwl_rates[rate].ieee;
  1835. /*
  1836. * "antenna number"
  1837. *
  1838. * It seems that the antenna field in the phy flags value
  1839. * is actually a bitfield. This is undefined by radiotap,
  1840. * it wants an actual antenna number but I always get "7"
  1841. * for most legacy frames I receive indicating that the
  1842. * same frame was received on all three RX chains.
  1843. *
  1844. * I think this field should be removed in favour of a
  1845. * new 802.11n radiotap field "RX chains" that is defined
  1846. * as a bitmask.
  1847. */
  1848. antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
  1849. iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
  1850. /* set the preamble flag if appropriate */
  1851. if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  1852. iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
  1853. stats->flag |= RX_FLAG_RADIOTAP;
  1854. }
  1855. static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
  1856. {
  1857. /* 0 - mgmt, 1 - cnt, 2 - data */
  1858. int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
  1859. priv->rx_stats[idx].cnt++;
  1860. priv->rx_stats[idx].bytes += len;
  1861. }
  1862. /*
  1863. * returns non-zero if packet should be dropped
  1864. */
  1865. static int iwl4965_set_decrypted_flag(struct iwl_priv *priv,
  1866. struct ieee80211_hdr *hdr,
  1867. u32 decrypt_res,
  1868. struct ieee80211_rx_status *stats)
  1869. {
  1870. u16 fc = le16_to_cpu(hdr->frame_control);
  1871. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  1872. return 0;
  1873. if (!(fc & IEEE80211_FCTL_PROTECTED))
  1874. return 0;
  1875. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  1876. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  1877. case RX_RES_STATUS_SEC_TYPE_TKIP:
  1878. /* The uCode has got a bad phase 1 Key, pushes the packet.
  1879. * Decryption will be done in SW. */
  1880. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  1881. RX_RES_STATUS_BAD_KEY_TTAK)
  1882. break;
  1883. case RX_RES_STATUS_SEC_TYPE_WEP:
  1884. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  1885. RX_RES_STATUS_BAD_ICV_MIC) {
  1886. /* bad ICV, the packet is destroyed since the
  1887. * decryption is inplace, drop it */
  1888. IWL_DEBUG_RX("Packet destroyed\n");
  1889. return -1;
  1890. }
  1891. case RX_RES_STATUS_SEC_TYPE_CCMP:
  1892. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  1893. RX_RES_STATUS_DECRYPT_OK) {
  1894. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  1895. stats->flag |= RX_FLAG_DECRYPTED;
  1896. }
  1897. break;
  1898. default:
  1899. break;
  1900. }
  1901. return 0;
  1902. }
  1903. static u32 iwl4965_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
  1904. {
  1905. u32 decrypt_out = 0;
  1906. if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
  1907. RX_RES_STATUS_STATION_FOUND)
  1908. decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
  1909. RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
  1910. decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
  1911. /* packet was not encrypted */
  1912. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  1913. RX_RES_STATUS_SEC_TYPE_NONE)
  1914. return decrypt_out;
  1915. /* packet was encrypted with unknown alg */
  1916. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  1917. RX_RES_STATUS_SEC_TYPE_ERR)
  1918. return decrypt_out;
  1919. /* decryption was not done in HW */
  1920. if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
  1921. RX_MPDU_RES_STATUS_DEC_DONE_MSK)
  1922. return decrypt_out;
  1923. switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
  1924. case RX_RES_STATUS_SEC_TYPE_CCMP:
  1925. /* alg is CCM: check MIC only */
  1926. if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
  1927. /* Bad MIC */
  1928. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  1929. else
  1930. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  1931. break;
  1932. case RX_RES_STATUS_SEC_TYPE_TKIP:
  1933. if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
  1934. /* Bad TTAK */
  1935. decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
  1936. break;
  1937. }
  1938. /* fall through if TTAK OK */
  1939. default:
  1940. if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
  1941. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  1942. else
  1943. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  1944. break;
  1945. };
  1946. IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
  1947. decrypt_in, decrypt_out);
  1948. return decrypt_out;
  1949. }
  1950. static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
  1951. int include_phy,
  1952. struct iwl_rx_mem_buffer *rxb,
  1953. struct ieee80211_rx_status *stats)
  1954. {
  1955. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1956. struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
  1957. (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
  1958. struct ieee80211_hdr *hdr;
  1959. u16 len;
  1960. __le32 *rx_end;
  1961. unsigned int skblen;
  1962. u32 ampdu_status;
  1963. u32 ampdu_status_legacy;
  1964. if (!include_phy && priv->last_phy_res[0])
  1965. rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
  1966. if (!rx_start) {
  1967. IWL_ERROR("MPDU frame without a PHY data\n");
  1968. return;
  1969. }
  1970. if (include_phy) {
  1971. hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
  1972. rx_start->cfg_phy_cnt);
  1973. len = le16_to_cpu(rx_start->byte_count);
  1974. rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
  1975. sizeof(struct iwl4965_rx_phy_res) +
  1976. rx_start->cfg_phy_cnt + len);
  1977. } else {
  1978. struct iwl4965_rx_mpdu_res_start *amsdu =
  1979. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  1980. hdr = (struct ieee80211_hdr *)(pkt->u.raw +
  1981. sizeof(struct iwl4965_rx_mpdu_res_start));
  1982. len = le16_to_cpu(amsdu->byte_count);
  1983. rx_start->byte_count = amsdu->byte_count;
  1984. rx_end = (__le32 *) (((u8 *) hdr) + len);
  1985. }
  1986. /* In monitor mode allow 802.11 ACk frames (10 bytes) */
  1987. if (len > priv->hw_params.max_pkt_size ||
  1988. len < ((priv->iw_mode == IEEE80211_IF_TYPE_MNTR) ? 10 : 16)) {
  1989. IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
  1990. return;
  1991. }
  1992. ampdu_status = le32_to_cpu(*rx_end);
  1993. skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
  1994. if (!include_phy) {
  1995. /* New status scheme, need to translate */
  1996. ampdu_status_legacy = ampdu_status;
  1997. ampdu_status = iwl4965_translate_rx_status(priv, ampdu_status);
  1998. }
  1999. /* start from MAC */
  2000. skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
  2001. skb_put(rxb->skb, len); /* end where data ends */
  2002. /* We only process data packets if the interface is open */
  2003. if (unlikely(!priv->is_open)) {
  2004. IWL_DEBUG_DROP_LIMIT
  2005. ("Dropping packet while interface is not open.\n");
  2006. return;
  2007. }
  2008. stats->flag = 0;
  2009. hdr = (struct ieee80211_hdr *)rxb->skb->data;
  2010. /* in case of HW accelerated crypto and bad decryption, drop */
  2011. if (!priv->hw_params.sw_crypto &&
  2012. iwl4965_set_decrypted_flag(priv, hdr, ampdu_status, stats))
  2013. return;
  2014. if (priv->add_radiotap)
  2015. iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
  2016. iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
  2017. ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
  2018. priv->alloc_rxb_skb--;
  2019. rxb->skb = NULL;
  2020. }
  2021. /* Calc max signal level (dBm) among 3 possible receivers */
  2022. static int iwl4965_calc_rssi(struct iwl_priv *priv,
  2023. struct iwl4965_rx_phy_res *rx_resp)
  2024. {
  2025. /* data from PHY/DSP regarding signal strength, etc.,
  2026. * contents are always there, not configurable by host. */
  2027. struct iwl4965_rx_non_cfg_phy *ncphy =
  2028. (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
  2029. u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
  2030. >> IWL_AGC_DB_POS;
  2031. u32 valid_antennae =
  2032. (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
  2033. >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
  2034. u8 max_rssi = 0;
  2035. u32 i;
  2036. /* Find max rssi among 3 possible receivers.
  2037. * These values are measured by the digital signal processor (DSP).
  2038. * They should stay fairly constant even as the signal strength varies,
  2039. * if the radio's automatic gain control (AGC) is working right.
  2040. * AGC value (see below) will provide the "interesting" info. */
  2041. for (i = 0; i < 3; i++)
  2042. if (valid_antennae & (1 << i))
  2043. max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
  2044. IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
  2045. ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
  2046. max_rssi, agc);
  2047. /* dBm = max_rssi dB - agc dB - constant.
  2048. * Higher AGC (higher radio gain) means lower signal. */
  2049. return (max_rssi - agc - IWL_RSSI_OFFSET);
  2050. }
  2051. static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
  2052. {
  2053. unsigned long flags;
  2054. spin_lock_irqsave(&priv->sta_lock, flags);
  2055. priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
  2056. priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
  2057. priv->stations[sta_id].sta.sta.modify_mask = 0;
  2058. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  2059. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2060. iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  2061. }
  2062. static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
  2063. {
  2064. /* FIXME: need locking over ps_status ??? */
  2065. u8 sta_id = iwl_find_station(priv, addr);
  2066. if (sta_id != IWL_INVALID_STATION) {
  2067. u8 sta_awake = priv->stations[sta_id].
  2068. ps_status == STA_PS_STATUS_WAKE;
  2069. if (sta_awake && ps_bit)
  2070. priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
  2071. else if (!sta_awake && !ps_bit) {
  2072. iwl4965_sta_modify_ps_wake(priv, sta_id);
  2073. priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
  2074. }
  2075. }
  2076. }
  2077. #ifdef CONFIG_IWLWIFI_DEBUG
  2078. /**
  2079. * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
  2080. *
  2081. * You may hack this function to show different aspects of received frames,
  2082. * including selective frame dumps.
  2083. * group100 parameter selects whether to show 1 out of 100 good frames.
  2084. *
  2085. * TODO: This was originally written for 3945, need to audit for
  2086. * proper operation with 4965.
  2087. */
  2088. static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
  2089. struct iwl_rx_packet *pkt,
  2090. struct ieee80211_hdr *header, int group100)
  2091. {
  2092. u32 to_us;
  2093. u32 print_summary = 0;
  2094. u32 print_dump = 0; /* set to 1 to dump all frames' contents */
  2095. u32 hundred = 0;
  2096. u32 dataframe = 0;
  2097. u16 fc;
  2098. u16 seq_ctl;
  2099. u16 channel;
  2100. u16 phy_flags;
  2101. int rate_sym;
  2102. u16 length;
  2103. u16 status;
  2104. u16 bcn_tmr;
  2105. u32 tsf_low;
  2106. u64 tsf;
  2107. u8 rssi;
  2108. u8 agc;
  2109. u16 sig_avg;
  2110. u16 noise_diff;
  2111. struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
  2112. struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
  2113. struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
  2114. u8 *data = IWL_RX_DATA(pkt);
  2115. if (likely(!(priv->debug_level & IWL_DL_RX)))
  2116. return;
  2117. /* MAC header */
  2118. fc = le16_to_cpu(header->frame_control);
  2119. seq_ctl = le16_to_cpu(header->seq_ctrl);
  2120. /* metadata */
  2121. channel = le16_to_cpu(rx_hdr->channel);
  2122. phy_flags = le16_to_cpu(rx_hdr->phy_flags);
  2123. rate_sym = rx_hdr->rate;
  2124. length = le16_to_cpu(rx_hdr->len);
  2125. /* end-of-frame status and timestamp */
  2126. status = le32_to_cpu(rx_end->status);
  2127. bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
  2128. tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
  2129. tsf = le64_to_cpu(rx_end->timestamp);
  2130. /* signal statistics */
  2131. rssi = rx_stats->rssi;
  2132. agc = rx_stats->agc;
  2133. sig_avg = le16_to_cpu(rx_stats->sig_avg);
  2134. noise_diff = le16_to_cpu(rx_stats->noise_diff);
  2135. to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
  2136. /* if data frame is to us and all is good,
  2137. * (optionally) print summary for only 1 out of every 100 */
  2138. if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
  2139. (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
  2140. dataframe = 1;
  2141. if (!group100)
  2142. print_summary = 1; /* print each frame */
  2143. else if (priv->framecnt_to_us < 100) {
  2144. priv->framecnt_to_us++;
  2145. print_summary = 0;
  2146. } else {
  2147. priv->framecnt_to_us = 0;
  2148. print_summary = 1;
  2149. hundred = 1;
  2150. }
  2151. } else {
  2152. /* print summary for all other frames */
  2153. print_summary = 1;
  2154. }
  2155. if (print_summary) {
  2156. char *title;
  2157. int rate_idx;
  2158. u32 bitrate;
  2159. if (hundred)
  2160. title = "100Frames";
  2161. else if (fc & IEEE80211_FCTL_RETRY)
  2162. title = "Retry";
  2163. else if (ieee80211_is_assoc_response(fc))
  2164. title = "AscRsp";
  2165. else if (ieee80211_is_reassoc_response(fc))
  2166. title = "RasRsp";
  2167. else if (ieee80211_is_probe_response(fc)) {
  2168. title = "PrbRsp";
  2169. print_dump = 1; /* dump frame contents */
  2170. } else if (ieee80211_is_beacon(fc)) {
  2171. title = "Beacon";
  2172. print_dump = 1; /* dump frame contents */
  2173. } else if (ieee80211_is_atim(fc))
  2174. title = "ATIM";
  2175. else if (ieee80211_is_auth(fc))
  2176. title = "Auth";
  2177. else if (ieee80211_is_deauth(fc))
  2178. title = "DeAuth";
  2179. else if (ieee80211_is_disassoc(fc))
  2180. title = "DisAssoc";
  2181. else
  2182. title = "Frame";
  2183. rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
  2184. if (unlikely(rate_idx == -1))
  2185. bitrate = 0;
  2186. else
  2187. bitrate = iwl_rates[rate_idx].ieee / 2;
  2188. /* print frame summary.
  2189. * MAC addresses show just the last byte (for brevity),
  2190. * but you can hack it to show more, if you'd like to. */
  2191. if (dataframe)
  2192. IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
  2193. "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
  2194. title, fc, header->addr1[5],
  2195. length, rssi, channel, bitrate);
  2196. else {
  2197. /* src/dst addresses assume managed mode */
  2198. IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
  2199. "src=0x%02x, rssi=%u, tim=%lu usec, "
  2200. "phy=0x%02x, chnl=%d\n",
  2201. title, fc, header->addr1[5],
  2202. header->addr3[5], rssi,
  2203. tsf_low - priv->scan_start_tsf,
  2204. phy_flags, channel);
  2205. }
  2206. }
  2207. if (print_dump)
  2208. iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
  2209. }
  2210. #else
  2211. static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
  2212. struct iwl_rx_packet *pkt,
  2213. struct ieee80211_hdr *header,
  2214. int group100)
  2215. {
  2216. }
  2217. #endif
  2218. /* Called for REPLY_RX (legacy ABG frames), or
  2219. * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
  2220. void iwl4965_rx_reply_rx(struct iwl_priv *priv,
  2221. struct iwl_rx_mem_buffer *rxb)
  2222. {
  2223. struct ieee80211_hdr *header;
  2224. struct ieee80211_rx_status rx_status;
  2225. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2226. /* Use phy data (Rx signal strength, etc.) contained within
  2227. * this rx packet for legacy frames,
  2228. * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
  2229. int include_phy = (pkt->hdr.cmd == REPLY_RX);
  2230. struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
  2231. (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
  2232. (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
  2233. __le32 *rx_end;
  2234. unsigned int len = 0;
  2235. u16 fc;
  2236. u8 network_packet;
  2237. rx_status.mactime = le64_to_cpu(rx_start->timestamp);
  2238. rx_status.freq =
  2239. ieee80211_channel_to_frequency(le16_to_cpu(rx_start->channel));
  2240. rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
  2241. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  2242. rx_status.rate_idx =
  2243. iwl4965_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
  2244. if (rx_status.band == IEEE80211_BAND_5GHZ)
  2245. rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
  2246. rx_status.antenna = 0;
  2247. rx_status.flag = 0;
  2248. if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
  2249. IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
  2250. rx_start->cfg_phy_cnt);
  2251. return;
  2252. }
  2253. if (!include_phy) {
  2254. if (priv->last_phy_res[0])
  2255. rx_start = (struct iwl4965_rx_phy_res *)
  2256. &priv->last_phy_res[1];
  2257. else
  2258. rx_start = NULL;
  2259. }
  2260. if (!rx_start) {
  2261. IWL_ERROR("MPDU frame without a PHY data\n");
  2262. return;
  2263. }
  2264. if (include_phy) {
  2265. header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
  2266. + rx_start->cfg_phy_cnt);
  2267. len = le16_to_cpu(rx_start->byte_count);
  2268. rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
  2269. sizeof(struct iwl4965_rx_phy_res) + len);
  2270. } else {
  2271. struct iwl4965_rx_mpdu_res_start *amsdu =
  2272. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  2273. header = (void *)(pkt->u.raw +
  2274. sizeof(struct iwl4965_rx_mpdu_res_start));
  2275. len = le16_to_cpu(amsdu->byte_count);
  2276. rx_end = (__le32 *) (pkt->u.raw +
  2277. sizeof(struct iwl4965_rx_mpdu_res_start) + len);
  2278. }
  2279. if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
  2280. !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
  2281. IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
  2282. le32_to_cpu(*rx_end));
  2283. return;
  2284. }
  2285. priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
  2286. /* Find max signal strength (dBm) among 3 antenna/receiver chains */
  2287. rx_status.signal = iwl4965_calc_rssi(priv, rx_start);
  2288. /* Meaningful noise values are available only from beacon statistics,
  2289. * which are gathered only when associated, and indicate noise
  2290. * only for the associated network channel ...
  2291. * Ignore these noise values while scanning (other channels) */
  2292. if (iwl_is_associated(priv) &&
  2293. !test_bit(STATUS_SCANNING, &priv->status)) {
  2294. rx_status.noise = priv->last_rx_noise;
  2295. rx_status.qual = iwl4965_calc_sig_qual(rx_status.signal,
  2296. rx_status.noise);
  2297. } else {
  2298. rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  2299. rx_status.qual = iwl4965_calc_sig_qual(rx_status.signal, 0);
  2300. }
  2301. /* Reset beacon noise level if not associated. */
  2302. if (!iwl_is_associated(priv))
  2303. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  2304. /* Set "1" to report good data frames in groups of 100 */
  2305. /* FIXME: need to optimze the call: */
  2306. iwl4965_dbg_report_frame(priv, pkt, header, 1);
  2307. IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
  2308. rx_status.signal, rx_status.noise, rx_status.signal,
  2309. (unsigned long long)rx_status.mactime);
  2310. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
  2311. iwl4965_handle_data_packet(priv, 1, include_phy,
  2312. rxb, &rx_status);
  2313. return;
  2314. }
  2315. network_packet = iwl4965_is_network_packet(priv, header);
  2316. if (network_packet) {
  2317. priv->last_rx_rssi = rx_status.signal;
  2318. priv->last_beacon_time = priv->ucode_beacon_time;
  2319. priv->last_tsf = le64_to_cpu(rx_start->timestamp);
  2320. }
  2321. fc = le16_to_cpu(header->frame_control);
  2322. switch (fc & IEEE80211_FCTL_FTYPE) {
  2323. case IEEE80211_FTYPE_MGMT:
  2324. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  2325. iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  2326. header->addr2);
  2327. iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
  2328. break;
  2329. case IEEE80211_FTYPE_CTL:
  2330. switch (fc & IEEE80211_FCTL_STYPE) {
  2331. case IEEE80211_STYPE_BACK_REQ:
  2332. IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
  2333. iwl4965_handle_data_packet(priv, 0, include_phy,
  2334. rxb, &rx_status);
  2335. break;
  2336. default:
  2337. break;
  2338. }
  2339. break;
  2340. case IEEE80211_FTYPE_DATA: {
  2341. DECLARE_MAC_BUF(mac1);
  2342. DECLARE_MAC_BUF(mac2);
  2343. DECLARE_MAC_BUF(mac3);
  2344. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  2345. iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  2346. header->addr2);
  2347. if (unlikely(!network_packet))
  2348. IWL_DEBUG_DROP("Dropping (non network): "
  2349. "%s, %s, %s\n",
  2350. print_mac(mac1, header->addr1),
  2351. print_mac(mac2, header->addr2),
  2352. print_mac(mac3, header->addr3));
  2353. else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
  2354. IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
  2355. print_mac(mac1, header->addr1),
  2356. print_mac(mac2, header->addr2),
  2357. print_mac(mac3, header->addr3));
  2358. else
  2359. iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
  2360. &rx_status);
  2361. break;
  2362. }
  2363. default:
  2364. break;
  2365. }
  2366. }
  2367. /**
  2368. * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
  2369. *
  2370. * Go through block-ack's bitmap of ACK'd frames, update driver's record of
  2371. * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
  2372. */
  2373. static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
  2374. struct iwl_ht_agg *agg,
  2375. struct iwl4965_compressed_ba_resp*
  2376. ba_resp)
  2377. {
  2378. int i, sh, ack;
  2379. u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
  2380. u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
  2381. u64 bitmap;
  2382. int successes = 0;
  2383. struct ieee80211_tx_info *info;
  2384. if (unlikely(!agg->wait_for_ba)) {
  2385. IWL_ERROR("Received BA when not expected\n");
  2386. return -EINVAL;
  2387. }
  2388. /* Mark that the expected block-ack response arrived */
  2389. agg->wait_for_ba = 0;
  2390. IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
  2391. /* Calculate shift to align block-ack bits with our Tx window bits */
  2392. sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
  2393. if (sh < 0) /* tbw something is wrong with indices */
  2394. sh += 0x100;
  2395. /* don't use 64-bit values for now */
  2396. bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
  2397. if (agg->frame_count > (64 - sh)) {
  2398. IWL_DEBUG_TX_REPLY("more frames than bitmap size");
  2399. return -1;
  2400. }
  2401. /* check for success or failure according to the
  2402. * transmitted bitmap and block-ack bitmap */
  2403. bitmap &= agg->bitmap;
  2404. /* For each frame attempted in aggregation,
  2405. * update driver's record of tx frame's status. */
  2406. for (i = 0; i < agg->frame_count ; i++) {
  2407. ack = bitmap & (1 << i);
  2408. successes += !!ack;
  2409. IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
  2410. ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
  2411. agg->start_idx + i);
  2412. }
  2413. info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
  2414. memset(&info->status, 0, sizeof(info->status));
  2415. info->flags = IEEE80211_TX_STAT_ACK;
  2416. info->flags |= IEEE80211_TX_STAT_AMPDU;
  2417. info->status.ampdu_ack_map = successes;
  2418. info->status.ampdu_ack_len = agg->frame_count;
  2419. iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
  2420. IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
  2421. return 0;
  2422. }
  2423. /**
  2424. * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
  2425. */
  2426. static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
  2427. u16 txq_id)
  2428. {
  2429. /* Simply stop the queue, but don't change any configuration;
  2430. * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
  2431. iwl_write_prph(priv,
  2432. IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
  2433. (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
  2434. (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
  2435. }
  2436. /**
  2437. * txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE
  2438. * priv->lock must be held by the caller
  2439. */
  2440. static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
  2441. u16 ssn_idx, u8 tx_fifo)
  2442. {
  2443. int ret = 0;
  2444. if (IWL49_FIRST_AMPDU_QUEUE > txq_id) {
  2445. IWL_WARNING("queue number too small: %d, must be > %d\n",
  2446. txq_id, IWL49_FIRST_AMPDU_QUEUE);
  2447. return -EINVAL;
  2448. }
  2449. ret = iwl_grab_nic_access(priv);
  2450. if (ret)
  2451. return ret;
  2452. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  2453. iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
  2454. priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
  2455. priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
  2456. /* supposes that ssn_idx is valid (!= 0xFFF) */
  2457. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  2458. iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
  2459. iwl_txq_ctx_deactivate(priv, txq_id);
  2460. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
  2461. iwl_release_nic_access(priv);
  2462. return 0;
  2463. }
  2464. /**
  2465. * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
  2466. *
  2467. * Handles block-acknowledge notification from device, which reports success
  2468. * of frames sent via aggregation.
  2469. */
  2470. static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
  2471. struct iwl_rx_mem_buffer *rxb)
  2472. {
  2473. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2474. struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
  2475. int index;
  2476. struct iwl_tx_queue *txq = NULL;
  2477. struct iwl_ht_agg *agg;
  2478. DECLARE_MAC_BUF(mac);
  2479. /* "flow" corresponds to Tx queue */
  2480. u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
  2481. /* "ssn" is start of block-ack Tx window, corresponds to index
  2482. * (in Tx queue's circular buffer) of first TFD/frame in window */
  2483. u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
  2484. if (scd_flow >= priv->hw_params.max_txq_num) {
  2485. IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
  2486. return;
  2487. }
  2488. txq = &priv->txq[scd_flow];
  2489. agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
  2490. /* Find index just before block-ack window */
  2491. index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
  2492. /* TODO: Need to get this copy more safely - now good for debug */
  2493. IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
  2494. "sta_id = %d\n",
  2495. agg->wait_for_ba,
  2496. print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
  2497. ba_resp->sta_id);
  2498. IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
  2499. "%d, scd_ssn = %d\n",
  2500. ba_resp->tid,
  2501. ba_resp->seq_ctl,
  2502. (unsigned long long)le64_to_cpu(ba_resp->bitmap),
  2503. ba_resp->scd_flow,
  2504. ba_resp->scd_ssn);
  2505. IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
  2506. agg->start_idx,
  2507. (unsigned long long)agg->bitmap);
  2508. /* Update driver's record of ACK vs. not for each frame in window */
  2509. iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
  2510. /* Release all TFDs before the SSN, i.e. all TFDs in front of
  2511. * block-ack window (we assume that they've been successfully
  2512. * transmitted ... if not, it's too late anyway). */
  2513. if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
  2514. /* calculate mac80211 ampdu sw queue to wake */
  2515. int ampdu_q =
  2516. scd_flow - priv->hw_params.first_ampdu_q + priv->hw->queues;
  2517. int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
  2518. priv->stations[ba_resp->sta_id].
  2519. tid[ba_resp->tid].tfds_in_queue -= freed;
  2520. if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
  2521. priv->mac80211_registered &&
  2522. agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
  2523. ieee80211_wake_queue(priv->hw, ampdu_q);
  2524. iwl_txq_check_empty(priv, ba_resp->sta_id,
  2525. ba_resp->tid, scd_flow);
  2526. }
  2527. }
  2528. /**
  2529. * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
  2530. */
  2531. static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
  2532. u16 txq_id)
  2533. {
  2534. u32 tbl_dw_addr;
  2535. u32 tbl_dw;
  2536. u16 scd_q2ratid;
  2537. scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
  2538. tbl_dw_addr = priv->scd_base_addr +
  2539. IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
  2540. tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
  2541. if (txq_id & 0x1)
  2542. tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
  2543. else
  2544. tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
  2545. iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
  2546. return 0;
  2547. }
  2548. /**
  2549. * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
  2550. *
  2551. * NOTE: txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE,
  2552. * i.e. it must be one of the higher queues used for aggregation
  2553. */
  2554. static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id,
  2555. int tx_fifo, int sta_id, int tid, u16 ssn_idx)
  2556. {
  2557. unsigned long flags;
  2558. int ret;
  2559. u16 ra_tid;
  2560. if (IWL49_FIRST_AMPDU_QUEUE > txq_id)
  2561. IWL_WARNING("queue number too small: %d, must be > %d\n",
  2562. txq_id, IWL49_FIRST_AMPDU_QUEUE);
  2563. ra_tid = BUILD_RAxTID(sta_id, tid);
  2564. /* Modify device's station table to Tx this TID */
  2565. iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
  2566. spin_lock_irqsave(&priv->lock, flags);
  2567. ret = iwl_grab_nic_access(priv);
  2568. if (ret) {
  2569. spin_unlock_irqrestore(&priv->lock, flags);
  2570. return ret;
  2571. }
  2572. /* Stop this Tx queue before configuring it */
  2573. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  2574. /* Map receiver-address / traffic-ID to this queue */
  2575. iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
  2576. /* Set this queue as a chain-building queue */
  2577. iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
  2578. /* Place first TFD at index corresponding to start sequence number.
  2579. * Assumes that ssn_idx is valid (!= 0xFFF) */
  2580. priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
  2581. priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
  2582. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  2583. /* Set up Tx window size and frame limit for this queue */
  2584. iwl_write_targ_mem(priv,
  2585. priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
  2586. (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  2587. IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  2588. iwl_write_targ_mem(priv, priv->scd_base_addr +
  2589. IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
  2590. (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
  2591. & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  2592. iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
  2593. /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
  2594. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
  2595. iwl_release_nic_access(priv);
  2596. spin_unlock_irqrestore(&priv->lock, flags);
  2597. return 0;
  2598. }
  2599. static int iwl4965_rx_agg_start(struct iwl_priv *priv,
  2600. const u8 *addr, int tid, u16 ssn)
  2601. {
  2602. unsigned long flags;
  2603. int sta_id;
  2604. sta_id = iwl_find_station(priv, addr);
  2605. if (sta_id == IWL_INVALID_STATION)
  2606. return -ENXIO;
  2607. spin_lock_irqsave(&priv->sta_lock, flags);
  2608. priv->stations[sta_id].sta.station_flags_msk = 0;
  2609. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
  2610. priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
  2611. priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
  2612. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  2613. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2614. return iwl_send_add_sta(priv, &priv->stations[sta_id].sta,
  2615. CMD_ASYNC);
  2616. }
  2617. static int iwl4965_rx_agg_stop(struct iwl_priv *priv,
  2618. const u8 *addr, int tid)
  2619. {
  2620. unsigned long flags;
  2621. int sta_id;
  2622. sta_id = iwl_find_station(priv, addr);
  2623. if (sta_id == IWL_INVALID_STATION)
  2624. return -ENXIO;
  2625. spin_lock_irqsave(&priv->sta_lock, flags);
  2626. priv->stations[sta_id].sta.station_flags_msk = 0;
  2627. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
  2628. priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
  2629. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  2630. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2631. return iwl_send_add_sta(priv, &priv->stations[sta_id].sta,
  2632. CMD_ASYNC);
  2633. }
  2634. int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
  2635. enum ieee80211_ampdu_mlme_action action,
  2636. const u8 *addr, u16 tid, u16 *ssn)
  2637. {
  2638. struct iwl_priv *priv = hw->priv;
  2639. DECLARE_MAC_BUF(mac);
  2640. IWL_DEBUG_HT("A-MPDU action on addr %s tid %d\n",
  2641. print_mac(mac, addr), tid);
  2642. switch (action) {
  2643. case IEEE80211_AMPDU_RX_START:
  2644. IWL_DEBUG_HT("start Rx\n");
  2645. return iwl4965_rx_agg_start(priv, addr, tid, *ssn);
  2646. case IEEE80211_AMPDU_RX_STOP:
  2647. IWL_DEBUG_HT("stop Rx\n");
  2648. return iwl4965_rx_agg_stop(priv, addr, tid);
  2649. case IEEE80211_AMPDU_TX_START:
  2650. IWL_DEBUG_HT("start Tx\n");
  2651. return iwl_tx_agg_start(priv, addr, tid, ssn);
  2652. case IEEE80211_AMPDU_TX_STOP:
  2653. IWL_DEBUG_HT("stop Tx\n");
  2654. return iwl_tx_agg_stop(priv, addr, tid);
  2655. default:
  2656. IWL_DEBUG_HT("unknown\n");
  2657. return -EINVAL;
  2658. break;
  2659. }
  2660. return 0;
  2661. }
  2662. static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len)
  2663. {
  2664. switch (cmd_id) {
  2665. case REPLY_RXON:
  2666. return (u16) sizeof(struct iwl4965_rxon_cmd);
  2667. default:
  2668. return len;
  2669. }
  2670. }
  2671. static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
  2672. {
  2673. struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data;
  2674. addsta->mode = cmd->mode;
  2675. memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
  2676. memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
  2677. addsta->station_flags = cmd->station_flags;
  2678. addsta->station_flags_msk = cmd->station_flags_msk;
  2679. addsta->tid_disable_tx = cmd->tid_disable_tx;
  2680. addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
  2681. addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
  2682. addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
  2683. addsta->reserved1 = __constant_cpu_to_le16(0);
  2684. addsta->reserved2 = __constant_cpu_to_le32(0);
  2685. return (u16)sizeof(struct iwl4965_addsta_cmd);
  2686. }
  2687. static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
  2688. {
  2689. return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN;
  2690. }
  2691. /**
  2692. * iwl4965_tx_status_reply_tx - Handle Tx rspnse for frames in aggregation queue
  2693. */
  2694. static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv,
  2695. struct iwl_ht_agg *agg,
  2696. struct iwl4965_tx_resp *tx_resp,
  2697. int txq_id, u16 start_idx)
  2698. {
  2699. u16 status;
  2700. struct agg_tx_status *frame_status = tx_resp->u.agg_status;
  2701. struct ieee80211_tx_info *info = NULL;
  2702. struct ieee80211_hdr *hdr = NULL;
  2703. int i, sh, idx;
  2704. u16 seq;
  2705. if (agg->wait_for_ba)
  2706. IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
  2707. agg->frame_count = tx_resp->frame_count;
  2708. agg->start_idx = start_idx;
  2709. agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
  2710. agg->bitmap = 0;
  2711. /* # frames attempted by Tx command */
  2712. if (agg->frame_count == 1) {
  2713. /* Only one frame was attempted; no block-ack will arrive */
  2714. status = le16_to_cpu(frame_status[0].status);
  2715. idx = start_idx;
  2716. /* FIXME: code repetition */
  2717. IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
  2718. agg->frame_count, agg->start_idx, idx);
  2719. info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
  2720. info->status.retry_count = tx_resp->failure_frame;
  2721. info->flags &= ~IEEE80211_TX_CTL_AMPDU;
  2722. info->flags |= iwl_is_tx_success(status)?
  2723. IEEE80211_TX_STAT_ACK : 0;
  2724. iwl4965_hwrate_to_tx_control(priv,
  2725. le32_to_cpu(tx_resp->rate_n_flags),
  2726. info);
  2727. /* FIXME: code repetition end */
  2728. IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
  2729. status & 0xff, tx_resp->failure_frame);
  2730. IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n",
  2731. iwl4965_hw_get_rate_n_flags(tx_resp->rate_n_flags));
  2732. agg->wait_for_ba = 0;
  2733. } else {
  2734. /* Two or more frames were attempted; expect block-ack */
  2735. u64 bitmap = 0;
  2736. int start = agg->start_idx;
  2737. /* Construct bit-map of pending frames within Tx window */
  2738. for (i = 0; i < agg->frame_count; i++) {
  2739. u16 sc;
  2740. status = le16_to_cpu(frame_status[i].status);
  2741. seq = le16_to_cpu(frame_status[i].sequence);
  2742. idx = SEQ_TO_INDEX(seq);
  2743. txq_id = SEQ_TO_QUEUE(seq);
  2744. if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
  2745. AGG_TX_STATE_ABORT_MSK))
  2746. continue;
  2747. IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
  2748. agg->frame_count, txq_id, idx);
  2749. hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
  2750. sc = le16_to_cpu(hdr->seq_ctrl);
  2751. if (idx != (SEQ_TO_SN(sc) & 0xff)) {
  2752. IWL_ERROR("BUG_ON idx doesn't match seq control"
  2753. " idx=%d, seq_idx=%d, seq=%d\n",
  2754. idx, SEQ_TO_SN(sc),
  2755. hdr->seq_ctrl);
  2756. return -1;
  2757. }
  2758. IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
  2759. i, idx, SEQ_TO_SN(sc));
  2760. sh = idx - start;
  2761. if (sh > 64) {
  2762. sh = (start - idx) + 0xff;
  2763. bitmap = bitmap << sh;
  2764. sh = 0;
  2765. start = idx;
  2766. } else if (sh < -64)
  2767. sh = 0xff - (start - idx);
  2768. else if (sh < 0) {
  2769. sh = start - idx;
  2770. start = idx;
  2771. bitmap = bitmap << sh;
  2772. sh = 0;
  2773. }
  2774. bitmap |= (1 << sh);
  2775. IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%x\n",
  2776. start, (u32)(bitmap & 0xFFFFFFFF));
  2777. }
  2778. agg->bitmap = bitmap;
  2779. agg->start_idx = start;
  2780. agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
  2781. IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
  2782. agg->frame_count, agg->start_idx,
  2783. (unsigned long long)agg->bitmap);
  2784. if (bitmap)
  2785. agg->wait_for_ba = 1;
  2786. }
  2787. return 0;
  2788. }
  2789. /**
  2790. * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
  2791. */
  2792. static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
  2793. struct iwl_rx_mem_buffer *rxb)
  2794. {
  2795. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2796. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2797. int txq_id = SEQ_TO_QUEUE(sequence);
  2798. int index = SEQ_TO_INDEX(sequence);
  2799. struct iwl_tx_queue *txq = &priv->txq[txq_id];
  2800. struct ieee80211_tx_info *info;
  2801. struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
  2802. u32 status = le32_to_cpu(tx_resp->u.status);
  2803. int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION;
  2804. u16 fc;
  2805. struct ieee80211_hdr *hdr;
  2806. u8 *qc = NULL;
  2807. if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
  2808. IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
  2809. "is out of range [0-%d] %d %d\n", txq_id,
  2810. index, txq->q.n_bd, txq->q.write_ptr,
  2811. txq->q.read_ptr);
  2812. return;
  2813. }
  2814. info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
  2815. memset(&info->status, 0, sizeof(info->status));
  2816. hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
  2817. fc = le16_to_cpu(hdr->frame_control);
  2818. if (ieee80211_is_qos_data(fc)) {
  2819. qc = ieee80211_get_qos_ctrl(hdr, ieee80211_get_hdrlen(fc));
  2820. tid = qc[0] & 0xf;
  2821. }
  2822. sta_id = iwl_get_ra_sta_id(priv, hdr);
  2823. if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
  2824. IWL_ERROR("Station not known\n");
  2825. return;
  2826. }
  2827. if (txq->sched_retry) {
  2828. const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
  2829. struct iwl_ht_agg *agg = NULL;
  2830. if (!qc)
  2831. return;
  2832. agg = &priv->stations[sta_id].tid[tid].agg;
  2833. iwl4965_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
  2834. if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) {
  2835. /* TODO: send BAR */
  2836. }
  2837. if (txq->q.read_ptr != (scd_ssn & 0xff)) {
  2838. int freed, ampdu_q;
  2839. index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
  2840. IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
  2841. "%d index %d\n", scd_ssn , index);
  2842. freed = iwl_tx_queue_reclaim(priv, txq_id, index);
  2843. priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
  2844. if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
  2845. txq_id >= 0 && priv->mac80211_registered &&
  2846. agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) {
  2847. /* calculate mac80211 ampdu sw queue to wake */
  2848. ampdu_q = txq_id - IWL49_FIRST_AMPDU_QUEUE +
  2849. priv->hw->queues;
  2850. if (agg->state == IWL_AGG_OFF)
  2851. ieee80211_wake_queue(priv->hw, txq_id);
  2852. else
  2853. ieee80211_wake_queue(priv->hw, ampdu_q);
  2854. }
  2855. iwl_txq_check_empty(priv, sta_id, tid, txq_id);
  2856. }
  2857. } else {
  2858. info->status.retry_count = tx_resp->failure_frame;
  2859. info->flags |=
  2860. iwl_is_tx_success(status) ? IEEE80211_TX_STAT_ACK : 0;
  2861. iwl4965_hwrate_to_tx_control(priv,
  2862. le32_to_cpu(tx_resp->rate_n_flags),
  2863. info);
  2864. IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags "
  2865. "0x%x retries %d\n", txq_id,
  2866. iwl_get_tx_fail_reason(status),
  2867. status, le32_to_cpu(tx_resp->rate_n_flags),
  2868. tx_resp->failure_frame);
  2869. IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
  2870. if (index != -1) {
  2871. int freed = iwl_tx_queue_reclaim(priv, txq_id, index);
  2872. if (tid != MAX_TID_COUNT)
  2873. priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
  2874. if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
  2875. (txq_id >= 0) && priv->mac80211_registered)
  2876. ieee80211_wake_queue(priv->hw, txq_id);
  2877. if (tid != MAX_TID_COUNT)
  2878. iwl_txq_check_empty(priv, sta_id, tid, txq_id);
  2879. }
  2880. }
  2881. if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
  2882. IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
  2883. }
  2884. /* Set up 4965-specific Rx frame reply handlers */
  2885. static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
  2886. {
  2887. /* Legacy Rx frames */
  2888. priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
  2889. /* Tx response */
  2890. priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
  2891. /* block ack */
  2892. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
  2893. }
  2894. static void iwl4965_setup_deferred_work(struct iwl_priv *priv)
  2895. {
  2896. INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
  2897. }
  2898. static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
  2899. {
  2900. cancel_work_sync(&priv->txpower_work);
  2901. }
  2902. static struct iwl_hcmd_ops iwl4965_hcmd = {
  2903. .rxon_assoc = iwl4965_send_rxon_assoc,
  2904. };
  2905. static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
  2906. .get_hcmd_size = iwl4965_get_hcmd_size,
  2907. .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
  2908. .chain_noise_reset = iwl4965_chain_noise_reset,
  2909. .gain_computation = iwl4965_gain_computation,
  2910. };
  2911. static struct iwl_lib_ops iwl4965_lib = {
  2912. .set_hw_params = iwl4965_hw_set_hw_params,
  2913. .alloc_shared_mem = iwl4965_alloc_shared_mem,
  2914. .free_shared_mem = iwl4965_free_shared_mem,
  2915. .shared_mem_rx_idx = iwl4965_shared_mem_rx_idx,
  2916. .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
  2917. .txq_set_sched = iwl4965_txq_set_sched,
  2918. .txq_agg_enable = iwl4965_txq_agg_enable,
  2919. .txq_agg_disable = iwl4965_txq_agg_disable,
  2920. .rx_handler_setup = iwl4965_rx_handler_setup,
  2921. .setup_deferred_work = iwl4965_setup_deferred_work,
  2922. .cancel_deferred_work = iwl4965_cancel_deferred_work,
  2923. .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
  2924. .alive_notify = iwl4965_alive_notify,
  2925. .init_alive_start = iwl4965_init_alive_start,
  2926. .load_ucode = iwl4965_load_bsm,
  2927. .apm_ops = {
  2928. .init = iwl4965_apm_init,
  2929. .reset = iwl4965_apm_reset,
  2930. .stop = iwl4965_apm_stop,
  2931. .config = iwl4965_nic_config,
  2932. .set_pwr_src = iwl4965_set_pwr_src,
  2933. },
  2934. .eeprom_ops = {
  2935. .regulatory_bands = {
  2936. EEPROM_REGULATORY_BAND_1_CHANNELS,
  2937. EEPROM_REGULATORY_BAND_2_CHANNELS,
  2938. EEPROM_REGULATORY_BAND_3_CHANNELS,
  2939. EEPROM_REGULATORY_BAND_4_CHANNELS,
  2940. EEPROM_REGULATORY_BAND_5_CHANNELS,
  2941. EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS,
  2942. EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS
  2943. },
  2944. .verify_signature = iwlcore_eeprom_verify_signature,
  2945. .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
  2946. .release_semaphore = iwlcore_eeprom_release_semaphore,
  2947. .check_version = iwl4965_eeprom_check_version,
  2948. .query_addr = iwlcore_eeprom_query_addr,
  2949. },
  2950. .radio_kill_sw = iwl4965_radio_kill_sw,
  2951. .set_power = iwl4965_set_power,
  2952. .send_tx_power = iwl4965_send_tx_power,
  2953. .update_chain_flags = iwl4965_update_chain_flags,
  2954. };
  2955. static struct iwl_ops iwl4965_ops = {
  2956. .lib = &iwl4965_lib,
  2957. .hcmd = &iwl4965_hcmd,
  2958. .utils = &iwl4965_hcmd_utils,
  2959. };
  2960. struct iwl_cfg iwl4965_agn_cfg = {
  2961. .name = "4965AGN",
  2962. .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
  2963. .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
  2964. .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
  2965. .ops = &iwl4965_ops,
  2966. .mod_params = &iwl4965_mod_params,
  2967. };
  2968. module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
  2969. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  2970. module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
  2971. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  2972. module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
  2973. MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])\n");
  2974. module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
  2975. MODULE_PARM_DESC(debug, "debug output mask");
  2976. module_param_named(
  2977. disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
  2978. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  2979. module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
  2980. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  2981. /* QoS */
  2982. module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
  2983. MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
  2984. module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
  2985. MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
  2986. module_param_named(fw_restart4965, iwl4965_mod_params.restart_fw, int, 0444);
  2987. MODULE_PARM_DESC(fw_restart4965, "restart firmware in case of error");