psb_intel_sdvo.c 82 KB

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  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2007 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. * Authors:
  26. * Eric Anholt <eric@anholt.net>
  27. */
  28. #include <linux/module.h>
  29. #include <linux/i2c.h>
  30. #include <linux/slab.h>
  31. #include <linux/delay.h>
  32. #include <drm/drmP.h>
  33. #include <drm/drm_crtc.h>
  34. #include <drm/drm_edid.h>
  35. #include "psb_intel_drv.h"
  36. #include <drm/gma_drm.h>
  37. #include "psb_drv.h"
  38. #include "psb_intel_sdvo_regs.h"
  39. #include "psb_intel_reg.h"
  40. #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
  41. #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
  42. #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
  43. #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
  44. #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
  45. SDVO_TV_MASK)
  46. #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
  47. #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
  48. #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
  49. #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
  50. static const char *tv_format_names[] = {
  51. "NTSC_M" , "NTSC_J" , "NTSC_443",
  52. "PAL_B" , "PAL_D" , "PAL_G" ,
  53. "PAL_H" , "PAL_I" , "PAL_M" ,
  54. "PAL_N" , "PAL_NC" , "PAL_60" ,
  55. "SECAM_B" , "SECAM_D" , "SECAM_G" ,
  56. "SECAM_K" , "SECAM_K1", "SECAM_L" ,
  57. "SECAM_60"
  58. };
  59. #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
  60. struct psb_intel_sdvo {
  61. struct psb_intel_encoder base;
  62. struct i2c_adapter *i2c;
  63. u8 slave_addr;
  64. struct i2c_adapter ddc;
  65. /* Register for the SDVO device: SDVOB or SDVOC */
  66. int sdvo_reg;
  67. /* Active outputs controlled by this SDVO output */
  68. uint16_t controlled_output;
  69. /*
  70. * Capabilities of the SDVO device returned by
  71. * i830_sdvo_get_capabilities()
  72. */
  73. struct psb_intel_sdvo_caps caps;
  74. /* Pixel clock limitations reported by the SDVO device, in kHz */
  75. int pixel_clock_min, pixel_clock_max;
  76. /*
  77. * For multiple function SDVO device,
  78. * this is for current attached outputs.
  79. */
  80. uint16_t attached_output;
  81. /**
  82. * This is used to select the color range of RBG outputs in HDMI mode.
  83. * It is only valid when using TMDS encoding and 8 bit per color mode.
  84. */
  85. uint32_t color_range;
  86. /**
  87. * This is set if we're going to treat the device as TV-out.
  88. *
  89. * While we have these nice friendly flags for output types that ought
  90. * to decide this for us, the S-Video output on our HDMI+S-Video card
  91. * shows up as RGB1 (VGA).
  92. */
  93. bool is_tv;
  94. /* This is for current tv format name */
  95. int tv_format_index;
  96. /**
  97. * This is set if we treat the device as HDMI, instead of DVI.
  98. */
  99. bool is_hdmi;
  100. bool has_hdmi_monitor;
  101. bool has_hdmi_audio;
  102. /**
  103. * This is set if we detect output of sdvo device as LVDS and
  104. * have a valid fixed mode to use with the panel.
  105. */
  106. bool is_lvds;
  107. /**
  108. * This is sdvo fixed pannel mode pointer
  109. */
  110. struct drm_display_mode *sdvo_lvds_fixed_mode;
  111. /* DDC bus used by this SDVO encoder */
  112. uint8_t ddc_bus;
  113. /* Input timings for adjusted_mode */
  114. struct psb_intel_sdvo_dtd input_dtd;
  115. /* Saved SDVO output states */
  116. uint32_t saveSDVO; /* Can be SDVOB or SDVOC depending on sdvo_reg */
  117. };
  118. struct psb_intel_sdvo_connector {
  119. struct psb_intel_connector base;
  120. /* Mark the type of connector */
  121. uint16_t output_flag;
  122. int force_audio;
  123. /* This contains all current supported TV format */
  124. u8 tv_format_supported[TV_FORMAT_NUM];
  125. int format_supported_num;
  126. struct drm_property *tv_format;
  127. /* add the property for the SDVO-TV */
  128. struct drm_property *left;
  129. struct drm_property *right;
  130. struct drm_property *top;
  131. struct drm_property *bottom;
  132. struct drm_property *hpos;
  133. struct drm_property *vpos;
  134. struct drm_property *contrast;
  135. struct drm_property *saturation;
  136. struct drm_property *hue;
  137. struct drm_property *sharpness;
  138. struct drm_property *flicker_filter;
  139. struct drm_property *flicker_filter_adaptive;
  140. struct drm_property *flicker_filter_2d;
  141. struct drm_property *tv_chroma_filter;
  142. struct drm_property *tv_luma_filter;
  143. struct drm_property *dot_crawl;
  144. /* add the property for the SDVO-TV/LVDS */
  145. struct drm_property *brightness;
  146. /* Add variable to record current setting for the above property */
  147. u32 left_margin, right_margin, top_margin, bottom_margin;
  148. /* this is to get the range of margin.*/
  149. u32 max_hscan, max_vscan;
  150. u32 max_hpos, cur_hpos;
  151. u32 max_vpos, cur_vpos;
  152. u32 cur_brightness, max_brightness;
  153. u32 cur_contrast, max_contrast;
  154. u32 cur_saturation, max_saturation;
  155. u32 cur_hue, max_hue;
  156. u32 cur_sharpness, max_sharpness;
  157. u32 cur_flicker_filter, max_flicker_filter;
  158. u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
  159. u32 cur_flicker_filter_2d, max_flicker_filter_2d;
  160. u32 cur_tv_chroma_filter, max_tv_chroma_filter;
  161. u32 cur_tv_luma_filter, max_tv_luma_filter;
  162. u32 cur_dot_crawl, max_dot_crawl;
  163. };
  164. static struct psb_intel_sdvo *to_psb_intel_sdvo(struct drm_encoder *encoder)
  165. {
  166. return container_of(encoder, struct psb_intel_sdvo, base.base);
  167. }
  168. static struct psb_intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
  169. {
  170. return container_of(gma_attached_encoder(connector),
  171. struct psb_intel_sdvo, base);
  172. }
  173. static struct psb_intel_sdvo_connector *to_psb_intel_sdvo_connector(struct drm_connector *connector)
  174. {
  175. return container_of(to_psb_intel_connector(connector), struct psb_intel_sdvo_connector, base);
  176. }
  177. static bool
  178. psb_intel_sdvo_output_setup(struct psb_intel_sdvo *psb_intel_sdvo, uint16_t flags);
  179. static bool
  180. psb_intel_sdvo_tv_create_property(struct psb_intel_sdvo *psb_intel_sdvo,
  181. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
  182. int type);
  183. static bool
  184. psb_intel_sdvo_create_enhance_property(struct psb_intel_sdvo *psb_intel_sdvo,
  185. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector);
  186. /**
  187. * Writes the SDVOB or SDVOC with the given value, but always writes both
  188. * SDVOB and SDVOC to work around apparent hardware issues (according to
  189. * comments in the BIOS).
  190. */
  191. static void psb_intel_sdvo_write_sdvox(struct psb_intel_sdvo *psb_intel_sdvo, u32 val)
  192. {
  193. struct drm_device *dev = psb_intel_sdvo->base.base.dev;
  194. u32 bval = val, cval = val;
  195. int i;
  196. if (psb_intel_sdvo->sdvo_reg == SDVOB) {
  197. cval = REG_READ(SDVOC);
  198. } else {
  199. bval = REG_READ(SDVOB);
  200. }
  201. /*
  202. * Write the registers twice for luck. Sometimes,
  203. * writing them only once doesn't appear to 'stick'.
  204. * The BIOS does this too. Yay, magic
  205. */
  206. for (i = 0; i < 2; i++)
  207. {
  208. REG_WRITE(SDVOB, bval);
  209. REG_READ(SDVOB);
  210. REG_WRITE(SDVOC, cval);
  211. REG_READ(SDVOC);
  212. }
  213. }
  214. static bool psb_intel_sdvo_read_byte(struct psb_intel_sdvo *psb_intel_sdvo, u8 addr, u8 *ch)
  215. {
  216. struct i2c_msg msgs[] = {
  217. {
  218. .addr = psb_intel_sdvo->slave_addr,
  219. .flags = 0,
  220. .len = 1,
  221. .buf = &addr,
  222. },
  223. {
  224. .addr = psb_intel_sdvo->slave_addr,
  225. .flags = I2C_M_RD,
  226. .len = 1,
  227. .buf = ch,
  228. }
  229. };
  230. int ret;
  231. if ((ret = i2c_transfer(psb_intel_sdvo->i2c, msgs, 2)) == 2)
  232. return true;
  233. DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
  234. return false;
  235. }
  236. #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
  237. /** Mapping of command numbers to names, for debug output */
  238. static const struct _sdvo_cmd_name {
  239. u8 cmd;
  240. const char *name;
  241. } sdvo_cmd_names[] = {
  242. SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
  243. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
  244. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
  245. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
  246. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
  247. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
  248. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
  249. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
  250. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
  251. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
  252. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
  253. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
  254. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
  255. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
  256. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
  257. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
  258. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
  259. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  260. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
  261. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  262. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
  263. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
  264. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
  265. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
  266. SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
  267. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
  268. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
  269. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
  270. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
  271. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
  272. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
  273. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
  274. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
  275. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
  276. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
  277. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
  278. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
  279. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
  280. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
  281. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
  282. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
  283. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
  284. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
  285. /* Add the op code for SDVO enhancements */
  286. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
  287. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
  288. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
  289. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
  290. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
  291. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
  292. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
  293. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
  294. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
  295. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
  296. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
  297. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
  298. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
  299. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
  300. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
  301. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
  302. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
  303. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
  304. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
  305. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
  306. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
  307. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
  308. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
  309. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
  310. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
  311. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
  312. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
  313. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
  314. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
  315. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
  316. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
  317. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
  318. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
  319. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
  320. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
  321. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
  322. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
  323. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
  324. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
  325. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
  326. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
  327. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
  328. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
  329. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
  330. /* HDMI op code */
  331. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
  332. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
  333. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
  334. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
  335. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
  336. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
  337. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
  338. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
  339. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
  340. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
  341. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
  342. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
  343. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
  344. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
  345. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
  346. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
  347. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
  348. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
  349. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
  350. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
  351. };
  352. #define IS_SDVOB(reg) (reg == SDVOB)
  353. #define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
  354. static void psb_intel_sdvo_debug_write(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd,
  355. const void *args, int args_len)
  356. {
  357. int i;
  358. DRM_DEBUG_KMS("%s: W: %02X ",
  359. SDVO_NAME(psb_intel_sdvo), cmd);
  360. for (i = 0; i < args_len; i++)
  361. DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
  362. for (; i < 8; i++)
  363. DRM_LOG_KMS(" ");
  364. for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
  365. if (cmd == sdvo_cmd_names[i].cmd) {
  366. DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
  367. break;
  368. }
  369. }
  370. if (i == ARRAY_SIZE(sdvo_cmd_names))
  371. DRM_LOG_KMS("(%02X)", cmd);
  372. DRM_LOG_KMS("\n");
  373. }
  374. static const char *cmd_status_names[] = {
  375. "Power on",
  376. "Success",
  377. "Not supported",
  378. "Invalid arg",
  379. "Pending",
  380. "Target not specified",
  381. "Scaling not supported"
  382. };
  383. static bool psb_intel_sdvo_write_cmd(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd,
  384. const void *args, int args_len)
  385. {
  386. u8 buf[args_len*2 + 2], status;
  387. struct i2c_msg msgs[args_len + 3];
  388. int i, ret;
  389. psb_intel_sdvo_debug_write(psb_intel_sdvo, cmd, args, args_len);
  390. for (i = 0; i < args_len; i++) {
  391. msgs[i].addr = psb_intel_sdvo->slave_addr;
  392. msgs[i].flags = 0;
  393. msgs[i].len = 2;
  394. msgs[i].buf = buf + 2 *i;
  395. buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
  396. buf[2*i + 1] = ((u8*)args)[i];
  397. }
  398. msgs[i].addr = psb_intel_sdvo->slave_addr;
  399. msgs[i].flags = 0;
  400. msgs[i].len = 2;
  401. msgs[i].buf = buf + 2*i;
  402. buf[2*i + 0] = SDVO_I2C_OPCODE;
  403. buf[2*i + 1] = cmd;
  404. /* the following two are to read the response */
  405. status = SDVO_I2C_CMD_STATUS;
  406. msgs[i+1].addr = psb_intel_sdvo->slave_addr;
  407. msgs[i+1].flags = 0;
  408. msgs[i+1].len = 1;
  409. msgs[i+1].buf = &status;
  410. msgs[i+2].addr = psb_intel_sdvo->slave_addr;
  411. msgs[i+2].flags = I2C_M_RD;
  412. msgs[i+2].len = 1;
  413. msgs[i+2].buf = &status;
  414. ret = i2c_transfer(psb_intel_sdvo->i2c, msgs, i+3);
  415. if (ret < 0) {
  416. DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
  417. return false;
  418. }
  419. if (ret != i+3) {
  420. /* failure in I2C transfer */
  421. DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
  422. return false;
  423. }
  424. return true;
  425. }
  426. static bool psb_intel_sdvo_read_response(struct psb_intel_sdvo *psb_intel_sdvo,
  427. void *response, int response_len)
  428. {
  429. u8 retry = 5;
  430. u8 status;
  431. int i;
  432. DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(psb_intel_sdvo));
  433. /*
  434. * The documentation states that all commands will be
  435. * processed within 15µs, and that we need only poll
  436. * the status byte a maximum of 3 times in order for the
  437. * command to be complete.
  438. *
  439. * Check 5 times in case the hardware failed to read the docs.
  440. */
  441. if (!psb_intel_sdvo_read_byte(psb_intel_sdvo,
  442. SDVO_I2C_CMD_STATUS,
  443. &status))
  444. goto log_fail;
  445. while (status == SDVO_CMD_STATUS_PENDING && retry--) {
  446. udelay(15);
  447. if (!psb_intel_sdvo_read_byte(psb_intel_sdvo,
  448. SDVO_I2C_CMD_STATUS,
  449. &status))
  450. goto log_fail;
  451. }
  452. if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
  453. DRM_LOG_KMS("(%s)", cmd_status_names[status]);
  454. else
  455. DRM_LOG_KMS("(??? %d)", status);
  456. if (status != SDVO_CMD_STATUS_SUCCESS)
  457. goto log_fail;
  458. /* Read the command response */
  459. for (i = 0; i < response_len; i++) {
  460. if (!psb_intel_sdvo_read_byte(psb_intel_sdvo,
  461. SDVO_I2C_RETURN_0 + i,
  462. &((u8 *)response)[i]))
  463. goto log_fail;
  464. DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
  465. }
  466. DRM_LOG_KMS("\n");
  467. return true;
  468. log_fail:
  469. DRM_LOG_KMS("... failed\n");
  470. return false;
  471. }
  472. static int psb_intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
  473. {
  474. if (mode->clock >= 100000)
  475. return 1;
  476. else if (mode->clock >= 50000)
  477. return 2;
  478. else
  479. return 4;
  480. }
  481. static bool psb_intel_sdvo_set_control_bus_switch(struct psb_intel_sdvo *psb_intel_sdvo,
  482. u8 ddc_bus)
  483. {
  484. /* This must be the immediately preceding write before the i2c xfer */
  485. return psb_intel_sdvo_write_cmd(psb_intel_sdvo,
  486. SDVO_CMD_SET_CONTROL_BUS_SWITCH,
  487. &ddc_bus, 1);
  488. }
  489. static bool psb_intel_sdvo_set_value(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd, const void *data, int len)
  490. {
  491. if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo, cmd, data, len))
  492. return false;
  493. return psb_intel_sdvo_read_response(psb_intel_sdvo, NULL, 0);
  494. }
  495. static bool
  496. psb_intel_sdvo_get_value(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd, void *value, int len)
  497. {
  498. if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo, cmd, NULL, 0))
  499. return false;
  500. return psb_intel_sdvo_read_response(psb_intel_sdvo, value, len);
  501. }
  502. static bool psb_intel_sdvo_set_target_input(struct psb_intel_sdvo *psb_intel_sdvo)
  503. {
  504. struct psb_intel_sdvo_set_target_input_args targets = {0};
  505. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  506. SDVO_CMD_SET_TARGET_INPUT,
  507. &targets, sizeof(targets));
  508. }
  509. /**
  510. * Return whether each input is trained.
  511. *
  512. * This function is making an assumption about the layout of the response,
  513. * which should be checked against the docs.
  514. */
  515. static bool psb_intel_sdvo_get_trained_inputs(struct psb_intel_sdvo *psb_intel_sdvo, bool *input_1, bool *input_2)
  516. {
  517. struct psb_intel_sdvo_get_trained_inputs_response response;
  518. BUILD_BUG_ON(sizeof(response) != 1);
  519. if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
  520. &response, sizeof(response)))
  521. return false;
  522. *input_1 = response.input0_trained;
  523. *input_2 = response.input1_trained;
  524. return true;
  525. }
  526. static bool psb_intel_sdvo_set_active_outputs(struct psb_intel_sdvo *psb_intel_sdvo,
  527. u16 outputs)
  528. {
  529. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  530. SDVO_CMD_SET_ACTIVE_OUTPUTS,
  531. &outputs, sizeof(outputs));
  532. }
  533. static bool psb_intel_sdvo_set_encoder_power_state(struct psb_intel_sdvo *psb_intel_sdvo,
  534. int mode)
  535. {
  536. u8 state = SDVO_ENCODER_STATE_ON;
  537. switch (mode) {
  538. case DRM_MODE_DPMS_ON:
  539. state = SDVO_ENCODER_STATE_ON;
  540. break;
  541. case DRM_MODE_DPMS_STANDBY:
  542. state = SDVO_ENCODER_STATE_STANDBY;
  543. break;
  544. case DRM_MODE_DPMS_SUSPEND:
  545. state = SDVO_ENCODER_STATE_SUSPEND;
  546. break;
  547. case DRM_MODE_DPMS_OFF:
  548. state = SDVO_ENCODER_STATE_OFF;
  549. break;
  550. }
  551. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  552. SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
  553. }
  554. static bool psb_intel_sdvo_get_input_pixel_clock_range(struct psb_intel_sdvo *psb_intel_sdvo,
  555. int *clock_min,
  556. int *clock_max)
  557. {
  558. struct psb_intel_sdvo_pixel_clock_range clocks;
  559. BUILD_BUG_ON(sizeof(clocks) != 4);
  560. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  561. SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
  562. &clocks, sizeof(clocks)))
  563. return false;
  564. /* Convert the values from units of 10 kHz to kHz. */
  565. *clock_min = clocks.min * 10;
  566. *clock_max = clocks.max * 10;
  567. return true;
  568. }
  569. static bool psb_intel_sdvo_set_target_output(struct psb_intel_sdvo *psb_intel_sdvo,
  570. u16 outputs)
  571. {
  572. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  573. SDVO_CMD_SET_TARGET_OUTPUT,
  574. &outputs, sizeof(outputs));
  575. }
  576. static bool psb_intel_sdvo_set_timing(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd,
  577. struct psb_intel_sdvo_dtd *dtd)
  578. {
  579. return psb_intel_sdvo_set_value(psb_intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
  580. psb_intel_sdvo_set_value(psb_intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  581. }
  582. static bool psb_intel_sdvo_set_input_timing(struct psb_intel_sdvo *psb_intel_sdvo,
  583. struct psb_intel_sdvo_dtd *dtd)
  584. {
  585. return psb_intel_sdvo_set_timing(psb_intel_sdvo,
  586. SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
  587. }
  588. static bool psb_intel_sdvo_set_output_timing(struct psb_intel_sdvo *psb_intel_sdvo,
  589. struct psb_intel_sdvo_dtd *dtd)
  590. {
  591. return psb_intel_sdvo_set_timing(psb_intel_sdvo,
  592. SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
  593. }
  594. static bool
  595. psb_intel_sdvo_create_preferred_input_timing(struct psb_intel_sdvo *psb_intel_sdvo,
  596. uint16_t clock,
  597. uint16_t width,
  598. uint16_t height)
  599. {
  600. struct psb_intel_sdvo_preferred_input_timing_args args;
  601. memset(&args, 0, sizeof(args));
  602. args.clock = clock;
  603. args.width = width;
  604. args.height = height;
  605. args.interlace = 0;
  606. if (psb_intel_sdvo->is_lvds &&
  607. (psb_intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
  608. psb_intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
  609. args.scaled = 1;
  610. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  611. SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
  612. &args, sizeof(args));
  613. }
  614. static bool psb_intel_sdvo_get_preferred_input_timing(struct psb_intel_sdvo *psb_intel_sdvo,
  615. struct psb_intel_sdvo_dtd *dtd)
  616. {
  617. BUILD_BUG_ON(sizeof(dtd->part1) != 8);
  618. BUILD_BUG_ON(sizeof(dtd->part2) != 8);
  619. return psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
  620. &dtd->part1, sizeof(dtd->part1)) &&
  621. psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
  622. &dtd->part2, sizeof(dtd->part2));
  623. }
  624. static bool psb_intel_sdvo_set_clock_rate_mult(struct psb_intel_sdvo *psb_intel_sdvo, u8 val)
  625. {
  626. return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
  627. }
  628. static void psb_intel_sdvo_get_dtd_from_mode(struct psb_intel_sdvo_dtd *dtd,
  629. const struct drm_display_mode *mode)
  630. {
  631. uint16_t width, height;
  632. uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
  633. uint16_t h_sync_offset, v_sync_offset;
  634. width = mode->crtc_hdisplay;
  635. height = mode->crtc_vdisplay;
  636. /* do some mode translations */
  637. h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
  638. h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
  639. v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
  640. v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
  641. h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
  642. v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
  643. dtd->part1.clock = mode->clock / 10;
  644. dtd->part1.h_active = width & 0xff;
  645. dtd->part1.h_blank = h_blank_len & 0xff;
  646. dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
  647. ((h_blank_len >> 8) & 0xf);
  648. dtd->part1.v_active = height & 0xff;
  649. dtd->part1.v_blank = v_blank_len & 0xff;
  650. dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
  651. ((v_blank_len >> 8) & 0xf);
  652. dtd->part2.h_sync_off = h_sync_offset & 0xff;
  653. dtd->part2.h_sync_width = h_sync_len & 0xff;
  654. dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
  655. (v_sync_len & 0xf);
  656. dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
  657. ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
  658. ((v_sync_len & 0x30) >> 4);
  659. dtd->part2.dtd_flags = 0x18;
  660. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  661. dtd->part2.dtd_flags |= 0x2;
  662. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  663. dtd->part2.dtd_flags |= 0x4;
  664. dtd->part2.sdvo_flags = 0;
  665. dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
  666. dtd->part2.reserved = 0;
  667. }
  668. static void psb_intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
  669. const struct psb_intel_sdvo_dtd *dtd)
  670. {
  671. mode->hdisplay = dtd->part1.h_active;
  672. mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
  673. mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
  674. mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
  675. mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
  676. mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
  677. mode->htotal = mode->hdisplay + dtd->part1.h_blank;
  678. mode->htotal += (dtd->part1.h_high & 0xf) << 8;
  679. mode->vdisplay = dtd->part1.v_active;
  680. mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
  681. mode->vsync_start = mode->vdisplay;
  682. mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
  683. mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
  684. mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
  685. mode->vsync_end = mode->vsync_start +
  686. (dtd->part2.v_sync_off_width & 0xf);
  687. mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
  688. mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
  689. mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
  690. mode->clock = dtd->part1.clock * 10;
  691. mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
  692. if (dtd->part2.dtd_flags & 0x2)
  693. mode->flags |= DRM_MODE_FLAG_PHSYNC;
  694. if (dtd->part2.dtd_flags & 0x4)
  695. mode->flags |= DRM_MODE_FLAG_PVSYNC;
  696. }
  697. static bool psb_intel_sdvo_check_supp_encode(struct psb_intel_sdvo *psb_intel_sdvo)
  698. {
  699. struct psb_intel_sdvo_encode encode;
  700. BUILD_BUG_ON(sizeof(encode) != 2);
  701. return psb_intel_sdvo_get_value(psb_intel_sdvo,
  702. SDVO_CMD_GET_SUPP_ENCODE,
  703. &encode, sizeof(encode));
  704. }
  705. static bool psb_intel_sdvo_set_encode(struct psb_intel_sdvo *psb_intel_sdvo,
  706. uint8_t mode)
  707. {
  708. return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
  709. }
  710. static bool psb_intel_sdvo_set_colorimetry(struct psb_intel_sdvo *psb_intel_sdvo,
  711. uint8_t mode)
  712. {
  713. return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
  714. }
  715. #if 0
  716. static void psb_intel_sdvo_dump_hdmi_buf(struct psb_intel_sdvo *psb_intel_sdvo)
  717. {
  718. int i, j;
  719. uint8_t set_buf_index[2];
  720. uint8_t av_split;
  721. uint8_t buf_size;
  722. uint8_t buf[48];
  723. uint8_t *pos;
  724. psb_intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
  725. for (i = 0; i <= av_split; i++) {
  726. set_buf_index[0] = i; set_buf_index[1] = 0;
  727. psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
  728. set_buf_index, 2);
  729. psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
  730. psb_intel_sdvo_read_response(encoder, &buf_size, 1);
  731. pos = buf;
  732. for (j = 0; j <= buf_size; j += 8) {
  733. psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
  734. NULL, 0);
  735. psb_intel_sdvo_read_response(encoder, pos, 8);
  736. pos += 8;
  737. }
  738. }
  739. }
  740. #endif
  741. static bool psb_intel_sdvo_set_avi_infoframe(struct psb_intel_sdvo *psb_intel_sdvo)
  742. {
  743. DRM_INFO("HDMI is not supported yet");
  744. return false;
  745. #if 0
  746. struct dip_infoframe avi_if = {
  747. .type = DIP_TYPE_AVI,
  748. .ver = DIP_VERSION_AVI,
  749. .len = DIP_LEN_AVI,
  750. };
  751. uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
  752. uint8_t set_buf_index[2] = { 1, 0 };
  753. uint64_t *data = (uint64_t *)&avi_if;
  754. unsigned i;
  755. intel_dip_infoframe_csum(&avi_if);
  756. if (!psb_intel_sdvo_set_value(psb_intel_sdvo,
  757. SDVO_CMD_SET_HBUF_INDEX,
  758. set_buf_index, 2))
  759. return false;
  760. for (i = 0; i < sizeof(avi_if); i += 8) {
  761. if (!psb_intel_sdvo_set_value(psb_intel_sdvo,
  762. SDVO_CMD_SET_HBUF_DATA,
  763. data, 8))
  764. return false;
  765. data++;
  766. }
  767. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  768. SDVO_CMD_SET_HBUF_TXRATE,
  769. &tx_rate, 1);
  770. #endif
  771. }
  772. static bool psb_intel_sdvo_set_tv_format(struct psb_intel_sdvo *psb_intel_sdvo)
  773. {
  774. struct psb_intel_sdvo_tv_format format;
  775. uint32_t format_map;
  776. format_map = 1 << psb_intel_sdvo->tv_format_index;
  777. memset(&format, 0, sizeof(format));
  778. memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
  779. BUILD_BUG_ON(sizeof(format) != 6);
  780. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  781. SDVO_CMD_SET_TV_FORMAT,
  782. &format, sizeof(format));
  783. }
  784. static bool
  785. psb_intel_sdvo_set_output_timings_from_mode(struct psb_intel_sdvo *psb_intel_sdvo,
  786. const struct drm_display_mode *mode)
  787. {
  788. struct psb_intel_sdvo_dtd output_dtd;
  789. if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo,
  790. psb_intel_sdvo->attached_output))
  791. return false;
  792. psb_intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  793. if (!psb_intel_sdvo_set_output_timing(psb_intel_sdvo, &output_dtd))
  794. return false;
  795. return true;
  796. }
  797. static bool
  798. psb_intel_sdvo_set_input_timings_for_mode(struct psb_intel_sdvo *psb_intel_sdvo,
  799. const struct drm_display_mode *mode,
  800. struct drm_display_mode *adjusted_mode)
  801. {
  802. /* Reset the input timing to the screen. Assume always input 0. */
  803. if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo))
  804. return false;
  805. if (!psb_intel_sdvo_create_preferred_input_timing(psb_intel_sdvo,
  806. mode->clock / 10,
  807. mode->hdisplay,
  808. mode->vdisplay))
  809. return false;
  810. if (!psb_intel_sdvo_get_preferred_input_timing(psb_intel_sdvo,
  811. &psb_intel_sdvo->input_dtd))
  812. return false;
  813. psb_intel_sdvo_get_mode_from_dtd(adjusted_mode, &psb_intel_sdvo->input_dtd);
  814. drm_mode_set_crtcinfo(adjusted_mode, 0);
  815. return true;
  816. }
  817. static bool psb_intel_sdvo_mode_fixup(struct drm_encoder *encoder,
  818. const struct drm_display_mode *mode,
  819. struct drm_display_mode *adjusted_mode)
  820. {
  821. struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
  822. int multiplier;
  823. /* We need to construct preferred input timings based on our
  824. * output timings. To do that, we have to set the output
  825. * timings, even though this isn't really the right place in
  826. * the sequence to do it. Oh well.
  827. */
  828. if (psb_intel_sdvo->is_tv) {
  829. if (!psb_intel_sdvo_set_output_timings_from_mode(psb_intel_sdvo, mode))
  830. return false;
  831. (void) psb_intel_sdvo_set_input_timings_for_mode(psb_intel_sdvo,
  832. mode,
  833. adjusted_mode);
  834. } else if (psb_intel_sdvo->is_lvds) {
  835. if (!psb_intel_sdvo_set_output_timings_from_mode(psb_intel_sdvo,
  836. psb_intel_sdvo->sdvo_lvds_fixed_mode))
  837. return false;
  838. (void) psb_intel_sdvo_set_input_timings_for_mode(psb_intel_sdvo,
  839. mode,
  840. adjusted_mode);
  841. }
  842. /* Make the CRTC code factor in the SDVO pixel multiplier. The
  843. * SDVO device will factor out the multiplier during mode_set.
  844. */
  845. multiplier = psb_intel_sdvo_get_pixel_multiplier(adjusted_mode);
  846. psb_intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
  847. return true;
  848. }
  849. static void psb_intel_sdvo_mode_set(struct drm_encoder *encoder,
  850. struct drm_display_mode *mode,
  851. struct drm_display_mode *adjusted_mode)
  852. {
  853. struct drm_device *dev = encoder->dev;
  854. struct drm_crtc *crtc = encoder->crtc;
  855. struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
  856. struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
  857. u32 sdvox;
  858. struct psb_intel_sdvo_in_out_map in_out;
  859. struct psb_intel_sdvo_dtd input_dtd;
  860. int pixel_multiplier = psb_intel_mode_get_pixel_multiplier(adjusted_mode);
  861. int rate;
  862. if (!mode)
  863. return;
  864. /* First, set the input mapping for the first input to our controlled
  865. * output. This is only correct if we're a single-input device, in
  866. * which case the first input is the output from the appropriate SDVO
  867. * channel on the motherboard. In a two-input device, the first input
  868. * will be SDVOB and the second SDVOC.
  869. */
  870. in_out.in0 = psb_intel_sdvo->attached_output;
  871. in_out.in1 = 0;
  872. psb_intel_sdvo_set_value(psb_intel_sdvo,
  873. SDVO_CMD_SET_IN_OUT_MAP,
  874. &in_out, sizeof(in_out));
  875. /* Set the output timings to the screen */
  876. if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo,
  877. psb_intel_sdvo->attached_output))
  878. return;
  879. /* We have tried to get input timing in mode_fixup, and filled into
  880. * adjusted_mode.
  881. */
  882. if (psb_intel_sdvo->is_tv || psb_intel_sdvo->is_lvds) {
  883. input_dtd = psb_intel_sdvo->input_dtd;
  884. } else {
  885. /* Set the output timing to the screen */
  886. if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo,
  887. psb_intel_sdvo->attached_output))
  888. return;
  889. psb_intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
  890. (void) psb_intel_sdvo_set_output_timing(psb_intel_sdvo, &input_dtd);
  891. }
  892. /* Set the input timing to the screen. Assume always input 0. */
  893. if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo))
  894. return;
  895. if (psb_intel_sdvo->has_hdmi_monitor) {
  896. psb_intel_sdvo_set_encode(psb_intel_sdvo, SDVO_ENCODE_HDMI);
  897. psb_intel_sdvo_set_colorimetry(psb_intel_sdvo,
  898. SDVO_COLORIMETRY_RGB256);
  899. psb_intel_sdvo_set_avi_infoframe(psb_intel_sdvo);
  900. } else
  901. psb_intel_sdvo_set_encode(psb_intel_sdvo, SDVO_ENCODE_DVI);
  902. if (psb_intel_sdvo->is_tv &&
  903. !psb_intel_sdvo_set_tv_format(psb_intel_sdvo))
  904. return;
  905. (void) psb_intel_sdvo_set_input_timing(psb_intel_sdvo, &input_dtd);
  906. switch (pixel_multiplier) {
  907. default:
  908. case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
  909. case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
  910. case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
  911. }
  912. if (!psb_intel_sdvo_set_clock_rate_mult(psb_intel_sdvo, rate))
  913. return;
  914. /* Set the SDVO control regs. */
  915. sdvox = REG_READ(psb_intel_sdvo->sdvo_reg);
  916. switch (psb_intel_sdvo->sdvo_reg) {
  917. case SDVOB:
  918. sdvox &= SDVOB_PRESERVE_MASK;
  919. break;
  920. case SDVOC:
  921. sdvox &= SDVOC_PRESERVE_MASK;
  922. break;
  923. }
  924. sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
  925. if (gma_crtc->pipe == 1)
  926. sdvox |= SDVO_PIPE_B_SELECT;
  927. if (psb_intel_sdvo->has_hdmi_audio)
  928. sdvox |= SDVO_AUDIO_ENABLE;
  929. /* FIXME: Check if this is needed for PSB
  930. sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
  931. */
  932. if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL)
  933. sdvox |= SDVO_STALL_SELECT;
  934. psb_intel_sdvo_write_sdvox(psb_intel_sdvo, sdvox);
  935. }
  936. static void psb_intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
  937. {
  938. struct drm_device *dev = encoder->dev;
  939. struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
  940. u32 temp;
  941. switch (mode) {
  942. case DRM_MODE_DPMS_ON:
  943. DRM_DEBUG("DPMS_ON");
  944. break;
  945. case DRM_MODE_DPMS_OFF:
  946. DRM_DEBUG("DPMS_OFF");
  947. break;
  948. default:
  949. DRM_DEBUG("DPMS: %d", mode);
  950. }
  951. if (mode != DRM_MODE_DPMS_ON) {
  952. psb_intel_sdvo_set_active_outputs(psb_intel_sdvo, 0);
  953. if (0)
  954. psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode);
  955. if (mode == DRM_MODE_DPMS_OFF) {
  956. temp = REG_READ(psb_intel_sdvo->sdvo_reg);
  957. if ((temp & SDVO_ENABLE) != 0) {
  958. psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp & ~SDVO_ENABLE);
  959. }
  960. }
  961. } else {
  962. bool input1, input2;
  963. int i;
  964. u8 status;
  965. temp = REG_READ(psb_intel_sdvo->sdvo_reg);
  966. if ((temp & SDVO_ENABLE) == 0)
  967. psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp | SDVO_ENABLE);
  968. for (i = 0; i < 2; i++)
  969. gma_wait_for_vblank(dev);
  970. status = psb_intel_sdvo_get_trained_inputs(psb_intel_sdvo, &input1, &input2);
  971. /* Warn if the device reported failure to sync.
  972. * A lot of SDVO devices fail to notify of sync, but it's
  973. * a given it the status is a success, we succeeded.
  974. */
  975. if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
  976. DRM_DEBUG_KMS("First %s output reported failure to "
  977. "sync\n", SDVO_NAME(psb_intel_sdvo));
  978. }
  979. if (0)
  980. psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode);
  981. psb_intel_sdvo_set_active_outputs(psb_intel_sdvo, psb_intel_sdvo->attached_output);
  982. }
  983. return;
  984. }
  985. static int psb_intel_sdvo_mode_valid(struct drm_connector *connector,
  986. struct drm_display_mode *mode)
  987. {
  988. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  989. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  990. return MODE_NO_DBLESCAN;
  991. if (psb_intel_sdvo->pixel_clock_min > mode->clock)
  992. return MODE_CLOCK_LOW;
  993. if (psb_intel_sdvo->pixel_clock_max < mode->clock)
  994. return MODE_CLOCK_HIGH;
  995. if (psb_intel_sdvo->is_lvds) {
  996. if (mode->hdisplay > psb_intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
  997. return MODE_PANEL;
  998. if (mode->vdisplay > psb_intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
  999. return MODE_PANEL;
  1000. }
  1001. return MODE_OK;
  1002. }
  1003. static bool psb_intel_sdvo_get_capabilities(struct psb_intel_sdvo *psb_intel_sdvo, struct psb_intel_sdvo_caps *caps)
  1004. {
  1005. BUILD_BUG_ON(sizeof(*caps) != 8);
  1006. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  1007. SDVO_CMD_GET_DEVICE_CAPS,
  1008. caps, sizeof(*caps)))
  1009. return false;
  1010. DRM_DEBUG_KMS("SDVO capabilities:\n"
  1011. " vendor_id: %d\n"
  1012. " device_id: %d\n"
  1013. " device_rev_id: %d\n"
  1014. " sdvo_version_major: %d\n"
  1015. " sdvo_version_minor: %d\n"
  1016. " sdvo_inputs_mask: %d\n"
  1017. " smooth_scaling: %d\n"
  1018. " sharp_scaling: %d\n"
  1019. " up_scaling: %d\n"
  1020. " down_scaling: %d\n"
  1021. " stall_support: %d\n"
  1022. " output_flags: %d\n",
  1023. caps->vendor_id,
  1024. caps->device_id,
  1025. caps->device_rev_id,
  1026. caps->sdvo_version_major,
  1027. caps->sdvo_version_minor,
  1028. caps->sdvo_inputs_mask,
  1029. caps->smooth_scaling,
  1030. caps->sharp_scaling,
  1031. caps->up_scaling,
  1032. caps->down_scaling,
  1033. caps->stall_support,
  1034. caps->output_flags);
  1035. return true;
  1036. }
  1037. /* No use! */
  1038. #if 0
  1039. struct drm_connector* psb_intel_sdvo_find(struct drm_device *dev, int sdvoB)
  1040. {
  1041. struct drm_connector *connector = NULL;
  1042. struct psb_intel_sdvo *iout = NULL;
  1043. struct psb_intel_sdvo *sdvo;
  1044. /* find the sdvo connector */
  1045. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  1046. iout = to_psb_intel_sdvo(connector);
  1047. if (iout->type != INTEL_OUTPUT_SDVO)
  1048. continue;
  1049. sdvo = iout->dev_priv;
  1050. if (sdvo->sdvo_reg == SDVOB && sdvoB)
  1051. return connector;
  1052. if (sdvo->sdvo_reg == SDVOC && !sdvoB)
  1053. return connector;
  1054. }
  1055. return NULL;
  1056. }
  1057. int psb_intel_sdvo_supports_hotplug(struct drm_connector *connector)
  1058. {
  1059. u8 response[2];
  1060. u8 status;
  1061. struct psb_intel_sdvo *psb_intel_sdvo;
  1062. DRM_DEBUG_KMS("\n");
  1063. if (!connector)
  1064. return 0;
  1065. psb_intel_sdvo = to_psb_intel_sdvo(connector);
  1066. return psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
  1067. &response, 2) && response[0];
  1068. }
  1069. void psb_intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
  1070. {
  1071. u8 response[2];
  1072. u8 status;
  1073. struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(connector);
  1074. psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
  1075. psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2);
  1076. if (on) {
  1077. psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
  1078. status = psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2);
  1079. psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
  1080. } else {
  1081. response[0] = 0;
  1082. response[1] = 0;
  1083. psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
  1084. }
  1085. psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
  1086. psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2);
  1087. }
  1088. #endif
  1089. static bool
  1090. psb_intel_sdvo_multifunc_encoder(struct psb_intel_sdvo *psb_intel_sdvo)
  1091. {
  1092. /* Is there more than one type of output? */
  1093. int caps = psb_intel_sdvo->caps.output_flags & 0xf;
  1094. return caps & -caps;
  1095. }
  1096. static struct edid *
  1097. psb_intel_sdvo_get_edid(struct drm_connector *connector)
  1098. {
  1099. struct psb_intel_sdvo *sdvo = intel_attached_sdvo(connector);
  1100. return drm_get_edid(connector, &sdvo->ddc);
  1101. }
  1102. /* Mac mini hack -- use the same DDC as the analog connector */
  1103. static struct edid *
  1104. psb_intel_sdvo_get_analog_edid(struct drm_connector *connector)
  1105. {
  1106. struct drm_psb_private *dev_priv = connector->dev->dev_private;
  1107. return drm_get_edid(connector,
  1108. &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
  1109. }
  1110. static enum drm_connector_status
  1111. psb_intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
  1112. {
  1113. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1114. enum drm_connector_status status;
  1115. struct edid *edid;
  1116. edid = psb_intel_sdvo_get_edid(connector);
  1117. if (edid == NULL && psb_intel_sdvo_multifunc_encoder(psb_intel_sdvo)) {
  1118. u8 ddc, saved_ddc = psb_intel_sdvo->ddc_bus;
  1119. /*
  1120. * Don't use the 1 as the argument of DDC bus switch to get
  1121. * the EDID. It is used for SDVO SPD ROM.
  1122. */
  1123. for (ddc = psb_intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
  1124. psb_intel_sdvo->ddc_bus = ddc;
  1125. edid = psb_intel_sdvo_get_edid(connector);
  1126. if (edid)
  1127. break;
  1128. }
  1129. /*
  1130. * If we found the EDID on the other bus,
  1131. * assume that is the correct DDC bus.
  1132. */
  1133. if (edid == NULL)
  1134. psb_intel_sdvo->ddc_bus = saved_ddc;
  1135. }
  1136. /*
  1137. * When there is no edid and no monitor is connected with VGA
  1138. * port, try to use the CRT ddc to read the EDID for DVI-connector.
  1139. */
  1140. if (edid == NULL)
  1141. edid = psb_intel_sdvo_get_analog_edid(connector);
  1142. status = connector_status_unknown;
  1143. if (edid != NULL) {
  1144. /* DDC bus is shared, match EDID to connector type */
  1145. if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  1146. status = connector_status_connected;
  1147. if (psb_intel_sdvo->is_hdmi) {
  1148. psb_intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
  1149. psb_intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
  1150. }
  1151. } else
  1152. status = connector_status_disconnected;
  1153. kfree(edid);
  1154. }
  1155. if (status == connector_status_connected) {
  1156. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1157. if (psb_intel_sdvo_connector->force_audio)
  1158. psb_intel_sdvo->has_hdmi_audio = psb_intel_sdvo_connector->force_audio > 0;
  1159. }
  1160. return status;
  1161. }
  1162. static enum drm_connector_status
  1163. psb_intel_sdvo_detect(struct drm_connector *connector, bool force)
  1164. {
  1165. uint16_t response;
  1166. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1167. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1168. enum drm_connector_status ret;
  1169. if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo,
  1170. SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
  1171. return connector_status_unknown;
  1172. /* add 30ms delay when the output type might be TV */
  1173. if (psb_intel_sdvo->caps.output_flags &
  1174. (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0))
  1175. mdelay(30);
  1176. if (!psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2))
  1177. return connector_status_unknown;
  1178. DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
  1179. response & 0xff, response >> 8,
  1180. psb_intel_sdvo_connector->output_flag);
  1181. if (response == 0)
  1182. return connector_status_disconnected;
  1183. psb_intel_sdvo->attached_output = response;
  1184. psb_intel_sdvo->has_hdmi_monitor = false;
  1185. psb_intel_sdvo->has_hdmi_audio = false;
  1186. if ((psb_intel_sdvo_connector->output_flag & response) == 0)
  1187. ret = connector_status_disconnected;
  1188. else if (IS_TMDS(psb_intel_sdvo_connector))
  1189. ret = psb_intel_sdvo_hdmi_sink_detect(connector);
  1190. else {
  1191. struct edid *edid;
  1192. /* if we have an edid check it matches the connection */
  1193. edid = psb_intel_sdvo_get_edid(connector);
  1194. if (edid == NULL)
  1195. edid = psb_intel_sdvo_get_analog_edid(connector);
  1196. if (edid != NULL) {
  1197. if (edid->input & DRM_EDID_INPUT_DIGITAL)
  1198. ret = connector_status_disconnected;
  1199. else
  1200. ret = connector_status_connected;
  1201. kfree(edid);
  1202. } else
  1203. ret = connector_status_connected;
  1204. }
  1205. /* May update encoder flag for like clock for SDVO TV, etc.*/
  1206. if (ret == connector_status_connected) {
  1207. psb_intel_sdvo->is_tv = false;
  1208. psb_intel_sdvo->is_lvds = false;
  1209. psb_intel_sdvo->base.needs_tv_clock = false;
  1210. if (response & SDVO_TV_MASK) {
  1211. psb_intel_sdvo->is_tv = true;
  1212. psb_intel_sdvo->base.needs_tv_clock = true;
  1213. }
  1214. if (response & SDVO_LVDS_MASK)
  1215. psb_intel_sdvo->is_lvds = psb_intel_sdvo->sdvo_lvds_fixed_mode != NULL;
  1216. }
  1217. return ret;
  1218. }
  1219. static void psb_intel_sdvo_get_ddc_modes(struct drm_connector *connector)
  1220. {
  1221. struct edid *edid;
  1222. /* set the bus switch and get the modes */
  1223. edid = psb_intel_sdvo_get_edid(connector);
  1224. /*
  1225. * Mac mini hack. On this device, the DVI-I connector shares one DDC
  1226. * link between analog and digital outputs. So, if the regular SDVO
  1227. * DDC fails, check to see if the analog output is disconnected, in
  1228. * which case we'll look there for the digital DDC data.
  1229. */
  1230. if (edid == NULL)
  1231. edid = psb_intel_sdvo_get_analog_edid(connector);
  1232. if (edid != NULL) {
  1233. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1234. bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
  1235. bool connector_is_digital = !!IS_TMDS(psb_intel_sdvo_connector);
  1236. if (connector_is_digital == monitor_is_digital) {
  1237. drm_mode_connector_update_edid_property(connector, edid);
  1238. drm_add_edid_modes(connector, edid);
  1239. }
  1240. kfree(edid);
  1241. }
  1242. }
  1243. /*
  1244. * Set of SDVO TV modes.
  1245. * Note! This is in reply order (see loop in get_tv_modes).
  1246. * XXX: all 60Hz refresh?
  1247. */
  1248. static const struct drm_display_mode sdvo_tv_modes[] = {
  1249. { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
  1250. 416, 0, 200, 201, 232, 233, 0,
  1251. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1252. { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
  1253. 416, 0, 240, 241, 272, 273, 0,
  1254. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1255. { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
  1256. 496, 0, 300, 301, 332, 333, 0,
  1257. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1258. { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
  1259. 736, 0, 350, 351, 382, 383, 0,
  1260. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1261. { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
  1262. 736, 0, 400, 401, 432, 433, 0,
  1263. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1264. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
  1265. 736, 0, 480, 481, 512, 513, 0,
  1266. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1267. { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
  1268. 800, 0, 480, 481, 512, 513, 0,
  1269. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1270. { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
  1271. 800, 0, 576, 577, 608, 609, 0,
  1272. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1273. { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
  1274. 816, 0, 350, 351, 382, 383, 0,
  1275. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1276. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
  1277. 816, 0, 400, 401, 432, 433, 0,
  1278. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1279. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
  1280. 816, 0, 480, 481, 512, 513, 0,
  1281. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1282. { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
  1283. 816, 0, 540, 541, 572, 573, 0,
  1284. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1285. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
  1286. 816, 0, 576, 577, 608, 609, 0,
  1287. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1288. { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
  1289. 864, 0, 576, 577, 608, 609, 0,
  1290. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1291. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
  1292. 896, 0, 600, 601, 632, 633, 0,
  1293. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1294. { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
  1295. 928, 0, 624, 625, 656, 657, 0,
  1296. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1297. { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
  1298. 1016, 0, 766, 767, 798, 799, 0,
  1299. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1300. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
  1301. 1120, 0, 768, 769, 800, 801, 0,
  1302. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1303. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
  1304. 1376, 0, 1024, 1025, 1056, 1057, 0,
  1305. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1306. };
  1307. static void psb_intel_sdvo_get_tv_modes(struct drm_connector *connector)
  1308. {
  1309. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1310. struct psb_intel_sdvo_sdtv_resolution_request tv_res;
  1311. uint32_t reply = 0, format_map = 0;
  1312. int i;
  1313. /* Read the list of supported input resolutions for the selected TV
  1314. * format.
  1315. */
  1316. format_map = 1 << psb_intel_sdvo->tv_format_index;
  1317. memcpy(&tv_res, &format_map,
  1318. min(sizeof(format_map), sizeof(struct psb_intel_sdvo_sdtv_resolution_request)));
  1319. if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo, psb_intel_sdvo->attached_output))
  1320. return;
  1321. BUILD_BUG_ON(sizeof(tv_res) != 3);
  1322. if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo,
  1323. SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
  1324. &tv_res, sizeof(tv_res)))
  1325. return;
  1326. if (!psb_intel_sdvo_read_response(psb_intel_sdvo, &reply, 3))
  1327. return;
  1328. for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
  1329. if (reply & (1 << i)) {
  1330. struct drm_display_mode *nmode;
  1331. nmode = drm_mode_duplicate(connector->dev,
  1332. &sdvo_tv_modes[i]);
  1333. if (nmode)
  1334. drm_mode_probed_add(connector, nmode);
  1335. }
  1336. }
  1337. static void psb_intel_sdvo_get_lvds_modes(struct drm_connector *connector)
  1338. {
  1339. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1340. struct drm_psb_private *dev_priv = connector->dev->dev_private;
  1341. struct drm_display_mode *newmode;
  1342. /*
  1343. * Attempt to get the mode list from DDC.
  1344. * Assume that the preferred modes are
  1345. * arranged in priority order.
  1346. */
  1347. psb_intel_ddc_get_modes(connector, psb_intel_sdvo->i2c);
  1348. if (list_empty(&connector->probed_modes) == false)
  1349. goto end;
  1350. /* Fetch modes from VBT */
  1351. if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
  1352. newmode = drm_mode_duplicate(connector->dev,
  1353. dev_priv->sdvo_lvds_vbt_mode);
  1354. if (newmode != NULL) {
  1355. /* Guarantee the mode is preferred */
  1356. newmode->type = (DRM_MODE_TYPE_PREFERRED |
  1357. DRM_MODE_TYPE_DRIVER);
  1358. drm_mode_probed_add(connector, newmode);
  1359. }
  1360. }
  1361. end:
  1362. list_for_each_entry(newmode, &connector->probed_modes, head) {
  1363. if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
  1364. psb_intel_sdvo->sdvo_lvds_fixed_mode =
  1365. drm_mode_duplicate(connector->dev, newmode);
  1366. drm_mode_set_crtcinfo(psb_intel_sdvo->sdvo_lvds_fixed_mode,
  1367. 0);
  1368. psb_intel_sdvo->is_lvds = true;
  1369. break;
  1370. }
  1371. }
  1372. }
  1373. static int psb_intel_sdvo_get_modes(struct drm_connector *connector)
  1374. {
  1375. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1376. if (IS_TV(psb_intel_sdvo_connector))
  1377. psb_intel_sdvo_get_tv_modes(connector);
  1378. else if (IS_LVDS(psb_intel_sdvo_connector))
  1379. psb_intel_sdvo_get_lvds_modes(connector);
  1380. else
  1381. psb_intel_sdvo_get_ddc_modes(connector);
  1382. return !list_empty(&connector->probed_modes);
  1383. }
  1384. static void
  1385. psb_intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
  1386. {
  1387. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1388. struct drm_device *dev = connector->dev;
  1389. if (psb_intel_sdvo_connector->left)
  1390. drm_property_destroy(dev, psb_intel_sdvo_connector->left);
  1391. if (psb_intel_sdvo_connector->right)
  1392. drm_property_destroy(dev, psb_intel_sdvo_connector->right);
  1393. if (psb_intel_sdvo_connector->top)
  1394. drm_property_destroy(dev, psb_intel_sdvo_connector->top);
  1395. if (psb_intel_sdvo_connector->bottom)
  1396. drm_property_destroy(dev, psb_intel_sdvo_connector->bottom);
  1397. if (psb_intel_sdvo_connector->hpos)
  1398. drm_property_destroy(dev, psb_intel_sdvo_connector->hpos);
  1399. if (psb_intel_sdvo_connector->vpos)
  1400. drm_property_destroy(dev, psb_intel_sdvo_connector->vpos);
  1401. if (psb_intel_sdvo_connector->saturation)
  1402. drm_property_destroy(dev, psb_intel_sdvo_connector->saturation);
  1403. if (psb_intel_sdvo_connector->contrast)
  1404. drm_property_destroy(dev, psb_intel_sdvo_connector->contrast);
  1405. if (psb_intel_sdvo_connector->hue)
  1406. drm_property_destroy(dev, psb_intel_sdvo_connector->hue);
  1407. if (psb_intel_sdvo_connector->sharpness)
  1408. drm_property_destroy(dev, psb_intel_sdvo_connector->sharpness);
  1409. if (psb_intel_sdvo_connector->flicker_filter)
  1410. drm_property_destroy(dev, psb_intel_sdvo_connector->flicker_filter);
  1411. if (psb_intel_sdvo_connector->flicker_filter_2d)
  1412. drm_property_destroy(dev, psb_intel_sdvo_connector->flicker_filter_2d);
  1413. if (psb_intel_sdvo_connector->flicker_filter_adaptive)
  1414. drm_property_destroy(dev, psb_intel_sdvo_connector->flicker_filter_adaptive);
  1415. if (psb_intel_sdvo_connector->tv_luma_filter)
  1416. drm_property_destroy(dev, psb_intel_sdvo_connector->tv_luma_filter);
  1417. if (psb_intel_sdvo_connector->tv_chroma_filter)
  1418. drm_property_destroy(dev, psb_intel_sdvo_connector->tv_chroma_filter);
  1419. if (psb_intel_sdvo_connector->dot_crawl)
  1420. drm_property_destroy(dev, psb_intel_sdvo_connector->dot_crawl);
  1421. if (psb_intel_sdvo_connector->brightness)
  1422. drm_property_destroy(dev, psb_intel_sdvo_connector->brightness);
  1423. }
  1424. static void psb_intel_sdvo_destroy(struct drm_connector *connector)
  1425. {
  1426. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1427. if (psb_intel_sdvo_connector->tv_format)
  1428. drm_property_destroy(connector->dev,
  1429. psb_intel_sdvo_connector->tv_format);
  1430. psb_intel_sdvo_destroy_enhance_property(connector);
  1431. drm_sysfs_connector_remove(connector);
  1432. drm_connector_cleanup(connector);
  1433. kfree(connector);
  1434. }
  1435. static bool psb_intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
  1436. {
  1437. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1438. struct edid *edid;
  1439. bool has_audio = false;
  1440. if (!psb_intel_sdvo->is_hdmi)
  1441. return false;
  1442. edid = psb_intel_sdvo_get_edid(connector);
  1443. if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
  1444. has_audio = drm_detect_monitor_audio(edid);
  1445. return has_audio;
  1446. }
  1447. static int
  1448. psb_intel_sdvo_set_property(struct drm_connector *connector,
  1449. struct drm_property *property,
  1450. uint64_t val)
  1451. {
  1452. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1453. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1454. struct drm_psb_private *dev_priv = connector->dev->dev_private;
  1455. uint16_t temp_value;
  1456. uint8_t cmd;
  1457. int ret;
  1458. ret = drm_object_property_set_value(&connector->base, property, val);
  1459. if (ret)
  1460. return ret;
  1461. if (property == dev_priv->force_audio_property) {
  1462. int i = val;
  1463. bool has_audio;
  1464. if (i == psb_intel_sdvo_connector->force_audio)
  1465. return 0;
  1466. psb_intel_sdvo_connector->force_audio = i;
  1467. if (i == 0)
  1468. has_audio = psb_intel_sdvo_detect_hdmi_audio(connector);
  1469. else
  1470. has_audio = i > 0;
  1471. if (has_audio == psb_intel_sdvo->has_hdmi_audio)
  1472. return 0;
  1473. psb_intel_sdvo->has_hdmi_audio = has_audio;
  1474. goto done;
  1475. }
  1476. if (property == dev_priv->broadcast_rgb_property) {
  1477. if (val == !!psb_intel_sdvo->color_range)
  1478. return 0;
  1479. psb_intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
  1480. goto done;
  1481. }
  1482. #define CHECK_PROPERTY(name, NAME) \
  1483. if (psb_intel_sdvo_connector->name == property) { \
  1484. if (psb_intel_sdvo_connector->cur_##name == temp_value) return 0; \
  1485. if (psb_intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
  1486. cmd = SDVO_CMD_SET_##NAME; \
  1487. psb_intel_sdvo_connector->cur_##name = temp_value; \
  1488. goto set_value; \
  1489. }
  1490. if (property == psb_intel_sdvo_connector->tv_format) {
  1491. if (val >= TV_FORMAT_NUM)
  1492. return -EINVAL;
  1493. if (psb_intel_sdvo->tv_format_index ==
  1494. psb_intel_sdvo_connector->tv_format_supported[val])
  1495. return 0;
  1496. psb_intel_sdvo->tv_format_index = psb_intel_sdvo_connector->tv_format_supported[val];
  1497. goto done;
  1498. } else if (IS_TV_OR_LVDS(psb_intel_sdvo_connector)) {
  1499. temp_value = val;
  1500. if (psb_intel_sdvo_connector->left == property) {
  1501. drm_object_property_set_value(&connector->base,
  1502. psb_intel_sdvo_connector->right, val);
  1503. if (psb_intel_sdvo_connector->left_margin == temp_value)
  1504. return 0;
  1505. psb_intel_sdvo_connector->left_margin = temp_value;
  1506. psb_intel_sdvo_connector->right_margin = temp_value;
  1507. temp_value = psb_intel_sdvo_connector->max_hscan -
  1508. psb_intel_sdvo_connector->left_margin;
  1509. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1510. goto set_value;
  1511. } else if (psb_intel_sdvo_connector->right == property) {
  1512. drm_object_property_set_value(&connector->base,
  1513. psb_intel_sdvo_connector->left, val);
  1514. if (psb_intel_sdvo_connector->right_margin == temp_value)
  1515. return 0;
  1516. psb_intel_sdvo_connector->left_margin = temp_value;
  1517. psb_intel_sdvo_connector->right_margin = temp_value;
  1518. temp_value = psb_intel_sdvo_connector->max_hscan -
  1519. psb_intel_sdvo_connector->left_margin;
  1520. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1521. goto set_value;
  1522. } else if (psb_intel_sdvo_connector->top == property) {
  1523. drm_object_property_set_value(&connector->base,
  1524. psb_intel_sdvo_connector->bottom, val);
  1525. if (psb_intel_sdvo_connector->top_margin == temp_value)
  1526. return 0;
  1527. psb_intel_sdvo_connector->top_margin = temp_value;
  1528. psb_intel_sdvo_connector->bottom_margin = temp_value;
  1529. temp_value = psb_intel_sdvo_connector->max_vscan -
  1530. psb_intel_sdvo_connector->top_margin;
  1531. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1532. goto set_value;
  1533. } else if (psb_intel_sdvo_connector->bottom == property) {
  1534. drm_object_property_set_value(&connector->base,
  1535. psb_intel_sdvo_connector->top, val);
  1536. if (psb_intel_sdvo_connector->bottom_margin == temp_value)
  1537. return 0;
  1538. psb_intel_sdvo_connector->top_margin = temp_value;
  1539. psb_intel_sdvo_connector->bottom_margin = temp_value;
  1540. temp_value = psb_intel_sdvo_connector->max_vscan -
  1541. psb_intel_sdvo_connector->top_margin;
  1542. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1543. goto set_value;
  1544. }
  1545. CHECK_PROPERTY(hpos, HPOS)
  1546. CHECK_PROPERTY(vpos, VPOS)
  1547. CHECK_PROPERTY(saturation, SATURATION)
  1548. CHECK_PROPERTY(contrast, CONTRAST)
  1549. CHECK_PROPERTY(hue, HUE)
  1550. CHECK_PROPERTY(brightness, BRIGHTNESS)
  1551. CHECK_PROPERTY(sharpness, SHARPNESS)
  1552. CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
  1553. CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
  1554. CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
  1555. CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
  1556. CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
  1557. CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
  1558. }
  1559. return -EINVAL; /* unknown property */
  1560. set_value:
  1561. if (!psb_intel_sdvo_set_value(psb_intel_sdvo, cmd, &temp_value, 2))
  1562. return -EIO;
  1563. done:
  1564. if (psb_intel_sdvo->base.base.crtc) {
  1565. struct drm_crtc *crtc = psb_intel_sdvo->base.base.crtc;
  1566. drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
  1567. crtc->y, crtc->fb);
  1568. }
  1569. return 0;
  1570. #undef CHECK_PROPERTY
  1571. }
  1572. static void psb_intel_sdvo_save(struct drm_connector *connector)
  1573. {
  1574. struct drm_device *dev = connector->dev;
  1575. struct psb_intel_encoder *psb_intel_encoder =
  1576. gma_attached_encoder(connector);
  1577. struct psb_intel_sdvo *sdvo =
  1578. to_psb_intel_sdvo(&psb_intel_encoder->base);
  1579. sdvo->saveSDVO = REG_READ(sdvo->sdvo_reg);
  1580. }
  1581. static void psb_intel_sdvo_restore(struct drm_connector *connector)
  1582. {
  1583. struct drm_device *dev = connector->dev;
  1584. struct drm_encoder *encoder = &gma_attached_encoder(connector)->base;
  1585. struct psb_intel_sdvo *sdvo = to_psb_intel_sdvo(encoder);
  1586. struct drm_crtc *crtc = encoder->crtc;
  1587. REG_WRITE(sdvo->sdvo_reg, sdvo->saveSDVO);
  1588. /* Force a full mode set on the crtc. We're supposed to have the
  1589. mode_config lock already. */
  1590. if (connector->status == connector_status_connected)
  1591. drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
  1592. NULL);
  1593. }
  1594. static const struct drm_encoder_helper_funcs psb_intel_sdvo_helper_funcs = {
  1595. .dpms = psb_intel_sdvo_dpms,
  1596. .mode_fixup = psb_intel_sdvo_mode_fixup,
  1597. .prepare = gma_encoder_prepare,
  1598. .mode_set = psb_intel_sdvo_mode_set,
  1599. .commit = gma_encoder_commit,
  1600. };
  1601. static const struct drm_connector_funcs psb_intel_sdvo_connector_funcs = {
  1602. .dpms = drm_helper_connector_dpms,
  1603. .save = psb_intel_sdvo_save,
  1604. .restore = psb_intel_sdvo_restore,
  1605. .detect = psb_intel_sdvo_detect,
  1606. .fill_modes = drm_helper_probe_single_connector_modes,
  1607. .set_property = psb_intel_sdvo_set_property,
  1608. .destroy = psb_intel_sdvo_destroy,
  1609. };
  1610. static const struct drm_connector_helper_funcs psb_intel_sdvo_connector_helper_funcs = {
  1611. .get_modes = psb_intel_sdvo_get_modes,
  1612. .mode_valid = psb_intel_sdvo_mode_valid,
  1613. .best_encoder = gma_best_encoder,
  1614. };
  1615. static void psb_intel_sdvo_enc_destroy(struct drm_encoder *encoder)
  1616. {
  1617. struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
  1618. if (psb_intel_sdvo->sdvo_lvds_fixed_mode != NULL)
  1619. drm_mode_destroy(encoder->dev,
  1620. psb_intel_sdvo->sdvo_lvds_fixed_mode);
  1621. i2c_del_adapter(&psb_intel_sdvo->ddc);
  1622. gma_encoder_destroy(encoder);
  1623. }
  1624. static const struct drm_encoder_funcs psb_intel_sdvo_enc_funcs = {
  1625. .destroy = psb_intel_sdvo_enc_destroy,
  1626. };
  1627. static void
  1628. psb_intel_sdvo_guess_ddc_bus(struct psb_intel_sdvo *sdvo)
  1629. {
  1630. /* FIXME: At the moment, ddc_bus = 2 is the only thing that works.
  1631. * We need to figure out if this is true for all available poulsbo
  1632. * hardware, or if we need to fiddle with the guessing code above.
  1633. * The problem might go away if we can parse sdvo mappings from bios */
  1634. sdvo->ddc_bus = 2;
  1635. #if 0
  1636. uint16_t mask = 0;
  1637. unsigned int num_bits;
  1638. /* Make a mask of outputs less than or equal to our own priority in the
  1639. * list.
  1640. */
  1641. switch (sdvo->controlled_output) {
  1642. case SDVO_OUTPUT_LVDS1:
  1643. mask |= SDVO_OUTPUT_LVDS1;
  1644. case SDVO_OUTPUT_LVDS0:
  1645. mask |= SDVO_OUTPUT_LVDS0;
  1646. case SDVO_OUTPUT_TMDS1:
  1647. mask |= SDVO_OUTPUT_TMDS1;
  1648. case SDVO_OUTPUT_TMDS0:
  1649. mask |= SDVO_OUTPUT_TMDS0;
  1650. case SDVO_OUTPUT_RGB1:
  1651. mask |= SDVO_OUTPUT_RGB1;
  1652. case SDVO_OUTPUT_RGB0:
  1653. mask |= SDVO_OUTPUT_RGB0;
  1654. break;
  1655. }
  1656. /* Count bits to find what number we are in the priority list. */
  1657. mask &= sdvo->caps.output_flags;
  1658. num_bits = hweight16(mask);
  1659. /* If more than 3 outputs, default to DDC bus 3 for now. */
  1660. if (num_bits > 3)
  1661. num_bits = 3;
  1662. /* Corresponds to SDVO_CONTROL_BUS_DDCx */
  1663. sdvo->ddc_bus = 1 << num_bits;
  1664. #endif
  1665. }
  1666. /**
  1667. * Choose the appropriate DDC bus for control bus switch command for this
  1668. * SDVO output based on the controlled output.
  1669. *
  1670. * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
  1671. * outputs, then LVDS outputs.
  1672. */
  1673. static void
  1674. psb_intel_sdvo_select_ddc_bus(struct drm_psb_private *dev_priv,
  1675. struct psb_intel_sdvo *sdvo, u32 reg)
  1676. {
  1677. struct sdvo_device_mapping *mapping;
  1678. if (IS_SDVOB(reg))
  1679. mapping = &(dev_priv->sdvo_mappings[0]);
  1680. else
  1681. mapping = &(dev_priv->sdvo_mappings[1]);
  1682. if (mapping->initialized)
  1683. sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
  1684. else
  1685. psb_intel_sdvo_guess_ddc_bus(sdvo);
  1686. }
  1687. static void
  1688. psb_intel_sdvo_select_i2c_bus(struct drm_psb_private *dev_priv,
  1689. struct psb_intel_sdvo *sdvo, u32 reg)
  1690. {
  1691. struct sdvo_device_mapping *mapping;
  1692. u8 pin, speed;
  1693. if (IS_SDVOB(reg))
  1694. mapping = &dev_priv->sdvo_mappings[0];
  1695. else
  1696. mapping = &dev_priv->sdvo_mappings[1];
  1697. pin = GMBUS_PORT_DPB;
  1698. speed = GMBUS_RATE_1MHZ >> 8;
  1699. if (mapping->initialized) {
  1700. pin = mapping->i2c_pin;
  1701. speed = mapping->i2c_speed;
  1702. }
  1703. if (pin < GMBUS_NUM_PORTS) {
  1704. sdvo->i2c = &dev_priv->gmbus[pin].adapter;
  1705. gma_intel_gmbus_set_speed(sdvo->i2c, speed);
  1706. gma_intel_gmbus_force_bit(sdvo->i2c, true);
  1707. } else
  1708. sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter;
  1709. }
  1710. static bool
  1711. psb_intel_sdvo_is_hdmi_connector(struct psb_intel_sdvo *psb_intel_sdvo, int device)
  1712. {
  1713. return psb_intel_sdvo_check_supp_encode(psb_intel_sdvo);
  1714. }
  1715. static u8
  1716. psb_intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
  1717. {
  1718. struct drm_psb_private *dev_priv = dev->dev_private;
  1719. struct sdvo_device_mapping *my_mapping, *other_mapping;
  1720. if (IS_SDVOB(sdvo_reg)) {
  1721. my_mapping = &dev_priv->sdvo_mappings[0];
  1722. other_mapping = &dev_priv->sdvo_mappings[1];
  1723. } else {
  1724. my_mapping = &dev_priv->sdvo_mappings[1];
  1725. other_mapping = &dev_priv->sdvo_mappings[0];
  1726. }
  1727. /* If the BIOS described our SDVO device, take advantage of it. */
  1728. if (my_mapping->slave_addr)
  1729. return my_mapping->slave_addr;
  1730. /* If the BIOS only described a different SDVO device, use the
  1731. * address that it isn't using.
  1732. */
  1733. if (other_mapping->slave_addr) {
  1734. if (other_mapping->slave_addr == 0x70)
  1735. return 0x72;
  1736. else
  1737. return 0x70;
  1738. }
  1739. /* No SDVO device info is found for another DVO port,
  1740. * so use mapping assumption we had before BIOS parsing.
  1741. */
  1742. if (IS_SDVOB(sdvo_reg))
  1743. return 0x70;
  1744. else
  1745. return 0x72;
  1746. }
  1747. static void
  1748. psb_intel_sdvo_connector_init(struct psb_intel_sdvo_connector *connector,
  1749. struct psb_intel_sdvo *encoder)
  1750. {
  1751. drm_connector_init(encoder->base.base.dev,
  1752. &connector->base.base,
  1753. &psb_intel_sdvo_connector_funcs,
  1754. connector->base.base.connector_type);
  1755. drm_connector_helper_add(&connector->base.base,
  1756. &psb_intel_sdvo_connector_helper_funcs);
  1757. connector->base.base.interlace_allowed = 0;
  1758. connector->base.base.doublescan_allowed = 0;
  1759. connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
  1760. gma_connector_attach_encoder(&connector->base, &encoder->base);
  1761. drm_sysfs_connector_add(&connector->base.base);
  1762. }
  1763. static void
  1764. psb_intel_sdvo_add_hdmi_properties(struct psb_intel_sdvo_connector *connector)
  1765. {
  1766. /* FIXME: We don't support HDMI at the moment
  1767. struct drm_device *dev = connector->base.base.dev;
  1768. intel_attach_force_audio_property(&connector->base.base);
  1769. intel_attach_broadcast_rgb_property(&connector->base.base);
  1770. */
  1771. }
  1772. static bool
  1773. psb_intel_sdvo_dvi_init(struct psb_intel_sdvo *psb_intel_sdvo, int device)
  1774. {
  1775. struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
  1776. struct drm_connector *connector;
  1777. struct psb_intel_connector *intel_connector;
  1778. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
  1779. psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
  1780. if (!psb_intel_sdvo_connector)
  1781. return false;
  1782. if (device == 0) {
  1783. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
  1784. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
  1785. } else if (device == 1) {
  1786. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
  1787. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
  1788. }
  1789. intel_connector = &psb_intel_sdvo_connector->base;
  1790. connector = &intel_connector->base;
  1791. // connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
  1792. encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
  1793. connector->connector_type = DRM_MODE_CONNECTOR_DVID;
  1794. if (psb_intel_sdvo_is_hdmi_connector(psb_intel_sdvo, device)) {
  1795. connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
  1796. psb_intel_sdvo->is_hdmi = true;
  1797. }
  1798. psb_intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1799. (1 << INTEL_ANALOG_CLONE_BIT));
  1800. psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo);
  1801. if (psb_intel_sdvo->is_hdmi)
  1802. psb_intel_sdvo_add_hdmi_properties(psb_intel_sdvo_connector);
  1803. return true;
  1804. }
  1805. static bool
  1806. psb_intel_sdvo_tv_init(struct psb_intel_sdvo *psb_intel_sdvo, int type)
  1807. {
  1808. struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
  1809. struct drm_connector *connector;
  1810. struct psb_intel_connector *intel_connector;
  1811. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
  1812. psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
  1813. if (!psb_intel_sdvo_connector)
  1814. return false;
  1815. intel_connector = &psb_intel_sdvo_connector->base;
  1816. connector = &intel_connector->base;
  1817. encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
  1818. connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
  1819. psb_intel_sdvo->controlled_output |= type;
  1820. psb_intel_sdvo_connector->output_flag = type;
  1821. psb_intel_sdvo->is_tv = true;
  1822. psb_intel_sdvo->base.needs_tv_clock = true;
  1823. psb_intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
  1824. psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo);
  1825. if (!psb_intel_sdvo_tv_create_property(psb_intel_sdvo, psb_intel_sdvo_connector, type))
  1826. goto err;
  1827. if (!psb_intel_sdvo_create_enhance_property(psb_intel_sdvo, psb_intel_sdvo_connector))
  1828. goto err;
  1829. return true;
  1830. err:
  1831. psb_intel_sdvo_destroy(connector);
  1832. return false;
  1833. }
  1834. static bool
  1835. psb_intel_sdvo_analog_init(struct psb_intel_sdvo *psb_intel_sdvo, int device)
  1836. {
  1837. struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
  1838. struct drm_connector *connector;
  1839. struct psb_intel_connector *intel_connector;
  1840. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
  1841. psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
  1842. if (!psb_intel_sdvo_connector)
  1843. return false;
  1844. intel_connector = &psb_intel_sdvo_connector->base;
  1845. connector = &intel_connector->base;
  1846. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  1847. encoder->encoder_type = DRM_MODE_ENCODER_DAC;
  1848. connector->connector_type = DRM_MODE_CONNECTOR_VGA;
  1849. if (device == 0) {
  1850. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
  1851. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
  1852. } else if (device == 1) {
  1853. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
  1854. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
  1855. }
  1856. psb_intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1857. (1 << INTEL_ANALOG_CLONE_BIT));
  1858. psb_intel_sdvo_connector_init(psb_intel_sdvo_connector,
  1859. psb_intel_sdvo);
  1860. return true;
  1861. }
  1862. static bool
  1863. psb_intel_sdvo_lvds_init(struct psb_intel_sdvo *psb_intel_sdvo, int device)
  1864. {
  1865. struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
  1866. struct drm_connector *connector;
  1867. struct psb_intel_connector *intel_connector;
  1868. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
  1869. psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
  1870. if (!psb_intel_sdvo_connector)
  1871. return false;
  1872. intel_connector = &psb_intel_sdvo_connector->base;
  1873. connector = &intel_connector->base;
  1874. encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
  1875. connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
  1876. if (device == 0) {
  1877. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
  1878. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
  1879. } else if (device == 1) {
  1880. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
  1881. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
  1882. }
  1883. psb_intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
  1884. (1 << INTEL_SDVO_LVDS_CLONE_BIT));
  1885. psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo);
  1886. if (!psb_intel_sdvo_create_enhance_property(psb_intel_sdvo, psb_intel_sdvo_connector))
  1887. goto err;
  1888. return true;
  1889. err:
  1890. psb_intel_sdvo_destroy(connector);
  1891. return false;
  1892. }
  1893. static bool
  1894. psb_intel_sdvo_output_setup(struct psb_intel_sdvo *psb_intel_sdvo, uint16_t flags)
  1895. {
  1896. psb_intel_sdvo->is_tv = false;
  1897. psb_intel_sdvo->base.needs_tv_clock = false;
  1898. psb_intel_sdvo->is_lvds = false;
  1899. /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
  1900. if (flags & SDVO_OUTPUT_TMDS0)
  1901. if (!psb_intel_sdvo_dvi_init(psb_intel_sdvo, 0))
  1902. return false;
  1903. if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
  1904. if (!psb_intel_sdvo_dvi_init(psb_intel_sdvo, 1))
  1905. return false;
  1906. /* TV has no XXX1 function block */
  1907. if (flags & SDVO_OUTPUT_SVID0)
  1908. if (!psb_intel_sdvo_tv_init(psb_intel_sdvo, SDVO_OUTPUT_SVID0))
  1909. return false;
  1910. if (flags & SDVO_OUTPUT_CVBS0)
  1911. if (!psb_intel_sdvo_tv_init(psb_intel_sdvo, SDVO_OUTPUT_CVBS0))
  1912. return false;
  1913. if (flags & SDVO_OUTPUT_RGB0)
  1914. if (!psb_intel_sdvo_analog_init(psb_intel_sdvo, 0))
  1915. return false;
  1916. if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
  1917. if (!psb_intel_sdvo_analog_init(psb_intel_sdvo, 1))
  1918. return false;
  1919. if (flags & SDVO_OUTPUT_LVDS0)
  1920. if (!psb_intel_sdvo_lvds_init(psb_intel_sdvo, 0))
  1921. return false;
  1922. if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
  1923. if (!psb_intel_sdvo_lvds_init(psb_intel_sdvo, 1))
  1924. return false;
  1925. if ((flags & SDVO_OUTPUT_MASK) == 0) {
  1926. unsigned char bytes[2];
  1927. psb_intel_sdvo->controlled_output = 0;
  1928. memcpy(bytes, &psb_intel_sdvo->caps.output_flags, 2);
  1929. DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
  1930. SDVO_NAME(psb_intel_sdvo),
  1931. bytes[0], bytes[1]);
  1932. return false;
  1933. }
  1934. psb_intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
  1935. return true;
  1936. }
  1937. static bool psb_intel_sdvo_tv_create_property(struct psb_intel_sdvo *psb_intel_sdvo,
  1938. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
  1939. int type)
  1940. {
  1941. struct drm_device *dev = psb_intel_sdvo->base.base.dev;
  1942. struct psb_intel_sdvo_tv_format format;
  1943. uint32_t format_map, i;
  1944. if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo, type))
  1945. return false;
  1946. BUILD_BUG_ON(sizeof(format) != 6);
  1947. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  1948. SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
  1949. &format, sizeof(format)))
  1950. return false;
  1951. memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
  1952. if (format_map == 0)
  1953. return false;
  1954. psb_intel_sdvo_connector->format_supported_num = 0;
  1955. for (i = 0 ; i < TV_FORMAT_NUM; i++)
  1956. if (format_map & (1 << i))
  1957. psb_intel_sdvo_connector->tv_format_supported[psb_intel_sdvo_connector->format_supported_num++] = i;
  1958. psb_intel_sdvo_connector->tv_format =
  1959. drm_property_create(dev, DRM_MODE_PROP_ENUM,
  1960. "mode", psb_intel_sdvo_connector->format_supported_num);
  1961. if (!psb_intel_sdvo_connector->tv_format)
  1962. return false;
  1963. for (i = 0; i < psb_intel_sdvo_connector->format_supported_num; i++)
  1964. drm_property_add_enum(
  1965. psb_intel_sdvo_connector->tv_format, i,
  1966. i, tv_format_names[psb_intel_sdvo_connector->tv_format_supported[i]]);
  1967. psb_intel_sdvo->tv_format_index = psb_intel_sdvo_connector->tv_format_supported[0];
  1968. drm_object_attach_property(&psb_intel_sdvo_connector->base.base.base,
  1969. psb_intel_sdvo_connector->tv_format, 0);
  1970. return true;
  1971. }
  1972. #define ENHANCEMENT(name, NAME) do { \
  1973. if (enhancements.name) { \
  1974. if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
  1975. !psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
  1976. return false; \
  1977. psb_intel_sdvo_connector->max_##name = data_value[0]; \
  1978. psb_intel_sdvo_connector->cur_##name = response; \
  1979. psb_intel_sdvo_connector->name = \
  1980. drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
  1981. if (!psb_intel_sdvo_connector->name) return false; \
  1982. drm_object_attach_property(&connector->base, \
  1983. psb_intel_sdvo_connector->name, \
  1984. psb_intel_sdvo_connector->cur_##name); \
  1985. DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
  1986. data_value[0], data_value[1], response); \
  1987. } \
  1988. } while(0)
  1989. static bool
  1990. psb_intel_sdvo_create_enhance_property_tv(struct psb_intel_sdvo *psb_intel_sdvo,
  1991. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
  1992. struct psb_intel_sdvo_enhancements_reply enhancements)
  1993. {
  1994. struct drm_device *dev = psb_intel_sdvo->base.base.dev;
  1995. struct drm_connector *connector = &psb_intel_sdvo_connector->base.base;
  1996. uint16_t response, data_value[2];
  1997. /* when horizontal overscan is supported, Add the left/right property */
  1998. if (enhancements.overscan_h) {
  1999. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  2000. SDVO_CMD_GET_MAX_OVERSCAN_H,
  2001. &data_value, 4))
  2002. return false;
  2003. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  2004. SDVO_CMD_GET_OVERSCAN_H,
  2005. &response, 2))
  2006. return false;
  2007. psb_intel_sdvo_connector->max_hscan = data_value[0];
  2008. psb_intel_sdvo_connector->left_margin = data_value[0] - response;
  2009. psb_intel_sdvo_connector->right_margin = psb_intel_sdvo_connector->left_margin;
  2010. psb_intel_sdvo_connector->left =
  2011. drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
  2012. if (!psb_intel_sdvo_connector->left)
  2013. return false;
  2014. drm_object_attach_property(&connector->base,
  2015. psb_intel_sdvo_connector->left,
  2016. psb_intel_sdvo_connector->left_margin);
  2017. psb_intel_sdvo_connector->right =
  2018. drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
  2019. if (!psb_intel_sdvo_connector->right)
  2020. return false;
  2021. drm_object_attach_property(&connector->base,
  2022. psb_intel_sdvo_connector->right,
  2023. psb_intel_sdvo_connector->right_margin);
  2024. DRM_DEBUG_KMS("h_overscan: max %d, "
  2025. "default %d, current %d\n",
  2026. data_value[0], data_value[1], response);
  2027. }
  2028. if (enhancements.overscan_v) {
  2029. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  2030. SDVO_CMD_GET_MAX_OVERSCAN_V,
  2031. &data_value, 4))
  2032. return false;
  2033. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  2034. SDVO_CMD_GET_OVERSCAN_V,
  2035. &response, 2))
  2036. return false;
  2037. psb_intel_sdvo_connector->max_vscan = data_value[0];
  2038. psb_intel_sdvo_connector->top_margin = data_value[0] - response;
  2039. psb_intel_sdvo_connector->bottom_margin = psb_intel_sdvo_connector->top_margin;
  2040. psb_intel_sdvo_connector->top =
  2041. drm_property_create_range(dev, 0, "top_margin", 0, data_value[0]);
  2042. if (!psb_intel_sdvo_connector->top)
  2043. return false;
  2044. drm_object_attach_property(&connector->base,
  2045. psb_intel_sdvo_connector->top,
  2046. psb_intel_sdvo_connector->top_margin);
  2047. psb_intel_sdvo_connector->bottom =
  2048. drm_property_create_range(dev, 0, "bottom_margin", 0, data_value[0]);
  2049. if (!psb_intel_sdvo_connector->bottom)
  2050. return false;
  2051. drm_object_attach_property(&connector->base,
  2052. psb_intel_sdvo_connector->bottom,
  2053. psb_intel_sdvo_connector->bottom_margin);
  2054. DRM_DEBUG_KMS("v_overscan: max %d, "
  2055. "default %d, current %d\n",
  2056. data_value[0], data_value[1], response);
  2057. }
  2058. ENHANCEMENT(hpos, HPOS);
  2059. ENHANCEMENT(vpos, VPOS);
  2060. ENHANCEMENT(saturation, SATURATION);
  2061. ENHANCEMENT(contrast, CONTRAST);
  2062. ENHANCEMENT(hue, HUE);
  2063. ENHANCEMENT(sharpness, SHARPNESS);
  2064. ENHANCEMENT(brightness, BRIGHTNESS);
  2065. ENHANCEMENT(flicker_filter, FLICKER_FILTER);
  2066. ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
  2067. ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
  2068. ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
  2069. ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
  2070. if (enhancements.dot_crawl) {
  2071. if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
  2072. return false;
  2073. psb_intel_sdvo_connector->max_dot_crawl = 1;
  2074. psb_intel_sdvo_connector->cur_dot_crawl = response & 0x1;
  2075. psb_intel_sdvo_connector->dot_crawl =
  2076. drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
  2077. if (!psb_intel_sdvo_connector->dot_crawl)
  2078. return false;
  2079. drm_object_attach_property(&connector->base,
  2080. psb_intel_sdvo_connector->dot_crawl,
  2081. psb_intel_sdvo_connector->cur_dot_crawl);
  2082. DRM_DEBUG_KMS("dot crawl: current %d\n", response);
  2083. }
  2084. return true;
  2085. }
  2086. static bool
  2087. psb_intel_sdvo_create_enhance_property_lvds(struct psb_intel_sdvo *psb_intel_sdvo,
  2088. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
  2089. struct psb_intel_sdvo_enhancements_reply enhancements)
  2090. {
  2091. struct drm_device *dev = psb_intel_sdvo->base.base.dev;
  2092. struct drm_connector *connector = &psb_intel_sdvo_connector->base.base;
  2093. uint16_t response, data_value[2];
  2094. ENHANCEMENT(brightness, BRIGHTNESS);
  2095. return true;
  2096. }
  2097. #undef ENHANCEMENT
  2098. static bool psb_intel_sdvo_create_enhance_property(struct psb_intel_sdvo *psb_intel_sdvo,
  2099. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector)
  2100. {
  2101. union {
  2102. struct psb_intel_sdvo_enhancements_reply reply;
  2103. uint16_t response;
  2104. } enhancements;
  2105. BUILD_BUG_ON(sizeof(enhancements) != 2);
  2106. enhancements.response = 0;
  2107. psb_intel_sdvo_get_value(psb_intel_sdvo,
  2108. SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
  2109. &enhancements, sizeof(enhancements));
  2110. if (enhancements.response == 0) {
  2111. DRM_DEBUG_KMS("No enhancement is supported\n");
  2112. return true;
  2113. }
  2114. if (IS_TV(psb_intel_sdvo_connector))
  2115. return psb_intel_sdvo_create_enhance_property_tv(psb_intel_sdvo, psb_intel_sdvo_connector, enhancements.reply);
  2116. else if(IS_LVDS(psb_intel_sdvo_connector))
  2117. return psb_intel_sdvo_create_enhance_property_lvds(psb_intel_sdvo, psb_intel_sdvo_connector, enhancements.reply);
  2118. else
  2119. return true;
  2120. }
  2121. static int psb_intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
  2122. struct i2c_msg *msgs,
  2123. int num)
  2124. {
  2125. struct psb_intel_sdvo *sdvo = adapter->algo_data;
  2126. if (!psb_intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
  2127. return -EIO;
  2128. return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
  2129. }
  2130. static u32 psb_intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
  2131. {
  2132. struct psb_intel_sdvo *sdvo = adapter->algo_data;
  2133. return sdvo->i2c->algo->functionality(sdvo->i2c);
  2134. }
  2135. static const struct i2c_algorithm psb_intel_sdvo_ddc_proxy = {
  2136. .master_xfer = psb_intel_sdvo_ddc_proxy_xfer,
  2137. .functionality = psb_intel_sdvo_ddc_proxy_func
  2138. };
  2139. static bool
  2140. psb_intel_sdvo_init_ddc_proxy(struct psb_intel_sdvo *sdvo,
  2141. struct drm_device *dev)
  2142. {
  2143. sdvo->ddc.owner = THIS_MODULE;
  2144. sdvo->ddc.class = I2C_CLASS_DDC;
  2145. snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
  2146. sdvo->ddc.dev.parent = &dev->pdev->dev;
  2147. sdvo->ddc.algo_data = sdvo;
  2148. sdvo->ddc.algo = &psb_intel_sdvo_ddc_proxy;
  2149. return i2c_add_adapter(&sdvo->ddc) == 0;
  2150. }
  2151. bool psb_intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
  2152. {
  2153. struct drm_psb_private *dev_priv = dev->dev_private;
  2154. struct psb_intel_encoder *psb_intel_encoder;
  2155. struct psb_intel_sdvo *psb_intel_sdvo;
  2156. int i;
  2157. psb_intel_sdvo = kzalloc(sizeof(struct psb_intel_sdvo), GFP_KERNEL);
  2158. if (!psb_intel_sdvo)
  2159. return false;
  2160. psb_intel_sdvo->sdvo_reg = sdvo_reg;
  2161. psb_intel_sdvo->slave_addr = psb_intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1;
  2162. psb_intel_sdvo_select_i2c_bus(dev_priv, psb_intel_sdvo, sdvo_reg);
  2163. if (!psb_intel_sdvo_init_ddc_proxy(psb_intel_sdvo, dev)) {
  2164. kfree(psb_intel_sdvo);
  2165. return false;
  2166. }
  2167. /* encoder type will be decided later */
  2168. psb_intel_encoder = &psb_intel_sdvo->base;
  2169. psb_intel_encoder->type = INTEL_OUTPUT_SDVO;
  2170. drm_encoder_init(dev, &psb_intel_encoder->base, &psb_intel_sdvo_enc_funcs, 0);
  2171. /* Read the regs to test if we can talk to the device */
  2172. for (i = 0; i < 0x40; i++) {
  2173. u8 byte;
  2174. if (!psb_intel_sdvo_read_byte(psb_intel_sdvo, i, &byte)) {
  2175. DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
  2176. IS_SDVOB(sdvo_reg) ? 'B' : 'C');
  2177. goto err;
  2178. }
  2179. }
  2180. if (IS_SDVOB(sdvo_reg))
  2181. dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
  2182. else
  2183. dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
  2184. drm_encoder_helper_add(&psb_intel_encoder->base, &psb_intel_sdvo_helper_funcs);
  2185. /* In default case sdvo lvds is false */
  2186. if (!psb_intel_sdvo_get_capabilities(psb_intel_sdvo, &psb_intel_sdvo->caps))
  2187. goto err;
  2188. if (psb_intel_sdvo_output_setup(psb_intel_sdvo,
  2189. psb_intel_sdvo->caps.output_flags) != true) {
  2190. DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
  2191. IS_SDVOB(sdvo_reg) ? 'B' : 'C');
  2192. goto err;
  2193. }
  2194. psb_intel_sdvo_select_ddc_bus(dev_priv, psb_intel_sdvo, sdvo_reg);
  2195. /* Set the input timing to the screen. Assume always input 0. */
  2196. if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo))
  2197. goto err;
  2198. if (!psb_intel_sdvo_get_input_pixel_clock_range(psb_intel_sdvo,
  2199. &psb_intel_sdvo->pixel_clock_min,
  2200. &psb_intel_sdvo->pixel_clock_max))
  2201. goto err;
  2202. DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
  2203. "clock range %dMHz - %dMHz, "
  2204. "input 1: %c, input 2: %c, "
  2205. "output 1: %c, output 2: %c\n",
  2206. SDVO_NAME(psb_intel_sdvo),
  2207. psb_intel_sdvo->caps.vendor_id, psb_intel_sdvo->caps.device_id,
  2208. psb_intel_sdvo->caps.device_rev_id,
  2209. psb_intel_sdvo->pixel_clock_min / 1000,
  2210. psb_intel_sdvo->pixel_clock_max / 1000,
  2211. (psb_intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
  2212. (psb_intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
  2213. /* check currently supported outputs */
  2214. psb_intel_sdvo->caps.output_flags &
  2215. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
  2216. psb_intel_sdvo->caps.output_flags &
  2217. (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
  2218. return true;
  2219. err:
  2220. drm_encoder_cleanup(&psb_intel_encoder->base);
  2221. i2c_del_adapter(&psb_intel_sdvo->ddc);
  2222. kfree(psb_intel_sdvo);
  2223. return false;
  2224. }