devs.c 39 KB

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  1. /* linux/arch/arm/plat-samsung/devs.c
  2. *
  3. * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * Base SAMSUNG platform device definitions
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/types.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/list.h>
  16. #include <linux/timer.h>
  17. #include <linux/init.h>
  18. #include <linux/serial_core.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/io.h>
  21. #include <linux/slab.h>
  22. #include <linux/string.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/fb.h>
  25. #include <linux/gfp.h>
  26. #include <linux/mtd/mtd.h>
  27. #include <linux/mtd/onenand.h>
  28. #include <linux/mtd/partitions.h>
  29. #include <linux/mmc/host.h>
  30. #include <linux/ioport.h>
  31. #include <linux/platform_data/s3c-hsudc.h>
  32. #include <linux/platform_data/s3c-hsotg.h>
  33. #include <media/s5p_hdmi.h>
  34. #include <asm/irq.h>
  35. #include <asm/mach/arch.h>
  36. #include <asm/mach/map.h>
  37. #include <asm/mach/irq.h>
  38. #include <mach/hardware.h>
  39. #include <mach/dma.h>
  40. #include <mach/irqs.h>
  41. #include <mach/map.h>
  42. #include <plat/cpu.h>
  43. #include <plat/devs.h>
  44. #include <plat/adc.h>
  45. #include <linux/platform_data/ata-samsung_cf.h>
  46. #include <linux/platform_data/usb-ehci-s5p.h>
  47. #include <plat/fb.h>
  48. #include <plat/fb-s3c2410.h>
  49. #include <plat/hdmi.h>
  50. #include <linux/platform_data/hwmon-s3c.h>
  51. #include <linux/platform_data/i2c-s3c2410.h>
  52. #include <plat/keypad.h>
  53. #include <linux/platform_data/mmc-s3cmci.h>
  54. #include <linux/platform_data/mtd-nand-s3c2410.h>
  55. #include <plat/sdhci.h>
  56. #include <linux/platform_data/touchscreen-s3c2410.h>
  57. #include <linux/platform_data/usb-s3c2410_udc.h>
  58. #include <linux/platform_data/usb-ohci-s3c2410.h>
  59. #include <plat/usb-phy.h>
  60. #include <plat/regs-iic.h>
  61. #include <plat/regs-serial.h>
  62. #include <plat/regs-spi.h>
  63. #include <linux/platform_data/spi-s3c64xx.h>
  64. static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);
  65. /* AC97 */
  66. #ifdef CONFIG_CPU_S3C2440
  67. static struct resource s3c_ac97_resource[] = {
  68. [0] = DEFINE_RES_MEM(S3C2440_PA_AC97, S3C2440_SZ_AC97),
  69. [1] = DEFINE_RES_IRQ(IRQ_S3C244X_AC97),
  70. [2] = DEFINE_RES_DMA_NAMED(DMACH_PCM_OUT, "PCM out"),
  71. [3] = DEFINE_RES_DMA_NAMED(DMACH_PCM_IN, "PCM in"),
  72. [4] = DEFINE_RES_DMA_NAMED(DMACH_MIC_IN, "Mic in"),
  73. };
  74. struct platform_device s3c_device_ac97 = {
  75. .name = "samsung-ac97",
  76. .id = -1,
  77. .num_resources = ARRAY_SIZE(s3c_ac97_resource),
  78. .resource = s3c_ac97_resource,
  79. .dev = {
  80. .dma_mask = &samsung_device_dma_mask,
  81. .coherent_dma_mask = DMA_BIT_MASK(32),
  82. }
  83. };
  84. #endif /* CONFIG_CPU_S3C2440 */
  85. /* ADC */
  86. #ifdef CONFIG_PLAT_S3C24XX
  87. static struct resource s3c_adc_resource[] = {
  88. [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
  89. [1] = DEFINE_RES_IRQ(IRQ_TC),
  90. [2] = DEFINE_RES_IRQ(IRQ_ADC),
  91. };
  92. struct platform_device s3c_device_adc = {
  93. .name = "s3c24xx-adc",
  94. .id = -1,
  95. .num_resources = ARRAY_SIZE(s3c_adc_resource),
  96. .resource = s3c_adc_resource,
  97. };
  98. #endif /* CONFIG_PLAT_S3C24XX */
  99. #if defined(CONFIG_SAMSUNG_DEV_ADC)
  100. static struct resource s3c_adc_resource[] = {
  101. [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
  102. [1] = DEFINE_RES_IRQ(IRQ_TC),
  103. [2] = DEFINE_RES_IRQ(IRQ_ADC),
  104. };
  105. struct platform_device s3c_device_adc = {
  106. .name = "samsung-adc",
  107. .id = -1,
  108. .num_resources = ARRAY_SIZE(s3c_adc_resource),
  109. .resource = s3c_adc_resource,
  110. };
  111. #endif /* CONFIG_SAMSUNG_DEV_ADC */
  112. /* Camif Controller */
  113. #ifdef CONFIG_CPU_S3C2440
  114. static struct resource s3c_camif_resource[] = {
  115. [0] = DEFINE_RES_MEM(S3C2440_PA_CAMIF, S3C2440_SZ_CAMIF),
  116. [1] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_C),
  117. [2] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_P),
  118. };
  119. struct platform_device s3c_device_camif = {
  120. .name = "s3c2440-camif",
  121. .id = -1,
  122. .num_resources = ARRAY_SIZE(s3c_camif_resource),
  123. .resource = s3c_camif_resource,
  124. .dev = {
  125. .dma_mask = &samsung_device_dma_mask,
  126. .coherent_dma_mask = DMA_BIT_MASK(32),
  127. }
  128. };
  129. #endif /* CONFIG_CPU_S3C2440 */
  130. /* ASOC DMA */
  131. struct platform_device samsung_asoc_dma = {
  132. .name = "samsung-audio",
  133. .id = -1,
  134. .dev = {
  135. .dma_mask = &samsung_device_dma_mask,
  136. .coherent_dma_mask = DMA_BIT_MASK(32),
  137. }
  138. };
  139. struct platform_device samsung_asoc_idma = {
  140. .name = "samsung-idma",
  141. .id = -1,
  142. .dev = {
  143. .dma_mask = &samsung_device_dma_mask,
  144. .coherent_dma_mask = DMA_BIT_MASK(32),
  145. }
  146. };
  147. /* FB */
  148. #ifdef CONFIG_S3C_DEV_FB
  149. static struct resource s3c_fb_resource[] = {
  150. [0] = DEFINE_RES_MEM(S3C_PA_FB, SZ_16K),
  151. [1] = DEFINE_RES_IRQ(IRQ_LCD_VSYNC),
  152. [2] = DEFINE_RES_IRQ(IRQ_LCD_FIFO),
  153. [3] = DEFINE_RES_IRQ(IRQ_LCD_SYSTEM),
  154. };
  155. struct platform_device s3c_device_fb = {
  156. .name = "s3c-fb",
  157. .id = -1,
  158. .num_resources = ARRAY_SIZE(s3c_fb_resource),
  159. .resource = s3c_fb_resource,
  160. .dev = {
  161. .dma_mask = &samsung_device_dma_mask,
  162. .coherent_dma_mask = DMA_BIT_MASK(32),
  163. },
  164. };
  165. void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
  166. {
  167. s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
  168. &s3c_device_fb);
  169. }
  170. #endif /* CONFIG_S3C_DEV_FB */
  171. /* FIMC */
  172. #ifdef CONFIG_S5P_DEV_FIMC0
  173. static struct resource s5p_fimc0_resource[] = {
  174. [0] = DEFINE_RES_MEM(S5P_PA_FIMC0, SZ_4K),
  175. [1] = DEFINE_RES_IRQ(IRQ_FIMC0),
  176. };
  177. struct platform_device s5p_device_fimc0 = {
  178. .name = "s5p-fimc",
  179. .id = 0,
  180. .num_resources = ARRAY_SIZE(s5p_fimc0_resource),
  181. .resource = s5p_fimc0_resource,
  182. .dev = {
  183. .dma_mask = &samsung_device_dma_mask,
  184. .coherent_dma_mask = DMA_BIT_MASK(32),
  185. },
  186. };
  187. struct platform_device s5p_device_fimc_md = {
  188. .name = "s5p-fimc-md",
  189. .id = -1,
  190. };
  191. #endif /* CONFIG_S5P_DEV_FIMC0 */
  192. #ifdef CONFIG_S5P_DEV_FIMC1
  193. static struct resource s5p_fimc1_resource[] = {
  194. [0] = DEFINE_RES_MEM(S5P_PA_FIMC1, SZ_4K),
  195. [1] = DEFINE_RES_IRQ(IRQ_FIMC1),
  196. };
  197. struct platform_device s5p_device_fimc1 = {
  198. .name = "s5p-fimc",
  199. .id = 1,
  200. .num_resources = ARRAY_SIZE(s5p_fimc1_resource),
  201. .resource = s5p_fimc1_resource,
  202. .dev = {
  203. .dma_mask = &samsung_device_dma_mask,
  204. .coherent_dma_mask = DMA_BIT_MASK(32),
  205. },
  206. };
  207. #endif /* CONFIG_S5P_DEV_FIMC1 */
  208. #ifdef CONFIG_S5P_DEV_FIMC2
  209. static struct resource s5p_fimc2_resource[] = {
  210. [0] = DEFINE_RES_MEM(S5P_PA_FIMC2, SZ_4K),
  211. [1] = DEFINE_RES_IRQ(IRQ_FIMC2),
  212. };
  213. struct platform_device s5p_device_fimc2 = {
  214. .name = "s5p-fimc",
  215. .id = 2,
  216. .num_resources = ARRAY_SIZE(s5p_fimc2_resource),
  217. .resource = s5p_fimc2_resource,
  218. .dev = {
  219. .dma_mask = &samsung_device_dma_mask,
  220. .coherent_dma_mask = DMA_BIT_MASK(32),
  221. },
  222. };
  223. #endif /* CONFIG_S5P_DEV_FIMC2 */
  224. #ifdef CONFIG_S5P_DEV_FIMC3
  225. static struct resource s5p_fimc3_resource[] = {
  226. [0] = DEFINE_RES_MEM(S5P_PA_FIMC3, SZ_4K),
  227. [1] = DEFINE_RES_IRQ(IRQ_FIMC3),
  228. };
  229. struct platform_device s5p_device_fimc3 = {
  230. .name = "s5p-fimc",
  231. .id = 3,
  232. .num_resources = ARRAY_SIZE(s5p_fimc3_resource),
  233. .resource = s5p_fimc3_resource,
  234. .dev = {
  235. .dma_mask = &samsung_device_dma_mask,
  236. .coherent_dma_mask = DMA_BIT_MASK(32),
  237. },
  238. };
  239. #endif /* CONFIG_S5P_DEV_FIMC3 */
  240. /* G2D */
  241. #ifdef CONFIG_S5P_DEV_G2D
  242. static struct resource s5p_g2d_resource[] = {
  243. [0] = DEFINE_RES_MEM(S5P_PA_G2D, SZ_4K),
  244. [1] = DEFINE_RES_IRQ(IRQ_2D),
  245. };
  246. struct platform_device s5p_device_g2d = {
  247. .name = "s5p-g2d",
  248. .id = 0,
  249. .num_resources = ARRAY_SIZE(s5p_g2d_resource),
  250. .resource = s5p_g2d_resource,
  251. .dev = {
  252. .dma_mask = &samsung_device_dma_mask,
  253. .coherent_dma_mask = DMA_BIT_MASK(32),
  254. },
  255. };
  256. #endif /* CONFIG_S5P_DEV_G2D */
  257. #ifdef CONFIG_S5P_DEV_JPEG
  258. static struct resource s5p_jpeg_resource[] = {
  259. [0] = DEFINE_RES_MEM(S5P_PA_JPEG, SZ_4K),
  260. [1] = DEFINE_RES_IRQ(IRQ_JPEG),
  261. };
  262. struct platform_device s5p_device_jpeg = {
  263. .name = "s5p-jpeg",
  264. .id = 0,
  265. .num_resources = ARRAY_SIZE(s5p_jpeg_resource),
  266. .resource = s5p_jpeg_resource,
  267. .dev = {
  268. .dma_mask = &samsung_device_dma_mask,
  269. .coherent_dma_mask = DMA_BIT_MASK(32),
  270. },
  271. };
  272. #endif /* CONFIG_S5P_DEV_JPEG */
  273. /* FIMD0 */
  274. #ifdef CONFIG_S5P_DEV_FIMD0
  275. static struct resource s5p_fimd0_resource[] = {
  276. [0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K),
  277. [1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC),
  278. [2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO),
  279. [3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM),
  280. };
  281. struct platform_device s5p_device_fimd0 = {
  282. .name = "s5p-fb",
  283. .id = 0,
  284. .num_resources = ARRAY_SIZE(s5p_fimd0_resource),
  285. .resource = s5p_fimd0_resource,
  286. .dev = {
  287. .dma_mask = &samsung_device_dma_mask,
  288. .coherent_dma_mask = DMA_BIT_MASK(32),
  289. },
  290. };
  291. void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd)
  292. {
  293. s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
  294. &s5p_device_fimd0);
  295. }
  296. #endif /* CONFIG_S5P_DEV_FIMD0 */
  297. /* HWMON */
  298. #ifdef CONFIG_S3C_DEV_HWMON
  299. struct platform_device s3c_device_hwmon = {
  300. .name = "s3c-hwmon",
  301. .id = -1,
  302. .dev.parent = &s3c_device_adc.dev,
  303. };
  304. void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd)
  305. {
  306. s3c_set_platdata(pd, sizeof(struct s3c_hwmon_pdata),
  307. &s3c_device_hwmon);
  308. }
  309. #endif /* CONFIG_S3C_DEV_HWMON */
  310. /* HSMMC */
  311. #ifdef CONFIG_S3C_DEV_HSMMC
  312. static struct resource s3c_hsmmc_resource[] = {
  313. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC0, SZ_4K),
  314. [1] = DEFINE_RES_IRQ(IRQ_HSMMC0),
  315. };
  316. struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
  317. .max_width = 4,
  318. .host_caps = (MMC_CAP_4_BIT_DATA |
  319. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  320. };
  321. struct platform_device s3c_device_hsmmc0 = {
  322. .name = "s3c-sdhci",
  323. .id = 0,
  324. .num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
  325. .resource = s3c_hsmmc_resource,
  326. .dev = {
  327. .dma_mask = &samsung_device_dma_mask,
  328. .coherent_dma_mask = DMA_BIT_MASK(32),
  329. .platform_data = &s3c_hsmmc0_def_platdata,
  330. },
  331. };
  332. void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
  333. {
  334. s3c_sdhci_set_platdata(pd, &s3c_hsmmc0_def_platdata);
  335. }
  336. #endif /* CONFIG_S3C_DEV_HSMMC */
  337. #ifdef CONFIG_S3C_DEV_HSMMC1
  338. static struct resource s3c_hsmmc1_resource[] = {
  339. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC1, SZ_4K),
  340. [1] = DEFINE_RES_IRQ(IRQ_HSMMC1),
  341. };
  342. struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
  343. .max_width = 4,
  344. .host_caps = (MMC_CAP_4_BIT_DATA |
  345. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  346. };
  347. struct platform_device s3c_device_hsmmc1 = {
  348. .name = "s3c-sdhci",
  349. .id = 1,
  350. .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
  351. .resource = s3c_hsmmc1_resource,
  352. .dev = {
  353. .dma_mask = &samsung_device_dma_mask,
  354. .coherent_dma_mask = DMA_BIT_MASK(32),
  355. .platform_data = &s3c_hsmmc1_def_platdata,
  356. },
  357. };
  358. void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
  359. {
  360. s3c_sdhci_set_platdata(pd, &s3c_hsmmc1_def_platdata);
  361. }
  362. #endif /* CONFIG_S3C_DEV_HSMMC1 */
  363. /* HSMMC2 */
  364. #ifdef CONFIG_S3C_DEV_HSMMC2
  365. static struct resource s3c_hsmmc2_resource[] = {
  366. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC2, SZ_4K),
  367. [1] = DEFINE_RES_IRQ(IRQ_HSMMC2),
  368. };
  369. struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = {
  370. .max_width = 4,
  371. .host_caps = (MMC_CAP_4_BIT_DATA |
  372. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  373. };
  374. struct platform_device s3c_device_hsmmc2 = {
  375. .name = "s3c-sdhci",
  376. .id = 2,
  377. .num_resources = ARRAY_SIZE(s3c_hsmmc2_resource),
  378. .resource = s3c_hsmmc2_resource,
  379. .dev = {
  380. .dma_mask = &samsung_device_dma_mask,
  381. .coherent_dma_mask = DMA_BIT_MASK(32),
  382. .platform_data = &s3c_hsmmc2_def_platdata,
  383. },
  384. };
  385. void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
  386. {
  387. s3c_sdhci_set_platdata(pd, &s3c_hsmmc2_def_platdata);
  388. }
  389. #endif /* CONFIG_S3C_DEV_HSMMC2 */
  390. #ifdef CONFIG_S3C_DEV_HSMMC3
  391. static struct resource s3c_hsmmc3_resource[] = {
  392. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC3, SZ_4K),
  393. [1] = DEFINE_RES_IRQ(IRQ_HSMMC3),
  394. };
  395. struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = {
  396. .max_width = 4,
  397. .host_caps = (MMC_CAP_4_BIT_DATA |
  398. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  399. };
  400. struct platform_device s3c_device_hsmmc3 = {
  401. .name = "s3c-sdhci",
  402. .id = 3,
  403. .num_resources = ARRAY_SIZE(s3c_hsmmc3_resource),
  404. .resource = s3c_hsmmc3_resource,
  405. .dev = {
  406. .dma_mask = &samsung_device_dma_mask,
  407. .coherent_dma_mask = DMA_BIT_MASK(32),
  408. .platform_data = &s3c_hsmmc3_def_platdata,
  409. },
  410. };
  411. void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
  412. {
  413. s3c_sdhci_set_platdata(pd, &s3c_hsmmc3_def_platdata);
  414. }
  415. #endif /* CONFIG_S3C_DEV_HSMMC3 */
  416. /* I2C */
  417. static struct resource s3c_i2c0_resource[] = {
  418. [0] = DEFINE_RES_MEM(S3C_PA_IIC, SZ_4K),
  419. [1] = DEFINE_RES_IRQ(IRQ_IIC),
  420. };
  421. struct platform_device s3c_device_i2c0 = {
  422. .name = "s3c2410-i2c",
  423. .id = 0,
  424. .num_resources = ARRAY_SIZE(s3c_i2c0_resource),
  425. .resource = s3c_i2c0_resource,
  426. };
  427. struct s3c2410_platform_i2c default_i2c_data __initdata = {
  428. .flags = 0,
  429. .slave_addr = 0x10,
  430. .frequency = 100*1000,
  431. .sda_delay = 100,
  432. };
  433. void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
  434. {
  435. struct s3c2410_platform_i2c *npd;
  436. if (!pd) {
  437. pd = &default_i2c_data;
  438. pd->bus_num = 0;
  439. }
  440. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  441. &s3c_device_i2c0);
  442. if (!npd->cfg_gpio)
  443. npd->cfg_gpio = s3c_i2c0_cfg_gpio;
  444. }
  445. #ifdef CONFIG_S3C_DEV_I2C1
  446. static struct resource s3c_i2c1_resource[] = {
  447. [0] = DEFINE_RES_MEM(S3C_PA_IIC1, SZ_4K),
  448. [1] = DEFINE_RES_IRQ(IRQ_IIC1),
  449. };
  450. struct platform_device s3c_device_i2c1 = {
  451. .name = "s3c2410-i2c",
  452. .id = 1,
  453. .num_resources = ARRAY_SIZE(s3c_i2c1_resource),
  454. .resource = s3c_i2c1_resource,
  455. };
  456. void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
  457. {
  458. struct s3c2410_platform_i2c *npd;
  459. if (!pd) {
  460. pd = &default_i2c_data;
  461. pd->bus_num = 1;
  462. }
  463. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  464. &s3c_device_i2c1);
  465. if (!npd->cfg_gpio)
  466. npd->cfg_gpio = s3c_i2c1_cfg_gpio;
  467. }
  468. #endif /* CONFIG_S3C_DEV_I2C1 */
  469. #ifdef CONFIG_S3C_DEV_I2C2
  470. static struct resource s3c_i2c2_resource[] = {
  471. [0] = DEFINE_RES_MEM(S3C_PA_IIC2, SZ_4K),
  472. [1] = DEFINE_RES_IRQ(IRQ_IIC2),
  473. };
  474. struct platform_device s3c_device_i2c2 = {
  475. .name = "s3c2410-i2c",
  476. .id = 2,
  477. .num_resources = ARRAY_SIZE(s3c_i2c2_resource),
  478. .resource = s3c_i2c2_resource,
  479. };
  480. void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd)
  481. {
  482. struct s3c2410_platform_i2c *npd;
  483. if (!pd) {
  484. pd = &default_i2c_data;
  485. pd->bus_num = 2;
  486. }
  487. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  488. &s3c_device_i2c2);
  489. if (!npd->cfg_gpio)
  490. npd->cfg_gpio = s3c_i2c2_cfg_gpio;
  491. }
  492. #endif /* CONFIG_S3C_DEV_I2C2 */
  493. #ifdef CONFIG_S3C_DEV_I2C3
  494. static struct resource s3c_i2c3_resource[] = {
  495. [0] = DEFINE_RES_MEM(S3C_PA_IIC3, SZ_4K),
  496. [1] = DEFINE_RES_IRQ(IRQ_IIC3),
  497. };
  498. struct platform_device s3c_device_i2c3 = {
  499. .name = "s3c2440-i2c",
  500. .id = 3,
  501. .num_resources = ARRAY_SIZE(s3c_i2c3_resource),
  502. .resource = s3c_i2c3_resource,
  503. };
  504. void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd)
  505. {
  506. struct s3c2410_platform_i2c *npd;
  507. if (!pd) {
  508. pd = &default_i2c_data;
  509. pd->bus_num = 3;
  510. }
  511. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  512. &s3c_device_i2c3);
  513. if (!npd->cfg_gpio)
  514. npd->cfg_gpio = s3c_i2c3_cfg_gpio;
  515. }
  516. #endif /*CONFIG_S3C_DEV_I2C3 */
  517. #ifdef CONFIG_S3C_DEV_I2C4
  518. static struct resource s3c_i2c4_resource[] = {
  519. [0] = DEFINE_RES_MEM(S3C_PA_IIC4, SZ_4K),
  520. [1] = DEFINE_RES_IRQ(IRQ_IIC4),
  521. };
  522. struct platform_device s3c_device_i2c4 = {
  523. .name = "s3c2440-i2c",
  524. .id = 4,
  525. .num_resources = ARRAY_SIZE(s3c_i2c4_resource),
  526. .resource = s3c_i2c4_resource,
  527. };
  528. void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd)
  529. {
  530. struct s3c2410_platform_i2c *npd;
  531. if (!pd) {
  532. pd = &default_i2c_data;
  533. pd->bus_num = 4;
  534. }
  535. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  536. &s3c_device_i2c4);
  537. if (!npd->cfg_gpio)
  538. npd->cfg_gpio = s3c_i2c4_cfg_gpio;
  539. }
  540. #endif /*CONFIG_S3C_DEV_I2C4 */
  541. #ifdef CONFIG_S3C_DEV_I2C5
  542. static struct resource s3c_i2c5_resource[] = {
  543. [0] = DEFINE_RES_MEM(S3C_PA_IIC5, SZ_4K),
  544. [1] = DEFINE_RES_IRQ(IRQ_IIC5),
  545. };
  546. struct platform_device s3c_device_i2c5 = {
  547. .name = "s3c2440-i2c",
  548. .id = 5,
  549. .num_resources = ARRAY_SIZE(s3c_i2c5_resource),
  550. .resource = s3c_i2c5_resource,
  551. };
  552. void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd)
  553. {
  554. struct s3c2410_platform_i2c *npd;
  555. if (!pd) {
  556. pd = &default_i2c_data;
  557. pd->bus_num = 5;
  558. }
  559. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  560. &s3c_device_i2c5);
  561. if (!npd->cfg_gpio)
  562. npd->cfg_gpio = s3c_i2c5_cfg_gpio;
  563. }
  564. #endif /*CONFIG_S3C_DEV_I2C5 */
  565. #ifdef CONFIG_S3C_DEV_I2C6
  566. static struct resource s3c_i2c6_resource[] = {
  567. [0] = DEFINE_RES_MEM(S3C_PA_IIC6, SZ_4K),
  568. [1] = DEFINE_RES_IRQ(IRQ_IIC6),
  569. };
  570. struct platform_device s3c_device_i2c6 = {
  571. .name = "s3c2440-i2c",
  572. .id = 6,
  573. .num_resources = ARRAY_SIZE(s3c_i2c6_resource),
  574. .resource = s3c_i2c6_resource,
  575. };
  576. void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd)
  577. {
  578. struct s3c2410_platform_i2c *npd;
  579. if (!pd) {
  580. pd = &default_i2c_data;
  581. pd->bus_num = 6;
  582. }
  583. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  584. &s3c_device_i2c6);
  585. if (!npd->cfg_gpio)
  586. npd->cfg_gpio = s3c_i2c6_cfg_gpio;
  587. }
  588. #endif /* CONFIG_S3C_DEV_I2C6 */
  589. #ifdef CONFIG_S3C_DEV_I2C7
  590. static struct resource s3c_i2c7_resource[] = {
  591. [0] = DEFINE_RES_MEM(S3C_PA_IIC7, SZ_4K),
  592. [1] = DEFINE_RES_IRQ(IRQ_IIC7),
  593. };
  594. struct platform_device s3c_device_i2c7 = {
  595. .name = "s3c2440-i2c",
  596. .id = 7,
  597. .num_resources = ARRAY_SIZE(s3c_i2c7_resource),
  598. .resource = s3c_i2c7_resource,
  599. };
  600. void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd)
  601. {
  602. struct s3c2410_platform_i2c *npd;
  603. if (!pd) {
  604. pd = &default_i2c_data;
  605. pd->bus_num = 7;
  606. }
  607. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  608. &s3c_device_i2c7);
  609. if (!npd->cfg_gpio)
  610. npd->cfg_gpio = s3c_i2c7_cfg_gpio;
  611. }
  612. #endif /* CONFIG_S3C_DEV_I2C7 */
  613. /* I2C HDMIPHY */
  614. #ifdef CONFIG_S5P_DEV_I2C_HDMIPHY
  615. static struct resource s5p_i2c_resource[] = {
  616. [0] = DEFINE_RES_MEM(S5P_PA_IIC_HDMIPHY, SZ_4K),
  617. [1] = DEFINE_RES_IRQ(IRQ_IIC_HDMIPHY),
  618. };
  619. struct platform_device s5p_device_i2c_hdmiphy = {
  620. .name = "s3c2440-hdmiphy-i2c",
  621. .id = -1,
  622. .num_resources = ARRAY_SIZE(s5p_i2c_resource),
  623. .resource = s5p_i2c_resource,
  624. };
  625. void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
  626. {
  627. struct s3c2410_platform_i2c *npd;
  628. if (!pd) {
  629. pd = &default_i2c_data;
  630. if (soc_is_exynos4210() ||
  631. soc_is_exynos4212() || soc_is_exynos4412())
  632. pd->bus_num = 8;
  633. else if (soc_is_s5pv210())
  634. pd->bus_num = 3;
  635. else
  636. pd->bus_num = 0;
  637. }
  638. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  639. &s5p_device_i2c_hdmiphy);
  640. }
  641. static struct s5p_hdmi_platform_data s5p_hdmi_def_platdata;
  642. void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
  643. struct i2c_board_info *mhl_info, int mhl_bus)
  644. {
  645. struct s5p_hdmi_platform_data *pd = &s5p_hdmi_def_platdata;
  646. if (soc_is_exynos4210() ||
  647. soc_is_exynos4212() || soc_is_exynos4412())
  648. pd->hdmiphy_bus = 8;
  649. else if (soc_is_s5pv210())
  650. pd->hdmiphy_bus = 3;
  651. else
  652. pd->hdmiphy_bus = 0;
  653. pd->hdmiphy_info = hdmiphy_info;
  654. pd->mhl_info = mhl_info;
  655. pd->mhl_bus = mhl_bus;
  656. s3c_set_platdata(pd, sizeof(struct s5p_hdmi_platform_data),
  657. &s5p_device_hdmi);
  658. }
  659. #endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */
  660. /* I2S */
  661. #ifdef CONFIG_PLAT_S3C24XX
  662. static struct resource s3c_iis_resource[] = {
  663. [0] = DEFINE_RES_MEM(S3C24XX_PA_IIS, S3C24XX_SZ_IIS),
  664. };
  665. struct platform_device s3c_device_iis = {
  666. .name = "s3c24xx-iis",
  667. .id = -1,
  668. .num_resources = ARRAY_SIZE(s3c_iis_resource),
  669. .resource = s3c_iis_resource,
  670. .dev = {
  671. .dma_mask = &samsung_device_dma_mask,
  672. .coherent_dma_mask = DMA_BIT_MASK(32),
  673. }
  674. };
  675. #endif /* CONFIG_PLAT_S3C24XX */
  676. /* IDE CFCON */
  677. #ifdef CONFIG_SAMSUNG_DEV_IDE
  678. static struct resource s3c_cfcon_resource[] = {
  679. [0] = DEFINE_RES_MEM(SAMSUNG_PA_CFCON, SZ_16K),
  680. [1] = DEFINE_RES_IRQ(IRQ_CFCON),
  681. };
  682. struct platform_device s3c_device_cfcon = {
  683. .id = 0,
  684. .num_resources = ARRAY_SIZE(s3c_cfcon_resource),
  685. .resource = s3c_cfcon_resource,
  686. };
  687. void __init s3c_ide_set_platdata(struct s3c_ide_platdata *pdata)
  688. {
  689. s3c_set_platdata(pdata, sizeof(struct s3c_ide_platdata),
  690. &s3c_device_cfcon);
  691. }
  692. #endif /* CONFIG_SAMSUNG_DEV_IDE */
  693. /* KEYPAD */
  694. #ifdef CONFIG_SAMSUNG_DEV_KEYPAD
  695. static struct resource samsung_keypad_resources[] = {
  696. [0] = DEFINE_RES_MEM(SAMSUNG_PA_KEYPAD, SZ_32),
  697. [1] = DEFINE_RES_IRQ(IRQ_KEYPAD),
  698. };
  699. struct platform_device samsung_device_keypad = {
  700. .name = "samsung-keypad",
  701. .id = -1,
  702. .num_resources = ARRAY_SIZE(samsung_keypad_resources),
  703. .resource = samsung_keypad_resources,
  704. };
  705. void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
  706. {
  707. struct samsung_keypad_platdata *npd;
  708. npd = s3c_set_platdata(pd, sizeof(struct samsung_keypad_platdata),
  709. &samsung_device_keypad);
  710. if (!npd->cfg_gpio)
  711. npd->cfg_gpio = samsung_keypad_cfg_gpio;
  712. }
  713. #endif /* CONFIG_SAMSUNG_DEV_KEYPAD */
  714. /* LCD Controller */
  715. #ifdef CONFIG_PLAT_S3C24XX
  716. static struct resource s3c_lcd_resource[] = {
  717. [0] = DEFINE_RES_MEM(S3C24XX_PA_LCD, S3C24XX_SZ_LCD),
  718. [1] = DEFINE_RES_IRQ(IRQ_LCD),
  719. };
  720. struct platform_device s3c_device_lcd = {
  721. .name = "s3c2410-lcd",
  722. .id = -1,
  723. .num_resources = ARRAY_SIZE(s3c_lcd_resource),
  724. .resource = s3c_lcd_resource,
  725. .dev = {
  726. .dma_mask = &samsung_device_dma_mask,
  727. .coherent_dma_mask = DMA_BIT_MASK(32),
  728. }
  729. };
  730. void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
  731. {
  732. struct s3c2410fb_mach_info *npd;
  733. npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_lcd);
  734. if (npd) {
  735. npd->displays = kmemdup(pd->displays,
  736. sizeof(struct s3c2410fb_display) * npd->num_displays,
  737. GFP_KERNEL);
  738. if (!npd->displays)
  739. printk(KERN_ERR "no memory for LCD display data\n");
  740. } else {
  741. printk(KERN_ERR "no memory for LCD platform data\n");
  742. }
  743. }
  744. #endif /* CONFIG_PLAT_S3C24XX */
  745. /* MFC */
  746. #ifdef CONFIG_S5P_DEV_MFC
  747. static struct resource s5p_mfc_resource[] = {
  748. [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K),
  749. [1] = DEFINE_RES_IRQ(IRQ_MFC),
  750. };
  751. struct platform_device s5p_device_mfc = {
  752. .name = "s5p-mfc",
  753. .id = -1,
  754. .num_resources = ARRAY_SIZE(s5p_mfc_resource),
  755. .resource = s5p_mfc_resource,
  756. };
  757. /*
  758. * MFC hardware has 2 memory interfaces which are modelled as two separate
  759. * platform devices to let dma-mapping distinguish between them.
  760. *
  761. * MFC parent device (s5p_device_mfc) must be registered before memory
  762. * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
  763. */
  764. struct platform_device s5p_device_mfc_l = {
  765. .name = "s5p-mfc-l",
  766. .id = -1,
  767. .dev = {
  768. .parent = &s5p_device_mfc.dev,
  769. .dma_mask = &samsung_device_dma_mask,
  770. .coherent_dma_mask = DMA_BIT_MASK(32),
  771. },
  772. };
  773. struct platform_device s5p_device_mfc_r = {
  774. .name = "s5p-mfc-r",
  775. .id = -1,
  776. .dev = {
  777. .parent = &s5p_device_mfc.dev,
  778. .dma_mask = &samsung_device_dma_mask,
  779. .coherent_dma_mask = DMA_BIT_MASK(32),
  780. },
  781. };
  782. #endif /* CONFIG_S5P_DEV_MFC */
  783. /* MIPI CSIS */
  784. #ifdef CONFIG_S5P_DEV_CSIS0
  785. static struct resource s5p_mipi_csis0_resource[] = {
  786. [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS0, SZ_16K),
  787. [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS0),
  788. };
  789. struct platform_device s5p_device_mipi_csis0 = {
  790. .name = "s5p-mipi-csis",
  791. .id = 0,
  792. .num_resources = ARRAY_SIZE(s5p_mipi_csis0_resource),
  793. .resource = s5p_mipi_csis0_resource,
  794. };
  795. #endif /* CONFIG_S5P_DEV_CSIS0 */
  796. #ifdef CONFIG_S5P_DEV_CSIS1
  797. static struct resource s5p_mipi_csis1_resource[] = {
  798. [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS1, SZ_16K),
  799. [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS1),
  800. };
  801. struct platform_device s5p_device_mipi_csis1 = {
  802. .name = "s5p-mipi-csis",
  803. .id = 1,
  804. .num_resources = ARRAY_SIZE(s5p_mipi_csis1_resource),
  805. .resource = s5p_mipi_csis1_resource,
  806. };
  807. #endif
  808. /* NAND */
  809. #ifdef CONFIG_S3C_DEV_NAND
  810. static struct resource s3c_nand_resource[] = {
  811. [0] = DEFINE_RES_MEM(S3C_PA_NAND, SZ_1M),
  812. };
  813. struct platform_device s3c_device_nand = {
  814. .name = "s3c2410-nand",
  815. .id = -1,
  816. .num_resources = ARRAY_SIZE(s3c_nand_resource),
  817. .resource = s3c_nand_resource,
  818. };
  819. /*
  820. * s3c_nand_copy_set() - copy nand set data
  821. * @set: The new structure, directly copied from the old.
  822. *
  823. * Copy all the fields from the NAND set field from what is probably __initdata
  824. * to new kernel memory. The code returns 0 if the copy happened correctly or
  825. * an error code for the calling function to display.
  826. *
  827. * Note, we currently do not try and look to see if we've already copied the
  828. * data in a previous set.
  829. */
  830. static int __init s3c_nand_copy_set(struct s3c2410_nand_set *set)
  831. {
  832. void *ptr;
  833. int size;
  834. size = sizeof(struct mtd_partition) * set->nr_partitions;
  835. if (size) {
  836. ptr = kmemdup(set->partitions, size, GFP_KERNEL);
  837. set->partitions = ptr;
  838. if (!ptr)
  839. return -ENOMEM;
  840. }
  841. if (set->nr_map && set->nr_chips) {
  842. size = sizeof(int) * set->nr_chips;
  843. ptr = kmemdup(set->nr_map, size, GFP_KERNEL);
  844. set->nr_map = ptr;
  845. if (!ptr)
  846. return -ENOMEM;
  847. }
  848. if (set->ecc_layout) {
  849. ptr = kmemdup(set->ecc_layout,
  850. sizeof(struct nand_ecclayout), GFP_KERNEL);
  851. set->ecc_layout = ptr;
  852. if (!ptr)
  853. return -ENOMEM;
  854. }
  855. return 0;
  856. }
  857. void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand)
  858. {
  859. struct s3c2410_platform_nand *npd;
  860. int size;
  861. int ret;
  862. /* note, if we get a failure in allocation, we simply drop out of the
  863. * function. If there is so little memory available at initialisation
  864. * time then there is little chance the system is going to run.
  865. */
  866. npd = s3c_set_platdata(nand, sizeof(struct s3c2410_platform_nand),
  867. &s3c_device_nand);
  868. if (!npd)
  869. return;
  870. /* now see if we need to copy any of the nand set data */
  871. size = sizeof(struct s3c2410_nand_set) * npd->nr_sets;
  872. if (size) {
  873. struct s3c2410_nand_set *from = npd->sets;
  874. struct s3c2410_nand_set *to;
  875. int i;
  876. to = kmemdup(from, size, GFP_KERNEL);
  877. npd->sets = to; /* set, even if we failed */
  878. if (!to) {
  879. printk(KERN_ERR "%s: no memory for sets\n", __func__);
  880. return;
  881. }
  882. for (i = 0; i < npd->nr_sets; i++) {
  883. ret = s3c_nand_copy_set(to);
  884. if (ret) {
  885. printk(KERN_ERR "%s: failed to copy set %d\n",
  886. __func__, i);
  887. return;
  888. }
  889. to++;
  890. }
  891. }
  892. }
  893. #endif /* CONFIG_S3C_DEV_NAND */
  894. /* ONENAND */
  895. #ifdef CONFIG_S3C_DEV_ONENAND
  896. static struct resource s3c_onenand_resources[] = {
  897. [0] = DEFINE_RES_MEM(S3C_PA_ONENAND, SZ_1K),
  898. [1] = DEFINE_RES_MEM(S3C_PA_ONENAND_BUF, S3C_SZ_ONENAND_BUF),
  899. [2] = DEFINE_RES_IRQ(IRQ_ONENAND),
  900. };
  901. struct platform_device s3c_device_onenand = {
  902. .name = "samsung-onenand",
  903. .id = 0,
  904. .num_resources = ARRAY_SIZE(s3c_onenand_resources),
  905. .resource = s3c_onenand_resources,
  906. };
  907. #endif /* CONFIG_S3C_DEV_ONENAND */
  908. #ifdef CONFIG_S3C64XX_DEV_ONENAND1
  909. static struct resource s3c64xx_onenand1_resources[] = {
  910. [0] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1, SZ_1K),
  911. [1] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1_BUF, S3C64XX_SZ_ONENAND1_BUF),
  912. [2] = DEFINE_RES_IRQ(IRQ_ONENAND1),
  913. };
  914. struct platform_device s3c64xx_device_onenand1 = {
  915. .name = "samsung-onenand",
  916. .id = 1,
  917. .num_resources = ARRAY_SIZE(s3c64xx_onenand1_resources),
  918. .resource = s3c64xx_onenand1_resources,
  919. };
  920. void __init s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
  921. {
  922. s3c_set_platdata(pdata, sizeof(struct onenand_platform_data),
  923. &s3c64xx_device_onenand1);
  924. }
  925. #endif /* CONFIG_S3C64XX_DEV_ONENAND1 */
  926. #ifdef CONFIG_S5P_DEV_ONENAND
  927. static struct resource s5p_onenand_resources[] = {
  928. [0] = DEFINE_RES_MEM(S5P_PA_ONENAND, SZ_128K),
  929. [1] = DEFINE_RES_MEM(S5P_PA_ONENAND_DMA, SZ_8K),
  930. [2] = DEFINE_RES_IRQ(IRQ_ONENAND_AUDI),
  931. };
  932. struct platform_device s5p_device_onenand = {
  933. .name = "s5pc110-onenand",
  934. .id = -1,
  935. .num_resources = ARRAY_SIZE(s5p_onenand_resources),
  936. .resource = s5p_onenand_resources,
  937. };
  938. #endif /* CONFIG_S5P_DEV_ONENAND */
  939. /* PMU */
  940. #ifdef CONFIG_PLAT_S5P
  941. static struct resource s5p_pmu_resource[] = {
  942. DEFINE_RES_IRQ(IRQ_PMU)
  943. };
  944. static struct platform_device s5p_device_pmu = {
  945. .name = "arm-pmu",
  946. .id = -1,
  947. .num_resources = ARRAY_SIZE(s5p_pmu_resource),
  948. .resource = s5p_pmu_resource,
  949. };
  950. static int __init s5p_pmu_init(void)
  951. {
  952. platform_device_register(&s5p_device_pmu);
  953. return 0;
  954. }
  955. arch_initcall(s5p_pmu_init);
  956. #endif /* CONFIG_PLAT_S5P */
  957. /* PWM Timer */
  958. #ifdef CONFIG_SAMSUNG_DEV_PWM
  959. #define TIMER_RESOURCE_SIZE (1)
  960. #define TIMER_RESOURCE(_tmr, _irq) \
  961. (struct resource [TIMER_RESOURCE_SIZE]) { \
  962. [0] = { \
  963. .start = _irq, \
  964. .end = _irq, \
  965. .flags = IORESOURCE_IRQ \
  966. } \
  967. }
  968. #define DEFINE_S3C_TIMER(_tmr_no, _irq) \
  969. .name = "s3c24xx-pwm", \
  970. .id = _tmr_no, \
  971. .num_resources = TIMER_RESOURCE_SIZE, \
  972. .resource = TIMER_RESOURCE(_tmr_no, _irq), \
  973. /*
  974. * since we already have an static mapping for the timer,
  975. * we do not bother setting any IO resource for the base.
  976. */
  977. struct platform_device s3c_device_timer[] = {
  978. [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) },
  979. [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) },
  980. [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) },
  981. [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) },
  982. [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) },
  983. };
  984. #endif /* CONFIG_SAMSUNG_DEV_PWM */
  985. /* RTC */
  986. #ifdef CONFIG_PLAT_S3C24XX
  987. static struct resource s3c_rtc_resource[] = {
  988. [0] = DEFINE_RES_MEM(S3C24XX_PA_RTC, SZ_256),
  989. [1] = DEFINE_RES_IRQ(IRQ_RTC),
  990. [2] = DEFINE_RES_IRQ(IRQ_TICK),
  991. };
  992. struct platform_device s3c_device_rtc = {
  993. .name = "s3c2410-rtc",
  994. .id = -1,
  995. .num_resources = ARRAY_SIZE(s3c_rtc_resource),
  996. .resource = s3c_rtc_resource,
  997. };
  998. #endif /* CONFIG_PLAT_S3C24XX */
  999. #ifdef CONFIG_S3C_DEV_RTC
  1000. static struct resource s3c_rtc_resource[] = {
  1001. [0] = DEFINE_RES_MEM(S3C_PA_RTC, SZ_256),
  1002. [1] = DEFINE_RES_IRQ(IRQ_RTC_ALARM),
  1003. [2] = DEFINE_RES_IRQ(IRQ_RTC_TIC),
  1004. };
  1005. struct platform_device s3c_device_rtc = {
  1006. .name = "s3c64xx-rtc",
  1007. .id = -1,
  1008. .num_resources = ARRAY_SIZE(s3c_rtc_resource),
  1009. .resource = s3c_rtc_resource,
  1010. };
  1011. #endif /* CONFIG_S3C_DEV_RTC */
  1012. /* SDI */
  1013. #ifdef CONFIG_PLAT_S3C24XX
  1014. static struct resource s3c_sdi_resource[] = {
  1015. [0] = DEFINE_RES_MEM(S3C24XX_PA_SDI, S3C24XX_SZ_SDI),
  1016. [1] = DEFINE_RES_IRQ(IRQ_SDI),
  1017. };
  1018. struct platform_device s3c_device_sdi = {
  1019. .name = "s3c2410-sdi",
  1020. .id = -1,
  1021. .num_resources = ARRAY_SIZE(s3c_sdi_resource),
  1022. .resource = s3c_sdi_resource,
  1023. };
  1024. void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata)
  1025. {
  1026. s3c_set_platdata(pdata, sizeof(struct s3c24xx_mci_pdata),
  1027. &s3c_device_sdi);
  1028. }
  1029. #endif /* CONFIG_PLAT_S3C24XX */
  1030. /* SPI */
  1031. #ifdef CONFIG_PLAT_S3C24XX
  1032. static struct resource s3c_spi0_resource[] = {
  1033. [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI, SZ_32),
  1034. [1] = DEFINE_RES_IRQ(IRQ_SPI0),
  1035. };
  1036. struct platform_device s3c_device_spi0 = {
  1037. .name = "s3c2410-spi",
  1038. .id = 0,
  1039. .num_resources = ARRAY_SIZE(s3c_spi0_resource),
  1040. .resource = s3c_spi0_resource,
  1041. .dev = {
  1042. .dma_mask = &samsung_device_dma_mask,
  1043. .coherent_dma_mask = DMA_BIT_MASK(32),
  1044. }
  1045. };
  1046. static struct resource s3c_spi1_resource[] = {
  1047. [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI1, SZ_32),
  1048. [1] = DEFINE_RES_IRQ(IRQ_SPI1),
  1049. };
  1050. struct platform_device s3c_device_spi1 = {
  1051. .name = "s3c2410-spi",
  1052. .id = 1,
  1053. .num_resources = ARRAY_SIZE(s3c_spi1_resource),
  1054. .resource = s3c_spi1_resource,
  1055. .dev = {
  1056. .dma_mask = &samsung_device_dma_mask,
  1057. .coherent_dma_mask = DMA_BIT_MASK(32),
  1058. }
  1059. };
  1060. #endif /* CONFIG_PLAT_S3C24XX */
  1061. /* Touchscreen */
  1062. #ifdef CONFIG_PLAT_S3C24XX
  1063. static struct resource s3c_ts_resource[] = {
  1064. [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
  1065. [1] = DEFINE_RES_IRQ(IRQ_TC),
  1066. };
  1067. struct platform_device s3c_device_ts = {
  1068. .name = "s3c2410-ts",
  1069. .id = -1,
  1070. .dev.parent = &s3c_device_adc.dev,
  1071. .num_resources = ARRAY_SIZE(s3c_ts_resource),
  1072. .resource = s3c_ts_resource,
  1073. };
  1074. void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *hard_s3c2410ts_info)
  1075. {
  1076. s3c_set_platdata(hard_s3c2410ts_info,
  1077. sizeof(struct s3c2410_ts_mach_info), &s3c_device_ts);
  1078. }
  1079. #endif /* CONFIG_PLAT_S3C24XX */
  1080. #ifdef CONFIG_SAMSUNG_DEV_TS
  1081. static struct resource s3c_ts_resource[] = {
  1082. [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
  1083. [1] = DEFINE_RES_IRQ(IRQ_TC),
  1084. };
  1085. static struct s3c2410_ts_mach_info default_ts_data __initdata = {
  1086. .delay = 10000,
  1087. .presc = 49,
  1088. .oversampling_shift = 2,
  1089. };
  1090. struct platform_device s3c_device_ts = {
  1091. .name = "s3c64xx-ts",
  1092. .id = -1,
  1093. .num_resources = ARRAY_SIZE(s3c_ts_resource),
  1094. .resource = s3c_ts_resource,
  1095. };
  1096. void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
  1097. {
  1098. if (!pd)
  1099. pd = &default_ts_data;
  1100. s3c_set_platdata(pd, sizeof(struct s3c2410_ts_mach_info),
  1101. &s3c_device_ts);
  1102. }
  1103. #endif /* CONFIG_SAMSUNG_DEV_TS */
  1104. /* TV */
  1105. #ifdef CONFIG_S5P_DEV_TV
  1106. static struct resource s5p_hdmi_resources[] = {
  1107. [0] = DEFINE_RES_MEM(S5P_PA_HDMI, SZ_1M),
  1108. [1] = DEFINE_RES_IRQ(IRQ_HDMI),
  1109. };
  1110. struct platform_device s5p_device_hdmi = {
  1111. .name = "s5p-hdmi",
  1112. .id = -1,
  1113. .num_resources = ARRAY_SIZE(s5p_hdmi_resources),
  1114. .resource = s5p_hdmi_resources,
  1115. };
  1116. static struct resource s5p_sdo_resources[] = {
  1117. [0] = DEFINE_RES_MEM(S5P_PA_SDO, SZ_64K),
  1118. [1] = DEFINE_RES_IRQ(IRQ_SDO),
  1119. };
  1120. struct platform_device s5p_device_sdo = {
  1121. .name = "s5p-sdo",
  1122. .id = -1,
  1123. .num_resources = ARRAY_SIZE(s5p_sdo_resources),
  1124. .resource = s5p_sdo_resources,
  1125. };
  1126. static struct resource s5p_mixer_resources[] = {
  1127. [0] = DEFINE_RES_MEM_NAMED(S5P_PA_MIXER, SZ_64K, "mxr"),
  1128. [1] = DEFINE_RES_MEM_NAMED(S5P_PA_VP, SZ_64K, "vp"),
  1129. [2] = DEFINE_RES_IRQ_NAMED(IRQ_MIXER, "irq"),
  1130. };
  1131. struct platform_device s5p_device_mixer = {
  1132. .name = "s5p-mixer",
  1133. .id = -1,
  1134. .num_resources = ARRAY_SIZE(s5p_mixer_resources),
  1135. .resource = s5p_mixer_resources,
  1136. .dev = {
  1137. .dma_mask = &samsung_device_dma_mask,
  1138. .coherent_dma_mask = DMA_BIT_MASK(32),
  1139. }
  1140. };
  1141. #endif /* CONFIG_S5P_DEV_TV */
  1142. /* USB */
  1143. #ifdef CONFIG_S3C_DEV_USB_HOST
  1144. static struct resource s3c_usb_resource[] = {
  1145. [0] = DEFINE_RES_MEM(S3C_PA_USBHOST, SZ_256),
  1146. [1] = DEFINE_RES_IRQ(IRQ_USBH),
  1147. };
  1148. struct platform_device s3c_device_ohci = {
  1149. .name = "s3c2410-ohci",
  1150. .id = -1,
  1151. .num_resources = ARRAY_SIZE(s3c_usb_resource),
  1152. .resource = s3c_usb_resource,
  1153. .dev = {
  1154. .dma_mask = &samsung_device_dma_mask,
  1155. .coherent_dma_mask = DMA_BIT_MASK(32),
  1156. }
  1157. };
  1158. /*
  1159. * s3c_ohci_set_platdata - initialise OHCI device platform data
  1160. * @info: The platform data.
  1161. *
  1162. * This call copies the @info passed in and sets the device .platform_data
  1163. * field to that copy. The @info is copied so that the original can be marked
  1164. * __initdata.
  1165. */
  1166. void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info)
  1167. {
  1168. s3c_set_platdata(info, sizeof(struct s3c2410_hcd_info),
  1169. &s3c_device_ohci);
  1170. }
  1171. #endif /* CONFIG_S3C_DEV_USB_HOST */
  1172. /* USB Device (Gadget) */
  1173. #ifdef CONFIG_PLAT_S3C24XX
  1174. static struct resource s3c_usbgadget_resource[] = {
  1175. [0] = DEFINE_RES_MEM(S3C24XX_PA_USBDEV, S3C24XX_SZ_USBDEV),
  1176. [1] = DEFINE_RES_IRQ(IRQ_USBD),
  1177. };
  1178. struct platform_device s3c_device_usbgadget = {
  1179. .name = "s3c2410-usbgadget",
  1180. .id = -1,
  1181. .num_resources = ARRAY_SIZE(s3c_usbgadget_resource),
  1182. .resource = s3c_usbgadget_resource,
  1183. };
  1184. void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
  1185. {
  1186. s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usbgadget);
  1187. }
  1188. #endif /* CONFIG_PLAT_S3C24XX */
  1189. /* USB EHCI Host Controller */
  1190. #ifdef CONFIG_S5P_DEV_USB_EHCI
  1191. static struct resource s5p_ehci_resource[] = {
  1192. [0] = DEFINE_RES_MEM(S5P_PA_EHCI, SZ_256),
  1193. [1] = DEFINE_RES_IRQ(IRQ_USB_HOST),
  1194. };
  1195. struct platform_device s5p_device_ehci = {
  1196. .name = "s5p-ehci",
  1197. .id = -1,
  1198. .num_resources = ARRAY_SIZE(s5p_ehci_resource),
  1199. .resource = s5p_ehci_resource,
  1200. .dev = {
  1201. .dma_mask = &samsung_device_dma_mask,
  1202. .coherent_dma_mask = DMA_BIT_MASK(32),
  1203. }
  1204. };
  1205. void __init s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd)
  1206. {
  1207. struct s5p_ehci_platdata *npd;
  1208. npd = s3c_set_platdata(pd, sizeof(struct s5p_ehci_platdata),
  1209. &s5p_device_ehci);
  1210. if (!npd->phy_init)
  1211. npd->phy_init = s5p_usb_phy_init;
  1212. if (!npd->phy_exit)
  1213. npd->phy_exit = s5p_usb_phy_exit;
  1214. }
  1215. #endif /* CONFIG_S5P_DEV_USB_EHCI */
  1216. /* USB HSOTG */
  1217. #ifdef CONFIG_S3C_DEV_USB_HSOTG
  1218. static struct resource s3c_usb_hsotg_resources[] = {
  1219. [0] = DEFINE_RES_MEM(S3C_PA_USB_HSOTG, SZ_128K),
  1220. [1] = DEFINE_RES_IRQ(IRQ_OTG),
  1221. };
  1222. struct platform_device s3c_device_usb_hsotg = {
  1223. .name = "s3c-hsotg",
  1224. .id = -1,
  1225. .num_resources = ARRAY_SIZE(s3c_usb_hsotg_resources),
  1226. .resource = s3c_usb_hsotg_resources,
  1227. .dev = {
  1228. .dma_mask = &samsung_device_dma_mask,
  1229. .coherent_dma_mask = DMA_BIT_MASK(32),
  1230. },
  1231. };
  1232. void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
  1233. {
  1234. struct s3c_hsotg_plat *npd;
  1235. npd = s3c_set_platdata(pd, sizeof(struct s3c_hsotg_plat),
  1236. &s3c_device_usb_hsotg);
  1237. if (!npd->phy_init)
  1238. npd->phy_init = s5p_usb_phy_init;
  1239. if (!npd->phy_exit)
  1240. npd->phy_exit = s5p_usb_phy_exit;
  1241. }
  1242. #endif /* CONFIG_S3C_DEV_USB_HSOTG */
  1243. /* USB High Spped 2.0 Device (Gadget) */
  1244. #ifdef CONFIG_PLAT_S3C24XX
  1245. static struct resource s3c_hsudc_resource[] = {
  1246. [0] = DEFINE_RES_MEM(S3C2416_PA_HSUDC, S3C2416_SZ_HSUDC),
  1247. [1] = DEFINE_RES_IRQ(IRQ_USBD),
  1248. };
  1249. struct platform_device s3c_device_usb_hsudc = {
  1250. .name = "s3c-hsudc",
  1251. .id = -1,
  1252. .num_resources = ARRAY_SIZE(s3c_hsudc_resource),
  1253. .resource = s3c_hsudc_resource,
  1254. .dev = {
  1255. .dma_mask = &samsung_device_dma_mask,
  1256. .coherent_dma_mask = DMA_BIT_MASK(32),
  1257. },
  1258. };
  1259. void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd)
  1260. {
  1261. s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usb_hsudc);
  1262. }
  1263. #endif /* CONFIG_PLAT_S3C24XX */
  1264. /* WDT */
  1265. #ifdef CONFIG_S3C_DEV_WDT
  1266. static struct resource s3c_wdt_resource[] = {
  1267. [0] = DEFINE_RES_MEM(S3C_PA_WDT, SZ_1K),
  1268. [1] = DEFINE_RES_IRQ(IRQ_WDT),
  1269. };
  1270. struct platform_device s3c_device_wdt = {
  1271. .name = "s3c2410-wdt",
  1272. .id = -1,
  1273. .num_resources = ARRAY_SIZE(s3c_wdt_resource),
  1274. .resource = s3c_wdt_resource,
  1275. };
  1276. #endif /* CONFIG_S3C_DEV_WDT */
  1277. #ifdef CONFIG_S3C64XX_DEV_SPI0
  1278. static struct resource s3c64xx_spi0_resource[] = {
  1279. [0] = DEFINE_RES_MEM(S3C_PA_SPI0, SZ_256),
  1280. [1] = DEFINE_RES_DMA(DMACH_SPI0_TX),
  1281. [2] = DEFINE_RES_DMA(DMACH_SPI0_RX),
  1282. [3] = DEFINE_RES_IRQ(IRQ_SPI0),
  1283. };
  1284. struct platform_device s3c64xx_device_spi0 = {
  1285. .name = "s3c6410-spi",
  1286. .id = 0,
  1287. .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
  1288. .resource = s3c64xx_spi0_resource,
  1289. .dev = {
  1290. .dma_mask = &samsung_device_dma_mask,
  1291. .coherent_dma_mask = DMA_BIT_MASK(32),
  1292. },
  1293. };
  1294. void __init s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
  1295. int num_cs)
  1296. {
  1297. struct s3c64xx_spi_info pd;
  1298. /* Reject invalid configuration */
  1299. if (!num_cs || src_clk_nr < 0) {
  1300. pr_err("%s: Invalid SPI configuration\n", __func__);
  1301. return;
  1302. }
  1303. pd.num_cs = num_cs;
  1304. pd.src_clk_nr = src_clk_nr;
  1305. pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio;
  1306. s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi0);
  1307. }
  1308. #endif /* CONFIG_S3C64XX_DEV_SPI0 */
  1309. #ifdef CONFIG_S3C64XX_DEV_SPI1
  1310. static struct resource s3c64xx_spi1_resource[] = {
  1311. [0] = DEFINE_RES_MEM(S3C_PA_SPI1, SZ_256),
  1312. [1] = DEFINE_RES_DMA(DMACH_SPI1_TX),
  1313. [2] = DEFINE_RES_DMA(DMACH_SPI1_RX),
  1314. [3] = DEFINE_RES_IRQ(IRQ_SPI1),
  1315. };
  1316. struct platform_device s3c64xx_device_spi1 = {
  1317. .name = "s3c6410-spi",
  1318. .id = 1,
  1319. .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
  1320. .resource = s3c64xx_spi1_resource,
  1321. .dev = {
  1322. .dma_mask = &samsung_device_dma_mask,
  1323. .coherent_dma_mask = DMA_BIT_MASK(32),
  1324. },
  1325. };
  1326. void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
  1327. int num_cs)
  1328. {
  1329. struct s3c64xx_spi_info pd;
  1330. /* Reject invalid configuration */
  1331. if (!num_cs || src_clk_nr < 0) {
  1332. pr_err("%s: Invalid SPI configuration\n", __func__);
  1333. return;
  1334. }
  1335. pd.num_cs = num_cs;
  1336. pd.src_clk_nr = src_clk_nr;
  1337. pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio;
  1338. s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1);
  1339. }
  1340. #endif /* CONFIG_S3C64XX_DEV_SPI1 */
  1341. #ifdef CONFIG_S3C64XX_DEV_SPI2
  1342. static struct resource s3c64xx_spi2_resource[] = {
  1343. [0] = DEFINE_RES_MEM(S3C_PA_SPI2, SZ_256),
  1344. [1] = DEFINE_RES_DMA(DMACH_SPI2_TX),
  1345. [2] = DEFINE_RES_DMA(DMACH_SPI2_RX),
  1346. [3] = DEFINE_RES_IRQ(IRQ_SPI2),
  1347. };
  1348. struct platform_device s3c64xx_device_spi2 = {
  1349. .name = "s3c6410-spi",
  1350. .id = 2,
  1351. .num_resources = ARRAY_SIZE(s3c64xx_spi2_resource),
  1352. .resource = s3c64xx_spi2_resource,
  1353. .dev = {
  1354. .dma_mask = &samsung_device_dma_mask,
  1355. .coherent_dma_mask = DMA_BIT_MASK(32),
  1356. },
  1357. };
  1358. void __init s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
  1359. int num_cs)
  1360. {
  1361. struct s3c64xx_spi_info pd;
  1362. /* Reject invalid configuration */
  1363. if (!num_cs || src_clk_nr < 0) {
  1364. pr_err("%s: Invalid SPI configuration\n", __func__);
  1365. return;
  1366. }
  1367. pd.num_cs = num_cs;
  1368. pd.src_clk_nr = src_clk_nr;
  1369. pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio;
  1370. s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2);
  1371. }
  1372. #endif /* CONFIG_S3C64XX_DEV_SPI2 */