stex.c 32 KB

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  1. /*
  2. * SuperTrak EX Series Storage Controller driver for Linux
  3. *
  4. * Copyright (C) 2005, 2006 Promise Technology Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. *
  11. * Written By:
  12. * Ed Lin <promise_linux@promise.com>
  13. *
  14. */
  15. #include <linux/init.h>
  16. #include <linux/errno.h>
  17. #include <linux/kernel.h>
  18. #include <linux/delay.h>
  19. #include <linux/time.h>
  20. #include <linux/pci.h>
  21. #include <linux/blkdev.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/types.h>
  24. #include <linux/module.h>
  25. #include <linux/spinlock.h>
  26. #include <asm/io.h>
  27. #include <asm/irq.h>
  28. #include <asm/byteorder.h>
  29. #include <scsi/scsi.h>
  30. #include <scsi/scsi_device.h>
  31. #include <scsi/scsi_cmnd.h>
  32. #include <scsi/scsi_host.h>
  33. #include <scsi/scsi_tcq.h>
  34. #include <scsi/scsi_dbg.h>
  35. #include <scsi/scsi_eh.h>
  36. #define DRV_NAME "stex"
  37. #define ST_DRIVER_VERSION "3.6.0000.1"
  38. #define ST_VER_MAJOR 3
  39. #define ST_VER_MINOR 6
  40. #define ST_OEM 0
  41. #define ST_BUILD_VER 1
  42. enum {
  43. /* MU register offset */
  44. IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
  45. IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
  46. OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
  47. OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
  48. IDBL = 0x20, /* MU_INBOUND_DOORBELL */
  49. IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
  50. IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
  51. ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */
  52. OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
  53. OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
  54. /* MU register value */
  55. MU_INBOUND_DOORBELL_HANDSHAKE = 1,
  56. MU_INBOUND_DOORBELL_REQHEADCHANGED = 2,
  57. MU_INBOUND_DOORBELL_STATUSTAILCHANGED = 4,
  58. MU_INBOUND_DOORBELL_HMUSTOPPED = 8,
  59. MU_INBOUND_DOORBELL_RESET = 16,
  60. MU_OUTBOUND_DOORBELL_HANDSHAKE = 1,
  61. MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = 2,
  62. MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = 4,
  63. MU_OUTBOUND_DOORBELL_BUSCHANGE = 8,
  64. MU_OUTBOUND_DOORBELL_HASEVENT = 16,
  65. /* MU status code */
  66. MU_STATE_STARTING = 1,
  67. MU_STATE_FMU_READY_FOR_HANDSHAKE = 2,
  68. MU_STATE_SEND_HANDSHAKE_FRAME = 3,
  69. MU_STATE_STARTED = 4,
  70. MU_STATE_RESETTING = 5,
  71. MU_MAX_DELAY = 120,
  72. MU_HANDSHAKE_SIGNATURE = 0x55aaaa55,
  73. MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000,
  74. MU_HARD_RESET_WAIT = 30000,
  75. HMU_PARTNER_TYPE = 2,
  76. /* firmware returned values */
  77. SRB_STATUS_SUCCESS = 0x01,
  78. SRB_STATUS_ERROR = 0x04,
  79. SRB_STATUS_BUSY = 0x05,
  80. SRB_STATUS_INVALID_REQUEST = 0x06,
  81. SRB_STATUS_SELECTION_TIMEOUT = 0x0A,
  82. SRB_SEE_SENSE = 0x80,
  83. /* task attribute */
  84. TASK_ATTRIBUTE_SIMPLE = 0x0,
  85. TASK_ATTRIBUTE_HEADOFQUEUE = 0x1,
  86. TASK_ATTRIBUTE_ORDERED = 0x2,
  87. TASK_ATTRIBUTE_ACA = 0x4,
  88. /* request count, etc. */
  89. MU_MAX_REQUEST = 32,
  90. /* one message wasted, use MU_MAX_REQUEST+1
  91. to handle MU_MAX_REQUEST messages */
  92. MU_REQ_COUNT = (MU_MAX_REQUEST + 1),
  93. MU_STATUS_COUNT = (MU_MAX_REQUEST + 1),
  94. STEX_CDB_LENGTH = MAX_COMMAND_SIZE,
  95. REQ_VARIABLE_LEN = 1024,
  96. STATUS_VAR_LEN = 128,
  97. ST_CAN_QUEUE = MU_MAX_REQUEST,
  98. ST_CMD_PER_LUN = MU_MAX_REQUEST,
  99. ST_MAX_SG = 32,
  100. /* sg flags */
  101. SG_CF_EOT = 0x80, /* end of table */
  102. SG_CF_64B = 0x40, /* 64 bit item */
  103. SG_CF_HOST = 0x20, /* sg in host memory */
  104. st_shasta = 0,
  105. st_vsc = 1,
  106. st_vsc1 = 2,
  107. st_yosemite = 3,
  108. st_seq = 4,
  109. PASSTHRU_REQ_TYPE = 0x00000001,
  110. PASSTHRU_REQ_NO_WAKEUP = 0x00000100,
  111. ST_INTERNAL_TIMEOUT = 30,
  112. ST_TO_CMD = 0,
  113. ST_FROM_CMD = 1,
  114. /* vendor specific commands of Promise */
  115. MGT_CMD = 0xd8,
  116. SINBAND_MGT_CMD = 0xd9,
  117. ARRAY_CMD = 0xe0,
  118. CONTROLLER_CMD = 0xe1,
  119. DEBUGGING_CMD = 0xe2,
  120. PASSTHRU_CMD = 0xe3,
  121. PASSTHRU_GET_ADAPTER = 0x05,
  122. PASSTHRU_GET_DRVVER = 0x10,
  123. CTLR_CONFIG_CMD = 0x03,
  124. CTLR_SHUTDOWN = 0x0d,
  125. CTLR_POWER_STATE_CHANGE = 0x0e,
  126. CTLR_POWER_SAVING = 0x01,
  127. PASSTHRU_SIGNATURE = 0x4e415041,
  128. MGT_CMD_SIGNATURE = 0xba,
  129. INQUIRY_EVPD = 0x01,
  130. ST_ADDITIONAL_MEM = 0x200000,
  131. };
  132. /* SCSI inquiry data */
  133. typedef struct st_inq {
  134. u8 DeviceType :5;
  135. u8 DeviceTypeQualifier :3;
  136. u8 DeviceTypeModifier :7;
  137. u8 RemovableMedia :1;
  138. u8 Versions;
  139. u8 ResponseDataFormat :4;
  140. u8 HiSupport :1;
  141. u8 NormACA :1;
  142. u8 ReservedBit :1;
  143. u8 AERC :1;
  144. u8 AdditionalLength;
  145. u8 Reserved[2];
  146. u8 SoftReset :1;
  147. u8 CommandQueue :1;
  148. u8 Reserved2 :1;
  149. u8 LinkedCommands :1;
  150. u8 Synchronous :1;
  151. u8 Wide16Bit :1;
  152. u8 Wide32Bit :1;
  153. u8 RelativeAddressing :1;
  154. u8 VendorId[8];
  155. u8 ProductId[16];
  156. u8 ProductRevisionLevel[4];
  157. u8 VendorSpecific[20];
  158. u8 Reserved3[40];
  159. } ST_INQ;
  160. struct st_sgitem {
  161. u8 ctrl; /* SG_CF_xxx */
  162. u8 reserved[3];
  163. __le32 count;
  164. __le32 addr;
  165. __le32 addr_hi;
  166. };
  167. struct st_sgtable {
  168. __le16 sg_count;
  169. __le16 max_sg_count;
  170. __le32 sz_in_byte;
  171. struct st_sgitem table[ST_MAX_SG];
  172. };
  173. struct handshake_frame {
  174. __le32 rb_phy; /* request payload queue physical address */
  175. __le32 rb_phy_hi;
  176. __le16 req_sz; /* size of each request payload */
  177. __le16 req_cnt; /* count of reqs the buffer can hold */
  178. __le16 status_sz; /* size of each status payload */
  179. __le16 status_cnt; /* count of status the buffer can hold */
  180. __le32 hosttime; /* seconds from Jan 1, 1970 (GMT) */
  181. __le32 hosttime_hi;
  182. u8 partner_type; /* who sends this frame */
  183. u8 reserved0[7];
  184. __le32 partner_ver_major;
  185. __le32 partner_ver_minor;
  186. __le32 partner_ver_oem;
  187. __le32 partner_ver_build;
  188. __le32 extra_offset; /* NEW */
  189. __le32 extra_size; /* NEW */
  190. u32 reserved1[2];
  191. };
  192. struct req_msg {
  193. __le16 tag;
  194. u8 lun;
  195. u8 target;
  196. u8 task_attr;
  197. u8 task_manage;
  198. u8 prd_entry;
  199. u8 payload_sz; /* payload size in 4-byte, not used */
  200. u8 cdb[STEX_CDB_LENGTH];
  201. u8 variable[REQ_VARIABLE_LEN];
  202. };
  203. struct status_msg {
  204. __le16 tag;
  205. u8 lun;
  206. u8 target;
  207. u8 srb_status;
  208. u8 scsi_status;
  209. u8 reserved;
  210. u8 payload_sz; /* payload size in 4-byte */
  211. u8 variable[STATUS_VAR_LEN];
  212. };
  213. struct ver_info {
  214. u32 major;
  215. u32 minor;
  216. u32 oem;
  217. u32 build;
  218. u32 reserved[2];
  219. };
  220. struct st_frame {
  221. u32 base[6];
  222. u32 rom_addr;
  223. struct ver_info drv_ver;
  224. struct ver_info bios_ver;
  225. u32 bus;
  226. u32 slot;
  227. u32 irq_level;
  228. u32 irq_vec;
  229. u32 id;
  230. u32 subid;
  231. u32 dimm_size;
  232. u8 dimm_type;
  233. u8 reserved[3];
  234. u32 channel;
  235. u32 reserved1;
  236. };
  237. struct st_drvver {
  238. u32 major;
  239. u32 minor;
  240. u32 oem;
  241. u32 build;
  242. u32 signature[2];
  243. u8 console_id;
  244. u8 host_no;
  245. u8 reserved0[2];
  246. u32 reserved[3];
  247. };
  248. #define MU_REQ_BUFFER_SIZE (MU_REQ_COUNT * sizeof(struct req_msg))
  249. #define MU_STATUS_BUFFER_SIZE (MU_STATUS_COUNT * sizeof(struct status_msg))
  250. #define MU_BUFFER_SIZE (MU_REQ_BUFFER_SIZE + MU_STATUS_BUFFER_SIZE)
  251. #define STEX_EXTRA_SIZE max(sizeof(struct st_frame), sizeof(ST_INQ))
  252. #define STEX_BUFFER_SIZE (MU_BUFFER_SIZE + STEX_EXTRA_SIZE)
  253. struct st_ccb {
  254. struct req_msg *req;
  255. struct scsi_cmnd *cmd;
  256. void *sense_buffer;
  257. unsigned int sense_bufflen;
  258. int sg_count;
  259. u32 req_type;
  260. u8 srb_status;
  261. u8 scsi_status;
  262. };
  263. struct st_hba {
  264. void __iomem *mmio_base; /* iomapped PCI memory space */
  265. void *dma_mem;
  266. dma_addr_t dma_handle;
  267. size_t dma_size;
  268. struct Scsi_Host *host;
  269. struct pci_dev *pdev;
  270. u32 req_head;
  271. u32 req_tail;
  272. u32 status_head;
  273. u32 status_tail;
  274. struct status_msg *status_buffer;
  275. void *copy_buffer; /* temp buffer for driver-handled commands */
  276. struct st_ccb ccb[MU_MAX_REQUEST];
  277. struct st_ccb *wait_ccb;
  278. wait_queue_head_t waitq;
  279. unsigned int mu_status;
  280. int out_req_cnt;
  281. unsigned int cardtype;
  282. };
  283. static const char console_inq_page[] =
  284. {
  285. 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
  286. 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */
  287. 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */
  288. 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */
  289. 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */
  290. 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */
  291. 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */
  292. 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
  293. };
  294. MODULE_AUTHOR("Ed Lin");
  295. MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
  296. MODULE_LICENSE("GPL");
  297. MODULE_VERSION(ST_DRIVER_VERSION);
  298. static void stex_gettime(__le32 *time)
  299. {
  300. struct timeval tv;
  301. do_gettimeofday(&tv);
  302. *time = cpu_to_le32(tv.tv_sec & 0xffffffff);
  303. *(time + 1) = cpu_to_le32((tv.tv_sec >> 16) >> 16);
  304. }
  305. static struct status_msg *stex_get_status(struct st_hba *hba)
  306. {
  307. struct status_msg *status =
  308. hba->status_buffer + hba->status_tail;
  309. ++hba->status_tail;
  310. hba->status_tail %= MU_STATUS_COUNT;
  311. return status;
  312. }
  313. static void stex_invalid_field(struct scsi_cmnd *cmd,
  314. void (*done)(struct scsi_cmnd *))
  315. {
  316. cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
  317. /* "Invalid field in cbd" */
  318. scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24,
  319. 0x0);
  320. done(cmd);
  321. }
  322. static struct req_msg *stex_alloc_req(struct st_hba *hba)
  323. {
  324. struct req_msg *req = ((struct req_msg *)hba->dma_mem) +
  325. hba->req_head;
  326. ++hba->req_head;
  327. hba->req_head %= MU_REQ_COUNT;
  328. return req;
  329. }
  330. static int stex_map_sg(struct st_hba *hba,
  331. struct req_msg *req, struct st_ccb *ccb)
  332. {
  333. struct scsi_cmnd *cmd;
  334. struct scatterlist *sg;
  335. struct st_sgtable *dst;
  336. int i, nseg;
  337. cmd = ccb->cmd;
  338. dst = (struct st_sgtable *)req->variable;
  339. dst->max_sg_count = cpu_to_le16(ST_MAX_SG);
  340. dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
  341. nseg = scsi_dma_map(cmd);
  342. if (nseg < 0)
  343. return -EIO;
  344. if (nseg) {
  345. ccb->sg_count = nseg;
  346. dst->sg_count = cpu_to_le16((u16)nseg);
  347. scsi_for_each_sg(cmd, sg, nseg, i) {
  348. dst->table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
  349. dst->table[i].addr =
  350. cpu_to_le32(sg_dma_address(sg) & 0xffffffff);
  351. dst->table[i].addr_hi =
  352. cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
  353. dst->table[i].ctrl = SG_CF_64B | SG_CF_HOST;
  354. }
  355. dst->table[--i].ctrl |= SG_CF_EOT;
  356. }
  357. return 0;
  358. }
  359. static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
  360. {
  361. struct st_frame *p;
  362. size_t count = sizeof(struct st_frame);
  363. p = hba->copy_buffer;
  364. count = scsi_sg_copy_to_buffer(ccb->cmd, p, count);
  365. memset(p->base, 0, sizeof(u32)*6);
  366. *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
  367. p->rom_addr = 0;
  368. p->drv_ver.major = ST_VER_MAJOR;
  369. p->drv_ver.minor = ST_VER_MINOR;
  370. p->drv_ver.oem = ST_OEM;
  371. p->drv_ver.build = ST_BUILD_VER;
  372. p->bus = hba->pdev->bus->number;
  373. p->slot = hba->pdev->devfn;
  374. p->irq_level = 0;
  375. p->irq_vec = hba->pdev->irq;
  376. p->id = hba->pdev->vendor << 16 | hba->pdev->device;
  377. p->subid =
  378. hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
  379. count = scsi_sg_copy_from_buffer(ccb->cmd, p, count);
  380. }
  381. static void
  382. stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
  383. {
  384. req->tag = cpu_to_le16(tag);
  385. req->task_attr = TASK_ATTRIBUTE_SIMPLE;
  386. req->task_manage = 0; /* not supported yet */
  387. hba->ccb[tag].req = req;
  388. hba->out_req_cnt++;
  389. writel(hba->req_head, hba->mmio_base + IMR0);
  390. writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
  391. readl(hba->mmio_base + IDBL); /* flush */
  392. }
  393. static int
  394. stex_slave_alloc(struct scsi_device *sdev)
  395. {
  396. /* Cheat: usually extracted from Inquiry data */
  397. sdev->tagged_supported = 1;
  398. scsi_activate_tcq(sdev, ST_CMD_PER_LUN);
  399. return 0;
  400. }
  401. static int
  402. stex_slave_config(struct scsi_device *sdev)
  403. {
  404. sdev->use_10_for_rw = 1;
  405. sdev->use_10_for_ms = 1;
  406. blk_queue_rq_timeout(sdev->request_queue, 60 * HZ);
  407. sdev->tagged_supported = 1;
  408. return 0;
  409. }
  410. static void
  411. stex_slave_destroy(struct scsi_device *sdev)
  412. {
  413. scsi_deactivate_tcq(sdev, 1);
  414. }
  415. static int
  416. stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *))
  417. {
  418. struct st_hba *hba;
  419. struct Scsi_Host *host;
  420. unsigned int id,lun;
  421. struct req_msg *req;
  422. u16 tag;
  423. host = cmd->device->host;
  424. id = cmd->device->id;
  425. lun = cmd->device->lun;
  426. hba = (struct st_hba *) &host->hostdata[0];
  427. switch (cmd->cmnd[0]) {
  428. case MODE_SENSE_10:
  429. {
  430. static char ms10_caching_page[12] =
  431. { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
  432. unsigned char page;
  433. page = cmd->cmnd[2] & 0x3f;
  434. if (page == 0x8 || page == 0x3f) {
  435. scsi_sg_copy_from_buffer(cmd, ms10_caching_page,
  436. sizeof(ms10_caching_page));
  437. cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
  438. done(cmd);
  439. } else
  440. stex_invalid_field(cmd, done);
  441. return 0;
  442. }
  443. case REPORT_LUNS:
  444. /*
  445. * The shasta firmware does not report actual luns in the
  446. * target, so fail the command to force sequential lun scan.
  447. * Also, the console device does not support this command.
  448. */
  449. if (hba->cardtype == st_shasta || id == host->max_id - 1) {
  450. stex_invalid_field(cmd, done);
  451. return 0;
  452. }
  453. break;
  454. case TEST_UNIT_READY:
  455. if (id == host->max_id - 1) {
  456. cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
  457. done(cmd);
  458. return 0;
  459. }
  460. break;
  461. case INQUIRY:
  462. if (id != host->max_id - 1)
  463. break;
  464. if (lun == 0 && (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
  465. scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page,
  466. sizeof(console_inq_page));
  467. cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
  468. done(cmd);
  469. } else
  470. stex_invalid_field(cmd, done);
  471. return 0;
  472. case PASSTHRU_CMD:
  473. if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
  474. struct st_drvver ver;
  475. size_t cp_len = sizeof(ver);
  476. ver.major = ST_VER_MAJOR;
  477. ver.minor = ST_VER_MINOR;
  478. ver.oem = ST_OEM;
  479. ver.build = ST_BUILD_VER;
  480. ver.signature[0] = PASSTHRU_SIGNATURE;
  481. ver.console_id = host->max_id - 1;
  482. ver.host_no = hba->host->host_no;
  483. cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len);
  484. cmd->result = sizeof(ver) == cp_len ?
  485. DID_OK << 16 | COMMAND_COMPLETE << 8 :
  486. DID_ERROR << 16 | COMMAND_COMPLETE << 8;
  487. done(cmd);
  488. return 0;
  489. }
  490. default:
  491. break;
  492. }
  493. cmd->scsi_done = done;
  494. tag = cmd->request->tag;
  495. if (unlikely(tag >= host->can_queue))
  496. return SCSI_MLQUEUE_HOST_BUSY;
  497. req = stex_alloc_req(hba);
  498. req->lun = lun;
  499. req->target = id;
  500. /* cdb */
  501. memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
  502. hba->ccb[tag].cmd = cmd;
  503. hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
  504. hba->ccb[tag].sense_buffer = cmd->sense_buffer;
  505. hba->ccb[tag].req_type = 0;
  506. if (cmd->sc_data_direction != DMA_NONE)
  507. stex_map_sg(hba, req, &hba->ccb[tag]);
  508. stex_send_cmd(hba, req, tag);
  509. return 0;
  510. }
  511. static void stex_scsi_done(struct st_ccb *ccb)
  512. {
  513. struct scsi_cmnd *cmd = ccb->cmd;
  514. int result;
  515. if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
  516. result = ccb->scsi_status;
  517. switch (ccb->scsi_status) {
  518. case SAM_STAT_GOOD:
  519. result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
  520. break;
  521. case SAM_STAT_CHECK_CONDITION:
  522. result |= DRIVER_SENSE << 24;
  523. break;
  524. case SAM_STAT_BUSY:
  525. result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
  526. break;
  527. default:
  528. result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
  529. break;
  530. }
  531. }
  532. else if (ccb->srb_status & SRB_SEE_SENSE)
  533. result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
  534. else switch (ccb->srb_status) {
  535. case SRB_STATUS_SELECTION_TIMEOUT:
  536. result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
  537. break;
  538. case SRB_STATUS_BUSY:
  539. result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
  540. break;
  541. case SRB_STATUS_INVALID_REQUEST:
  542. case SRB_STATUS_ERROR:
  543. default:
  544. result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
  545. break;
  546. }
  547. cmd->result = result;
  548. cmd->scsi_done(cmd);
  549. }
  550. static void stex_copy_data(struct st_ccb *ccb,
  551. struct status_msg *resp, unsigned int variable)
  552. {
  553. size_t count = variable;
  554. if (resp->scsi_status != SAM_STAT_GOOD) {
  555. if (ccb->sense_buffer != NULL)
  556. memcpy(ccb->sense_buffer, resp->variable,
  557. min(variable, ccb->sense_bufflen));
  558. return;
  559. }
  560. if (ccb->cmd == NULL)
  561. return;
  562. count = scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, count);
  563. }
  564. static void stex_ys_commands(struct st_hba *hba,
  565. struct st_ccb *ccb, struct status_msg *resp)
  566. {
  567. if (ccb->cmd->cmnd[0] == MGT_CMD &&
  568. resp->scsi_status != SAM_STAT_CHECK_CONDITION) {
  569. scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
  570. le32_to_cpu(*(__le32 *)&resp->variable[0]));
  571. return;
  572. }
  573. if (resp->srb_status != 0)
  574. return;
  575. /* determine inquiry command status by DeviceTypeQualifier */
  576. if (ccb->cmd->cmnd[0] == INQUIRY &&
  577. resp->scsi_status == SAM_STAT_GOOD) {
  578. ST_INQ *inq_data;
  579. scsi_sg_copy_to_buffer(ccb->cmd, hba->copy_buffer,
  580. STEX_EXTRA_SIZE);
  581. inq_data = (ST_INQ *)hba->copy_buffer;
  582. if (inq_data->DeviceTypeQualifier != 0)
  583. ccb->srb_status = SRB_STATUS_SELECTION_TIMEOUT;
  584. else
  585. ccb->srb_status = SRB_STATUS_SUCCESS;
  586. }
  587. }
  588. static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
  589. {
  590. void __iomem *base = hba->mmio_base;
  591. struct status_msg *resp;
  592. struct st_ccb *ccb;
  593. unsigned int size;
  594. u16 tag;
  595. if (!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED))
  596. return;
  597. /* status payloads */
  598. hba->status_head = readl(base + OMR1);
  599. if (unlikely(hba->status_head >= MU_STATUS_COUNT)) {
  600. printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
  601. pci_name(hba->pdev));
  602. return;
  603. }
  604. /*
  605. * it's not a valid status payload if:
  606. * 1. there are no pending requests(e.g. during init stage)
  607. * 2. there are some pending requests, but the controller is in
  608. * reset status, and its type is not st_yosemite
  609. * firmware of st_yosemite in reset status will return pending requests
  610. * to driver, so we allow it to pass
  611. */
  612. if (unlikely(hba->out_req_cnt <= 0 ||
  613. (hba->mu_status == MU_STATE_RESETTING &&
  614. hba->cardtype != st_yosemite))) {
  615. hba->status_tail = hba->status_head;
  616. goto update_status;
  617. }
  618. while (hba->status_tail != hba->status_head) {
  619. resp = stex_get_status(hba);
  620. tag = le16_to_cpu(resp->tag);
  621. if (unlikely(tag >= hba->host->can_queue)) {
  622. printk(KERN_WARNING DRV_NAME
  623. "(%s): invalid tag\n", pci_name(hba->pdev));
  624. continue;
  625. }
  626. ccb = &hba->ccb[tag];
  627. if (hba->wait_ccb == ccb)
  628. hba->wait_ccb = NULL;
  629. if (unlikely(ccb->req == NULL)) {
  630. printk(KERN_WARNING DRV_NAME
  631. "(%s): lagging req\n", pci_name(hba->pdev));
  632. hba->out_req_cnt--;
  633. continue;
  634. }
  635. size = resp->payload_sz * sizeof(u32); /* payload size */
  636. if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
  637. size > sizeof(*resp))) {
  638. printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
  639. pci_name(hba->pdev));
  640. } else {
  641. size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
  642. if (size)
  643. stex_copy_data(ccb, resp, size);
  644. }
  645. ccb->req = NULL;
  646. ccb->srb_status = resp->srb_status;
  647. ccb->scsi_status = resp->scsi_status;
  648. if (likely(ccb->cmd != NULL)) {
  649. if (hba->cardtype == st_yosemite)
  650. stex_ys_commands(hba, ccb, resp);
  651. if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
  652. ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
  653. stex_controller_info(hba, ccb);
  654. scsi_dma_unmap(ccb->cmd);
  655. stex_scsi_done(ccb);
  656. hba->out_req_cnt--;
  657. } else if (ccb->req_type & PASSTHRU_REQ_TYPE) {
  658. hba->out_req_cnt--;
  659. if (ccb->req_type & PASSTHRU_REQ_NO_WAKEUP) {
  660. ccb->req_type = 0;
  661. continue;
  662. }
  663. ccb->req_type = 0;
  664. if (waitqueue_active(&hba->waitq))
  665. wake_up(&hba->waitq);
  666. }
  667. }
  668. update_status:
  669. writel(hba->status_head, base + IMR1);
  670. readl(base + IMR1); /* flush */
  671. }
  672. static irqreturn_t stex_intr(int irq, void *__hba)
  673. {
  674. struct st_hba *hba = __hba;
  675. void __iomem *base = hba->mmio_base;
  676. u32 data;
  677. unsigned long flags;
  678. int handled = 0;
  679. spin_lock_irqsave(hba->host->host_lock, flags);
  680. data = readl(base + ODBL);
  681. if (data && data != 0xffffffff) {
  682. /* clear the interrupt */
  683. writel(data, base + ODBL);
  684. readl(base + ODBL); /* flush */
  685. stex_mu_intr(hba, data);
  686. handled = 1;
  687. }
  688. spin_unlock_irqrestore(hba->host->host_lock, flags);
  689. return IRQ_RETVAL(handled);
  690. }
  691. static int stex_handshake(struct st_hba *hba)
  692. {
  693. void __iomem *base = hba->mmio_base;
  694. struct handshake_frame *h;
  695. dma_addr_t status_phys;
  696. u32 data;
  697. unsigned long before;
  698. if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
  699. writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
  700. readl(base + IDBL);
  701. before = jiffies;
  702. while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
  703. if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
  704. printk(KERN_ERR DRV_NAME
  705. "(%s): no handshake signature\n",
  706. pci_name(hba->pdev));
  707. return -1;
  708. }
  709. rmb();
  710. msleep(1);
  711. }
  712. }
  713. udelay(10);
  714. data = readl(base + OMR1);
  715. if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
  716. data &= 0x0000ffff;
  717. if (hba->host->can_queue > data)
  718. hba->host->can_queue = data;
  719. }
  720. h = (struct handshake_frame *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
  721. h->rb_phy = cpu_to_le32(hba->dma_handle);
  722. h->rb_phy_hi = cpu_to_le32((hba->dma_handle >> 16) >> 16);
  723. h->req_sz = cpu_to_le16(sizeof(struct req_msg));
  724. h->req_cnt = cpu_to_le16(MU_REQ_COUNT);
  725. h->status_sz = cpu_to_le16(sizeof(struct status_msg));
  726. h->status_cnt = cpu_to_le16(MU_STATUS_COUNT);
  727. stex_gettime(&h->hosttime);
  728. h->partner_type = HMU_PARTNER_TYPE;
  729. if (hba->dma_size > STEX_BUFFER_SIZE) {
  730. h->extra_offset = cpu_to_le32(STEX_BUFFER_SIZE);
  731. h->extra_size = cpu_to_le32(ST_ADDITIONAL_MEM);
  732. } else
  733. h->extra_offset = h->extra_size = 0;
  734. status_phys = hba->dma_handle + MU_REQ_BUFFER_SIZE;
  735. writel(status_phys, base + IMR0);
  736. readl(base + IMR0);
  737. writel((status_phys >> 16) >> 16, base + IMR1);
  738. readl(base + IMR1);
  739. writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
  740. readl(base + OMR0);
  741. writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
  742. readl(base + IDBL); /* flush */
  743. udelay(10);
  744. before = jiffies;
  745. while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
  746. if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
  747. printk(KERN_ERR DRV_NAME
  748. "(%s): no signature after handshake frame\n",
  749. pci_name(hba->pdev));
  750. return -1;
  751. }
  752. rmb();
  753. msleep(1);
  754. }
  755. writel(0, base + IMR0);
  756. readl(base + IMR0);
  757. writel(0, base + OMR0);
  758. readl(base + OMR0);
  759. writel(0, base + IMR1);
  760. readl(base + IMR1);
  761. writel(0, base + OMR1);
  762. readl(base + OMR1); /* flush */
  763. hba->mu_status = MU_STATE_STARTED;
  764. return 0;
  765. }
  766. static int stex_abort(struct scsi_cmnd *cmd)
  767. {
  768. struct Scsi_Host *host = cmd->device->host;
  769. struct st_hba *hba = (struct st_hba *)host->hostdata;
  770. u16 tag = cmd->request->tag;
  771. void __iomem *base;
  772. u32 data;
  773. int result = SUCCESS;
  774. unsigned long flags;
  775. printk(KERN_INFO DRV_NAME
  776. "(%s): aborting command\n", pci_name(hba->pdev));
  777. scsi_print_command(cmd);
  778. base = hba->mmio_base;
  779. spin_lock_irqsave(host->host_lock, flags);
  780. if (tag < host->can_queue && hba->ccb[tag].cmd == cmd)
  781. hba->wait_ccb = &hba->ccb[tag];
  782. else {
  783. for (tag = 0; tag < host->can_queue; tag++)
  784. if (hba->ccb[tag].cmd == cmd) {
  785. hba->wait_ccb = &hba->ccb[tag];
  786. break;
  787. }
  788. if (tag >= host->can_queue)
  789. goto out;
  790. }
  791. data = readl(base + ODBL);
  792. if (data == 0 || data == 0xffffffff)
  793. goto fail_out;
  794. writel(data, base + ODBL);
  795. readl(base + ODBL); /* flush */
  796. stex_mu_intr(hba, data);
  797. if (hba->wait_ccb == NULL) {
  798. printk(KERN_WARNING DRV_NAME
  799. "(%s): lost interrupt\n", pci_name(hba->pdev));
  800. goto out;
  801. }
  802. fail_out:
  803. scsi_dma_unmap(cmd);
  804. hba->wait_ccb->req = NULL; /* nullify the req's future return */
  805. hba->wait_ccb = NULL;
  806. result = FAILED;
  807. out:
  808. spin_unlock_irqrestore(host->host_lock, flags);
  809. return result;
  810. }
  811. static void stex_hard_reset(struct st_hba *hba)
  812. {
  813. struct pci_bus *bus;
  814. int i;
  815. u16 pci_cmd;
  816. u8 pci_bctl;
  817. for (i = 0; i < 16; i++)
  818. pci_read_config_dword(hba->pdev, i * 4,
  819. &hba->pdev->saved_config_space[i]);
  820. /* Reset secondary bus. Our controller(MU/ATU) is the only device on
  821. secondary bus. Consult Intel 80331/3 developer's manual for detail */
  822. bus = hba->pdev->bus;
  823. pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
  824. pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
  825. pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
  826. /*
  827. * 1 ms may be enough for 8-port controllers. But 16-port controllers
  828. * require more time to finish bus reset. Use 100 ms here for safety
  829. */
  830. msleep(100);
  831. pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
  832. pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
  833. for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
  834. pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
  835. if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
  836. break;
  837. msleep(1);
  838. }
  839. ssleep(5);
  840. for (i = 0; i < 16; i++)
  841. pci_write_config_dword(hba->pdev, i * 4,
  842. hba->pdev->saved_config_space[i]);
  843. }
  844. static int stex_reset(struct scsi_cmnd *cmd)
  845. {
  846. struct st_hba *hba;
  847. unsigned long flags;
  848. unsigned long before;
  849. hba = (struct st_hba *) &cmd->device->host->hostdata[0];
  850. printk(KERN_INFO DRV_NAME
  851. "(%s): resetting host\n", pci_name(hba->pdev));
  852. scsi_print_command(cmd);
  853. hba->mu_status = MU_STATE_RESETTING;
  854. if (hba->cardtype == st_shasta)
  855. stex_hard_reset(hba);
  856. if (hba->cardtype != st_yosemite) {
  857. if (stex_handshake(hba)) {
  858. printk(KERN_WARNING DRV_NAME
  859. "(%s): resetting: handshake failed\n",
  860. pci_name(hba->pdev));
  861. return FAILED;
  862. }
  863. spin_lock_irqsave(hba->host->host_lock, flags);
  864. hba->req_head = 0;
  865. hba->req_tail = 0;
  866. hba->status_head = 0;
  867. hba->status_tail = 0;
  868. hba->out_req_cnt = 0;
  869. spin_unlock_irqrestore(hba->host->host_lock, flags);
  870. return SUCCESS;
  871. }
  872. /* st_yosemite */
  873. writel(MU_INBOUND_DOORBELL_RESET, hba->mmio_base + IDBL);
  874. readl(hba->mmio_base + IDBL); /* flush */
  875. before = jiffies;
  876. while (hba->out_req_cnt > 0) {
  877. if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
  878. printk(KERN_WARNING DRV_NAME
  879. "(%s): reset timeout\n", pci_name(hba->pdev));
  880. return FAILED;
  881. }
  882. msleep(1);
  883. }
  884. hba->mu_status = MU_STATE_STARTED;
  885. return SUCCESS;
  886. }
  887. static int stex_biosparam(struct scsi_device *sdev,
  888. struct block_device *bdev, sector_t capacity, int geom[])
  889. {
  890. int heads = 255, sectors = 63;
  891. if (capacity < 0x200000) {
  892. heads = 64;
  893. sectors = 32;
  894. }
  895. sector_div(capacity, heads * sectors);
  896. geom[0] = heads;
  897. geom[1] = sectors;
  898. geom[2] = capacity;
  899. return 0;
  900. }
  901. static struct scsi_host_template driver_template = {
  902. .module = THIS_MODULE,
  903. .name = DRV_NAME,
  904. .proc_name = DRV_NAME,
  905. .bios_param = stex_biosparam,
  906. .queuecommand = stex_queuecommand,
  907. .slave_alloc = stex_slave_alloc,
  908. .slave_configure = stex_slave_config,
  909. .slave_destroy = stex_slave_destroy,
  910. .eh_abort_handler = stex_abort,
  911. .eh_host_reset_handler = stex_reset,
  912. .can_queue = ST_CAN_QUEUE,
  913. .this_id = -1,
  914. .sg_tablesize = ST_MAX_SG,
  915. .cmd_per_lun = ST_CMD_PER_LUN,
  916. };
  917. static int stex_set_dma_mask(struct pci_dev * pdev)
  918. {
  919. int ret;
  920. if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)
  921. && !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
  922. return 0;
  923. ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  924. if (!ret)
  925. ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  926. return ret;
  927. }
  928. static int __devinit
  929. stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  930. {
  931. struct st_hba *hba;
  932. struct Scsi_Host *host;
  933. int err;
  934. err = pci_enable_device(pdev);
  935. if (err)
  936. return err;
  937. pci_set_master(pdev);
  938. host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
  939. if (!host) {
  940. printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
  941. pci_name(pdev));
  942. err = -ENOMEM;
  943. goto out_disable;
  944. }
  945. hba = (struct st_hba *)host->hostdata;
  946. memset(hba, 0, sizeof(struct st_hba));
  947. err = pci_request_regions(pdev, DRV_NAME);
  948. if (err < 0) {
  949. printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
  950. pci_name(pdev));
  951. goto out_scsi_host_put;
  952. }
  953. hba->mmio_base = pci_ioremap_bar(pdev, 0);
  954. if ( !hba->mmio_base) {
  955. printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
  956. pci_name(pdev));
  957. err = -ENOMEM;
  958. goto out_release_regions;
  959. }
  960. err = stex_set_dma_mask(pdev);
  961. if (err) {
  962. printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
  963. pci_name(pdev));
  964. goto out_iounmap;
  965. }
  966. hba->cardtype = (unsigned int) id->driver_data;
  967. if (hba->cardtype == st_vsc && (pdev->subsystem_device & 0xf) == 0x1)
  968. hba->cardtype = st_vsc1;
  969. hba->dma_size = (hba->cardtype == st_vsc1 || hba->cardtype == st_seq) ?
  970. (STEX_BUFFER_SIZE + ST_ADDITIONAL_MEM) : (STEX_BUFFER_SIZE);
  971. hba->dma_mem = dma_alloc_coherent(&pdev->dev,
  972. hba->dma_size, &hba->dma_handle, GFP_KERNEL);
  973. if (!hba->dma_mem) {
  974. err = -ENOMEM;
  975. printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
  976. pci_name(pdev));
  977. goto out_iounmap;
  978. }
  979. hba->status_buffer =
  980. (struct status_msg *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
  981. hba->copy_buffer = hba->dma_mem + MU_BUFFER_SIZE;
  982. hba->mu_status = MU_STATE_STARTING;
  983. if (hba->cardtype == st_shasta) {
  984. host->max_lun = 8;
  985. host->max_id = 16 + 1;
  986. } else if (hba->cardtype == st_yosemite) {
  987. host->max_lun = 128;
  988. host->max_id = 1 + 1;
  989. } else {
  990. /* st_vsc , st_vsc1 and st_seq */
  991. host->max_lun = 1;
  992. host->max_id = 128 + 1;
  993. }
  994. host->max_channel = 0;
  995. host->unique_id = host->host_no;
  996. host->max_cmd_len = STEX_CDB_LENGTH;
  997. hba->host = host;
  998. hba->pdev = pdev;
  999. init_waitqueue_head(&hba->waitq);
  1000. err = request_irq(pdev->irq, stex_intr, IRQF_SHARED, DRV_NAME, hba);
  1001. if (err) {
  1002. printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
  1003. pci_name(pdev));
  1004. goto out_pci_free;
  1005. }
  1006. err = stex_handshake(hba);
  1007. if (err)
  1008. goto out_free_irq;
  1009. err = scsi_init_shared_tag_map(host, host->can_queue);
  1010. if (err) {
  1011. printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
  1012. pci_name(pdev));
  1013. goto out_free_irq;
  1014. }
  1015. pci_set_drvdata(pdev, hba);
  1016. err = scsi_add_host(host, &pdev->dev);
  1017. if (err) {
  1018. printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
  1019. pci_name(pdev));
  1020. goto out_free_irq;
  1021. }
  1022. scsi_scan_host(host);
  1023. return 0;
  1024. out_free_irq:
  1025. free_irq(pdev->irq, hba);
  1026. out_pci_free:
  1027. dma_free_coherent(&pdev->dev, hba->dma_size,
  1028. hba->dma_mem, hba->dma_handle);
  1029. out_iounmap:
  1030. iounmap(hba->mmio_base);
  1031. out_release_regions:
  1032. pci_release_regions(pdev);
  1033. out_scsi_host_put:
  1034. scsi_host_put(host);
  1035. out_disable:
  1036. pci_disable_device(pdev);
  1037. return err;
  1038. }
  1039. static void stex_hba_stop(struct st_hba *hba)
  1040. {
  1041. struct req_msg *req;
  1042. unsigned long flags;
  1043. unsigned long before;
  1044. u16 tag = 0;
  1045. spin_lock_irqsave(hba->host->host_lock, flags);
  1046. req = stex_alloc_req(hba);
  1047. memset(req->cdb, 0, STEX_CDB_LENGTH);
  1048. if (hba->cardtype == st_yosemite) {
  1049. req->cdb[0] = MGT_CMD;
  1050. req->cdb[1] = MGT_CMD_SIGNATURE;
  1051. req->cdb[2] = CTLR_CONFIG_CMD;
  1052. req->cdb[3] = CTLR_SHUTDOWN;
  1053. } else {
  1054. req->cdb[0] = CONTROLLER_CMD;
  1055. req->cdb[1] = CTLR_POWER_STATE_CHANGE;
  1056. req->cdb[2] = CTLR_POWER_SAVING;
  1057. }
  1058. hba->ccb[tag].cmd = NULL;
  1059. hba->ccb[tag].sg_count = 0;
  1060. hba->ccb[tag].sense_bufflen = 0;
  1061. hba->ccb[tag].sense_buffer = NULL;
  1062. hba->ccb[tag].req_type |= PASSTHRU_REQ_TYPE;
  1063. stex_send_cmd(hba, req, tag);
  1064. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1065. before = jiffies;
  1066. while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
  1067. if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ))
  1068. return;
  1069. msleep(10);
  1070. }
  1071. }
  1072. static void stex_hba_free(struct st_hba *hba)
  1073. {
  1074. free_irq(hba->pdev->irq, hba);
  1075. iounmap(hba->mmio_base);
  1076. pci_release_regions(hba->pdev);
  1077. dma_free_coherent(&hba->pdev->dev, hba->dma_size,
  1078. hba->dma_mem, hba->dma_handle);
  1079. }
  1080. static void stex_remove(struct pci_dev *pdev)
  1081. {
  1082. struct st_hba *hba = pci_get_drvdata(pdev);
  1083. scsi_remove_host(hba->host);
  1084. pci_set_drvdata(pdev, NULL);
  1085. stex_hba_stop(hba);
  1086. stex_hba_free(hba);
  1087. scsi_host_put(hba->host);
  1088. pci_disable_device(pdev);
  1089. }
  1090. static void stex_shutdown(struct pci_dev *pdev)
  1091. {
  1092. struct st_hba *hba = pci_get_drvdata(pdev);
  1093. stex_hba_stop(hba);
  1094. }
  1095. static struct pci_device_id stex_pci_tbl[] = {
  1096. /* st_shasta */
  1097. { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1098. st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
  1099. { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1100. st_shasta }, /* SuperTrak EX12350 */
  1101. { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1102. st_shasta }, /* SuperTrak EX4350 */
  1103. { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1104. st_shasta }, /* SuperTrak EX24350 */
  1105. /* st_vsc */
  1106. { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
  1107. /* st_yosemite */
  1108. { 0x105a, 0x8650, PCI_ANY_ID, 0x4600, 0, 0,
  1109. st_yosemite }, /* SuperTrak EX4650 */
  1110. { 0x105a, 0x8650, PCI_ANY_ID, 0x4610, 0, 0,
  1111. st_yosemite }, /* SuperTrak EX4650o */
  1112. { 0x105a, 0x8650, PCI_ANY_ID, 0x8600, 0, 0,
  1113. st_yosemite }, /* SuperTrak EX8650EL */
  1114. { 0x105a, 0x8650, PCI_ANY_ID, 0x8601, 0, 0,
  1115. st_yosemite }, /* SuperTrak EX8650 */
  1116. { 0x105a, 0x8650, PCI_ANY_ID, 0x8602, 0, 0,
  1117. st_yosemite }, /* SuperTrak EX8654 */
  1118. { 0x105a, 0x8650, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1119. st_yosemite }, /* generic st_yosemite */
  1120. /* st_seq */
  1121. { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq },
  1122. { } /* terminate list */
  1123. };
  1124. MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
  1125. static struct pci_driver stex_pci_driver = {
  1126. .name = DRV_NAME,
  1127. .id_table = stex_pci_tbl,
  1128. .probe = stex_probe,
  1129. .remove = __devexit_p(stex_remove),
  1130. .shutdown = stex_shutdown,
  1131. };
  1132. static int __init stex_init(void)
  1133. {
  1134. printk(KERN_INFO DRV_NAME
  1135. ": Promise SuperTrak EX Driver version: %s\n",
  1136. ST_DRIVER_VERSION);
  1137. return pci_register_driver(&stex_pci_driver);
  1138. }
  1139. static void __exit stex_exit(void)
  1140. {
  1141. pci_unregister_driver(&stex_pci_driver);
  1142. }
  1143. module_init(stex_init);
  1144. module_exit(stex_exit);