iwl-agn.c 90 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/sched.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/wireless.h>
  39. #include <linux/firmware.h>
  40. #include <linux/etherdevice.h>
  41. #include <linux/if_arp.h>
  42. #include <net/mac80211.h>
  43. #include <asm/div64.h>
  44. #define DRV_NAME "iwlagn"
  45. #include "iwl-eeprom.h"
  46. #include "iwl-dev.h"
  47. #include "iwl-core.h"
  48. #include "iwl-io.h"
  49. #include "iwl-helpers.h"
  50. #include "iwl-sta.h"
  51. #include "iwl-calib.h"
  52. /******************************************************************************
  53. *
  54. * module boiler plate
  55. *
  56. ******************************************************************************/
  57. /*
  58. * module name, copyright, version, etc.
  59. */
  60. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  61. #ifdef CONFIG_IWLWIFI_DEBUG
  62. #define VD "d"
  63. #else
  64. #define VD
  65. #endif
  66. #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
  67. #define VS "s"
  68. #else
  69. #define VS
  70. #endif
  71. #define DRV_VERSION IWLWIFI_VERSION VD VS
  72. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  73. MODULE_VERSION(DRV_VERSION);
  74. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  75. MODULE_LICENSE("GPL");
  76. MODULE_ALIAS("iwl4965");
  77. /*************** STATION TABLE MANAGEMENT ****
  78. * mac80211 should be examined to determine if sta_info is duplicating
  79. * the functionality provided here
  80. */
  81. /**************************************************************/
  82. /**
  83. * iwl_commit_rxon - commit staging_rxon to hardware
  84. *
  85. * The RXON command in staging_rxon is committed to the hardware and
  86. * the active_rxon structure is updated with the new data. This
  87. * function correctly transitions out of the RXON_ASSOC_MSK state if
  88. * a HW tune is required based on the RXON structure changes.
  89. */
  90. int iwl_commit_rxon(struct iwl_priv *priv)
  91. {
  92. /* cast away the const for active_rxon in this function */
  93. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  94. int ret;
  95. bool new_assoc =
  96. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  97. if (!iwl_is_alive(priv))
  98. return -EBUSY;
  99. /* always get timestamp with Rx frame */
  100. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  101. /* allow CTS-to-self if possible. this is relevant only for
  102. * 5000, but will not damage 4965 */
  103. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  104. ret = iwl_check_rxon_cmd(priv);
  105. if (ret) {
  106. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  107. return -EINVAL;
  108. }
  109. /* If we don't need to send a full RXON, we can use
  110. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  111. * and other flags for the current radio configuration. */
  112. if (!iwl_full_rxon_required(priv)) {
  113. ret = iwl_send_rxon_assoc(priv);
  114. if (ret) {
  115. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  116. return ret;
  117. }
  118. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  119. return 0;
  120. }
  121. /* station table will be cleared */
  122. priv->assoc_station_added = 0;
  123. /* If we are currently associated and the new config requires
  124. * an RXON_ASSOC and the new config wants the associated mask enabled,
  125. * we must clear the associated from the active configuration
  126. * before we apply the new config */
  127. if (iwl_is_associated(priv) && new_assoc) {
  128. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  129. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  130. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  131. sizeof(struct iwl_rxon_cmd),
  132. &priv->active_rxon);
  133. /* If the mask clearing failed then we set
  134. * active_rxon back to what it was previously */
  135. if (ret) {
  136. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  137. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  138. return ret;
  139. }
  140. }
  141. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  142. "* with%s RXON_FILTER_ASSOC_MSK\n"
  143. "* channel = %d\n"
  144. "* bssid = %pM\n",
  145. (new_assoc ? "" : "out"),
  146. le16_to_cpu(priv->staging_rxon.channel),
  147. priv->staging_rxon.bssid_addr);
  148. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  149. /* Apply the new configuration
  150. * RXON unassoc clears the station table in uCode, send it before
  151. * we add the bcast station. If assoc bit is set, we will send RXON
  152. * after having added the bcast and bssid station.
  153. */
  154. if (!new_assoc) {
  155. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  156. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  157. if (ret) {
  158. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  159. return ret;
  160. }
  161. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  162. }
  163. iwl_clear_stations_table(priv);
  164. priv->start_calib = 0;
  165. /* Add the broadcast address so we can send broadcast frames */
  166. if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) ==
  167. IWL_INVALID_STATION) {
  168. IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
  169. return -EIO;
  170. }
  171. /* If we have set the ASSOC_MSK and we are in BSS mode then
  172. * add the IWL_AP_ID to the station rate table */
  173. if (new_assoc) {
  174. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  175. ret = iwl_rxon_add_station(priv,
  176. priv->active_rxon.bssid_addr, 1);
  177. if (ret == IWL_INVALID_STATION) {
  178. IWL_ERR(priv,
  179. "Error adding AP address for TX.\n");
  180. return -EIO;
  181. }
  182. priv->assoc_station_added = 1;
  183. if (priv->default_wep_key &&
  184. iwl_send_static_wepkey_cmd(priv, 0))
  185. IWL_ERR(priv,
  186. "Could not send WEP static key.\n");
  187. }
  188. /* Apply the new configuration
  189. * RXON assoc doesn't clear the station table in uCode,
  190. */
  191. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  192. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  193. if (ret) {
  194. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  195. return ret;
  196. }
  197. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  198. }
  199. iwl_init_sensitivity(priv);
  200. /* If we issue a new RXON command which required a tune then we must
  201. * send a new TXPOWER command or we won't be able to Tx any frames */
  202. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  203. if (ret) {
  204. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  205. return ret;
  206. }
  207. return 0;
  208. }
  209. void iwl_update_chain_flags(struct iwl_priv *priv)
  210. {
  211. if (priv->cfg->ops->hcmd->set_rxon_chain)
  212. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  213. iwlcore_commit_rxon(priv);
  214. }
  215. static void iwl_clear_free_frames(struct iwl_priv *priv)
  216. {
  217. struct list_head *element;
  218. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  219. priv->frames_count);
  220. while (!list_empty(&priv->free_frames)) {
  221. element = priv->free_frames.next;
  222. list_del(element);
  223. kfree(list_entry(element, struct iwl_frame, list));
  224. priv->frames_count--;
  225. }
  226. if (priv->frames_count) {
  227. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  228. priv->frames_count);
  229. priv->frames_count = 0;
  230. }
  231. }
  232. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  233. {
  234. struct iwl_frame *frame;
  235. struct list_head *element;
  236. if (list_empty(&priv->free_frames)) {
  237. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  238. if (!frame) {
  239. IWL_ERR(priv, "Could not allocate frame!\n");
  240. return NULL;
  241. }
  242. priv->frames_count++;
  243. return frame;
  244. }
  245. element = priv->free_frames.next;
  246. list_del(element);
  247. return list_entry(element, struct iwl_frame, list);
  248. }
  249. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  250. {
  251. memset(frame, 0, sizeof(*frame));
  252. list_add(&frame->list, &priv->free_frames);
  253. }
  254. static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
  255. struct ieee80211_hdr *hdr,
  256. int left)
  257. {
  258. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  259. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  260. (priv->iw_mode != NL80211_IFTYPE_AP)))
  261. return 0;
  262. if (priv->ibss_beacon->len > left)
  263. return 0;
  264. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  265. return priv->ibss_beacon->len;
  266. }
  267. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  268. struct iwl_frame *frame, u8 rate)
  269. {
  270. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  271. unsigned int frame_size;
  272. tx_beacon_cmd = &frame->u.beacon;
  273. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  274. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  275. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  276. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  277. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  278. BUG_ON(frame_size > MAX_MPDU_SIZE);
  279. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  280. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  281. tx_beacon_cmd->tx.rate_n_flags =
  282. iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  283. else
  284. tx_beacon_cmd->tx.rate_n_flags =
  285. iwl_hw_set_rate_n_flags(rate, 0);
  286. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  287. TX_CMD_FLG_TSF_MSK |
  288. TX_CMD_FLG_STA_RATE_MSK;
  289. return sizeof(*tx_beacon_cmd) + frame_size;
  290. }
  291. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  292. {
  293. struct iwl_frame *frame;
  294. unsigned int frame_size;
  295. int rc;
  296. u8 rate;
  297. frame = iwl_get_free_frame(priv);
  298. if (!frame) {
  299. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  300. "command.\n");
  301. return -ENOMEM;
  302. }
  303. rate = iwl_rate_get_lowest_plcp(priv);
  304. frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
  305. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  306. &frame->u.cmd[0]);
  307. iwl_free_frame(priv, frame);
  308. return rc;
  309. }
  310. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  311. {
  312. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  313. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  314. if (sizeof(dma_addr_t) > sizeof(u32))
  315. addr |=
  316. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  317. return addr;
  318. }
  319. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  320. {
  321. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  322. return le16_to_cpu(tb->hi_n_len) >> 4;
  323. }
  324. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  325. dma_addr_t addr, u16 len)
  326. {
  327. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  328. u16 hi_n_len = len << 4;
  329. put_unaligned_le32(addr, &tb->lo);
  330. if (sizeof(dma_addr_t) > sizeof(u32))
  331. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  332. tb->hi_n_len = cpu_to_le16(hi_n_len);
  333. tfd->num_tbs = idx + 1;
  334. }
  335. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  336. {
  337. return tfd->num_tbs & 0x1f;
  338. }
  339. /**
  340. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  341. * @priv - driver private data
  342. * @txq - tx queue
  343. *
  344. * Does NOT advance any TFD circular buffer read/write indexes
  345. * Does NOT free the TFD itself (which is within circular buffer)
  346. */
  347. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  348. {
  349. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  350. struct iwl_tfd *tfd;
  351. struct pci_dev *dev = priv->pci_dev;
  352. int index = txq->q.read_ptr;
  353. int i;
  354. int num_tbs;
  355. tfd = &tfd_tmp[index];
  356. /* Sanity check on number of chunks */
  357. num_tbs = iwl_tfd_get_num_tbs(tfd);
  358. if (num_tbs >= IWL_NUM_OF_TBS) {
  359. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  360. /* @todo issue fatal error, it is quite serious situation */
  361. return;
  362. }
  363. /* Unmap tx_cmd */
  364. if (num_tbs)
  365. pci_unmap_single(dev,
  366. pci_unmap_addr(&txq->meta[index], mapping),
  367. pci_unmap_len(&txq->meta[index], len),
  368. PCI_DMA_BIDIRECTIONAL);
  369. /* Unmap chunks, if any. */
  370. for (i = 1; i < num_tbs; i++) {
  371. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  372. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  373. if (txq->txb) {
  374. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  375. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  376. }
  377. }
  378. }
  379. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  380. struct iwl_tx_queue *txq,
  381. dma_addr_t addr, u16 len,
  382. u8 reset, u8 pad)
  383. {
  384. struct iwl_queue *q;
  385. struct iwl_tfd *tfd, *tfd_tmp;
  386. u32 num_tbs;
  387. q = &txq->q;
  388. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  389. tfd = &tfd_tmp[q->write_ptr];
  390. if (reset)
  391. memset(tfd, 0, sizeof(*tfd));
  392. num_tbs = iwl_tfd_get_num_tbs(tfd);
  393. /* Each TFD can point to a maximum 20 Tx buffers */
  394. if (num_tbs >= IWL_NUM_OF_TBS) {
  395. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  396. IWL_NUM_OF_TBS);
  397. return -EINVAL;
  398. }
  399. BUG_ON(addr & ~DMA_BIT_MASK(36));
  400. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  401. IWL_ERR(priv, "Unaligned address = %llx\n",
  402. (unsigned long long)addr);
  403. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  404. return 0;
  405. }
  406. /*
  407. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  408. * given Tx queue, and enable the DMA channel used for that queue.
  409. *
  410. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  411. * channels supported in hardware.
  412. */
  413. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  414. struct iwl_tx_queue *txq)
  415. {
  416. int txq_id = txq->q.id;
  417. /* Circular buffer (TFD queue in DRAM) physical base address */
  418. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  419. txq->q.dma_addr >> 8);
  420. return 0;
  421. }
  422. /******************************************************************************
  423. *
  424. * Generic RX handler implementations
  425. *
  426. ******************************************************************************/
  427. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  428. struct iwl_rx_mem_buffer *rxb)
  429. {
  430. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  431. struct iwl_alive_resp *palive;
  432. struct delayed_work *pwork;
  433. palive = &pkt->u.alive_frame;
  434. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  435. "0x%01X 0x%01X\n",
  436. palive->is_valid, palive->ver_type,
  437. palive->ver_subtype);
  438. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  439. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  440. memcpy(&priv->card_alive_init,
  441. &pkt->u.alive_frame,
  442. sizeof(struct iwl_init_alive_resp));
  443. pwork = &priv->init_alive_start;
  444. } else {
  445. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  446. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  447. sizeof(struct iwl_alive_resp));
  448. pwork = &priv->alive_start;
  449. }
  450. /* We delay the ALIVE response by 5ms to
  451. * give the HW RF Kill time to activate... */
  452. if (palive->is_valid == UCODE_VALID_OK)
  453. queue_delayed_work(priv->workqueue, pwork,
  454. msecs_to_jiffies(5));
  455. else
  456. IWL_WARN(priv, "uCode did not respond OK.\n");
  457. }
  458. static void iwl_bg_beacon_update(struct work_struct *work)
  459. {
  460. struct iwl_priv *priv =
  461. container_of(work, struct iwl_priv, beacon_update);
  462. struct sk_buff *beacon;
  463. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  464. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  465. if (!beacon) {
  466. IWL_ERR(priv, "update beacon failed\n");
  467. return;
  468. }
  469. mutex_lock(&priv->mutex);
  470. /* new beacon skb is allocated every time; dispose previous.*/
  471. if (priv->ibss_beacon)
  472. dev_kfree_skb(priv->ibss_beacon);
  473. priv->ibss_beacon = beacon;
  474. mutex_unlock(&priv->mutex);
  475. iwl_send_beacon_cmd(priv);
  476. }
  477. /**
  478. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  479. *
  480. * This callback is provided in order to send a statistics request.
  481. *
  482. * This timer function is continually reset to execute within
  483. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  484. * was received. We need to ensure we receive the statistics in order
  485. * to update the temperature used for calibrating the TXPOWER.
  486. */
  487. static void iwl_bg_statistics_periodic(unsigned long data)
  488. {
  489. struct iwl_priv *priv = (struct iwl_priv *)data;
  490. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  491. return;
  492. /* dont send host command if rf-kill is on */
  493. if (!iwl_is_ready_rf(priv))
  494. return;
  495. iwl_send_statistics_request(priv, CMD_ASYNC);
  496. }
  497. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  498. struct iwl_rx_mem_buffer *rxb)
  499. {
  500. #ifdef CONFIG_IWLWIFI_DEBUG
  501. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  502. struct iwl4965_beacon_notif *beacon =
  503. (struct iwl4965_beacon_notif *)pkt->u.raw;
  504. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  505. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  506. "tsf %d %d rate %d\n",
  507. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  508. beacon->beacon_notify_hdr.failure_frame,
  509. le32_to_cpu(beacon->ibss_mgr_status),
  510. le32_to_cpu(beacon->high_tsf),
  511. le32_to_cpu(beacon->low_tsf), rate);
  512. #endif
  513. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  514. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  515. queue_work(priv->workqueue, &priv->beacon_update);
  516. }
  517. /* Handle notification from uCode that card's power state is changing
  518. * due to software, hardware, or critical temperature RFKILL */
  519. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  520. struct iwl_rx_mem_buffer *rxb)
  521. {
  522. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  523. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  524. unsigned long status = priv->status;
  525. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
  526. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  527. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  528. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  529. RF_CARD_DISABLED)) {
  530. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  531. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  532. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  533. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  534. if (!(flags & RXON_CARD_DISABLED)) {
  535. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  536. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  537. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  538. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  539. }
  540. if (flags & RF_CARD_DISABLED)
  541. iwl_tt_enter_ct_kill(priv);
  542. }
  543. if (!(flags & RF_CARD_DISABLED))
  544. iwl_tt_exit_ct_kill(priv);
  545. if (flags & HW_CARD_DISABLED)
  546. set_bit(STATUS_RF_KILL_HW, &priv->status);
  547. else
  548. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  549. if (!(flags & RXON_CARD_DISABLED))
  550. iwl_scan_cancel(priv);
  551. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  552. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  553. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  554. test_bit(STATUS_RF_KILL_HW, &priv->status));
  555. else
  556. wake_up_interruptible(&priv->wait_command_queue);
  557. }
  558. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  559. {
  560. if (src == IWL_PWR_SRC_VAUX) {
  561. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  562. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  563. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  564. ~APMG_PS_CTRL_MSK_PWR_SRC);
  565. } else {
  566. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  567. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  568. ~APMG_PS_CTRL_MSK_PWR_SRC);
  569. }
  570. return 0;
  571. }
  572. /**
  573. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  574. *
  575. * Setup the RX handlers for each of the reply types sent from the uCode
  576. * to the host.
  577. *
  578. * This function chains into the hardware specific files for them to setup
  579. * any hardware specific handlers as well.
  580. */
  581. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  582. {
  583. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  584. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  585. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  586. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  587. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  588. iwl_rx_pm_debug_statistics_notif;
  589. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  590. /*
  591. * The same handler is used for both the REPLY to a discrete
  592. * statistics request from the host as well as for the periodic
  593. * statistics notifications (after received beacons) from the uCode.
  594. */
  595. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
  596. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  597. iwl_setup_spectrum_handlers(priv);
  598. iwl_setup_rx_scan_handlers(priv);
  599. /* status change handler */
  600. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  601. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  602. iwl_rx_missed_beacon_notif;
  603. /* Rx handlers */
  604. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
  605. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
  606. /* block ack */
  607. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
  608. /* Set up hardware specific Rx handlers */
  609. priv->cfg->ops->lib->rx_handler_setup(priv);
  610. }
  611. /**
  612. * iwl_rx_handle - Main entry function for receiving responses from uCode
  613. *
  614. * Uses the priv->rx_handlers callback function array to invoke
  615. * the appropriate handlers, including command responses,
  616. * frame-received notifications, and other notifications.
  617. */
  618. void iwl_rx_handle(struct iwl_priv *priv)
  619. {
  620. struct iwl_rx_mem_buffer *rxb;
  621. struct iwl_rx_packet *pkt;
  622. struct iwl_rx_queue *rxq = &priv->rxq;
  623. u32 r, i;
  624. int reclaim;
  625. unsigned long flags;
  626. u8 fill_rx = 0;
  627. u32 count = 8;
  628. int total_empty;
  629. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  630. * buffer that the driver may process (last buffer filled by ucode). */
  631. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  632. i = rxq->read;
  633. /* Rx interrupt, but nothing sent from uCode */
  634. if (i == r)
  635. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  636. /* calculate total frames need to be restock after handling RX */
  637. total_empty = r - priv->rxq.write_actual;
  638. if (total_empty < 0)
  639. total_empty += RX_QUEUE_SIZE;
  640. if (total_empty > (RX_QUEUE_SIZE / 2))
  641. fill_rx = 1;
  642. while (i != r) {
  643. rxb = rxq->queue[i];
  644. /* If an RXB doesn't have a Rx queue slot associated with it,
  645. * then a bug has been introduced in the queue refilling
  646. * routines -- catch it here */
  647. BUG_ON(rxb == NULL);
  648. rxq->queue[i] = NULL;
  649. pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
  650. priv->hw_params.rx_buf_size + 256,
  651. PCI_DMA_FROMDEVICE);
  652. pkt = (struct iwl_rx_packet *)rxb->skb->data;
  653. /* Reclaim a command buffer only if this packet is a response
  654. * to a (driver-originated) command.
  655. * If the packet (e.g. Rx frame) originated from uCode,
  656. * there is no command buffer to reclaim.
  657. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  658. * but apparently a few don't get set; catch them here. */
  659. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  660. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  661. (pkt->hdr.cmd != REPLY_RX) &&
  662. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  663. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  664. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  665. (pkt->hdr.cmd != REPLY_TX);
  666. /* Based on type of command response or notification,
  667. * handle those that need handling via function in
  668. * rx_handlers table. See iwl_setup_rx_handlers() */
  669. if (priv->rx_handlers[pkt->hdr.cmd]) {
  670. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  671. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  672. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  673. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  674. } else {
  675. /* No handling needed */
  676. IWL_DEBUG_RX(priv,
  677. "r %d i %d No handler needed for %s, 0x%02x\n",
  678. r, i, get_cmd_string(pkt->hdr.cmd),
  679. pkt->hdr.cmd);
  680. }
  681. if (reclaim) {
  682. /* Invoke any callbacks, transfer the skb to caller, and
  683. * fire off the (possibly) blocking iwl_send_cmd()
  684. * as we reclaim the driver command queue */
  685. if (rxb && rxb->skb)
  686. iwl_tx_cmd_complete(priv, rxb);
  687. else
  688. IWL_WARN(priv, "Claim null rxb?\n");
  689. }
  690. /* For now we just don't re-use anything. We can tweak this
  691. * later to try and re-use notification packets and SKBs that
  692. * fail to Rx correctly */
  693. if (rxb->skb != NULL) {
  694. priv->alloc_rxb_skb--;
  695. dev_kfree_skb_any(rxb->skb);
  696. rxb->skb = NULL;
  697. }
  698. spin_lock_irqsave(&rxq->lock, flags);
  699. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  700. spin_unlock_irqrestore(&rxq->lock, flags);
  701. i = (i + 1) & RX_QUEUE_MASK;
  702. /* If there are a lot of unused frames,
  703. * restock the Rx queue so ucode wont assert. */
  704. if (fill_rx) {
  705. count++;
  706. if (count >= 8) {
  707. priv->rxq.read = i;
  708. iwl_rx_replenish_now(priv);
  709. count = 0;
  710. }
  711. }
  712. }
  713. /* Backtrack one entry */
  714. priv->rxq.read = i;
  715. if (fill_rx)
  716. iwl_rx_replenish_now(priv);
  717. else
  718. iwl_rx_queue_restock(priv);
  719. }
  720. /* call this function to flush any scheduled tasklet */
  721. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  722. {
  723. /* wait to make sure we flush pending tasklet*/
  724. synchronize_irq(priv->pci_dev->irq);
  725. tasklet_kill(&priv->irq_tasklet);
  726. }
  727. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  728. {
  729. u32 inta, handled = 0;
  730. u32 inta_fh;
  731. unsigned long flags;
  732. #ifdef CONFIG_IWLWIFI_DEBUG
  733. u32 inta_mask;
  734. #endif
  735. spin_lock_irqsave(&priv->lock, flags);
  736. /* Ack/clear/reset pending uCode interrupts.
  737. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  738. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  739. inta = iwl_read32(priv, CSR_INT);
  740. iwl_write32(priv, CSR_INT, inta);
  741. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  742. * Any new interrupts that happen after this, either while we're
  743. * in this tasklet, or later, will show up in next ISR/tasklet. */
  744. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  745. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  746. #ifdef CONFIG_IWLWIFI_DEBUG
  747. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  748. /* just for debug */
  749. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  750. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  751. inta, inta_mask, inta_fh);
  752. }
  753. #endif
  754. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  755. * atomic, make sure that inta covers all the interrupts that
  756. * we've discovered, even if FH interrupt came in just after
  757. * reading CSR_INT. */
  758. if (inta_fh & CSR49_FH_INT_RX_MASK)
  759. inta |= CSR_INT_BIT_FH_RX;
  760. if (inta_fh & CSR49_FH_INT_TX_MASK)
  761. inta |= CSR_INT_BIT_FH_TX;
  762. /* Now service all interrupt bits discovered above. */
  763. if (inta & CSR_INT_BIT_HW_ERR) {
  764. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  765. /* Tell the device to stop sending interrupts */
  766. iwl_disable_interrupts(priv);
  767. priv->isr_stats.hw++;
  768. iwl_irq_handle_error(priv);
  769. handled |= CSR_INT_BIT_HW_ERR;
  770. spin_unlock_irqrestore(&priv->lock, flags);
  771. return;
  772. }
  773. #ifdef CONFIG_IWLWIFI_DEBUG
  774. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  775. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  776. if (inta & CSR_INT_BIT_SCD) {
  777. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  778. "the frame/frames.\n");
  779. priv->isr_stats.sch++;
  780. }
  781. /* Alive notification via Rx interrupt will do the real work */
  782. if (inta & CSR_INT_BIT_ALIVE) {
  783. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  784. priv->isr_stats.alive++;
  785. }
  786. }
  787. #endif
  788. /* Safely ignore these bits for debug checks below */
  789. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  790. /* HW RF KILL switch toggled */
  791. if (inta & CSR_INT_BIT_RF_KILL) {
  792. int hw_rf_kill = 0;
  793. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  794. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  795. hw_rf_kill = 1;
  796. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  797. hw_rf_kill ? "disable radio" : "enable radio");
  798. priv->isr_stats.rfkill++;
  799. /* driver only loads ucode once setting the interface up.
  800. * the driver allows loading the ucode even if the radio
  801. * is killed. Hence update the killswitch state here. The
  802. * rfkill handler will care about restarting if needed.
  803. */
  804. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  805. if (hw_rf_kill)
  806. set_bit(STATUS_RF_KILL_HW, &priv->status);
  807. else
  808. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  809. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  810. }
  811. handled |= CSR_INT_BIT_RF_KILL;
  812. }
  813. /* Chip got too hot and stopped itself */
  814. if (inta & CSR_INT_BIT_CT_KILL) {
  815. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  816. priv->isr_stats.ctkill++;
  817. handled |= CSR_INT_BIT_CT_KILL;
  818. }
  819. /* Error detected by uCode */
  820. if (inta & CSR_INT_BIT_SW_ERR) {
  821. IWL_ERR(priv, "Microcode SW error detected. "
  822. " Restarting 0x%X.\n", inta);
  823. priv->isr_stats.sw++;
  824. priv->isr_stats.sw_err = inta;
  825. iwl_irq_handle_error(priv);
  826. handled |= CSR_INT_BIT_SW_ERR;
  827. }
  828. /* uCode wakes up after power-down sleep */
  829. if (inta & CSR_INT_BIT_WAKEUP) {
  830. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  831. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  832. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  833. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  834. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  835. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  836. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  837. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  838. priv->isr_stats.wakeup++;
  839. handled |= CSR_INT_BIT_WAKEUP;
  840. }
  841. /* All uCode command responses, including Tx command responses,
  842. * Rx "responses" (frame-received notification), and other
  843. * notifications from uCode come through here*/
  844. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  845. iwl_rx_handle(priv);
  846. priv->isr_stats.rx++;
  847. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  848. }
  849. if (inta & CSR_INT_BIT_FH_TX) {
  850. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  851. priv->isr_stats.tx++;
  852. handled |= CSR_INT_BIT_FH_TX;
  853. /* FH finished to write, send event */
  854. priv->ucode_write_complete = 1;
  855. wake_up_interruptible(&priv->wait_command_queue);
  856. }
  857. if (inta & ~handled) {
  858. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  859. priv->isr_stats.unhandled++;
  860. }
  861. if (inta & ~(priv->inta_mask)) {
  862. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  863. inta & ~priv->inta_mask);
  864. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  865. }
  866. /* Re-enable all interrupts */
  867. /* only Re-enable if diabled by irq */
  868. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  869. iwl_enable_interrupts(priv);
  870. #ifdef CONFIG_IWLWIFI_DEBUG
  871. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  872. inta = iwl_read32(priv, CSR_INT);
  873. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  874. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  875. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  876. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  877. }
  878. #endif
  879. spin_unlock_irqrestore(&priv->lock, flags);
  880. }
  881. /* tasklet for iwlagn interrupt */
  882. static void iwl_irq_tasklet(struct iwl_priv *priv)
  883. {
  884. u32 inta = 0;
  885. u32 handled = 0;
  886. unsigned long flags;
  887. #ifdef CONFIG_IWLWIFI_DEBUG
  888. u32 inta_mask;
  889. #endif
  890. spin_lock_irqsave(&priv->lock, flags);
  891. /* Ack/clear/reset pending uCode interrupts.
  892. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  893. */
  894. iwl_write32(priv, CSR_INT, priv->inta);
  895. inta = priv->inta;
  896. #ifdef CONFIG_IWLWIFI_DEBUG
  897. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  898. /* just for debug */
  899. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  900. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  901. inta, inta_mask);
  902. }
  903. #endif
  904. /* saved interrupt in inta variable now we can reset priv->inta */
  905. priv->inta = 0;
  906. /* Now service all interrupt bits discovered above. */
  907. if (inta & CSR_INT_BIT_HW_ERR) {
  908. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  909. /* Tell the device to stop sending interrupts */
  910. iwl_disable_interrupts(priv);
  911. priv->isr_stats.hw++;
  912. iwl_irq_handle_error(priv);
  913. handled |= CSR_INT_BIT_HW_ERR;
  914. spin_unlock_irqrestore(&priv->lock, flags);
  915. return;
  916. }
  917. #ifdef CONFIG_IWLWIFI_DEBUG
  918. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  919. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  920. if (inta & CSR_INT_BIT_SCD) {
  921. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  922. "the frame/frames.\n");
  923. priv->isr_stats.sch++;
  924. }
  925. /* Alive notification via Rx interrupt will do the real work */
  926. if (inta & CSR_INT_BIT_ALIVE) {
  927. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  928. priv->isr_stats.alive++;
  929. }
  930. }
  931. #endif
  932. /* Safely ignore these bits for debug checks below */
  933. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  934. /* HW RF KILL switch toggled */
  935. if (inta & CSR_INT_BIT_RF_KILL) {
  936. int hw_rf_kill = 0;
  937. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  938. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  939. hw_rf_kill = 1;
  940. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  941. hw_rf_kill ? "disable radio" : "enable radio");
  942. priv->isr_stats.rfkill++;
  943. /* driver only loads ucode once setting the interface up.
  944. * the driver allows loading the ucode even if the radio
  945. * is killed. Hence update the killswitch state here. The
  946. * rfkill handler will care about restarting if needed.
  947. */
  948. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  949. if (hw_rf_kill)
  950. set_bit(STATUS_RF_KILL_HW, &priv->status);
  951. else
  952. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  953. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  954. }
  955. handled |= CSR_INT_BIT_RF_KILL;
  956. }
  957. /* Chip got too hot and stopped itself */
  958. if (inta & CSR_INT_BIT_CT_KILL) {
  959. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  960. priv->isr_stats.ctkill++;
  961. handled |= CSR_INT_BIT_CT_KILL;
  962. }
  963. /* Error detected by uCode */
  964. if (inta & CSR_INT_BIT_SW_ERR) {
  965. IWL_ERR(priv, "Microcode SW error detected. "
  966. " Restarting 0x%X.\n", inta);
  967. priv->isr_stats.sw++;
  968. priv->isr_stats.sw_err = inta;
  969. iwl_irq_handle_error(priv);
  970. handled |= CSR_INT_BIT_SW_ERR;
  971. }
  972. /* uCode wakes up after power-down sleep */
  973. if (inta & CSR_INT_BIT_WAKEUP) {
  974. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  975. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  976. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  977. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  978. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  979. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  980. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  981. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  982. priv->isr_stats.wakeup++;
  983. handled |= CSR_INT_BIT_WAKEUP;
  984. }
  985. /* All uCode command responses, including Tx command responses,
  986. * Rx "responses" (frame-received notification), and other
  987. * notifications from uCode come through here*/
  988. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  989. CSR_INT_BIT_RX_PERIODIC)) {
  990. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  991. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  992. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  993. iwl_write32(priv, CSR_FH_INT_STATUS,
  994. CSR49_FH_INT_RX_MASK);
  995. }
  996. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  997. handled |= CSR_INT_BIT_RX_PERIODIC;
  998. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  999. }
  1000. /* Sending RX interrupt require many steps to be done in the
  1001. * the device:
  1002. * 1- write interrupt to current index in ICT table.
  1003. * 2- dma RX frame.
  1004. * 3- update RX shared data to indicate last write index.
  1005. * 4- send interrupt.
  1006. * This could lead to RX race, driver could receive RX interrupt
  1007. * but the shared data changes does not reflect this.
  1008. * this could lead to RX race, RX periodic will solve this race
  1009. */
  1010. iwl_write32(priv, CSR_INT_PERIODIC_REG,
  1011. CSR_INT_PERIODIC_DIS);
  1012. iwl_rx_handle(priv);
  1013. /* Only set RX periodic if real RX is received. */
  1014. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1015. iwl_write32(priv, CSR_INT_PERIODIC_REG,
  1016. CSR_INT_PERIODIC_ENA);
  1017. priv->isr_stats.rx++;
  1018. }
  1019. if (inta & CSR_INT_BIT_FH_TX) {
  1020. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1021. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  1022. priv->isr_stats.tx++;
  1023. handled |= CSR_INT_BIT_FH_TX;
  1024. /* FH finished to write, send event */
  1025. priv->ucode_write_complete = 1;
  1026. wake_up_interruptible(&priv->wait_command_queue);
  1027. }
  1028. if (inta & ~handled) {
  1029. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1030. priv->isr_stats.unhandled++;
  1031. }
  1032. if (inta & ~(priv->inta_mask)) {
  1033. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1034. inta & ~priv->inta_mask);
  1035. }
  1036. /* Re-enable all interrupts */
  1037. /* only Re-enable if diabled by irq */
  1038. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1039. iwl_enable_interrupts(priv);
  1040. spin_unlock_irqrestore(&priv->lock, flags);
  1041. }
  1042. /******************************************************************************
  1043. *
  1044. * uCode download functions
  1045. *
  1046. ******************************************************************************/
  1047. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1048. {
  1049. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1050. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1051. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1052. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1053. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1054. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1055. }
  1056. static void iwl_nic_start(struct iwl_priv *priv)
  1057. {
  1058. /* Remove all resets to allow NIC to operate */
  1059. iwl_write32(priv, CSR_RESET, 0);
  1060. }
  1061. /**
  1062. * iwl_read_ucode - Read uCode images from disk file.
  1063. *
  1064. * Copy into buffers for card to fetch via bus-mastering
  1065. */
  1066. static int iwl_read_ucode(struct iwl_priv *priv)
  1067. {
  1068. struct iwl_ucode_header *ucode;
  1069. int ret = -EINVAL, index;
  1070. const struct firmware *ucode_raw;
  1071. const char *name_pre = priv->cfg->fw_name_pre;
  1072. const unsigned int api_max = priv->cfg->ucode_api_max;
  1073. const unsigned int api_min = priv->cfg->ucode_api_min;
  1074. char buf[25];
  1075. u8 *src;
  1076. size_t len;
  1077. u32 api_ver, build;
  1078. u32 inst_size, data_size, init_size, init_data_size, boot_size;
  1079. u16 eeprom_ver;
  1080. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1081. * request_firmware() is synchronous, file is in memory on return. */
  1082. for (index = api_max; index >= api_min; index--) {
  1083. sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
  1084. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  1085. if (ret < 0) {
  1086. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  1087. buf, ret);
  1088. if (ret == -ENOENT)
  1089. continue;
  1090. else
  1091. goto error;
  1092. } else {
  1093. if (index < api_max)
  1094. IWL_ERR(priv, "Loaded firmware %s, "
  1095. "which is deprecated. "
  1096. "Please use API v%u instead.\n",
  1097. buf, api_max);
  1098. IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
  1099. buf, ucode_raw->size);
  1100. break;
  1101. }
  1102. }
  1103. if (ret < 0)
  1104. goto error;
  1105. /* Make sure that we got at least the v1 header! */
  1106. if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
  1107. IWL_ERR(priv, "File size way too small!\n");
  1108. ret = -EINVAL;
  1109. goto err_release;
  1110. }
  1111. /* Data from ucode file: header followed by uCode images */
  1112. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1113. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1114. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1115. build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
  1116. inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
  1117. data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
  1118. init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
  1119. init_data_size =
  1120. priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
  1121. boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
  1122. src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
  1123. /* api_ver should match the api version forming part of the
  1124. * firmware filename ... but we don't check for that and only rely
  1125. * on the API version read from firmware header from here on forward */
  1126. if (api_ver < api_min || api_ver > api_max) {
  1127. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1128. "Driver supports v%u, firmware is v%u.\n",
  1129. api_max, api_ver);
  1130. priv->ucode_ver = 0;
  1131. ret = -EINVAL;
  1132. goto err_release;
  1133. }
  1134. if (api_ver != api_max)
  1135. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1136. "got v%u. New firmware can be obtained "
  1137. "from http://www.intellinuxwireless.org.\n",
  1138. api_max, api_ver);
  1139. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1140. IWL_UCODE_MAJOR(priv->ucode_ver),
  1141. IWL_UCODE_MINOR(priv->ucode_ver),
  1142. IWL_UCODE_API(priv->ucode_ver),
  1143. IWL_UCODE_SERIAL(priv->ucode_ver));
  1144. if (build)
  1145. IWL_DEBUG_INFO(priv, "Build %u\n", build);
  1146. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  1147. IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
  1148. (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
  1149. ? "OTP" : "EEPROM", eeprom_ver);
  1150. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1151. priv->ucode_ver);
  1152. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1153. inst_size);
  1154. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1155. data_size);
  1156. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1157. init_size);
  1158. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1159. init_data_size);
  1160. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1161. boot_size);
  1162. /* Verify size of file vs. image size info in file's header */
  1163. if (ucode_raw->size !=
  1164. priv->cfg->ops->ucode->get_header_size(api_ver) +
  1165. inst_size + data_size + init_size +
  1166. init_data_size + boot_size) {
  1167. IWL_DEBUG_INFO(priv,
  1168. "uCode file size %d does not match expected size\n",
  1169. (int)ucode_raw->size);
  1170. ret = -EINVAL;
  1171. goto err_release;
  1172. }
  1173. /* Verify that uCode images will fit in card's SRAM */
  1174. if (inst_size > priv->hw_params.max_inst_size) {
  1175. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1176. inst_size);
  1177. ret = -EINVAL;
  1178. goto err_release;
  1179. }
  1180. if (data_size > priv->hw_params.max_data_size) {
  1181. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1182. data_size);
  1183. ret = -EINVAL;
  1184. goto err_release;
  1185. }
  1186. if (init_size > priv->hw_params.max_inst_size) {
  1187. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1188. init_size);
  1189. ret = -EINVAL;
  1190. goto err_release;
  1191. }
  1192. if (init_data_size > priv->hw_params.max_data_size) {
  1193. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1194. init_data_size);
  1195. ret = -EINVAL;
  1196. goto err_release;
  1197. }
  1198. if (boot_size > priv->hw_params.max_bsm_size) {
  1199. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1200. boot_size);
  1201. ret = -EINVAL;
  1202. goto err_release;
  1203. }
  1204. /* Allocate ucode buffers for card's bus-master loading ... */
  1205. /* Runtime instructions and 2 copies of data:
  1206. * 1) unmodified from disk
  1207. * 2) backup cache for save/restore during power-downs */
  1208. priv->ucode_code.len = inst_size;
  1209. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1210. priv->ucode_data.len = data_size;
  1211. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1212. priv->ucode_data_backup.len = data_size;
  1213. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1214. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1215. !priv->ucode_data_backup.v_addr)
  1216. goto err_pci_alloc;
  1217. /* Initialization instructions and data */
  1218. if (init_size && init_data_size) {
  1219. priv->ucode_init.len = init_size;
  1220. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1221. priv->ucode_init_data.len = init_data_size;
  1222. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1223. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1224. goto err_pci_alloc;
  1225. }
  1226. /* Bootstrap (instructions only, no data) */
  1227. if (boot_size) {
  1228. priv->ucode_boot.len = boot_size;
  1229. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1230. if (!priv->ucode_boot.v_addr)
  1231. goto err_pci_alloc;
  1232. }
  1233. /* Copy images into buffers for card's bus-master reads ... */
  1234. /* Runtime instructions (first block of data in file) */
  1235. len = inst_size;
  1236. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1237. memcpy(priv->ucode_code.v_addr, src, len);
  1238. src += len;
  1239. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1240. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1241. /* Runtime data (2nd block)
  1242. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1243. len = data_size;
  1244. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1245. memcpy(priv->ucode_data.v_addr, src, len);
  1246. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1247. src += len;
  1248. /* Initialization instructions (3rd block) */
  1249. if (init_size) {
  1250. len = init_size;
  1251. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1252. len);
  1253. memcpy(priv->ucode_init.v_addr, src, len);
  1254. src += len;
  1255. }
  1256. /* Initialization data (4th block) */
  1257. if (init_data_size) {
  1258. len = init_data_size;
  1259. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1260. len);
  1261. memcpy(priv->ucode_init_data.v_addr, src, len);
  1262. src += len;
  1263. }
  1264. /* Bootstrap instructions (5th block) */
  1265. len = boot_size;
  1266. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1267. memcpy(priv->ucode_boot.v_addr, src, len);
  1268. /* We have our copies now, allow OS release its copies */
  1269. release_firmware(ucode_raw);
  1270. return 0;
  1271. err_pci_alloc:
  1272. IWL_ERR(priv, "failed to allocate pci memory\n");
  1273. ret = -ENOMEM;
  1274. iwl_dealloc_ucode_pci(priv);
  1275. err_release:
  1276. release_firmware(ucode_raw);
  1277. error:
  1278. return ret;
  1279. }
  1280. #ifdef CONFIG_IWLWIFI_DEBUG
  1281. static const char *desc_lookup_text[] = {
  1282. "OK",
  1283. "FAIL",
  1284. "BAD_PARAM",
  1285. "BAD_CHECKSUM",
  1286. "NMI_INTERRUPT_WDG",
  1287. "SYSASSERT",
  1288. "FATAL_ERROR",
  1289. "BAD_COMMAND",
  1290. "HW_ERROR_TUNE_LOCK",
  1291. "HW_ERROR_TEMPERATURE",
  1292. "ILLEGAL_CHAN_FREQ",
  1293. "VCC_NOT_STABLE",
  1294. "FH_ERROR",
  1295. "NMI_INTERRUPT_HOST",
  1296. "NMI_INTERRUPT_ACTION_PT",
  1297. "NMI_INTERRUPT_UNKNOWN",
  1298. "UCODE_VERSION_MISMATCH",
  1299. "HW_ERROR_ABS_LOCK",
  1300. "HW_ERROR_CAL_LOCK_FAIL",
  1301. "NMI_INTERRUPT_INST_ACTION_PT",
  1302. "NMI_INTERRUPT_DATA_ACTION_PT",
  1303. "NMI_TRM_HW_ER",
  1304. "NMI_INTERRUPT_TRM",
  1305. "NMI_INTERRUPT_BREAK_POINT"
  1306. "DEBUG_0",
  1307. "DEBUG_1",
  1308. "DEBUG_2",
  1309. "DEBUG_3",
  1310. "UNKNOWN"
  1311. };
  1312. static const char *desc_lookup(int i)
  1313. {
  1314. int max = ARRAY_SIZE(desc_lookup_text) - 1;
  1315. if (i < 0 || i > max)
  1316. i = max;
  1317. return desc_lookup_text[i];
  1318. }
  1319. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1320. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1321. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1322. {
  1323. u32 data2, line;
  1324. u32 desc, time, count, base, data1;
  1325. u32 blink1, blink2, ilink1, ilink2;
  1326. if (priv->ucode_type == UCODE_INIT)
  1327. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1328. else
  1329. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1330. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1331. IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
  1332. return;
  1333. }
  1334. count = iwl_read_targ_mem(priv, base);
  1335. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1336. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1337. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1338. priv->status, count);
  1339. }
  1340. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1341. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1342. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1343. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1344. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1345. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1346. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1347. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1348. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1349. IWL_ERR(priv, "Desc Time "
  1350. "data1 data2 line\n");
  1351. IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
  1352. desc_lookup(desc), desc, time, data1, data2, line);
  1353. IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
  1354. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
  1355. ilink1, ilink2);
  1356. }
  1357. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1358. /**
  1359. * iwl_print_event_log - Dump error event log to syslog
  1360. *
  1361. */
  1362. static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1363. u32 num_events, u32 mode)
  1364. {
  1365. u32 i;
  1366. u32 base; /* SRAM byte address of event log header */
  1367. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1368. u32 ptr; /* SRAM byte address of log data */
  1369. u32 ev, time, data; /* event log data */
  1370. if (num_events == 0)
  1371. return;
  1372. if (priv->ucode_type == UCODE_INIT)
  1373. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1374. else
  1375. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1376. if (mode == 0)
  1377. event_size = 2 * sizeof(u32);
  1378. else
  1379. event_size = 3 * sizeof(u32);
  1380. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1381. /* "time" is actually "data" for mode 0 (no timestamp).
  1382. * place event id # at far right for easier visual parsing. */
  1383. for (i = 0; i < num_events; i++) {
  1384. ev = iwl_read_targ_mem(priv, ptr);
  1385. ptr += sizeof(u32);
  1386. time = iwl_read_targ_mem(priv, ptr);
  1387. ptr += sizeof(u32);
  1388. if (mode == 0) {
  1389. /* data, ev */
  1390. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
  1391. } else {
  1392. data = iwl_read_targ_mem(priv, ptr);
  1393. ptr += sizeof(u32);
  1394. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1395. time, data, ev);
  1396. }
  1397. }
  1398. }
  1399. void iwl_dump_nic_event_log(struct iwl_priv *priv)
  1400. {
  1401. u32 base; /* SRAM byte address of event log header */
  1402. u32 capacity; /* event log capacity in # entries */
  1403. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1404. u32 num_wraps; /* # times uCode wrapped to top of log */
  1405. u32 next_entry; /* index of next entry to be written by uCode */
  1406. u32 size; /* # entries that we'll print */
  1407. if (priv->ucode_type == UCODE_INIT)
  1408. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1409. else
  1410. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1411. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1412. IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
  1413. return;
  1414. }
  1415. /* event log header */
  1416. capacity = iwl_read_targ_mem(priv, base);
  1417. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1418. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1419. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1420. size = num_wraps ? capacity : next_entry;
  1421. /* bail out if nothing in log */
  1422. if (size == 0) {
  1423. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1424. return;
  1425. }
  1426. IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
  1427. size, num_wraps);
  1428. /* if uCode has wrapped back to top of log, start at the oldest entry,
  1429. * i.e the next one that uCode would fill. */
  1430. if (num_wraps)
  1431. iwl_print_event_log(priv, next_entry,
  1432. capacity - next_entry, mode);
  1433. /* (then/else) start at top of log */
  1434. iwl_print_event_log(priv, 0, next_entry, mode);
  1435. }
  1436. #endif
  1437. /**
  1438. * iwl_alive_start - called after REPLY_ALIVE notification received
  1439. * from protocol/runtime uCode (initialization uCode's
  1440. * Alive gets handled by iwl_init_alive_start()).
  1441. */
  1442. static void iwl_alive_start(struct iwl_priv *priv)
  1443. {
  1444. int ret = 0;
  1445. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1446. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1447. /* We had an error bringing up the hardware, so take it
  1448. * all the way back down so we can try again */
  1449. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1450. goto restart;
  1451. }
  1452. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1453. * This is a paranoid check, because we would not have gotten the
  1454. * "runtime" alive if code weren't properly loaded. */
  1455. if (iwl_verify_ucode(priv)) {
  1456. /* Runtime instruction load was bad;
  1457. * take it all the way back down so we can try again */
  1458. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1459. goto restart;
  1460. }
  1461. iwl_clear_stations_table(priv);
  1462. ret = priv->cfg->ops->lib->alive_notify(priv);
  1463. if (ret) {
  1464. IWL_WARN(priv,
  1465. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1466. goto restart;
  1467. }
  1468. /* After the ALIVE response, we can send host commands to the uCode */
  1469. set_bit(STATUS_ALIVE, &priv->status);
  1470. if (iwl_is_rfkill(priv))
  1471. return;
  1472. ieee80211_wake_queues(priv->hw);
  1473. priv->active_rate = priv->rates_mask;
  1474. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1475. if (iwl_is_associated(priv)) {
  1476. struct iwl_rxon_cmd *active_rxon =
  1477. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1478. /* apply any changes in staging */
  1479. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1480. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1481. } else {
  1482. /* Initialize our rx_config data */
  1483. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1484. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1485. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1486. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1487. }
  1488. /* Configure Bluetooth device coexistence support */
  1489. iwl_send_bt_config(priv);
  1490. iwl_reset_run_time_calib(priv);
  1491. /* Configure the adapter for unassociated operation */
  1492. iwlcore_commit_rxon(priv);
  1493. /* At this point, the NIC is initialized and operational */
  1494. iwl_rf_kill_ct_config(priv);
  1495. iwl_leds_register(priv);
  1496. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1497. set_bit(STATUS_READY, &priv->status);
  1498. wake_up_interruptible(&priv->wait_command_queue);
  1499. iwl_power_update_mode(priv, true);
  1500. /* reassociate for ADHOC mode */
  1501. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  1502. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  1503. priv->vif);
  1504. if (beacon)
  1505. iwl_mac_beacon_update(priv->hw, beacon);
  1506. }
  1507. if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
  1508. iwl_set_mode(priv, priv->iw_mode);
  1509. return;
  1510. restart:
  1511. queue_work(priv->workqueue, &priv->restart);
  1512. }
  1513. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1514. static void __iwl_down(struct iwl_priv *priv)
  1515. {
  1516. unsigned long flags;
  1517. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1518. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1519. if (!exit_pending)
  1520. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1521. iwl_leds_unregister(priv);
  1522. iwl_clear_stations_table(priv);
  1523. /* Unblock any waiting calls */
  1524. wake_up_interruptible_all(&priv->wait_command_queue);
  1525. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1526. * exiting the module */
  1527. if (!exit_pending)
  1528. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1529. /* stop and reset the on-board processor */
  1530. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1531. /* tell the device to stop sending interrupts */
  1532. spin_lock_irqsave(&priv->lock, flags);
  1533. iwl_disable_interrupts(priv);
  1534. spin_unlock_irqrestore(&priv->lock, flags);
  1535. iwl_synchronize_irq(priv);
  1536. if (priv->mac80211_registered)
  1537. ieee80211_stop_queues(priv->hw);
  1538. /* If we have not previously called iwl_init() then
  1539. * clear all bits but the RF Kill bit and return */
  1540. if (!iwl_is_init(priv)) {
  1541. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1542. STATUS_RF_KILL_HW |
  1543. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1544. STATUS_GEO_CONFIGURED |
  1545. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1546. STATUS_EXIT_PENDING;
  1547. goto exit;
  1548. }
  1549. /* ...otherwise clear out all the status bits but the RF Kill
  1550. * bit and continue taking the NIC down. */
  1551. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1552. STATUS_RF_KILL_HW |
  1553. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1554. STATUS_GEO_CONFIGURED |
  1555. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1556. STATUS_FW_ERROR |
  1557. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1558. STATUS_EXIT_PENDING;
  1559. /* device going down, Stop using ICT table */
  1560. iwl_disable_ict(priv);
  1561. spin_lock_irqsave(&priv->lock, flags);
  1562. iwl_clear_bit(priv, CSR_GP_CNTRL,
  1563. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1564. spin_unlock_irqrestore(&priv->lock, flags);
  1565. iwl_txq_ctx_stop(priv);
  1566. iwl_rxq_stop(priv);
  1567. iwl_write_prph(priv, APMG_CLK_DIS_REG,
  1568. APMG_CLK_VAL_DMA_CLK_RQT);
  1569. udelay(5);
  1570. /* FIXME: apm_ops.suspend(priv) */
  1571. if (exit_pending)
  1572. priv->cfg->ops->lib->apm_ops.stop(priv);
  1573. else
  1574. priv->cfg->ops->lib->apm_ops.reset(priv);
  1575. exit:
  1576. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1577. if (priv->ibss_beacon)
  1578. dev_kfree_skb(priv->ibss_beacon);
  1579. priv->ibss_beacon = NULL;
  1580. /* clear out any free frames */
  1581. iwl_clear_free_frames(priv);
  1582. }
  1583. static void iwl_down(struct iwl_priv *priv)
  1584. {
  1585. mutex_lock(&priv->mutex);
  1586. __iwl_down(priv);
  1587. mutex_unlock(&priv->mutex);
  1588. iwl_cancel_deferred_work(priv);
  1589. }
  1590. #define HW_READY_TIMEOUT (50)
  1591. static int iwl_set_hw_ready(struct iwl_priv *priv)
  1592. {
  1593. int ret = 0;
  1594. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1595. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1596. /* See if we got it */
  1597. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1598. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1599. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1600. HW_READY_TIMEOUT);
  1601. if (ret != -ETIMEDOUT)
  1602. priv->hw_ready = true;
  1603. else
  1604. priv->hw_ready = false;
  1605. IWL_DEBUG_INFO(priv, "hardware %s\n",
  1606. (priv->hw_ready == 1) ? "ready" : "not ready");
  1607. return ret;
  1608. }
  1609. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  1610. {
  1611. int ret = 0;
  1612. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
  1613. ret = iwl_set_hw_ready(priv);
  1614. if (priv->hw_ready)
  1615. return ret;
  1616. /* If HW is not ready, prepare the conditions to check again */
  1617. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1618. CSR_HW_IF_CONFIG_REG_PREPARE);
  1619. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1620. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1621. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1622. /* HW should be ready by now, check again. */
  1623. if (ret != -ETIMEDOUT)
  1624. iwl_set_hw_ready(priv);
  1625. return ret;
  1626. }
  1627. #define MAX_HW_RESTARTS 5
  1628. static int __iwl_up(struct iwl_priv *priv)
  1629. {
  1630. int i;
  1631. int ret;
  1632. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1633. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1634. return -EIO;
  1635. }
  1636. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1637. IWL_ERR(priv, "ucode not available for device bringup\n");
  1638. return -EIO;
  1639. }
  1640. iwl_prepare_card_hw(priv);
  1641. if (!priv->hw_ready) {
  1642. IWL_WARN(priv, "Exit HW not ready\n");
  1643. return -EIO;
  1644. }
  1645. /* If platform's RF_KILL switch is NOT set to KILL */
  1646. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1647. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1648. else
  1649. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1650. if (iwl_is_rfkill(priv)) {
  1651. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  1652. iwl_enable_interrupts(priv);
  1653. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  1654. return 0;
  1655. }
  1656. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1657. ret = iwl_hw_nic_init(priv);
  1658. if (ret) {
  1659. IWL_ERR(priv, "Unable to init nic\n");
  1660. return ret;
  1661. }
  1662. /* make sure rfkill handshake bits are cleared */
  1663. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1664. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1665. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1666. /* clear (again), then enable host interrupts */
  1667. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1668. iwl_enable_interrupts(priv);
  1669. /* really make sure rfkill handshake bits are cleared */
  1670. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1671. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1672. /* Copy original ucode data image from disk into backup cache.
  1673. * This will be used to initialize the on-board processor's
  1674. * data SRAM for a clean start when the runtime program first loads. */
  1675. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  1676. priv->ucode_data.len);
  1677. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  1678. iwl_clear_stations_table(priv);
  1679. /* load bootstrap state machine,
  1680. * load bootstrap program into processor's memory,
  1681. * prepare to load the "initialize" uCode */
  1682. ret = priv->cfg->ops->lib->load_ucode(priv);
  1683. if (ret) {
  1684. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  1685. ret);
  1686. continue;
  1687. }
  1688. /* start card; "initialize" will load runtime ucode */
  1689. iwl_nic_start(priv);
  1690. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  1691. return 0;
  1692. }
  1693. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1694. __iwl_down(priv);
  1695. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1696. /* tried to restart and config the device for as long as our
  1697. * patience could withstand */
  1698. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  1699. return -EIO;
  1700. }
  1701. /*****************************************************************************
  1702. *
  1703. * Workqueue callbacks
  1704. *
  1705. *****************************************************************************/
  1706. static void iwl_bg_init_alive_start(struct work_struct *data)
  1707. {
  1708. struct iwl_priv *priv =
  1709. container_of(data, struct iwl_priv, init_alive_start.work);
  1710. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1711. return;
  1712. mutex_lock(&priv->mutex);
  1713. priv->cfg->ops->lib->init_alive_start(priv);
  1714. mutex_unlock(&priv->mutex);
  1715. }
  1716. static void iwl_bg_alive_start(struct work_struct *data)
  1717. {
  1718. struct iwl_priv *priv =
  1719. container_of(data, struct iwl_priv, alive_start.work);
  1720. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1721. return;
  1722. /* enable dram interrupt */
  1723. iwl_reset_ict(priv);
  1724. mutex_lock(&priv->mutex);
  1725. iwl_alive_start(priv);
  1726. mutex_unlock(&priv->mutex);
  1727. }
  1728. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  1729. {
  1730. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1731. run_time_calib_work);
  1732. mutex_lock(&priv->mutex);
  1733. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1734. test_bit(STATUS_SCANNING, &priv->status)) {
  1735. mutex_unlock(&priv->mutex);
  1736. return;
  1737. }
  1738. if (priv->start_calib) {
  1739. iwl_chain_noise_calibration(priv, &priv->statistics);
  1740. iwl_sensitivity_calibration(priv, &priv->statistics);
  1741. }
  1742. mutex_unlock(&priv->mutex);
  1743. return;
  1744. }
  1745. static void iwl_bg_up(struct work_struct *data)
  1746. {
  1747. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  1748. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1749. return;
  1750. mutex_lock(&priv->mutex);
  1751. __iwl_up(priv);
  1752. mutex_unlock(&priv->mutex);
  1753. }
  1754. static void iwl_bg_restart(struct work_struct *data)
  1755. {
  1756. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  1757. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1758. return;
  1759. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  1760. mutex_lock(&priv->mutex);
  1761. priv->vif = NULL;
  1762. priv->is_open = 0;
  1763. mutex_unlock(&priv->mutex);
  1764. iwl_down(priv);
  1765. ieee80211_restart_hw(priv->hw);
  1766. } else {
  1767. iwl_down(priv);
  1768. queue_work(priv->workqueue, &priv->up);
  1769. }
  1770. }
  1771. static void iwl_bg_rx_replenish(struct work_struct *data)
  1772. {
  1773. struct iwl_priv *priv =
  1774. container_of(data, struct iwl_priv, rx_replenish);
  1775. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1776. return;
  1777. mutex_lock(&priv->mutex);
  1778. iwl_rx_replenish(priv);
  1779. mutex_unlock(&priv->mutex);
  1780. }
  1781. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  1782. void iwl_post_associate(struct iwl_priv *priv)
  1783. {
  1784. struct ieee80211_conf *conf = NULL;
  1785. int ret = 0;
  1786. unsigned long flags;
  1787. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  1788. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  1789. return;
  1790. }
  1791. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  1792. priv->assoc_id, priv->active_rxon.bssid_addr);
  1793. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1794. return;
  1795. if (!priv->vif || !priv->is_open)
  1796. return;
  1797. iwl_scan_cancel_timeout(priv, 200);
  1798. conf = ieee80211_get_hw_conf(priv->hw);
  1799. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1800. iwlcore_commit_rxon(priv);
  1801. iwl_setup_rxon_timing(priv);
  1802. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1803. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1804. if (ret)
  1805. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1806. "Attempting to continue.\n");
  1807. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1808. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  1809. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1810. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1811. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1812. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  1813. priv->assoc_id, priv->beacon_int);
  1814. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1815. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1816. else
  1817. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1818. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1819. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1820. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1821. else
  1822. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1823. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1824. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1825. }
  1826. iwlcore_commit_rxon(priv);
  1827. switch (priv->iw_mode) {
  1828. case NL80211_IFTYPE_STATION:
  1829. break;
  1830. case NL80211_IFTYPE_ADHOC:
  1831. /* assume default assoc id */
  1832. priv->assoc_id = 1;
  1833. iwl_rxon_add_station(priv, priv->bssid, 0);
  1834. iwl_send_beacon_cmd(priv);
  1835. break;
  1836. default:
  1837. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  1838. __func__, priv->iw_mode);
  1839. break;
  1840. }
  1841. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1842. priv->assoc_station_added = 1;
  1843. spin_lock_irqsave(&priv->lock, flags);
  1844. iwl_activate_qos(priv, 0);
  1845. spin_unlock_irqrestore(&priv->lock, flags);
  1846. /* the chain noise calibration will enabled PM upon completion
  1847. * If chain noise has already been run, then we need to enable
  1848. * power management here */
  1849. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  1850. iwl_power_update_mode(priv, false);
  1851. /* Enable Rx differential gain and sensitivity calibrations */
  1852. iwl_chain_noise_reset(priv);
  1853. priv->start_calib = 1;
  1854. }
  1855. /*****************************************************************************
  1856. *
  1857. * mac80211 entry point functions
  1858. *
  1859. *****************************************************************************/
  1860. #define UCODE_READY_TIMEOUT (4 * HZ)
  1861. static int iwl_mac_start(struct ieee80211_hw *hw)
  1862. {
  1863. struct iwl_priv *priv = hw->priv;
  1864. int ret;
  1865. IWL_DEBUG_MAC80211(priv, "enter\n");
  1866. /* we should be verifying the device is ready to be opened */
  1867. mutex_lock(&priv->mutex);
  1868. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  1869. * ucode filename and max sizes are card-specific. */
  1870. if (!priv->ucode_code.len) {
  1871. ret = iwl_read_ucode(priv);
  1872. if (ret) {
  1873. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  1874. mutex_unlock(&priv->mutex);
  1875. return ret;
  1876. }
  1877. }
  1878. ret = __iwl_up(priv);
  1879. mutex_unlock(&priv->mutex);
  1880. if (ret)
  1881. return ret;
  1882. if (iwl_is_rfkill(priv))
  1883. goto out;
  1884. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  1885. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  1886. * mac80211 will not be run successfully. */
  1887. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  1888. test_bit(STATUS_READY, &priv->status),
  1889. UCODE_READY_TIMEOUT);
  1890. if (!ret) {
  1891. if (!test_bit(STATUS_READY, &priv->status)) {
  1892. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  1893. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  1894. return -ETIMEDOUT;
  1895. }
  1896. }
  1897. out:
  1898. priv->is_open = 1;
  1899. IWL_DEBUG_MAC80211(priv, "leave\n");
  1900. return 0;
  1901. }
  1902. static void iwl_mac_stop(struct ieee80211_hw *hw)
  1903. {
  1904. struct iwl_priv *priv = hw->priv;
  1905. IWL_DEBUG_MAC80211(priv, "enter\n");
  1906. if (!priv->is_open)
  1907. return;
  1908. priv->is_open = 0;
  1909. if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
  1910. /* stop mac, cancel any scan request and clear
  1911. * RXON_FILTER_ASSOC_MSK BIT
  1912. */
  1913. mutex_lock(&priv->mutex);
  1914. iwl_scan_cancel_timeout(priv, 100);
  1915. mutex_unlock(&priv->mutex);
  1916. }
  1917. iwl_down(priv);
  1918. flush_workqueue(priv->workqueue);
  1919. /* enable interrupts again in order to receive rfkill changes */
  1920. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1921. iwl_enable_interrupts(priv);
  1922. IWL_DEBUG_MAC80211(priv, "leave\n");
  1923. }
  1924. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  1925. {
  1926. struct iwl_priv *priv = hw->priv;
  1927. IWL_DEBUG_MACDUMP(priv, "enter\n");
  1928. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  1929. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  1930. if (iwl_tx_skb(priv, skb))
  1931. dev_kfree_skb_any(skb);
  1932. IWL_DEBUG_MACDUMP(priv, "leave\n");
  1933. return NETDEV_TX_OK;
  1934. }
  1935. void iwl_config_ap(struct iwl_priv *priv)
  1936. {
  1937. int ret = 0;
  1938. unsigned long flags;
  1939. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1940. return;
  1941. /* The following should be done only at AP bring up */
  1942. if (!iwl_is_associated(priv)) {
  1943. /* RXON - unassoc (to set timing command) */
  1944. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1945. iwlcore_commit_rxon(priv);
  1946. /* RXON Timing */
  1947. iwl_setup_rxon_timing(priv);
  1948. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1949. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1950. if (ret)
  1951. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1952. "Attempting to continue.\n");
  1953. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1954. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1955. /* FIXME: what should be the assoc_id for AP? */
  1956. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1957. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1958. priv->staging_rxon.flags |=
  1959. RXON_FLG_SHORT_PREAMBLE_MSK;
  1960. else
  1961. priv->staging_rxon.flags &=
  1962. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1963. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1964. if (priv->assoc_capability &
  1965. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1966. priv->staging_rxon.flags |=
  1967. RXON_FLG_SHORT_SLOT_MSK;
  1968. else
  1969. priv->staging_rxon.flags &=
  1970. ~RXON_FLG_SHORT_SLOT_MSK;
  1971. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1972. priv->staging_rxon.flags &=
  1973. ~RXON_FLG_SHORT_SLOT_MSK;
  1974. }
  1975. /* restore RXON assoc */
  1976. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1977. iwlcore_commit_rxon(priv);
  1978. spin_lock_irqsave(&priv->lock, flags);
  1979. iwl_activate_qos(priv, 1);
  1980. spin_unlock_irqrestore(&priv->lock, flags);
  1981. iwl_rxon_add_station(priv, iwl_bcast_addr, 0);
  1982. }
  1983. iwl_send_beacon_cmd(priv);
  1984. /* FIXME - we need to add code here to detect a totally new
  1985. * configuration, reset the AP, unassoc, rxon timing, assoc,
  1986. * clear sta table, add BCAST sta... */
  1987. }
  1988. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  1989. struct ieee80211_key_conf *keyconf, const u8 *addr,
  1990. u32 iv32, u16 *phase1key)
  1991. {
  1992. struct iwl_priv *priv = hw->priv;
  1993. IWL_DEBUG_MAC80211(priv, "enter\n");
  1994. iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
  1995. IWL_DEBUG_MAC80211(priv, "leave\n");
  1996. }
  1997. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  1998. struct ieee80211_vif *vif,
  1999. struct ieee80211_sta *sta,
  2000. struct ieee80211_key_conf *key)
  2001. {
  2002. struct iwl_priv *priv = hw->priv;
  2003. const u8 *addr;
  2004. int ret;
  2005. u8 sta_id;
  2006. bool is_default_wep_key = false;
  2007. IWL_DEBUG_MAC80211(priv, "enter\n");
  2008. if (priv->cfg->mod_params->sw_crypto) {
  2009. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2010. return -EOPNOTSUPP;
  2011. }
  2012. addr = sta ? sta->addr : iwl_bcast_addr;
  2013. sta_id = iwl_find_station(priv, addr);
  2014. if (sta_id == IWL_INVALID_STATION) {
  2015. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  2016. addr);
  2017. return -EINVAL;
  2018. }
  2019. mutex_lock(&priv->mutex);
  2020. iwl_scan_cancel_timeout(priv, 100);
  2021. mutex_unlock(&priv->mutex);
  2022. /* If we are getting WEP group key and we didn't receive any key mapping
  2023. * so far, we are in legacy wep mode (group key only), otherwise we are
  2024. * in 1X mode.
  2025. * In legacy wep mode, we use another host command to the uCode */
  2026. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  2027. priv->iw_mode != NL80211_IFTYPE_AP) {
  2028. if (cmd == SET_KEY)
  2029. is_default_wep_key = !priv->key_mapping_key;
  2030. else
  2031. is_default_wep_key =
  2032. (key->hw_key_idx == HW_KEY_DEFAULT);
  2033. }
  2034. switch (cmd) {
  2035. case SET_KEY:
  2036. if (is_default_wep_key)
  2037. ret = iwl_set_default_wep_key(priv, key);
  2038. else
  2039. ret = iwl_set_dynamic_key(priv, key, sta_id);
  2040. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2041. break;
  2042. case DISABLE_KEY:
  2043. if (is_default_wep_key)
  2044. ret = iwl_remove_default_wep_key(priv, key);
  2045. else
  2046. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  2047. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2048. break;
  2049. default:
  2050. ret = -EINVAL;
  2051. }
  2052. IWL_DEBUG_MAC80211(priv, "leave\n");
  2053. return ret;
  2054. }
  2055. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  2056. enum ieee80211_ampdu_mlme_action action,
  2057. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2058. {
  2059. struct iwl_priv *priv = hw->priv;
  2060. int ret;
  2061. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2062. sta->addr, tid);
  2063. if (!(priv->cfg->sku & IWL_SKU_N))
  2064. return -EACCES;
  2065. switch (action) {
  2066. case IEEE80211_AMPDU_RX_START:
  2067. IWL_DEBUG_HT(priv, "start Rx\n");
  2068. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  2069. case IEEE80211_AMPDU_RX_STOP:
  2070. IWL_DEBUG_HT(priv, "stop Rx\n");
  2071. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  2072. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2073. return 0;
  2074. else
  2075. return ret;
  2076. case IEEE80211_AMPDU_TX_START:
  2077. IWL_DEBUG_HT(priv, "start Tx\n");
  2078. return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
  2079. case IEEE80211_AMPDU_TX_STOP:
  2080. IWL_DEBUG_HT(priv, "stop Tx\n");
  2081. ret = iwl_tx_agg_stop(priv, sta->addr, tid);
  2082. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2083. return 0;
  2084. else
  2085. return ret;
  2086. default:
  2087. IWL_DEBUG_HT(priv, "unknown\n");
  2088. return -EINVAL;
  2089. break;
  2090. }
  2091. return 0;
  2092. }
  2093. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  2094. struct ieee80211_low_level_stats *stats)
  2095. {
  2096. struct iwl_priv *priv = hw->priv;
  2097. priv = hw->priv;
  2098. IWL_DEBUG_MAC80211(priv, "enter\n");
  2099. IWL_DEBUG_MAC80211(priv, "leave\n");
  2100. return 0;
  2101. }
  2102. /*****************************************************************************
  2103. *
  2104. * sysfs attributes
  2105. *
  2106. *****************************************************************************/
  2107. #ifdef CONFIG_IWLWIFI_DEBUG
  2108. /*
  2109. * The following adds a new attribute to the sysfs representation
  2110. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  2111. * used for controlling the debug level.
  2112. *
  2113. * See the level definitions in iwl for details.
  2114. *
  2115. * The debug_level being managed using sysfs below is a per device debug
  2116. * level that is used instead of the global debug level if it (the per
  2117. * device debug level) is set.
  2118. */
  2119. static ssize_t show_debug_level(struct device *d,
  2120. struct device_attribute *attr, char *buf)
  2121. {
  2122. struct iwl_priv *priv = dev_get_drvdata(d);
  2123. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  2124. }
  2125. static ssize_t store_debug_level(struct device *d,
  2126. struct device_attribute *attr,
  2127. const char *buf, size_t count)
  2128. {
  2129. struct iwl_priv *priv = dev_get_drvdata(d);
  2130. unsigned long val;
  2131. int ret;
  2132. ret = strict_strtoul(buf, 0, &val);
  2133. if (ret)
  2134. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  2135. else {
  2136. priv->debug_level = val;
  2137. if (iwl_alloc_traffic_mem(priv))
  2138. IWL_ERR(priv,
  2139. "Not enough memory to generate traffic log\n");
  2140. }
  2141. return strnlen(buf, count);
  2142. }
  2143. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2144. show_debug_level, store_debug_level);
  2145. #endif /* CONFIG_IWLWIFI_DEBUG */
  2146. static ssize_t show_temperature(struct device *d,
  2147. struct device_attribute *attr, char *buf)
  2148. {
  2149. struct iwl_priv *priv = dev_get_drvdata(d);
  2150. if (!iwl_is_alive(priv))
  2151. return -EAGAIN;
  2152. return sprintf(buf, "%d\n", priv->temperature);
  2153. }
  2154. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2155. static ssize_t show_tx_power(struct device *d,
  2156. struct device_attribute *attr, char *buf)
  2157. {
  2158. struct iwl_priv *priv = dev_get_drvdata(d);
  2159. if (!iwl_is_ready_rf(priv))
  2160. return sprintf(buf, "off\n");
  2161. else
  2162. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2163. }
  2164. static ssize_t store_tx_power(struct device *d,
  2165. struct device_attribute *attr,
  2166. const char *buf, size_t count)
  2167. {
  2168. struct iwl_priv *priv = dev_get_drvdata(d);
  2169. unsigned long val;
  2170. int ret;
  2171. ret = strict_strtoul(buf, 10, &val);
  2172. if (ret)
  2173. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2174. else {
  2175. ret = iwl_set_tx_power(priv, val, false);
  2176. if (ret)
  2177. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  2178. ret);
  2179. else
  2180. ret = count;
  2181. }
  2182. return ret;
  2183. }
  2184. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2185. static ssize_t show_flags(struct device *d,
  2186. struct device_attribute *attr, char *buf)
  2187. {
  2188. struct iwl_priv *priv = dev_get_drvdata(d);
  2189. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  2190. }
  2191. static ssize_t store_flags(struct device *d,
  2192. struct device_attribute *attr,
  2193. const char *buf, size_t count)
  2194. {
  2195. struct iwl_priv *priv = dev_get_drvdata(d);
  2196. unsigned long val;
  2197. u32 flags;
  2198. int ret = strict_strtoul(buf, 0, &val);
  2199. if (ret)
  2200. return ret;
  2201. flags = (u32)val;
  2202. mutex_lock(&priv->mutex);
  2203. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  2204. /* Cancel any currently running scans... */
  2205. if (iwl_scan_cancel_timeout(priv, 100))
  2206. IWL_WARN(priv, "Could not cancel scan.\n");
  2207. else {
  2208. IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
  2209. priv->staging_rxon.flags = cpu_to_le32(flags);
  2210. iwlcore_commit_rxon(priv);
  2211. }
  2212. }
  2213. mutex_unlock(&priv->mutex);
  2214. return count;
  2215. }
  2216. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  2217. static ssize_t show_filter_flags(struct device *d,
  2218. struct device_attribute *attr, char *buf)
  2219. {
  2220. struct iwl_priv *priv = dev_get_drvdata(d);
  2221. return sprintf(buf, "0x%04X\n",
  2222. le32_to_cpu(priv->active_rxon.filter_flags));
  2223. }
  2224. static ssize_t store_filter_flags(struct device *d,
  2225. struct device_attribute *attr,
  2226. const char *buf, size_t count)
  2227. {
  2228. struct iwl_priv *priv = dev_get_drvdata(d);
  2229. unsigned long val;
  2230. u32 filter_flags;
  2231. int ret = strict_strtoul(buf, 0, &val);
  2232. if (ret)
  2233. return ret;
  2234. filter_flags = (u32)val;
  2235. mutex_lock(&priv->mutex);
  2236. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  2237. /* Cancel any currently running scans... */
  2238. if (iwl_scan_cancel_timeout(priv, 100))
  2239. IWL_WARN(priv, "Could not cancel scan.\n");
  2240. else {
  2241. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  2242. "0x%04X\n", filter_flags);
  2243. priv->staging_rxon.filter_flags =
  2244. cpu_to_le32(filter_flags);
  2245. iwlcore_commit_rxon(priv);
  2246. }
  2247. }
  2248. mutex_unlock(&priv->mutex);
  2249. return count;
  2250. }
  2251. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  2252. store_filter_flags);
  2253. static ssize_t show_statistics(struct device *d,
  2254. struct device_attribute *attr, char *buf)
  2255. {
  2256. struct iwl_priv *priv = dev_get_drvdata(d);
  2257. u32 size = sizeof(struct iwl_notif_statistics);
  2258. u32 len = 0, ofs = 0;
  2259. u8 *data = (u8 *)&priv->statistics;
  2260. int rc = 0;
  2261. if (!iwl_is_alive(priv))
  2262. return -EAGAIN;
  2263. mutex_lock(&priv->mutex);
  2264. rc = iwl_send_statistics_request(priv, 0);
  2265. mutex_unlock(&priv->mutex);
  2266. if (rc) {
  2267. len = sprintf(buf,
  2268. "Error sending statistics request: 0x%08X\n", rc);
  2269. return len;
  2270. }
  2271. while (size && (PAGE_SIZE - len)) {
  2272. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2273. PAGE_SIZE - len, 1);
  2274. len = strlen(buf);
  2275. if (PAGE_SIZE - len)
  2276. buf[len++] = '\n';
  2277. ofs += 16;
  2278. size -= min(size, 16U);
  2279. }
  2280. return len;
  2281. }
  2282. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2283. /*****************************************************************************
  2284. *
  2285. * driver setup and teardown
  2286. *
  2287. *****************************************************************************/
  2288. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2289. {
  2290. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2291. init_waitqueue_head(&priv->wait_command_queue);
  2292. INIT_WORK(&priv->up, iwl_bg_up);
  2293. INIT_WORK(&priv->restart, iwl_bg_restart);
  2294. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2295. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2296. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2297. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2298. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2299. iwl_setup_scan_deferred_work(priv);
  2300. if (priv->cfg->ops->lib->setup_deferred_work)
  2301. priv->cfg->ops->lib->setup_deferred_work(priv);
  2302. init_timer(&priv->statistics_periodic);
  2303. priv->statistics_periodic.data = (unsigned long)priv;
  2304. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2305. if (!priv->cfg->use_isr_legacy)
  2306. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2307. iwl_irq_tasklet, (unsigned long)priv);
  2308. else
  2309. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2310. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2311. }
  2312. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2313. {
  2314. if (priv->cfg->ops->lib->cancel_deferred_work)
  2315. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2316. cancel_delayed_work_sync(&priv->init_alive_start);
  2317. cancel_delayed_work(&priv->scan_check);
  2318. cancel_delayed_work(&priv->alive_start);
  2319. cancel_work_sync(&priv->beacon_update);
  2320. del_timer_sync(&priv->statistics_periodic);
  2321. }
  2322. static struct attribute *iwl_sysfs_entries[] = {
  2323. &dev_attr_flags.attr,
  2324. &dev_attr_filter_flags.attr,
  2325. &dev_attr_statistics.attr,
  2326. &dev_attr_temperature.attr,
  2327. &dev_attr_tx_power.attr,
  2328. #ifdef CONFIG_IWLWIFI_DEBUG
  2329. &dev_attr_debug_level.attr,
  2330. #endif
  2331. NULL
  2332. };
  2333. static struct attribute_group iwl_attribute_group = {
  2334. .name = NULL, /* put in device directory */
  2335. .attrs = iwl_sysfs_entries,
  2336. };
  2337. static struct ieee80211_ops iwl_hw_ops = {
  2338. .tx = iwl_mac_tx,
  2339. .start = iwl_mac_start,
  2340. .stop = iwl_mac_stop,
  2341. .add_interface = iwl_mac_add_interface,
  2342. .remove_interface = iwl_mac_remove_interface,
  2343. .config = iwl_mac_config,
  2344. .configure_filter = iwl_configure_filter,
  2345. .set_key = iwl_mac_set_key,
  2346. .update_tkip_key = iwl_mac_update_tkip_key,
  2347. .get_stats = iwl_mac_get_stats,
  2348. .get_tx_stats = iwl_mac_get_tx_stats,
  2349. .conf_tx = iwl_mac_conf_tx,
  2350. .reset_tsf = iwl_mac_reset_tsf,
  2351. .bss_info_changed = iwl_bss_info_changed,
  2352. .ampdu_action = iwl_mac_ampdu_action,
  2353. .hw_scan = iwl_mac_hw_scan
  2354. };
  2355. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2356. {
  2357. int err = 0;
  2358. struct iwl_priv *priv;
  2359. struct ieee80211_hw *hw;
  2360. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2361. unsigned long flags;
  2362. u16 pci_cmd;
  2363. /************************
  2364. * 1. Allocating HW data
  2365. ************************/
  2366. /* Disabling hardware scan means that mac80211 will perform scans
  2367. * "the hard way", rather than using device's scan. */
  2368. if (cfg->mod_params->disable_hw_scan) {
  2369. if (iwl_debug_level & IWL_DL_INFO)
  2370. dev_printk(KERN_DEBUG, &(pdev->dev),
  2371. "Disabling hw_scan\n");
  2372. iwl_hw_ops.hw_scan = NULL;
  2373. }
  2374. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2375. if (!hw) {
  2376. err = -ENOMEM;
  2377. goto out;
  2378. }
  2379. priv = hw->priv;
  2380. /* At this point both hw and priv are allocated. */
  2381. SET_IEEE80211_DEV(hw, &pdev->dev);
  2382. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2383. priv->cfg = cfg;
  2384. priv->pci_dev = pdev;
  2385. priv->inta_mask = CSR_INI_SET_MASK;
  2386. #ifdef CONFIG_IWLWIFI_DEBUG
  2387. atomic_set(&priv->restrict_refcnt, 0);
  2388. #endif
  2389. if (iwl_alloc_traffic_mem(priv))
  2390. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  2391. /**************************
  2392. * 2. Initializing PCI bus
  2393. **************************/
  2394. if (pci_enable_device(pdev)) {
  2395. err = -ENODEV;
  2396. goto out_ieee80211_free_hw;
  2397. }
  2398. pci_set_master(pdev);
  2399. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2400. if (!err)
  2401. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2402. if (err) {
  2403. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2404. if (!err)
  2405. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2406. /* both attempts failed: */
  2407. if (err) {
  2408. IWL_WARN(priv, "No suitable DMA available.\n");
  2409. goto out_pci_disable_device;
  2410. }
  2411. }
  2412. err = pci_request_regions(pdev, DRV_NAME);
  2413. if (err)
  2414. goto out_pci_disable_device;
  2415. pci_set_drvdata(pdev, priv);
  2416. /***********************
  2417. * 3. Read REV register
  2418. ***********************/
  2419. priv->hw_base = pci_iomap(pdev, 0, 0);
  2420. if (!priv->hw_base) {
  2421. err = -ENODEV;
  2422. goto out_pci_release_regions;
  2423. }
  2424. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2425. (unsigned long long) pci_resource_len(pdev, 0));
  2426. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2427. /* this spin lock will be used in apm_ops.init and EEPROM access
  2428. * we should init now
  2429. */
  2430. spin_lock_init(&priv->reg_lock);
  2431. iwl_hw_detect(priv);
  2432. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
  2433. priv->cfg->name, priv->hw_rev);
  2434. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2435. * PCI Tx retries from interfering with C3 CPU state */
  2436. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2437. iwl_prepare_card_hw(priv);
  2438. if (!priv->hw_ready) {
  2439. IWL_WARN(priv, "Failed, HW not ready\n");
  2440. goto out_iounmap;
  2441. }
  2442. /* amp init */
  2443. err = priv->cfg->ops->lib->apm_ops.init(priv);
  2444. if (err < 0) {
  2445. IWL_ERR(priv, "Failed to init APMG\n");
  2446. goto out_iounmap;
  2447. }
  2448. /*****************
  2449. * 4. Read EEPROM
  2450. *****************/
  2451. /* Read the EEPROM */
  2452. err = iwl_eeprom_init(priv);
  2453. if (err) {
  2454. IWL_ERR(priv, "Unable to init EEPROM\n");
  2455. goto out_iounmap;
  2456. }
  2457. err = iwl_eeprom_check_version(priv);
  2458. if (err)
  2459. goto out_free_eeprom;
  2460. /* extract MAC Address */
  2461. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2462. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2463. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2464. /************************
  2465. * 5. Setup HW constants
  2466. ************************/
  2467. if (iwl_set_hw_params(priv)) {
  2468. IWL_ERR(priv, "failed to set hw parameters\n");
  2469. goto out_free_eeprom;
  2470. }
  2471. /*******************
  2472. * 6. Setup priv
  2473. *******************/
  2474. err = iwl_init_drv(priv);
  2475. if (err)
  2476. goto out_free_eeprom;
  2477. /* At this point both hw and priv are initialized. */
  2478. /********************
  2479. * 7. Setup services
  2480. ********************/
  2481. spin_lock_irqsave(&priv->lock, flags);
  2482. iwl_disable_interrupts(priv);
  2483. spin_unlock_irqrestore(&priv->lock, flags);
  2484. pci_enable_msi(priv->pci_dev);
  2485. iwl_alloc_isr_ict(priv);
  2486. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  2487. IRQF_SHARED, DRV_NAME, priv);
  2488. if (err) {
  2489. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  2490. goto out_disable_msi;
  2491. }
  2492. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  2493. if (err) {
  2494. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  2495. goto out_free_irq;
  2496. }
  2497. iwl_setup_deferred_work(priv);
  2498. iwl_setup_rx_handlers(priv);
  2499. /**********************************
  2500. * 8. Setup and register mac80211
  2501. **********************************/
  2502. /* enable interrupts if needed: hw bug w/a */
  2503. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  2504. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  2505. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  2506. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  2507. }
  2508. iwl_enable_interrupts(priv);
  2509. err = iwl_setup_mac(priv);
  2510. if (err)
  2511. goto out_remove_sysfs;
  2512. err = iwl_dbgfs_register(priv, DRV_NAME);
  2513. if (err)
  2514. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  2515. /* If platform's RF_KILL switch is NOT set to KILL */
  2516. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2517. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2518. else
  2519. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2520. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  2521. test_bit(STATUS_RF_KILL_HW, &priv->status));
  2522. iwl_power_initialize(priv);
  2523. iwl_tt_initialize(priv);
  2524. return 0;
  2525. out_remove_sysfs:
  2526. destroy_workqueue(priv->workqueue);
  2527. priv->workqueue = NULL;
  2528. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2529. out_free_irq:
  2530. free_irq(priv->pci_dev->irq, priv);
  2531. iwl_free_isr_ict(priv);
  2532. out_disable_msi:
  2533. pci_disable_msi(priv->pci_dev);
  2534. iwl_uninit_drv(priv);
  2535. out_free_eeprom:
  2536. iwl_eeprom_free(priv);
  2537. out_iounmap:
  2538. pci_iounmap(pdev, priv->hw_base);
  2539. out_pci_release_regions:
  2540. pci_set_drvdata(pdev, NULL);
  2541. pci_release_regions(pdev);
  2542. out_pci_disable_device:
  2543. pci_disable_device(pdev);
  2544. out_ieee80211_free_hw:
  2545. iwl_free_traffic_mem(priv);
  2546. ieee80211_free_hw(priv->hw);
  2547. out:
  2548. return err;
  2549. }
  2550. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  2551. {
  2552. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2553. unsigned long flags;
  2554. if (!priv)
  2555. return;
  2556. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  2557. iwl_dbgfs_unregister(priv);
  2558. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2559. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  2560. * to be called and iwl_down since we are removing the device
  2561. * we need to set STATUS_EXIT_PENDING bit.
  2562. */
  2563. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2564. if (priv->mac80211_registered) {
  2565. ieee80211_unregister_hw(priv->hw);
  2566. priv->mac80211_registered = 0;
  2567. } else {
  2568. iwl_down(priv);
  2569. }
  2570. iwl_tt_exit(priv);
  2571. /* make sure we flush any pending irq or
  2572. * tasklet for the driver
  2573. */
  2574. spin_lock_irqsave(&priv->lock, flags);
  2575. iwl_disable_interrupts(priv);
  2576. spin_unlock_irqrestore(&priv->lock, flags);
  2577. iwl_synchronize_irq(priv);
  2578. iwl_dealloc_ucode_pci(priv);
  2579. if (priv->rxq.bd)
  2580. iwl_rx_queue_free(priv, &priv->rxq);
  2581. iwl_hw_txq_ctx_free(priv);
  2582. iwl_clear_stations_table(priv);
  2583. iwl_eeprom_free(priv);
  2584. /*netif_stop_queue(dev); */
  2585. flush_workqueue(priv->workqueue);
  2586. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  2587. * priv->workqueue... so we can't take down the workqueue
  2588. * until now... */
  2589. destroy_workqueue(priv->workqueue);
  2590. priv->workqueue = NULL;
  2591. iwl_free_traffic_mem(priv);
  2592. free_irq(priv->pci_dev->irq, priv);
  2593. pci_disable_msi(priv->pci_dev);
  2594. pci_iounmap(pdev, priv->hw_base);
  2595. pci_release_regions(pdev);
  2596. pci_disable_device(pdev);
  2597. pci_set_drvdata(pdev, NULL);
  2598. iwl_uninit_drv(priv);
  2599. iwl_free_isr_ict(priv);
  2600. if (priv->ibss_beacon)
  2601. dev_kfree_skb(priv->ibss_beacon);
  2602. ieee80211_free_hw(priv->hw);
  2603. }
  2604. /*****************************************************************************
  2605. *
  2606. * driver and module entry point
  2607. *
  2608. *****************************************************************************/
  2609. /* Hardware specific file defines the PCI IDs table for that hardware module */
  2610. static struct pci_device_id iwl_hw_card_ids[] = {
  2611. #ifdef CONFIG_IWL4965
  2612. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  2613. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  2614. #endif /* CONFIG_IWL4965 */
  2615. #ifdef CONFIG_IWL5000
  2616. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
  2617. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
  2618. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
  2619. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
  2620. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
  2621. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
  2622. {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
  2623. {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
  2624. {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
  2625. {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
  2626. /* 5350 WiFi/WiMax */
  2627. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
  2628. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
  2629. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
  2630. /* 5150 Wifi/WiMax */
  2631. {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
  2632. {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
  2633. /* 6000/6050 Series */
  2634. {IWL_PCI_DEVICE(0x008D, PCI_ANY_ID, iwl6000h_2agn_cfg)},
  2635. {IWL_PCI_DEVICE(0x008E, PCI_ANY_ID, iwl6000h_2agn_cfg)},
  2636. {IWL_PCI_DEVICE(0x422B, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2637. {IWL_PCI_DEVICE(0x422C, PCI_ANY_ID, iwl6000i_2agn_cfg)},
  2638. {IWL_PCI_DEVICE(0x4238, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2639. {IWL_PCI_DEVICE(0x4239, PCI_ANY_ID, iwl6000i_2agn_cfg)},
  2640. {IWL_PCI_DEVICE(0x0086, PCI_ANY_ID, iwl6050_3agn_cfg)},
  2641. {IWL_PCI_DEVICE(0x0087, PCI_ANY_ID, iwl6050_2agn_cfg)},
  2642. {IWL_PCI_DEVICE(0x0088, PCI_ANY_ID, iwl6050_3agn_cfg)},
  2643. {IWL_PCI_DEVICE(0x0089, PCI_ANY_ID, iwl6050_2agn_cfg)},
  2644. /* 1000 Series WiFi */
  2645. {IWL_PCI_DEVICE(0x0083, PCI_ANY_ID, iwl1000_bgn_cfg)},
  2646. {IWL_PCI_DEVICE(0x0084, PCI_ANY_ID, iwl1000_bgn_cfg)},
  2647. #endif /* CONFIG_IWL5000 */
  2648. {0}
  2649. };
  2650. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  2651. static struct pci_driver iwl_driver = {
  2652. .name = DRV_NAME,
  2653. .id_table = iwl_hw_card_ids,
  2654. .probe = iwl_pci_probe,
  2655. .remove = __devexit_p(iwl_pci_remove),
  2656. #ifdef CONFIG_PM
  2657. .suspend = iwl_pci_suspend,
  2658. .resume = iwl_pci_resume,
  2659. #endif
  2660. };
  2661. static int __init iwl_init(void)
  2662. {
  2663. int ret;
  2664. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  2665. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  2666. ret = iwlagn_rate_control_register();
  2667. if (ret) {
  2668. printk(KERN_ERR DRV_NAME
  2669. "Unable to register rate control algorithm: %d\n", ret);
  2670. return ret;
  2671. }
  2672. ret = pci_register_driver(&iwl_driver);
  2673. if (ret) {
  2674. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  2675. goto error_register;
  2676. }
  2677. return ret;
  2678. error_register:
  2679. iwlagn_rate_control_unregister();
  2680. return ret;
  2681. }
  2682. static void __exit iwl_exit(void)
  2683. {
  2684. pci_unregister_driver(&iwl_driver);
  2685. iwlagn_rate_control_unregister();
  2686. }
  2687. module_exit(iwl_exit);
  2688. module_init(iwl_init);
  2689. #ifdef CONFIG_IWLWIFI_DEBUG
  2690. module_param_named(debug50, iwl_debug_level, uint, 0444);
  2691. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  2692. module_param_named(debug, iwl_debug_level, uint, 0644);
  2693. MODULE_PARM_DESC(debug, "debug output mask");
  2694. #endif