ci13xxx_udc.c 75 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105
  1. /*
  2. * ci13xxx_udc.c - MIPS USB IP core family device controller
  3. *
  4. * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5. *
  6. * Author: David Lopo
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. /*
  13. * Description: MIPS USB IP core family device controller
  14. * Currently it only supports IP part number CI13412
  15. *
  16. * This driver is composed of several blocks:
  17. * - HW: hardware interface
  18. * - DBG: debug facilities (optional)
  19. * - UTIL: utilities
  20. * - ISR: interrupts handling
  21. * - ENDPT: endpoint operations (Gadget API)
  22. * - GADGET: gadget operations (Gadget API)
  23. * - BUS: bus glue code, bus abstraction layer
  24. *
  25. * Compile Options
  26. * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
  27. * - STALL_IN: non-empty bulk-in pipes cannot be halted
  28. * if defined mass storage compliance succeeds but with warnings
  29. * => case 4: Hi > Dn
  30. * => case 5: Hi > Di
  31. * => case 8: Hi <> Do
  32. * if undefined usbtest 13 fails
  33. * - TRACE: enable function tracing (depends on DEBUG)
  34. *
  35. * Main Features
  36. * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
  37. * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
  38. * - Normal & LPM support
  39. *
  40. * USBTEST Report
  41. * - OK: 0-12, 13 (STALL_IN defined) & 14
  42. * - Not Supported: 15 & 16 (ISO)
  43. *
  44. * TODO List
  45. * - OTG
  46. * - Isochronous & Interrupt Traffic
  47. * - Handle requests which spawns into several TDs
  48. * - GET_STATUS(device) - always reports 0
  49. * - Gadget API (majority of optional features)
  50. * - Suspend & Remote Wakeup
  51. */
  52. #include <linux/delay.h>
  53. #include <linux/device.h>
  54. #include <linux/dmapool.h>
  55. #include <linux/dma-mapping.h>
  56. #include <linux/init.h>
  57. #include <linux/platform_device.h>
  58. #include <linux/module.h>
  59. #include <linux/interrupt.h>
  60. #include <linux/io.h>
  61. #include <linux/irq.h>
  62. #include <linux/kernel.h>
  63. #include <linux/slab.h>
  64. #include <linux/pm_runtime.h>
  65. #include <linux/usb/ch9.h>
  66. #include <linux/usb/gadget.h>
  67. #include <linux/usb/otg.h>
  68. #include "ci13xxx_udc.h"
  69. /******************************************************************************
  70. * DEFINE
  71. *****************************************************************************/
  72. #define DMA_ADDR_INVALID (~(dma_addr_t)0)
  73. /* control endpoint description */
  74. static const struct usb_endpoint_descriptor
  75. ctrl_endpt_out_desc = {
  76. .bLength = USB_DT_ENDPOINT_SIZE,
  77. .bDescriptorType = USB_DT_ENDPOINT,
  78. .bEndpointAddress = USB_DIR_OUT,
  79. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  80. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  81. };
  82. static const struct usb_endpoint_descriptor
  83. ctrl_endpt_in_desc = {
  84. .bLength = USB_DT_ENDPOINT_SIZE,
  85. .bDescriptorType = USB_DT_ENDPOINT,
  86. .bEndpointAddress = USB_DIR_IN,
  87. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  88. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  89. };
  90. /* UDC descriptor */
  91. static struct ci13xxx *_udc;
  92. /* Interrupt statistics */
  93. #define ISR_MASK 0x1F
  94. static struct {
  95. u32 test;
  96. u32 ui;
  97. u32 uei;
  98. u32 pci;
  99. u32 uri;
  100. u32 sli;
  101. u32 none;
  102. struct {
  103. u32 cnt;
  104. u32 buf[ISR_MASK+1];
  105. u32 idx;
  106. } hndl;
  107. } isr_statistics;
  108. /**
  109. * ffs_nr: find first (least significant) bit set
  110. * @x: the word to search
  111. *
  112. * This function returns bit number (instead of position)
  113. */
  114. static int ffs_nr(u32 x)
  115. {
  116. int n = ffs(x);
  117. return n ? n-1 : 32;
  118. }
  119. /******************************************************************************
  120. * HW block
  121. *****************************************************************************/
  122. /* MSM specific */
  123. #define ABS_AHBBURST (0x0090UL)
  124. #define ABS_AHBMODE (0x0098UL)
  125. /* UDC register map */
  126. static uintptr_t ci_regs_nolpm[] = {
  127. [CAP_CAPLENGTH] = 0x000UL,
  128. [CAP_HCCPARAMS] = 0x008UL,
  129. [CAP_DCCPARAMS] = 0x024UL,
  130. [CAP_TESTMODE] = 0x038UL,
  131. [OP_USBCMD] = 0x000UL,
  132. [OP_USBSTS] = 0x004UL,
  133. [OP_USBINTR] = 0x008UL,
  134. [OP_DEVICEADDR] = 0x014UL,
  135. [OP_ENDPTLISTADDR] = 0x018UL,
  136. [OP_PORTSC] = 0x044UL,
  137. [OP_DEVLC] = 0x084UL,
  138. [OP_USBMODE] = 0x068UL,
  139. [OP_ENDPTSETUPSTAT] = 0x06CUL,
  140. [OP_ENDPTPRIME] = 0x070UL,
  141. [OP_ENDPTFLUSH] = 0x074UL,
  142. [OP_ENDPTSTAT] = 0x078UL,
  143. [OP_ENDPTCOMPLETE] = 0x07CUL,
  144. [OP_ENDPTCTRL] = 0x080UL,
  145. };
  146. static uintptr_t ci_regs_lpm[] = {
  147. [CAP_CAPLENGTH] = 0x000UL,
  148. [CAP_HCCPARAMS] = 0x008UL,
  149. [CAP_DCCPARAMS] = 0x024UL,
  150. [CAP_TESTMODE] = 0x0FCUL,
  151. [OP_USBCMD] = 0x000UL,
  152. [OP_USBSTS] = 0x004UL,
  153. [OP_USBINTR] = 0x008UL,
  154. [OP_DEVICEADDR] = 0x014UL,
  155. [OP_ENDPTLISTADDR] = 0x018UL,
  156. [OP_PORTSC] = 0x044UL,
  157. [OP_DEVLC] = 0x084UL,
  158. [OP_USBMODE] = 0x0C8UL,
  159. [OP_ENDPTSETUPSTAT] = 0x0D8UL,
  160. [OP_ENDPTPRIME] = 0x0DCUL,
  161. [OP_ENDPTFLUSH] = 0x0E0UL,
  162. [OP_ENDPTSTAT] = 0x0E4UL,
  163. [OP_ENDPTCOMPLETE] = 0x0E8UL,
  164. [OP_ENDPTCTRL] = 0x0ECUL,
  165. };
  166. static int hw_alloc_regmap(struct ci13xxx *udc, bool is_lpm)
  167. {
  168. int i;
  169. kfree(udc->hw_bank.regmap);
  170. udc->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
  171. GFP_KERNEL);
  172. if (!udc->hw_bank.regmap)
  173. return -ENOMEM;
  174. for (i = 0; i < OP_ENDPTCTRL; i++)
  175. udc->hw_bank.regmap[i] =
  176. (i <= CAP_LAST ? udc->hw_bank.cap : udc->hw_bank.op) +
  177. (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
  178. for (; i <= OP_LAST; i++)
  179. udc->hw_bank.regmap[i] = udc->hw_bank.op +
  180. 4 * (i - OP_ENDPTCTRL) +
  181. (is_lpm
  182. ? ci_regs_lpm[OP_ENDPTCTRL]
  183. : ci_regs_nolpm[OP_ENDPTCTRL]);
  184. return 0;
  185. }
  186. /**
  187. * hw_ep_bit: calculates the bit number
  188. * @num: endpoint number
  189. * @dir: endpoint direction
  190. *
  191. * This function returns bit number
  192. */
  193. static inline int hw_ep_bit(int num, int dir)
  194. {
  195. return num + (dir ? 16 : 0);
  196. }
  197. static int ep_to_bit(struct ci13xxx *udc, int n)
  198. {
  199. int fill = 16 - udc->hw_ep_max / 2;
  200. if (n >= udc->hw_ep_max / 2)
  201. n += fill;
  202. return n;
  203. }
  204. /**
  205. * hw_read: reads from a hw register
  206. * @reg: register index
  207. * @mask: bitfield mask
  208. *
  209. * This function returns register contents
  210. */
  211. static u32 hw_read(struct ci13xxx *udc, enum ci13xxx_regs reg, u32 mask)
  212. {
  213. return ioread32(udc->hw_bank.regmap[reg]) & mask;
  214. }
  215. /**
  216. * hw_write: writes to a hw register
  217. * @reg: register index
  218. * @mask: bitfield mask
  219. * @data: new value
  220. */
  221. static void hw_write(struct ci13xxx *udc, enum ci13xxx_regs reg, u32 mask,
  222. u32 data)
  223. {
  224. if (~mask)
  225. data = (ioread32(udc->hw_bank.regmap[reg]) & ~mask)
  226. | (data & mask);
  227. iowrite32(data, udc->hw_bank.regmap[reg]);
  228. }
  229. /**
  230. * hw_test_and_clear: tests & clears a hw register
  231. * @reg: register index
  232. * @mask: bitfield mask
  233. *
  234. * This function returns register contents
  235. */
  236. static u32 hw_test_and_clear(struct ci13xxx *udc, enum ci13xxx_regs reg,
  237. u32 mask)
  238. {
  239. u32 val = ioread32(udc->hw_bank.regmap[reg]) & mask;
  240. iowrite32(val, udc->hw_bank.regmap[reg]);
  241. return val;
  242. }
  243. /**
  244. * hw_test_and_write: tests & writes a hw register
  245. * @reg: register index
  246. * @mask: bitfield mask
  247. * @data: new value
  248. *
  249. * This function returns register contents
  250. */
  251. static u32 hw_test_and_write(struct ci13xxx *udc, enum ci13xxx_regs reg,
  252. u32 mask, u32 data)
  253. {
  254. u32 val = hw_read(udc, reg, ~0);
  255. hw_write(udc, reg, mask, data);
  256. return (val & mask) >> ffs_nr(mask);
  257. }
  258. static int hw_device_init(struct ci13xxx *udc, void __iomem *base,
  259. uintptr_t cap_offset)
  260. {
  261. u32 reg;
  262. /* bank is a module variable */
  263. udc->hw_bank.abs = base;
  264. udc->hw_bank.cap = udc->hw_bank.abs;
  265. udc->hw_bank.cap += cap_offset;
  266. udc->hw_bank.op = udc->hw_bank.cap + ioread8(udc->hw_bank.cap);
  267. hw_alloc_regmap(udc, false);
  268. reg = hw_read(udc, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
  269. ffs_nr(HCCPARAMS_LEN);
  270. udc->hw_bank.lpm = reg;
  271. hw_alloc_regmap(udc, !!reg);
  272. udc->hw_bank.size = udc->hw_bank.op - udc->hw_bank.abs;
  273. udc->hw_bank.size += OP_LAST;
  274. udc->hw_bank.size /= sizeof(u32);
  275. reg = hw_read(udc, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
  276. ffs_nr(DCCPARAMS_DEN);
  277. udc->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
  278. if (udc->hw_ep_max == 0 || udc->hw_ep_max > ENDPT_MAX)
  279. return -ENODEV;
  280. /* setup lock mode ? */
  281. /* ENDPTSETUPSTAT is '0' by default */
  282. /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
  283. return 0;
  284. }
  285. /**
  286. * hw_device_reset: resets chip (execute without interruption)
  287. * @base: register base address
  288. *
  289. * This function returns an error code
  290. */
  291. static int hw_device_reset(struct ci13xxx *udc)
  292. {
  293. /* should flush & stop before reset */
  294. hw_write(udc, OP_ENDPTFLUSH, ~0, ~0);
  295. hw_write(udc, OP_USBCMD, USBCMD_RS, 0);
  296. hw_write(udc, OP_USBCMD, USBCMD_RST, USBCMD_RST);
  297. while (hw_read(udc, OP_USBCMD, USBCMD_RST))
  298. udelay(10); /* not RTOS friendly */
  299. if (udc->udc_driver->notify_event)
  300. udc->udc_driver->notify_event(udc,
  301. CI13XXX_CONTROLLER_RESET_EVENT);
  302. if (udc->udc_driver->flags & CI13XXX_DISABLE_STREAMING)
  303. hw_write(udc, OP_USBMODE, USBMODE_SDIS, USBMODE_SDIS);
  304. /* USBMODE should be configured step by step */
  305. hw_write(udc, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
  306. hw_write(udc, OP_USBMODE, USBMODE_CM, USBMODE_CM_DEVICE);
  307. /* HW >= 2.3 */
  308. hw_write(udc, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
  309. if (hw_read(udc, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DEVICE) {
  310. pr_err("cannot enter in device mode");
  311. pr_err("lpm = %i", udc->hw_bank.lpm);
  312. return -ENODEV;
  313. }
  314. return 0;
  315. }
  316. /**
  317. * hw_device_state: enables/disables interrupts & starts/stops device (execute
  318. * without interruption)
  319. * @dma: 0 => disable, !0 => enable and set dma engine
  320. *
  321. * This function returns an error code
  322. */
  323. static int hw_device_state(struct ci13xxx *udc, u32 dma)
  324. {
  325. if (dma) {
  326. hw_write(udc, OP_ENDPTLISTADDR, ~0, dma);
  327. /* interrupt, error, port change, reset, sleep/suspend */
  328. hw_write(udc, OP_USBINTR, ~0,
  329. USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
  330. hw_write(udc, OP_USBCMD, USBCMD_RS, USBCMD_RS);
  331. } else {
  332. hw_write(udc, OP_USBCMD, USBCMD_RS, 0);
  333. hw_write(udc, OP_USBINTR, ~0, 0);
  334. }
  335. return 0;
  336. }
  337. /**
  338. * hw_ep_flush: flush endpoint fifo (execute without interruption)
  339. * @num: endpoint number
  340. * @dir: endpoint direction
  341. *
  342. * This function returns an error code
  343. */
  344. static int hw_ep_flush(struct ci13xxx *udc, int num, int dir)
  345. {
  346. int n = hw_ep_bit(num, dir);
  347. do {
  348. /* flush any pending transfer */
  349. hw_write(udc, OP_ENDPTFLUSH, BIT(n), BIT(n));
  350. while (hw_read(udc, OP_ENDPTFLUSH, BIT(n)))
  351. cpu_relax();
  352. } while (hw_read(udc, OP_ENDPTSTAT, BIT(n)));
  353. return 0;
  354. }
  355. /**
  356. * hw_ep_disable: disables endpoint (execute without interruption)
  357. * @num: endpoint number
  358. * @dir: endpoint direction
  359. *
  360. * This function returns an error code
  361. */
  362. static int hw_ep_disable(struct ci13xxx *udc, int num, int dir)
  363. {
  364. hw_ep_flush(udc, num, dir);
  365. hw_write(udc, OP_ENDPTCTRL + num,
  366. dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
  367. return 0;
  368. }
  369. /**
  370. * hw_ep_enable: enables endpoint (execute without interruption)
  371. * @num: endpoint number
  372. * @dir: endpoint direction
  373. * @type: endpoint type
  374. *
  375. * This function returns an error code
  376. */
  377. static int hw_ep_enable(struct ci13xxx *udc, int num, int dir, int type)
  378. {
  379. u32 mask, data;
  380. if (dir) {
  381. mask = ENDPTCTRL_TXT; /* type */
  382. data = type << ffs_nr(mask);
  383. mask |= ENDPTCTRL_TXS; /* unstall */
  384. mask |= ENDPTCTRL_TXR; /* reset data toggle */
  385. data |= ENDPTCTRL_TXR;
  386. mask |= ENDPTCTRL_TXE; /* enable */
  387. data |= ENDPTCTRL_TXE;
  388. } else {
  389. mask = ENDPTCTRL_RXT; /* type */
  390. data = type << ffs_nr(mask);
  391. mask |= ENDPTCTRL_RXS; /* unstall */
  392. mask |= ENDPTCTRL_RXR; /* reset data toggle */
  393. data |= ENDPTCTRL_RXR;
  394. mask |= ENDPTCTRL_RXE; /* enable */
  395. data |= ENDPTCTRL_RXE;
  396. }
  397. hw_write(udc, OP_ENDPTCTRL + num, mask, data);
  398. return 0;
  399. }
  400. /**
  401. * hw_ep_get_halt: return endpoint halt status
  402. * @num: endpoint number
  403. * @dir: endpoint direction
  404. *
  405. * This function returns 1 if endpoint halted
  406. */
  407. static int hw_ep_get_halt(struct ci13xxx *udc, int num, int dir)
  408. {
  409. u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  410. return hw_read(udc, OP_ENDPTCTRL + num, mask) ? 1 : 0;
  411. }
  412. /**
  413. * hw_test_and_clear_setup_status: test & clear setup status (execute without
  414. * interruption)
  415. * @n: endpoint number
  416. *
  417. * This function returns setup status
  418. */
  419. static int hw_test_and_clear_setup_status(struct ci13xxx *udc, int n)
  420. {
  421. n = ep_to_bit(udc, n);
  422. return hw_test_and_clear(udc, OP_ENDPTSETUPSTAT, BIT(n));
  423. }
  424. /**
  425. * hw_ep_prime: primes endpoint (execute without interruption)
  426. * @num: endpoint number
  427. * @dir: endpoint direction
  428. * @is_ctrl: true if control endpoint
  429. *
  430. * This function returns an error code
  431. */
  432. static int hw_ep_prime(struct ci13xxx *udc, int num, int dir, int is_ctrl)
  433. {
  434. int n = hw_ep_bit(num, dir);
  435. if (is_ctrl && dir == RX && hw_read(udc, OP_ENDPTSETUPSTAT, BIT(num)))
  436. return -EAGAIN;
  437. hw_write(udc, OP_ENDPTPRIME, BIT(n), BIT(n));
  438. while (hw_read(udc, OP_ENDPTPRIME, BIT(n)))
  439. cpu_relax();
  440. if (is_ctrl && dir == RX && hw_read(udc, OP_ENDPTSETUPSTAT, BIT(num)))
  441. return -EAGAIN;
  442. /* status shoult be tested according with manual but it doesn't work */
  443. return 0;
  444. }
  445. /**
  446. * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
  447. * without interruption)
  448. * @num: endpoint number
  449. * @dir: endpoint direction
  450. * @value: true => stall, false => unstall
  451. *
  452. * This function returns an error code
  453. */
  454. static int hw_ep_set_halt(struct ci13xxx *udc, int num, int dir, int value)
  455. {
  456. if (value != 0 && value != 1)
  457. return -EINVAL;
  458. do {
  459. enum ci13xxx_regs reg = OP_ENDPTCTRL + num;
  460. u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  461. u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
  462. /* data toggle - reserved for EP0 but it's in ESS */
  463. hw_write(udc, reg, mask_xs|mask_xr,
  464. value ? mask_xs : mask_xr);
  465. } while (value != hw_ep_get_halt(udc, num, dir));
  466. return 0;
  467. }
  468. /**
  469. * hw_intr_clear: disables interrupt & clears interrupt status (execute without
  470. * interruption)
  471. * @n: interrupt bit
  472. *
  473. * This function returns an error code
  474. */
  475. static int hw_intr_clear(struct ci13xxx *udc, int n)
  476. {
  477. if (n >= REG_BITS)
  478. return -EINVAL;
  479. hw_write(udc, OP_USBINTR, BIT(n), 0);
  480. hw_write(udc, OP_USBSTS, BIT(n), BIT(n));
  481. return 0;
  482. }
  483. /**
  484. * hw_intr_force: enables interrupt & forces interrupt status (execute without
  485. * interruption)
  486. * @n: interrupt bit
  487. *
  488. * This function returns an error code
  489. */
  490. static int hw_intr_force(struct ci13xxx *udc, int n)
  491. {
  492. if (n >= REG_BITS)
  493. return -EINVAL;
  494. hw_write(udc, CAP_TESTMODE, TESTMODE_FORCE, TESTMODE_FORCE);
  495. hw_write(udc, OP_USBINTR, BIT(n), BIT(n));
  496. hw_write(udc, OP_USBSTS, BIT(n), BIT(n));
  497. hw_write(udc, CAP_TESTMODE, TESTMODE_FORCE, 0);
  498. return 0;
  499. }
  500. /**
  501. * hw_is_port_high_speed: test if port is high speed
  502. *
  503. * This function returns true if high speed port
  504. */
  505. static int hw_port_is_high_speed(struct ci13xxx *udc)
  506. {
  507. return udc->hw_bank.lpm ? hw_read(udc, OP_DEVLC, DEVLC_PSPD) :
  508. hw_read(udc, OP_PORTSC, PORTSC_HSP);
  509. }
  510. /**
  511. * hw_port_test_get: reads port test mode value
  512. *
  513. * This function returns port test mode value
  514. */
  515. static u8 hw_port_test_get(struct ci13xxx *udc)
  516. {
  517. return hw_read(udc, OP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
  518. }
  519. /**
  520. * hw_port_test_set: writes port test mode (execute without interruption)
  521. * @mode: new value
  522. *
  523. * This function returns an error code
  524. */
  525. static int hw_port_test_set(struct ci13xxx *udc, u8 mode)
  526. {
  527. const u8 TEST_MODE_MAX = 7;
  528. if (mode > TEST_MODE_MAX)
  529. return -EINVAL;
  530. hw_write(udc, OP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
  531. return 0;
  532. }
  533. /**
  534. * hw_read_intr_enable: returns interrupt enable register
  535. *
  536. * This function returns register data
  537. */
  538. static u32 hw_read_intr_enable(struct ci13xxx *udc)
  539. {
  540. return hw_read(udc, OP_USBINTR, ~0);
  541. }
  542. /**
  543. * hw_read_intr_status: returns interrupt status register
  544. *
  545. * This function returns register data
  546. */
  547. static u32 hw_read_intr_status(struct ci13xxx *udc)
  548. {
  549. return hw_read(udc, OP_USBSTS, ~0);
  550. }
  551. /**
  552. * hw_register_read: reads all device registers (execute without interruption)
  553. * @buf: destination buffer
  554. * @size: buffer size
  555. *
  556. * This function returns number of registers read
  557. */
  558. static size_t hw_register_read(struct ci13xxx *udc, u32 *buf, size_t size)
  559. {
  560. unsigned i;
  561. if (size > udc->hw_bank.size)
  562. size = udc->hw_bank.size;
  563. for (i = 0; i < size; i++)
  564. buf[i] = hw_read(udc, i * sizeof(u32), ~0);
  565. return size;
  566. }
  567. /**
  568. * hw_register_write: writes to register
  569. * @addr: register address
  570. * @data: register value
  571. *
  572. * This function returns an error code
  573. */
  574. static int hw_register_write(struct ci13xxx *udc, u16 addr, u32 data)
  575. {
  576. /* align */
  577. addr /= sizeof(u32);
  578. if (addr >= udc->hw_bank.size)
  579. return -EINVAL;
  580. /* align */
  581. addr *= sizeof(u32);
  582. hw_write(udc, addr, ~0, data);
  583. return 0;
  584. }
  585. /**
  586. * hw_test_and_clear_complete: test & clear complete status (execute without
  587. * interruption)
  588. * @n: endpoint number
  589. *
  590. * This function returns complete status
  591. */
  592. static int hw_test_and_clear_complete(struct ci13xxx *udc, int n)
  593. {
  594. n = ep_to_bit(udc, n);
  595. return hw_test_and_clear(udc, OP_ENDPTCOMPLETE, BIT(n));
  596. }
  597. /**
  598. * hw_test_and_clear_intr_active: test & clear active interrupts (execute
  599. * without interruption)
  600. *
  601. * This function returns active interrutps
  602. */
  603. static u32 hw_test_and_clear_intr_active(struct ci13xxx *udc)
  604. {
  605. u32 reg = hw_read_intr_status(udc) & hw_read_intr_enable(udc);
  606. hw_write(udc, OP_USBSTS, ~0, reg);
  607. return reg;
  608. }
  609. /**
  610. * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
  611. * interruption)
  612. *
  613. * This function returns guard value
  614. */
  615. static int hw_test_and_clear_setup_guard(struct ci13xxx *udc)
  616. {
  617. return hw_test_and_write(udc, OP_USBCMD, USBCMD_SUTW, 0);
  618. }
  619. /**
  620. * hw_test_and_set_setup_guard: test & set setup guard (execute without
  621. * interruption)
  622. *
  623. * This function returns guard value
  624. */
  625. static int hw_test_and_set_setup_guard(struct ci13xxx *udc)
  626. {
  627. return hw_test_and_write(udc, OP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
  628. }
  629. /**
  630. * hw_usb_set_address: configures USB address (execute without interruption)
  631. * @value: new USB address
  632. *
  633. * This function returns an error code
  634. */
  635. static int hw_usb_set_address(struct ci13xxx *udc, u8 value)
  636. {
  637. /* advance */
  638. hw_write(udc, OP_DEVICEADDR, DEVICEADDR_USBADR | DEVICEADDR_USBADRA,
  639. value << ffs_nr(DEVICEADDR_USBADR) | DEVICEADDR_USBADRA);
  640. return 0;
  641. }
  642. /**
  643. * hw_usb_reset: restart device after a bus reset (execute without
  644. * interruption)
  645. *
  646. * This function returns an error code
  647. */
  648. static int hw_usb_reset(struct ci13xxx *udc)
  649. {
  650. hw_usb_set_address(udc, 0);
  651. /* ESS flushes only at end?!? */
  652. hw_write(udc, OP_ENDPTFLUSH, ~0, ~0);
  653. /* clear setup token semaphores */
  654. hw_write(udc, OP_ENDPTSETUPSTAT, 0, 0);
  655. /* clear complete status */
  656. hw_write(udc, OP_ENDPTCOMPLETE, 0, 0);
  657. /* wait until all bits cleared */
  658. while (hw_read(udc, OP_ENDPTPRIME, ~0))
  659. udelay(10); /* not RTOS friendly */
  660. /* reset all endpoints ? */
  661. /* reset internal status and wait for further instructions
  662. no need to verify the port reset status (ESS does it) */
  663. return 0;
  664. }
  665. /******************************************************************************
  666. * DBG block
  667. *****************************************************************************/
  668. /**
  669. * show_device: prints information about device capabilities and status
  670. *
  671. * Check "device.h" for details
  672. */
  673. static ssize_t show_device(struct device *dev, struct device_attribute *attr,
  674. char *buf)
  675. {
  676. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  677. struct usb_gadget *gadget = &udc->gadget;
  678. int n = 0;
  679. dbg_trace("[%s] %p\n", __func__, buf);
  680. if (attr == NULL || buf == NULL) {
  681. dev_err(dev, "[%s] EINVAL\n", __func__);
  682. return 0;
  683. }
  684. n += scnprintf(buf + n, PAGE_SIZE - n, "speed = %d\n",
  685. gadget->speed);
  686. n += scnprintf(buf + n, PAGE_SIZE - n, "max_speed = %d\n",
  687. gadget->max_speed);
  688. /* TODO: Scheduled for removal in 3.8. */
  689. n += scnprintf(buf + n, PAGE_SIZE - n, "is_dualspeed = %d\n",
  690. gadget_is_dualspeed(gadget));
  691. n += scnprintf(buf + n, PAGE_SIZE - n, "is_otg = %d\n",
  692. gadget->is_otg);
  693. n += scnprintf(buf + n, PAGE_SIZE - n, "is_a_peripheral = %d\n",
  694. gadget->is_a_peripheral);
  695. n += scnprintf(buf + n, PAGE_SIZE - n, "b_hnp_enable = %d\n",
  696. gadget->b_hnp_enable);
  697. n += scnprintf(buf + n, PAGE_SIZE - n, "a_hnp_support = %d\n",
  698. gadget->a_hnp_support);
  699. n += scnprintf(buf + n, PAGE_SIZE - n, "a_alt_hnp_support = %d\n",
  700. gadget->a_alt_hnp_support);
  701. n += scnprintf(buf + n, PAGE_SIZE - n, "name = %s\n",
  702. (gadget->name ? gadget->name : ""));
  703. return n;
  704. }
  705. static DEVICE_ATTR(device, S_IRUSR, show_device, NULL);
  706. /**
  707. * show_driver: prints information about attached gadget (if any)
  708. *
  709. * Check "device.h" for details
  710. */
  711. static ssize_t show_driver(struct device *dev, struct device_attribute *attr,
  712. char *buf)
  713. {
  714. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  715. struct usb_gadget_driver *driver = udc->driver;
  716. int n = 0;
  717. dbg_trace("[%s] %p\n", __func__, buf);
  718. if (attr == NULL || buf == NULL) {
  719. dev_err(dev, "[%s] EINVAL\n", __func__);
  720. return 0;
  721. }
  722. if (driver == NULL)
  723. return scnprintf(buf, PAGE_SIZE,
  724. "There is no gadget attached!\n");
  725. n += scnprintf(buf + n, PAGE_SIZE - n, "function = %s\n",
  726. (driver->function ? driver->function : ""));
  727. n += scnprintf(buf + n, PAGE_SIZE - n, "max speed = %d\n",
  728. driver->max_speed);
  729. return n;
  730. }
  731. static DEVICE_ATTR(driver, S_IRUSR, show_driver, NULL);
  732. /* Maximum event message length */
  733. #define DBG_DATA_MSG 64UL
  734. /* Maximum event messages */
  735. #define DBG_DATA_MAX 128UL
  736. /* Event buffer descriptor */
  737. static struct {
  738. char (buf[DBG_DATA_MAX])[DBG_DATA_MSG]; /* buffer */
  739. unsigned idx; /* index */
  740. unsigned tty; /* print to console? */
  741. rwlock_t lck; /* lock */
  742. } dbg_data = {
  743. .idx = 0,
  744. .tty = 0,
  745. .lck = __RW_LOCK_UNLOCKED(lck)
  746. };
  747. /**
  748. * dbg_dec: decrements debug event index
  749. * @idx: buffer index
  750. */
  751. static void dbg_dec(unsigned *idx)
  752. {
  753. *idx = (*idx - 1) & (DBG_DATA_MAX-1);
  754. }
  755. /**
  756. * dbg_inc: increments debug event index
  757. * @idx: buffer index
  758. */
  759. static void dbg_inc(unsigned *idx)
  760. {
  761. *idx = (*idx + 1) & (DBG_DATA_MAX-1);
  762. }
  763. /**
  764. * dbg_print: prints the common part of the event
  765. * @addr: endpoint address
  766. * @name: event name
  767. * @status: status
  768. * @extra: extra information
  769. */
  770. static void dbg_print(u8 addr, const char *name, int status, const char *extra)
  771. {
  772. struct timeval tval;
  773. unsigned int stamp;
  774. unsigned long flags;
  775. write_lock_irqsave(&dbg_data.lck, flags);
  776. do_gettimeofday(&tval);
  777. stamp = tval.tv_sec & 0xFFFF; /* 2^32 = 4294967296. Limit to 4096s */
  778. stamp = stamp * 1000000 + tval.tv_usec;
  779. scnprintf(dbg_data.buf[dbg_data.idx], DBG_DATA_MSG,
  780. "%04X\t? %02X %-7.7s %4i ?\t%s\n",
  781. stamp, addr, name, status, extra);
  782. dbg_inc(&dbg_data.idx);
  783. write_unlock_irqrestore(&dbg_data.lck, flags);
  784. if (dbg_data.tty != 0)
  785. pr_notice("%04X\t? %02X %-7.7s %4i ?\t%s\n",
  786. stamp, addr, name, status, extra);
  787. }
  788. /**
  789. * dbg_done: prints a DONE event
  790. * @addr: endpoint address
  791. * @td: transfer descriptor
  792. * @status: status
  793. */
  794. static void dbg_done(u8 addr, const u32 token, int status)
  795. {
  796. char msg[DBG_DATA_MSG];
  797. scnprintf(msg, sizeof(msg), "%d %02X",
  798. (int)(token & TD_TOTAL_BYTES) >> ffs_nr(TD_TOTAL_BYTES),
  799. (int)(token & TD_STATUS) >> ffs_nr(TD_STATUS));
  800. dbg_print(addr, "DONE", status, msg);
  801. }
  802. /**
  803. * dbg_event: prints a generic event
  804. * @addr: endpoint address
  805. * @name: event name
  806. * @status: status
  807. */
  808. static void dbg_event(u8 addr, const char *name, int status)
  809. {
  810. if (name != NULL)
  811. dbg_print(addr, name, status, "");
  812. }
  813. /*
  814. * dbg_queue: prints a QUEUE event
  815. * @addr: endpoint address
  816. * @req: USB request
  817. * @status: status
  818. */
  819. static void dbg_queue(u8 addr, const struct usb_request *req, int status)
  820. {
  821. char msg[DBG_DATA_MSG];
  822. if (req != NULL) {
  823. scnprintf(msg, sizeof(msg),
  824. "%d %d", !req->no_interrupt, req->length);
  825. dbg_print(addr, "QUEUE", status, msg);
  826. }
  827. }
  828. /**
  829. * dbg_setup: prints a SETUP event
  830. * @addr: endpoint address
  831. * @req: setup request
  832. */
  833. static void dbg_setup(u8 addr, const struct usb_ctrlrequest *req)
  834. {
  835. char msg[DBG_DATA_MSG];
  836. if (req != NULL) {
  837. scnprintf(msg, sizeof(msg),
  838. "%02X %02X %04X %04X %d", req->bRequestType,
  839. req->bRequest, le16_to_cpu(req->wValue),
  840. le16_to_cpu(req->wIndex), le16_to_cpu(req->wLength));
  841. dbg_print(addr, "SETUP", 0, msg);
  842. }
  843. }
  844. /**
  845. * show_events: displays the event buffer
  846. *
  847. * Check "device.h" for details
  848. */
  849. static ssize_t show_events(struct device *dev, struct device_attribute *attr,
  850. char *buf)
  851. {
  852. unsigned long flags;
  853. unsigned i, j, n = 0;
  854. dbg_trace("[%s] %p\n", __func__, buf);
  855. if (attr == NULL || buf == NULL) {
  856. dev_err(dev, "[%s] EINVAL\n", __func__);
  857. return 0;
  858. }
  859. read_lock_irqsave(&dbg_data.lck, flags);
  860. i = dbg_data.idx;
  861. for (dbg_dec(&i); i != dbg_data.idx; dbg_dec(&i)) {
  862. n += strlen(dbg_data.buf[i]);
  863. if (n >= PAGE_SIZE) {
  864. n -= strlen(dbg_data.buf[i]);
  865. break;
  866. }
  867. }
  868. for (j = 0, dbg_inc(&i); j < n; dbg_inc(&i))
  869. j += scnprintf(buf + j, PAGE_SIZE - j,
  870. "%s", dbg_data.buf[i]);
  871. read_unlock_irqrestore(&dbg_data.lck, flags);
  872. return n;
  873. }
  874. /**
  875. * store_events: configure if events are going to be also printed to console
  876. *
  877. * Check "device.h" for details
  878. */
  879. static ssize_t store_events(struct device *dev, struct device_attribute *attr,
  880. const char *buf, size_t count)
  881. {
  882. unsigned tty;
  883. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  884. if (attr == NULL || buf == NULL) {
  885. dev_err(dev, "[%s] EINVAL\n", __func__);
  886. goto done;
  887. }
  888. if (sscanf(buf, "%u", &tty) != 1 || tty > 1) {
  889. dev_err(dev, "<1|0>: enable|disable console log\n");
  890. goto done;
  891. }
  892. dbg_data.tty = tty;
  893. dev_info(dev, "tty = %u", dbg_data.tty);
  894. done:
  895. return count;
  896. }
  897. static DEVICE_ATTR(events, S_IRUSR | S_IWUSR, show_events, store_events);
  898. /**
  899. * show_inters: interrupt status, enable status and historic
  900. *
  901. * Check "device.h" for details
  902. */
  903. static ssize_t show_inters(struct device *dev, struct device_attribute *attr,
  904. char *buf)
  905. {
  906. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  907. unsigned long flags;
  908. u32 intr;
  909. unsigned i, j, n = 0;
  910. dbg_trace("[%s] %p\n", __func__, buf);
  911. if (attr == NULL || buf == NULL) {
  912. dev_err(dev, "[%s] EINVAL\n", __func__);
  913. return 0;
  914. }
  915. spin_lock_irqsave(&udc->lock, flags);
  916. n += scnprintf(buf + n, PAGE_SIZE - n,
  917. "status = %08x\n", hw_read_intr_status(udc));
  918. n += scnprintf(buf + n, PAGE_SIZE - n,
  919. "enable = %08x\n", hw_read_intr_enable(udc));
  920. n += scnprintf(buf + n, PAGE_SIZE - n, "*test = %d\n",
  921. isr_statistics.test);
  922. n += scnprintf(buf + n, PAGE_SIZE - n, "? ui = %d\n",
  923. isr_statistics.ui);
  924. n += scnprintf(buf + n, PAGE_SIZE - n, "? uei = %d\n",
  925. isr_statistics.uei);
  926. n += scnprintf(buf + n, PAGE_SIZE - n, "? pci = %d\n",
  927. isr_statistics.pci);
  928. n += scnprintf(buf + n, PAGE_SIZE - n, "? uri = %d\n",
  929. isr_statistics.uri);
  930. n += scnprintf(buf + n, PAGE_SIZE - n, "? sli = %d\n",
  931. isr_statistics.sli);
  932. n += scnprintf(buf + n, PAGE_SIZE - n, "*none = %d\n",
  933. isr_statistics.none);
  934. n += scnprintf(buf + n, PAGE_SIZE - n, "*hndl = %d\n",
  935. isr_statistics.hndl.cnt);
  936. for (i = isr_statistics.hndl.idx, j = 0; j <= ISR_MASK; j++, i++) {
  937. i &= ISR_MASK;
  938. intr = isr_statistics.hndl.buf[i];
  939. if (USBi_UI & intr)
  940. n += scnprintf(buf + n, PAGE_SIZE - n, "ui ");
  941. intr &= ~USBi_UI;
  942. if (USBi_UEI & intr)
  943. n += scnprintf(buf + n, PAGE_SIZE - n, "uei ");
  944. intr &= ~USBi_UEI;
  945. if (USBi_PCI & intr)
  946. n += scnprintf(buf + n, PAGE_SIZE - n, "pci ");
  947. intr &= ~USBi_PCI;
  948. if (USBi_URI & intr)
  949. n += scnprintf(buf + n, PAGE_SIZE - n, "uri ");
  950. intr &= ~USBi_URI;
  951. if (USBi_SLI & intr)
  952. n += scnprintf(buf + n, PAGE_SIZE - n, "sli ");
  953. intr &= ~USBi_SLI;
  954. if (intr)
  955. n += scnprintf(buf + n, PAGE_SIZE - n, "??? ");
  956. if (isr_statistics.hndl.buf[i])
  957. n += scnprintf(buf + n, PAGE_SIZE - n, "\n");
  958. }
  959. spin_unlock_irqrestore(&udc->lock, flags);
  960. return n;
  961. }
  962. /**
  963. * store_inters: enable & force or disable an individual interrutps
  964. * (to be used for test purposes only)
  965. *
  966. * Check "device.h" for details
  967. */
  968. static ssize_t store_inters(struct device *dev, struct device_attribute *attr,
  969. const char *buf, size_t count)
  970. {
  971. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  972. unsigned long flags;
  973. unsigned en, bit;
  974. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  975. if (attr == NULL || buf == NULL) {
  976. dev_err(dev, "[%s] EINVAL\n", __func__);
  977. goto done;
  978. }
  979. if (sscanf(buf, "%u %u", &en, &bit) != 2 || en > 1) {
  980. dev_err(dev, "<1|0> <bit>: enable|disable interrupt");
  981. goto done;
  982. }
  983. spin_lock_irqsave(&udc->lock, flags);
  984. if (en) {
  985. if (hw_intr_force(udc, bit))
  986. dev_err(dev, "invalid bit number\n");
  987. else
  988. isr_statistics.test++;
  989. } else {
  990. if (hw_intr_clear(udc, bit))
  991. dev_err(dev, "invalid bit number\n");
  992. }
  993. spin_unlock_irqrestore(&udc->lock, flags);
  994. done:
  995. return count;
  996. }
  997. static DEVICE_ATTR(inters, S_IRUSR | S_IWUSR, show_inters, store_inters);
  998. /**
  999. * show_port_test: reads port test mode
  1000. *
  1001. * Check "device.h" for details
  1002. */
  1003. static ssize_t show_port_test(struct device *dev,
  1004. struct device_attribute *attr, char *buf)
  1005. {
  1006. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1007. unsigned long flags;
  1008. unsigned mode;
  1009. dbg_trace("[%s] %p\n", __func__, buf);
  1010. if (attr == NULL || buf == NULL) {
  1011. dev_err(dev, "[%s] EINVAL\n", __func__);
  1012. return 0;
  1013. }
  1014. spin_lock_irqsave(&udc->lock, flags);
  1015. mode = hw_port_test_get(udc);
  1016. spin_unlock_irqrestore(&udc->lock, flags);
  1017. return scnprintf(buf, PAGE_SIZE, "mode = %u\n", mode);
  1018. }
  1019. /**
  1020. * store_port_test: writes port test mode
  1021. *
  1022. * Check "device.h" for details
  1023. */
  1024. static ssize_t store_port_test(struct device *dev,
  1025. struct device_attribute *attr,
  1026. const char *buf, size_t count)
  1027. {
  1028. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1029. unsigned long flags;
  1030. unsigned mode;
  1031. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  1032. if (attr == NULL || buf == NULL) {
  1033. dev_err(dev, "[%s] EINVAL\n", __func__);
  1034. goto done;
  1035. }
  1036. if (sscanf(buf, "%u", &mode) != 1) {
  1037. dev_err(dev, "<mode>: set port test mode");
  1038. goto done;
  1039. }
  1040. spin_lock_irqsave(&udc->lock, flags);
  1041. if (hw_port_test_set(udc, mode))
  1042. dev_err(dev, "invalid mode\n");
  1043. spin_unlock_irqrestore(&udc->lock, flags);
  1044. done:
  1045. return count;
  1046. }
  1047. static DEVICE_ATTR(port_test, S_IRUSR | S_IWUSR,
  1048. show_port_test, store_port_test);
  1049. /**
  1050. * show_qheads: DMA contents of all queue heads
  1051. *
  1052. * Check "device.h" for details
  1053. */
  1054. static ssize_t show_qheads(struct device *dev, struct device_attribute *attr,
  1055. char *buf)
  1056. {
  1057. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1058. unsigned long flags;
  1059. unsigned i, j, n = 0;
  1060. dbg_trace("[%s] %p\n", __func__, buf);
  1061. if (attr == NULL || buf == NULL) {
  1062. dev_err(dev, "[%s] EINVAL\n", __func__);
  1063. return 0;
  1064. }
  1065. spin_lock_irqsave(&udc->lock, flags);
  1066. for (i = 0; i < udc->hw_ep_max/2; i++) {
  1067. struct ci13xxx_ep *mEpRx = &udc->ci13xxx_ep[i];
  1068. struct ci13xxx_ep *mEpTx =
  1069. &udc->ci13xxx_ep[i + udc->hw_ep_max/2];
  1070. n += scnprintf(buf + n, PAGE_SIZE - n,
  1071. "EP=%02i: RX=%08X TX=%08X\n",
  1072. i, (u32)mEpRx->qh.dma, (u32)mEpTx->qh.dma);
  1073. for (j = 0; j < (sizeof(struct ci13xxx_qh)/sizeof(u32)); j++) {
  1074. n += scnprintf(buf + n, PAGE_SIZE - n,
  1075. " %04X: %08X %08X\n", j,
  1076. *((u32 *)mEpRx->qh.ptr + j),
  1077. *((u32 *)mEpTx->qh.ptr + j));
  1078. }
  1079. }
  1080. spin_unlock_irqrestore(&udc->lock, flags);
  1081. return n;
  1082. }
  1083. static DEVICE_ATTR(qheads, S_IRUSR, show_qheads, NULL);
  1084. /**
  1085. * show_registers: dumps all registers
  1086. *
  1087. * Check "device.h" for details
  1088. */
  1089. #define DUMP_ENTRIES 512
  1090. static ssize_t show_registers(struct device *dev,
  1091. struct device_attribute *attr, char *buf)
  1092. {
  1093. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1094. unsigned long flags;
  1095. u32 *dump;
  1096. unsigned i, k, n = 0;
  1097. dbg_trace("[%s] %p\n", __func__, buf);
  1098. if (attr == NULL || buf == NULL) {
  1099. dev_err(dev, "[%s] EINVAL\n", __func__);
  1100. return 0;
  1101. }
  1102. dump = kmalloc(sizeof(u32) * DUMP_ENTRIES, GFP_KERNEL);
  1103. if (!dump) {
  1104. dev_err(dev, "%s: out of memory\n", __func__);
  1105. return 0;
  1106. }
  1107. spin_lock_irqsave(&udc->lock, flags);
  1108. k = hw_register_read(udc, dump, DUMP_ENTRIES);
  1109. spin_unlock_irqrestore(&udc->lock, flags);
  1110. for (i = 0; i < k; i++) {
  1111. n += scnprintf(buf + n, PAGE_SIZE - n,
  1112. "reg[0x%04X] = 0x%08X\n",
  1113. i * (unsigned)sizeof(u32), dump[i]);
  1114. }
  1115. kfree(dump);
  1116. return n;
  1117. }
  1118. /**
  1119. * store_registers: writes value to register address
  1120. *
  1121. * Check "device.h" for details
  1122. */
  1123. static ssize_t store_registers(struct device *dev,
  1124. struct device_attribute *attr,
  1125. const char *buf, size_t count)
  1126. {
  1127. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1128. unsigned long addr, data, flags;
  1129. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  1130. if (attr == NULL || buf == NULL) {
  1131. dev_err(dev, "[%s] EINVAL\n", __func__);
  1132. goto done;
  1133. }
  1134. if (sscanf(buf, "%li %li", &addr, &data) != 2) {
  1135. dev_err(dev, "<addr> <data>: write data to register address");
  1136. goto done;
  1137. }
  1138. spin_lock_irqsave(&udc->lock, flags);
  1139. if (hw_register_write(udc, addr, data))
  1140. dev_err(dev, "invalid address range\n");
  1141. spin_unlock_irqrestore(&udc->lock, flags);
  1142. done:
  1143. return count;
  1144. }
  1145. static DEVICE_ATTR(registers, S_IRUSR | S_IWUSR,
  1146. show_registers, store_registers);
  1147. /**
  1148. * show_requests: DMA contents of all requests currently queued (all endpts)
  1149. *
  1150. * Check "device.h" for details
  1151. */
  1152. static ssize_t show_requests(struct device *dev, struct device_attribute *attr,
  1153. char *buf)
  1154. {
  1155. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1156. unsigned long flags;
  1157. struct list_head *ptr = NULL;
  1158. struct ci13xxx_req *req = NULL;
  1159. unsigned i, j, n = 0, qSize = sizeof(struct ci13xxx_td)/sizeof(u32);
  1160. dbg_trace("[%s] %p\n", __func__, buf);
  1161. if (attr == NULL || buf == NULL) {
  1162. dev_err(dev, "[%s] EINVAL\n", __func__);
  1163. return 0;
  1164. }
  1165. spin_lock_irqsave(&udc->lock, flags);
  1166. for (i = 0; i < udc->hw_ep_max; i++)
  1167. list_for_each(ptr, &udc->ci13xxx_ep[i].qh.queue)
  1168. {
  1169. req = list_entry(ptr, struct ci13xxx_req, queue);
  1170. n += scnprintf(buf + n, PAGE_SIZE - n,
  1171. "EP=%02i: TD=%08X %s\n",
  1172. i % udc->hw_ep_max/2, (u32)req->dma,
  1173. ((i < udc->hw_ep_max/2) ? "RX" : "TX"));
  1174. for (j = 0; j < qSize; j++)
  1175. n += scnprintf(buf + n, PAGE_SIZE - n,
  1176. " %04X: %08X\n", j,
  1177. *((u32 *)req->ptr + j));
  1178. }
  1179. spin_unlock_irqrestore(&udc->lock, flags);
  1180. return n;
  1181. }
  1182. static DEVICE_ATTR(requests, S_IRUSR, show_requests, NULL);
  1183. /**
  1184. * dbg_create_files: initializes the attribute interface
  1185. * @dev: device
  1186. *
  1187. * This function returns an error code
  1188. */
  1189. __maybe_unused static int dbg_create_files(struct device *dev)
  1190. {
  1191. int retval = 0;
  1192. if (dev == NULL)
  1193. return -EINVAL;
  1194. retval = device_create_file(dev, &dev_attr_device);
  1195. if (retval)
  1196. goto done;
  1197. retval = device_create_file(dev, &dev_attr_driver);
  1198. if (retval)
  1199. goto rm_device;
  1200. retval = device_create_file(dev, &dev_attr_events);
  1201. if (retval)
  1202. goto rm_driver;
  1203. retval = device_create_file(dev, &dev_attr_inters);
  1204. if (retval)
  1205. goto rm_events;
  1206. retval = device_create_file(dev, &dev_attr_port_test);
  1207. if (retval)
  1208. goto rm_inters;
  1209. retval = device_create_file(dev, &dev_attr_qheads);
  1210. if (retval)
  1211. goto rm_port_test;
  1212. retval = device_create_file(dev, &dev_attr_registers);
  1213. if (retval)
  1214. goto rm_qheads;
  1215. retval = device_create_file(dev, &dev_attr_requests);
  1216. if (retval)
  1217. goto rm_registers;
  1218. return 0;
  1219. rm_registers:
  1220. device_remove_file(dev, &dev_attr_registers);
  1221. rm_qheads:
  1222. device_remove_file(dev, &dev_attr_qheads);
  1223. rm_port_test:
  1224. device_remove_file(dev, &dev_attr_port_test);
  1225. rm_inters:
  1226. device_remove_file(dev, &dev_attr_inters);
  1227. rm_events:
  1228. device_remove_file(dev, &dev_attr_events);
  1229. rm_driver:
  1230. device_remove_file(dev, &dev_attr_driver);
  1231. rm_device:
  1232. device_remove_file(dev, &dev_attr_device);
  1233. done:
  1234. return retval;
  1235. }
  1236. /**
  1237. * dbg_remove_files: destroys the attribute interface
  1238. * @dev: device
  1239. *
  1240. * This function returns an error code
  1241. */
  1242. __maybe_unused static int dbg_remove_files(struct device *dev)
  1243. {
  1244. if (dev == NULL)
  1245. return -EINVAL;
  1246. device_remove_file(dev, &dev_attr_requests);
  1247. device_remove_file(dev, &dev_attr_registers);
  1248. device_remove_file(dev, &dev_attr_qheads);
  1249. device_remove_file(dev, &dev_attr_port_test);
  1250. device_remove_file(dev, &dev_attr_inters);
  1251. device_remove_file(dev, &dev_attr_events);
  1252. device_remove_file(dev, &dev_attr_driver);
  1253. device_remove_file(dev, &dev_attr_device);
  1254. return 0;
  1255. }
  1256. /******************************************************************************
  1257. * UTIL block
  1258. *****************************************************************************/
  1259. /**
  1260. * _usb_addr: calculates endpoint address from direction & number
  1261. * @ep: endpoint
  1262. */
  1263. static inline u8 _usb_addr(struct ci13xxx_ep *ep)
  1264. {
  1265. return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
  1266. }
  1267. /**
  1268. * _hardware_queue: configures a request at hardware level
  1269. * @gadget: gadget
  1270. * @mEp: endpoint
  1271. *
  1272. * This function returns an error code
  1273. */
  1274. static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
  1275. {
  1276. struct ci13xxx *udc = mEp->udc;
  1277. unsigned i;
  1278. int ret = 0;
  1279. unsigned length = mReq->req.length;
  1280. trace("%p, %p", mEp, mReq);
  1281. /* don't queue twice */
  1282. if (mReq->req.status == -EALREADY)
  1283. return -EALREADY;
  1284. mReq->req.status = -EALREADY;
  1285. if (length && mReq->req.dma == DMA_ADDR_INVALID) {
  1286. mReq->req.dma = \
  1287. dma_map_single(mEp->device, mReq->req.buf,
  1288. length, mEp->dir ? DMA_TO_DEVICE :
  1289. DMA_FROM_DEVICE);
  1290. if (mReq->req.dma == 0)
  1291. return -ENOMEM;
  1292. mReq->map = 1;
  1293. }
  1294. if (mReq->req.zero && length && (length % mEp->ep.maxpacket == 0)) {
  1295. mReq->zptr = dma_pool_alloc(mEp->td_pool, GFP_ATOMIC,
  1296. &mReq->zdma);
  1297. if (mReq->zptr == NULL) {
  1298. if (mReq->map) {
  1299. dma_unmap_single(mEp->device, mReq->req.dma,
  1300. length, mEp->dir ? DMA_TO_DEVICE :
  1301. DMA_FROM_DEVICE);
  1302. mReq->req.dma = DMA_ADDR_INVALID;
  1303. mReq->map = 0;
  1304. }
  1305. return -ENOMEM;
  1306. }
  1307. memset(mReq->zptr, 0, sizeof(*mReq->zptr));
  1308. mReq->zptr->next = TD_TERMINATE;
  1309. mReq->zptr->token = TD_STATUS_ACTIVE;
  1310. if (!mReq->req.no_interrupt)
  1311. mReq->zptr->token |= TD_IOC;
  1312. }
  1313. /*
  1314. * TD configuration
  1315. * TODO - handle requests which spawns into several TDs
  1316. */
  1317. memset(mReq->ptr, 0, sizeof(*mReq->ptr));
  1318. mReq->ptr->token = length << ffs_nr(TD_TOTAL_BYTES);
  1319. mReq->ptr->token &= TD_TOTAL_BYTES;
  1320. mReq->ptr->token |= TD_STATUS_ACTIVE;
  1321. if (mReq->zptr) {
  1322. mReq->ptr->next = mReq->zdma;
  1323. } else {
  1324. mReq->ptr->next = TD_TERMINATE;
  1325. if (!mReq->req.no_interrupt)
  1326. mReq->ptr->token |= TD_IOC;
  1327. }
  1328. mReq->ptr->page[0] = mReq->req.dma;
  1329. for (i = 1; i < 5; i++)
  1330. mReq->ptr->page[i] =
  1331. (mReq->req.dma + i * CI13XXX_PAGE_SIZE) & ~TD_RESERVED_MASK;
  1332. if (!list_empty(&mEp->qh.queue)) {
  1333. struct ci13xxx_req *mReqPrev;
  1334. int n = hw_ep_bit(mEp->num, mEp->dir);
  1335. int tmp_stat;
  1336. mReqPrev = list_entry(mEp->qh.queue.prev,
  1337. struct ci13xxx_req, queue);
  1338. if (mReqPrev->zptr)
  1339. mReqPrev->zptr->next = mReq->dma & TD_ADDR_MASK;
  1340. else
  1341. mReqPrev->ptr->next = mReq->dma & TD_ADDR_MASK;
  1342. wmb();
  1343. if (hw_read(udc, OP_ENDPTPRIME, BIT(n)))
  1344. goto done;
  1345. do {
  1346. hw_write(udc, OP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
  1347. tmp_stat = hw_read(udc, OP_ENDPTSTAT, BIT(n));
  1348. } while (!hw_read(udc, OP_USBCMD, USBCMD_ATDTW));
  1349. hw_write(udc, OP_USBCMD, USBCMD_ATDTW, 0);
  1350. if (tmp_stat)
  1351. goto done;
  1352. }
  1353. /* QH configuration */
  1354. mEp->qh.ptr->td.next = mReq->dma; /* TERMINATE = 0 */
  1355. mEp->qh.ptr->td.token &= ~TD_STATUS; /* clear status */
  1356. mEp->qh.ptr->cap |= QH_ZLT;
  1357. wmb(); /* synchronize before ep prime */
  1358. ret = hw_ep_prime(udc, mEp->num, mEp->dir,
  1359. mEp->type == USB_ENDPOINT_XFER_CONTROL);
  1360. done:
  1361. return ret;
  1362. }
  1363. /**
  1364. * _hardware_dequeue: handles a request at hardware level
  1365. * @gadget: gadget
  1366. * @mEp: endpoint
  1367. *
  1368. * This function returns an error code
  1369. */
  1370. static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
  1371. {
  1372. trace("%p, %p", mEp, mReq);
  1373. if (mReq->req.status != -EALREADY)
  1374. return -EINVAL;
  1375. if ((TD_STATUS_ACTIVE & mReq->ptr->token) != 0)
  1376. return -EBUSY;
  1377. if (mReq->zptr) {
  1378. if ((TD_STATUS_ACTIVE & mReq->zptr->token) != 0)
  1379. return -EBUSY;
  1380. dma_pool_free(mEp->td_pool, mReq->zptr, mReq->zdma);
  1381. mReq->zptr = NULL;
  1382. }
  1383. mReq->req.status = 0;
  1384. if (mReq->map) {
  1385. dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
  1386. mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  1387. mReq->req.dma = DMA_ADDR_INVALID;
  1388. mReq->map = 0;
  1389. }
  1390. mReq->req.status = mReq->ptr->token & TD_STATUS;
  1391. if ((TD_STATUS_HALTED & mReq->req.status) != 0)
  1392. mReq->req.status = -1;
  1393. else if ((TD_STATUS_DT_ERR & mReq->req.status) != 0)
  1394. mReq->req.status = -1;
  1395. else if ((TD_STATUS_TR_ERR & mReq->req.status) != 0)
  1396. mReq->req.status = -1;
  1397. mReq->req.actual = mReq->ptr->token & TD_TOTAL_BYTES;
  1398. mReq->req.actual >>= ffs_nr(TD_TOTAL_BYTES);
  1399. mReq->req.actual = mReq->req.length - mReq->req.actual;
  1400. mReq->req.actual = mReq->req.status ? 0 : mReq->req.actual;
  1401. return mReq->req.actual;
  1402. }
  1403. /**
  1404. * _ep_nuke: dequeues all endpoint requests
  1405. * @mEp: endpoint
  1406. *
  1407. * This function returns an error code
  1408. * Caller must hold lock
  1409. */
  1410. static int _ep_nuke(struct ci13xxx_ep *mEp)
  1411. __releases(mEp->lock)
  1412. __acquires(mEp->lock)
  1413. {
  1414. trace("%p", mEp);
  1415. if (mEp == NULL)
  1416. return -EINVAL;
  1417. hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
  1418. while (!list_empty(&mEp->qh.queue)) {
  1419. /* pop oldest request */
  1420. struct ci13xxx_req *mReq = \
  1421. list_entry(mEp->qh.queue.next,
  1422. struct ci13xxx_req, queue);
  1423. list_del_init(&mReq->queue);
  1424. mReq->req.status = -ESHUTDOWN;
  1425. if (mReq->req.complete != NULL) {
  1426. spin_unlock(mEp->lock);
  1427. mReq->req.complete(&mEp->ep, &mReq->req);
  1428. spin_lock(mEp->lock);
  1429. }
  1430. }
  1431. return 0;
  1432. }
  1433. /**
  1434. * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
  1435. * @gadget: gadget
  1436. *
  1437. * This function returns an error code
  1438. */
  1439. static int _gadget_stop_activity(struct usb_gadget *gadget)
  1440. {
  1441. struct usb_ep *ep;
  1442. struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
  1443. unsigned long flags;
  1444. trace("%p", gadget);
  1445. if (gadget == NULL)
  1446. return -EINVAL;
  1447. spin_lock_irqsave(&udc->lock, flags);
  1448. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1449. udc->remote_wakeup = 0;
  1450. udc->suspended = 0;
  1451. spin_unlock_irqrestore(&udc->lock, flags);
  1452. /* flush all endpoints */
  1453. gadget_for_each_ep(ep, gadget) {
  1454. usb_ep_fifo_flush(ep);
  1455. }
  1456. usb_ep_fifo_flush(&udc->ep0out->ep);
  1457. usb_ep_fifo_flush(&udc->ep0in->ep);
  1458. udc->driver->disconnect(gadget);
  1459. /* make sure to disable all endpoints */
  1460. gadget_for_each_ep(ep, gadget) {
  1461. usb_ep_disable(ep);
  1462. }
  1463. if (udc->status != NULL) {
  1464. usb_ep_free_request(&udc->ep0in->ep, udc->status);
  1465. udc->status = NULL;
  1466. }
  1467. return 0;
  1468. }
  1469. /******************************************************************************
  1470. * ISR block
  1471. *****************************************************************************/
  1472. /**
  1473. * isr_reset_handler: USB reset interrupt handler
  1474. * @udc: UDC device
  1475. *
  1476. * This function resets USB engine after a bus reset occurred
  1477. */
  1478. static void isr_reset_handler(struct ci13xxx *udc)
  1479. __releases(udc->lock)
  1480. __acquires(udc->lock)
  1481. {
  1482. int retval;
  1483. trace("%p", udc);
  1484. if (udc == NULL) {
  1485. pr_err("EINVAL\n");
  1486. return;
  1487. }
  1488. dbg_event(0xFF, "BUS RST", 0);
  1489. spin_unlock(&udc->lock);
  1490. retval = _gadget_stop_activity(&udc->gadget);
  1491. if (retval)
  1492. goto done;
  1493. retval = hw_usb_reset(udc);
  1494. if (retval)
  1495. goto done;
  1496. udc->status = usb_ep_alloc_request(&udc->ep0in->ep, GFP_ATOMIC);
  1497. if (udc->status == NULL)
  1498. retval = -ENOMEM;
  1499. spin_lock(&udc->lock);
  1500. done:
  1501. if (retval)
  1502. pr_err("error: %i\n", retval);
  1503. }
  1504. /**
  1505. * isr_get_status_complete: get_status request complete function
  1506. * @ep: endpoint
  1507. * @req: request handled
  1508. *
  1509. * Caller must release lock
  1510. */
  1511. static void isr_get_status_complete(struct usb_ep *ep, struct usb_request *req)
  1512. {
  1513. trace("%p, %p", ep, req);
  1514. if (ep == NULL || req == NULL) {
  1515. pr_err("EINVAL\n");
  1516. return;
  1517. }
  1518. kfree(req->buf);
  1519. usb_ep_free_request(ep, req);
  1520. }
  1521. /**
  1522. * isr_get_status_response: get_status request response
  1523. * @udc: udc struct
  1524. * @setup: setup request packet
  1525. *
  1526. * This function returns an error code
  1527. */
  1528. static int isr_get_status_response(struct ci13xxx *udc,
  1529. struct usb_ctrlrequest *setup)
  1530. __releases(mEp->lock)
  1531. __acquires(mEp->lock)
  1532. {
  1533. struct ci13xxx_ep *mEp = udc->ep0in;
  1534. struct usb_request *req = NULL;
  1535. gfp_t gfp_flags = GFP_ATOMIC;
  1536. int dir, num, retval;
  1537. trace("%p, %p", mEp, setup);
  1538. if (mEp == NULL || setup == NULL)
  1539. return -EINVAL;
  1540. spin_unlock(mEp->lock);
  1541. req = usb_ep_alloc_request(&mEp->ep, gfp_flags);
  1542. spin_lock(mEp->lock);
  1543. if (req == NULL)
  1544. return -ENOMEM;
  1545. req->complete = isr_get_status_complete;
  1546. req->length = 2;
  1547. req->buf = kzalloc(req->length, gfp_flags);
  1548. if (req->buf == NULL) {
  1549. retval = -ENOMEM;
  1550. goto err_free_req;
  1551. }
  1552. if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  1553. /* Assume that device is bus powered for now. */
  1554. *(u16 *)req->buf = _udc->remote_wakeup << 1;
  1555. retval = 0;
  1556. } else if ((setup->bRequestType & USB_RECIP_MASK) \
  1557. == USB_RECIP_ENDPOINT) {
  1558. dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
  1559. TX : RX;
  1560. num = le16_to_cpu(setup->wIndex) & USB_ENDPOINT_NUMBER_MASK;
  1561. *(u16 *)req->buf = hw_ep_get_halt(udc, num, dir);
  1562. }
  1563. /* else do nothing; reserved for future use */
  1564. spin_unlock(mEp->lock);
  1565. retval = usb_ep_queue(&mEp->ep, req, gfp_flags);
  1566. spin_lock(mEp->lock);
  1567. if (retval)
  1568. goto err_free_buf;
  1569. return 0;
  1570. err_free_buf:
  1571. kfree(req->buf);
  1572. err_free_req:
  1573. spin_unlock(mEp->lock);
  1574. usb_ep_free_request(&mEp->ep, req);
  1575. spin_lock(mEp->lock);
  1576. return retval;
  1577. }
  1578. /**
  1579. * isr_setup_status_complete: setup_status request complete function
  1580. * @ep: endpoint
  1581. * @req: request handled
  1582. *
  1583. * Caller must release lock. Put the port in test mode if test mode
  1584. * feature is selected.
  1585. */
  1586. static void
  1587. isr_setup_status_complete(struct usb_ep *ep, struct usb_request *req)
  1588. {
  1589. struct ci13xxx *udc = req->context;
  1590. unsigned long flags;
  1591. trace("%p, %p", ep, req);
  1592. spin_lock_irqsave(&udc->lock, flags);
  1593. if (udc->test_mode)
  1594. hw_port_test_set(udc, udc->test_mode);
  1595. spin_unlock_irqrestore(&udc->lock, flags);
  1596. }
  1597. /**
  1598. * isr_setup_status_phase: queues the status phase of a setup transation
  1599. * @udc: udc struct
  1600. *
  1601. * This function returns an error code
  1602. */
  1603. static int isr_setup_status_phase(struct ci13xxx *udc)
  1604. __releases(mEp->lock)
  1605. __acquires(mEp->lock)
  1606. {
  1607. int retval;
  1608. struct ci13xxx_ep *mEp;
  1609. trace("%p", udc);
  1610. mEp = (udc->ep0_dir == TX) ? udc->ep0out : udc->ep0in;
  1611. udc->status->context = udc;
  1612. udc->status->complete = isr_setup_status_complete;
  1613. spin_unlock(mEp->lock);
  1614. retval = usb_ep_queue(&mEp->ep, udc->status, GFP_ATOMIC);
  1615. spin_lock(mEp->lock);
  1616. return retval;
  1617. }
  1618. /**
  1619. * isr_tr_complete_low: transaction complete low level handler
  1620. * @mEp: endpoint
  1621. *
  1622. * This function returns an error code
  1623. * Caller must hold lock
  1624. */
  1625. static int isr_tr_complete_low(struct ci13xxx_ep *mEp)
  1626. __releases(mEp->lock)
  1627. __acquires(mEp->lock)
  1628. {
  1629. struct ci13xxx_req *mReq, *mReqTemp;
  1630. struct ci13xxx_ep *mEpTemp = mEp;
  1631. int uninitialized_var(retval);
  1632. trace("%p", mEp);
  1633. if (list_empty(&mEp->qh.queue))
  1634. return -EINVAL;
  1635. list_for_each_entry_safe(mReq, mReqTemp, &mEp->qh.queue,
  1636. queue) {
  1637. retval = _hardware_dequeue(mEp, mReq);
  1638. if (retval < 0)
  1639. break;
  1640. list_del_init(&mReq->queue);
  1641. dbg_done(_usb_addr(mEp), mReq->ptr->token, retval);
  1642. if (mReq->req.complete != NULL) {
  1643. spin_unlock(mEp->lock);
  1644. if ((mEp->type == USB_ENDPOINT_XFER_CONTROL) &&
  1645. mReq->req.length)
  1646. mEpTemp = _udc->ep0in;
  1647. mReq->req.complete(&mEpTemp->ep, &mReq->req);
  1648. spin_lock(mEp->lock);
  1649. }
  1650. }
  1651. if (retval == -EBUSY)
  1652. retval = 0;
  1653. if (retval < 0)
  1654. dbg_event(_usb_addr(mEp), "DONE", retval);
  1655. return retval;
  1656. }
  1657. /**
  1658. * isr_tr_complete_handler: transaction complete interrupt handler
  1659. * @udc: UDC descriptor
  1660. *
  1661. * This function handles traffic events
  1662. */
  1663. static void isr_tr_complete_handler(struct ci13xxx *udc)
  1664. __releases(udc->lock)
  1665. __acquires(udc->lock)
  1666. {
  1667. unsigned i;
  1668. u8 tmode = 0;
  1669. trace("%p", udc);
  1670. if (udc == NULL) {
  1671. pr_err("EINVAL\n");
  1672. return;
  1673. }
  1674. for (i = 0; i < udc->hw_ep_max; i++) {
  1675. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
  1676. int type, num, dir, err = -EINVAL;
  1677. struct usb_ctrlrequest req;
  1678. if (mEp->ep.desc == NULL)
  1679. continue; /* not configured */
  1680. if (hw_test_and_clear_complete(udc, i)) {
  1681. err = isr_tr_complete_low(mEp);
  1682. if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
  1683. if (err > 0) /* needs status phase */
  1684. err = isr_setup_status_phase(udc);
  1685. if (err < 0) {
  1686. dbg_event(_usb_addr(mEp),
  1687. "ERROR", err);
  1688. spin_unlock(&udc->lock);
  1689. if (usb_ep_set_halt(&mEp->ep))
  1690. dev_err(&udc->gadget.dev,
  1691. "error: ep_set_halt\n");
  1692. spin_lock(&udc->lock);
  1693. }
  1694. }
  1695. }
  1696. if (mEp->type != USB_ENDPOINT_XFER_CONTROL ||
  1697. !hw_test_and_clear_setup_status(udc, i))
  1698. continue;
  1699. if (i != 0) {
  1700. dev_warn(&udc->gadget.dev,
  1701. "ctrl traffic received at endpoint\n");
  1702. continue;
  1703. }
  1704. /*
  1705. * Flush data and handshake transactions of previous
  1706. * setup packet.
  1707. */
  1708. _ep_nuke(udc->ep0out);
  1709. _ep_nuke(udc->ep0in);
  1710. /* read_setup_packet */
  1711. do {
  1712. hw_test_and_set_setup_guard(udc);
  1713. memcpy(&req, &mEp->qh.ptr->setup, sizeof(req));
  1714. } while (!hw_test_and_clear_setup_guard(udc));
  1715. type = req.bRequestType;
  1716. udc->ep0_dir = (type & USB_DIR_IN) ? TX : RX;
  1717. dbg_setup(_usb_addr(mEp), &req);
  1718. switch (req.bRequest) {
  1719. case USB_REQ_CLEAR_FEATURE:
  1720. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  1721. le16_to_cpu(req.wValue) ==
  1722. USB_ENDPOINT_HALT) {
  1723. if (req.wLength != 0)
  1724. break;
  1725. num = le16_to_cpu(req.wIndex);
  1726. dir = num & USB_ENDPOINT_DIR_MASK;
  1727. num &= USB_ENDPOINT_NUMBER_MASK;
  1728. if (dir) /* TX */
  1729. num += udc->hw_ep_max/2;
  1730. if (!udc->ci13xxx_ep[num].wedge) {
  1731. spin_unlock(&udc->lock);
  1732. err = usb_ep_clear_halt(
  1733. &udc->ci13xxx_ep[num].ep);
  1734. spin_lock(&udc->lock);
  1735. if (err)
  1736. break;
  1737. }
  1738. err = isr_setup_status_phase(udc);
  1739. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE) &&
  1740. le16_to_cpu(req.wValue) ==
  1741. USB_DEVICE_REMOTE_WAKEUP) {
  1742. if (req.wLength != 0)
  1743. break;
  1744. udc->remote_wakeup = 0;
  1745. err = isr_setup_status_phase(udc);
  1746. } else {
  1747. goto delegate;
  1748. }
  1749. break;
  1750. case USB_REQ_GET_STATUS:
  1751. if (type != (USB_DIR_IN|USB_RECIP_DEVICE) &&
  1752. type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
  1753. type != (USB_DIR_IN|USB_RECIP_INTERFACE))
  1754. goto delegate;
  1755. if (le16_to_cpu(req.wLength) != 2 ||
  1756. le16_to_cpu(req.wValue) != 0)
  1757. break;
  1758. err = isr_get_status_response(udc, &req);
  1759. break;
  1760. case USB_REQ_SET_ADDRESS:
  1761. if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
  1762. goto delegate;
  1763. if (le16_to_cpu(req.wLength) != 0 ||
  1764. le16_to_cpu(req.wIndex) != 0)
  1765. break;
  1766. err = hw_usb_set_address(udc,
  1767. (u8)le16_to_cpu(req.wValue));
  1768. if (err)
  1769. break;
  1770. err = isr_setup_status_phase(udc);
  1771. break;
  1772. case USB_REQ_SET_FEATURE:
  1773. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  1774. le16_to_cpu(req.wValue) ==
  1775. USB_ENDPOINT_HALT) {
  1776. if (req.wLength != 0)
  1777. break;
  1778. num = le16_to_cpu(req.wIndex);
  1779. dir = num & USB_ENDPOINT_DIR_MASK;
  1780. num &= USB_ENDPOINT_NUMBER_MASK;
  1781. if (dir) /* TX */
  1782. num += udc->hw_ep_max/2;
  1783. spin_unlock(&udc->lock);
  1784. err = usb_ep_set_halt(&udc->ci13xxx_ep[num].ep);
  1785. spin_lock(&udc->lock);
  1786. if (!err)
  1787. isr_setup_status_phase(udc);
  1788. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE)) {
  1789. if (req.wLength != 0)
  1790. break;
  1791. switch (le16_to_cpu(req.wValue)) {
  1792. case USB_DEVICE_REMOTE_WAKEUP:
  1793. udc->remote_wakeup = 1;
  1794. err = isr_setup_status_phase(udc);
  1795. break;
  1796. case USB_DEVICE_TEST_MODE:
  1797. tmode = le16_to_cpu(req.wIndex) >> 8;
  1798. switch (tmode) {
  1799. case TEST_J:
  1800. case TEST_K:
  1801. case TEST_SE0_NAK:
  1802. case TEST_PACKET:
  1803. case TEST_FORCE_EN:
  1804. udc->test_mode = tmode;
  1805. err = isr_setup_status_phase(
  1806. udc);
  1807. break;
  1808. default:
  1809. break;
  1810. }
  1811. default:
  1812. goto delegate;
  1813. }
  1814. } else {
  1815. goto delegate;
  1816. }
  1817. break;
  1818. default:
  1819. delegate:
  1820. if (req.wLength == 0) /* no data phase */
  1821. udc->ep0_dir = TX;
  1822. spin_unlock(&udc->lock);
  1823. err = udc->driver->setup(&udc->gadget, &req);
  1824. spin_lock(&udc->lock);
  1825. break;
  1826. }
  1827. if (err < 0) {
  1828. dbg_event(_usb_addr(mEp), "ERROR", err);
  1829. spin_unlock(&udc->lock);
  1830. if (usb_ep_set_halt(&mEp->ep))
  1831. dev_err(&udc->gadget.dev,
  1832. "error: ep_set_halt\n");
  1833. spin_lock(&udc->lock);
  1834. }
  1835. }
  1836. }
  1837. /******************************************************************************
  1838. * ENDPT block
  1839. *****************************************************************************/
  1840. /**
  1841. * ep_enable: configure endpoint, making it usable
  1842. *
  1843. * Check usb_ep_enable() at "usb_gadget.h" for details
  1844. */
  1845. static int ep_enable(struct usb_ep *ep,
  1846. const struct usb_endpoint_descriptor *desc)
  1847. {
  1848. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1849. int retval = 0;
  1850. unsigned long flags;
  1851. trace("%p, %p", ep, desc);
  1852. if (ep == NULL || desc == NULL)
  1853. return -EINVAL;
  1854. spin_lock_irqsave(mEp->lock, flags);
  1855. /* only internal SW should enable ctrl endpts */
  1856. mEp->ep.desc = desc;
  1857. if (!list_empty(&mEp->qh.queue))
  1858. warn("enabling a non-empty endpoint!");
  1859. mEp->dir = usb_endpoint_dir_in(desc) ? TX : RX;
  1860. mEp->num = usb_endpoint_num(desc);
  1861. mEp->type = usb_endpoint_type(desc);
  1862. mEp->ep.maxpacket = usb_endpoint_maxp(desc);
  1863. dbg_event(_usb_addr(mEp), "ENABLE", 0);
  1864. mEp->qh.ptr->cap = 0;
  1865. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  1866. mEp->qh.ptr->cap |= QH_IOS;
  1867. else if (mEp->type == USB_ENDPOINT_XFER_ISOC)
  1868. mEp->qh.ptr->cap &= ~QH_MULT;
  1869. else
  1870. mEp->qh.ptr->cap &= ~QH_ZLT;
  1871. mEp->qh.ptr->cap |=
  1872. (mEp->ep.maxpacket << ffs_nr(QH_MAX_PKT)) & QH_MAX_PKT;
  1873. mEp->qh.ptr->td.next |= TD_TERMINATE; /* needed? */
  1874. /*
  1875. * Enable endpoints in the HW other than ep0 as ep0
  1876. * is always enabled
  1877. */
  1878. if (mEp->num)
  1879. retval |= hw_ep_enable(mEp->udc, mEp->num, mEp->dir, mEp->type);
  1880. spin_unlock_irqrestore(mEp->lock, flags);
  1881. return retval;
  1882. }
  1883. /**
  1884. * ep_disable: endpoint is no longer usable
  1885. *
  1886. * Check usb_ep_disable() at "usb_gadget.h" for details
  1887. */
  1888. static int ep_disable(struct usb_ep *ep)
  1889. {
  1890. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1891. int direction, retval = 0;
  1892. unsigned long flags;
  1893. trace("%p", ep);
  1894. if (ep == NULL)
  1895. return -EINVAL;
  1896. else if (mEp->ep.desc == NULL)
  1897. return -EBUSY;
  1898. spin_lock_irqsave(mEp->lock, flags);
  1899. /* only internal SW should disable ctrl endpts */
  1900. direction = mEp->dir;
  1901. do {
  1902. dbg_event(_usb_addr(mEp), "DISABLE", 0);
  1903. retval |= _ep_nuke(mEp);
  1904. retval |= hw_ep_disable(mEp->udc, mEp->num, mEp->dir);
  1905. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  1906. mEp->dir = (mEp->dir == TX) ? RX : TX;
  1907. } while (mEp->dir != direction);
  1908. mEp->ep.desc = NULL;
  1909. spin_unlock_irqrestore(mEp->lock, flags);
  1910. return retval;
  1911. }
  1912. /**
  1913. * ep_alloc_request: allocate a request object to use with this endpoint
  1914. *
  1915. * Check usb_ep_alloc_request() at "usb_gadget.h" for details
  1916. */
  1917. static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
  1918. {
  1919. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1920. struct ci13xxx_req *mReq = NULL;
  1921. trace("%p, %i", ep, gfp_flags);
  1922. if (ep == NULL) {
  1923. pr_err("EINVAL\n");
  1924. return NULL;
  1925. }
  1926. mReq = kzalloc(sizeof(struct ci13xxx_req), gfp_flags);
  1927. if (mReq != NULL) {
  1928. INIT_LIST_HEAD(&mReq->queue);
  1929. mReq->req.dma = DMA_ADDR_INVALID;
  1930. mReq->ptr = dma_pool_alloc(mEp->td_pool, gfp_flags,
  1931. &mReq->dma);
  1932. if (mReq->ptr == NULL) {
  1933. kfree(mReq);
  1934. mReq = NULL;
  1935. }
  1936. }
  1937. dbg_event(_usb_addr(mEp), "ALLOC", mReq == NULL);
  1938. return (mReq == NULL) ? NULL : &mReq->req;
  1939. }
  1940. /**
  1941. * ep_free_request: frees a request object
  1942. *
  1943. * Check usb_ep_free_request() at "usb_gadget.h" for details
  1944. */
  1945. static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
  1946. {
  1947. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1948. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1949. unsigned long flags;
  1950. trace("%p, %p", ep, req);
  1951. if (ep == NULL || req == NULL) {
  1952. pr_err("EINVAL\n");
  1953. return;
  1954. } else if (!list_empty(&mReq->queue)) {
  1955. pr_err("EBUSY\n");
  1956. return;
  1957. }
  1958. spin_lock_irqsave(mEp->lock, flags);
  1959. if (mReq->ptr)
  1960. dma_pool_free(mEp->td_pool, mReq->ptr, mReq->dma);
  1961. kfree(mReq);
  1962. dbg_event(_usb_addr(mEp), "FREE", 0);
  1963. spin_unlock_irqrestore(mEp->lock, flags);
  1964. }
  1965. /**
  1966. * ep_queue: queues (submits) an I/O request to an endpoint
  1967. *
  1968. * Check usb_ep_queue()* at usb_gadget.h" for details
  1969. */
  1970. static int ep_queue(struct usb_ep *ep, struct usb_request *req,
  1971. gfp_t __maybe_unused gfp_flags)
  1972. {
  1973. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1974. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1975. int retval = 0;
  1976. unsigned long flags;
  1977. trace("%p, %p, %X", ep, req, gfp_flags);
  1978. if (ep == NULL || req == NULL || mEp->ep.desc == NULL)
  1979. return -EINVAL;
  1980. spin_lock_irqsave(mEp->lock, flags);
  1981. if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
  1982. if (req->length)
  1983. mEp = (_udc->ep0_dir == RX) ?
  1984. _udc->ep0out : _udc->ep0in;
  1985. if (!list_empty(&mEp->qh.queue)) {
  1986. _ep_nuke(mEp);
  1987. retval = -EOVERFLOW;
  1988. warn("endpoint ctrl %X nuked", _usb_addr(mEp));
  1989. }
  1990. }
  1991. /* first nuke then test link, e.g. previous status has not sent */
  1992. if (!list_empty(&mReq->queue)) {
  1993. retval = -EBUSY;
  1994. pr_err("request already in queue\n");
  1995. goto done;
  1996. }
  1997. if (req->length > 4 * CI13XXX_PAGE_SIZE) {
  1998. req->length = 4 * CI13XXX_PAGE_SIZE;
  1999. retval = -EMSGSIZE;
  2000. warn("request length truncated");
  2001. }
  2002. dbg_queue(_usb_addr(mEp), req, retval);
  2003. /* push request */
  2004. mReq->req.status = -EINPROGRESS;
  2005. mReq->req.actual = 0;
  2006. retval = _hardware_enqueue(mEp, mReq);
  2007. if (retval == -EALREADY) {
  2008. dbg_event(_usb_addr(mEp), "QUEUE", retval);
  2009. retval = 0;
  2010. }
  2011. if (!retval)
  2012. list_add_tail(&mReq->queue, &mEp->qh.queue);
  2013. done:
  2014. spin_unlock_irqrestore(mEp->lock, flags);
  2015. return retval;
  2016. }
  2017. /**
  2018. * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
  2019. *
  2020. * Check usb_ep_dequeue() at "usb_gadget.h" for details
  2021. */
  2022. static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
  2023. {
  2024. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2025. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  2026. unsigned long flags;
  2027. trace("%p, %p", ep, req);
  2028. if (ep == NULL || req == NULL || mReq->req.status != -EALREADY ||
  2029. mEp->ep.desc == NULL || list_empty(&mReq->queue) ||
  2030. list_empty(&mEp->qh.queue))
  2031. return -EINVAL;
  2032. spin_lock_irqsave(mEp->lock, flags);
  2033. dbg_event(_usb_addr(mEp), "DEQUEUE", 0);
  2034. hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
  2035. /* pop request */
  2036. list_del_init(&mReq->queue);
  2037. if (mReq->map) {
  2038. dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
  2039. mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  2040. mReq->req.dma = DMA_ADDR_INVALID;
  2041. mReq->map = 0;
  2042. }
  2043. req->status = -ECONNRESET;
  2044. if (mReq->req.complete != NULL) {
  2045. spin_unlock(mEp->lock);
  2046. mReq->req.complete(&mEp->ep, &mReq->req);
  2047. spin_lock(mEp->lock);
  2048. }
  2049. spin_unlock_irqrestore(mEp->lock, flags);
  2050. return 0;
  2051. }
  2052. /**
  2053. * ep_set_halt: sets the endpoint halt feature
  2054. *
  2055. * Check usb_ep_set_halt() at "usb_gadget.h" for details
  2056. */
  2057. static int ep_set_halt(struct usb_ep *ep, int value)
  2058. {
  2059. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2060. int direction, retval = 0;
  2061. unsigned long flags;
  2062. trace("%p, %i", ep, value);
  2063. if (ep == NULL || mEp->ep.desc == NULL)
  2064. return -EINVAL;
  2065. spin_lock_irqsave(mEp->lock, flags);
  2066. #ifndef STALL_IN
  2067. /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
  2068. if (value && mEp->type == USB_ENDPOINT_XFER_BULK && mEp->dir == TX &&
  2069. !list_empty(&mEp->qh.queue)) {
  2070. spin_unlock_irqrestore(mEp->lock, flags);
  2071. return -EAGAIN;
  2072. }
  2073. #endif
  2074. direction = mEp->dir;
  2075. do {
  2076. dbg_event(_usb_addr(mEp), "HALT", value);
  2077. retval |= hw_ep_set_halt(mEp->udc, mEp->num, mEp->dir, value);
  2078. if (!value)
  2079. mEp->wedge = 0;
  2080. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  2081. mEp->dir = (mEp->dir == TX) ? RX : TX;
  2082. } while (mEp->dir != direction);
  2083. spin_unlock_irqrestore(mEp->lock, flags);
  2084. return retval;
  2085. }
  2086. /**
  2087. * ep_set_wedge: sets the halt feature and ignores clear requests
  2088. *
  2089. * Check usb_ep_set_wedge() at "usb_gadget.h" for details
  2090. */
  2091. static int ep_set_wedge(struct usb_ep *ep)
  2092. {
  2093. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2094. unsigned long flags;
  2095. trace("%p", ep);
  2096. if (ep == NULL || mEp->ep.desc == NULL)
  2097. return -EINVAL;
  2098. spin_lock_irqsave(mEp->lock, flags);
  2099. dbg_event(_usb_addr(mEp), "WEDGE", 0);
  2100. mEp->wedge = 1;
  2101. spin_unlock_irqrestore(mEp->lock, flags);
  2102. return usb_ep_set_halt(ep);
  2103. }
  2104. /**
  2105. * ep_fifo_flush: flushes contents of a fifo
  2106. *
  2107. * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
  2108. */
  2109. static void ep_fifo_flush(struct usb_ep *ep)
  2110. {
  2111. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2112. unsigned long flags;
  2113. trace("%p", ep);
  2114. if (ep == NULL) {
  2115. pr_err("%02X: -EINVAL\n", _usb_addr(mEp));
  2116. return;
  2117. }
  2118. spin_lock_irqsave(mEp->lock, flags);
  2119. dbg_event(_usb_addr(mEp), "FFLUSH", 0);
  2120. hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
  2121. spin_unlock_irqrestore(mEp->lock, flags);
  2122. }
  2123. /**
  2124. * Endpoint-specific part of the API to the USB controller hardware
  2125. * Check "usb_gadget.h" for details
  2126. */
  2127. static const struct usb_ep_ops usb_ep_ops = {
  2128. .enable = ep_enable,
  2129. .disable = ep_disable,
  2130. .alloc_request = ep_alloc_request,
  2131. .free_request = ep_free_request,
  2132. .queue = ep_queue,
  2133. .dequeue = ep_dequeue,
  2134. .set_halt = ep_set_halt,
  2135. .set_wedge = ep_set_wedge,
  2136. .fifo_flush = ep_fifo_flush,
  2137. };
  2138. /******************************************************************************
  2139. * GADGET block
  2140. *****************************************************************************/
  2141. static int ci13xxx_vbus_session(struct usb_gadget *_gadget, int is_active)
  2142. {
  2143. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2144. unsigned long flags;
  2145. int gadget_ready = 0;
  2146. if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS))
  2147. return -EOPNOTSUPP;
  2148. spin_lock_irqsave(&udc->lock, flags);
  2149. udc->vbus_active = is_active;
  2150. if (udc->driver)
  2151. gadget_ready = 1;
  2152. spin_unlock_irqrestore(&udc->lock, flags);
  2153. if (gadget_ready) {
  2154. if (is_active) {
  2155. pm_runtime_get_sync(&_gadget->dev);
  2156. hw_device_reset(udc);
  2157. hw_device_state(udc, udc->ep0out->qh.dma);
  2158. } else {
  2159. hw_device_state(udc, 0);
  2160. if (udc->udc_driver->notify_event)
  2161. udc->udc_driver->notify_event(udc,
  2162. CI13XXX_CONTROLLER_STOPPED_EVENT);
  2163. _gadget_stop_activity(&udc->gadget);
  2164. pm_runtime_put_sync(&_gadget->dev);
  2165. }
  2166. }
  2167. return 0;
  2168. }
  2169. static int ci13xxx_wakeup(struct usb_gadget *_gadget)
  2170. {
  2171. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2172. unsigned long flags;
  2173. int ret = 0;
  2174. trace();
  2175. spin_lock_irqsave(&udc->lock, flags);
  2176. if (!udc->remote_wakeup) {
  2177. ret = -EOPNOTSUPP;
  2178. trace("remote wakeup feature is not enabled\n");
  2179. goto out;
  2180. }
  2181. if (!hw_read(udc, OP_PORTSC, PORTSC_SUSP)) {
  2182. ret = -EINVAL;
  2183. trace("port is not suspended\n");
  2184. goto out;
  2185. }
  2186. hw_write(udc, OP_PORTSC, PORTSC_FPR, PORTSC_FPR);
  2187. out:
  2188. spin_unlock_irqrestore(&udc->lock, flags);
  2189. return ret;
  2190. }
  2191. static int ci13xxx_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
  2192. {
  2193. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2194. if (udc->transceiver)
  2195. return usb_phy_set_power(udc->transceiver, mA);
  2196. return -ENOTSUPP;
  2197. }
  2198. static int ci13xxx_start(struct usb_gadget_driver *driver,
  2199. int (*bind)(struct usb_gadget *));
  2200. static int ci13xxx_stop(struct usb_gadget_driver *driver);
  2201. /**
  2202. * Device operations part of the API to the USB controller hardware,
  2203. * which don't involve endpoints (or i/o)
  2204. * Check "usb_gadget.h" for details
  2205. */
  2206. static const struct usb_gadget_ops usb_gadget_ops = {
  2207. .vbus_session = ci13xxx_vbus_session,
  2208. .wakeup = ci13xxx_wakeup,
  2209. .vbus_draw = ci13xxx_vbus_draw,
  2210. .start = ci13xxx_start,
  2211. .stop = ci13xxx_stop,
  2212. };
  2213. /**
  2214. * ci13xxx_start: register a gadget driver
  2215. * @driver: the driver being registered
  2216. * @bind: the driver's bind callback
  2217. *
  2218. * Check ci13xxx_start() at <linux/usb/gadget.h> for details.
  2219. * Interrupts are enabled here.
  2220. */
  2221. static int ci13xxx_start(struct usb_gadget_driver *driver,
  2222. int (*bind)(struct usb_gadget *))
  2223. {
  2224. struct ci13xxx *udc = _udc;
  2225. unsigned long flags;
  2226. int i, j;
  2227. int retval = -ENOMEM;
  2228. trace("%p", driver);
  2229. if (driver == NULL ||
  2230. bind == NULL ||
  2231. driver->setup == NULL ||
  2232. driver->disconnect == NULL)
  2233. return -EINVAL;
  2234. else if (udc == NULL)
  2235. return -ENODEV;
  2236. else if (udc->driver != NULL)
  2237. return -EBUSY;
  2238. /* alloc resources */
  2239. udc->qh_pool = dma_pool_create("ci13xxx_qh", &udc->gadget.dev,
  2240. sizeof(struct ci13xxx_qh),
  2241. 64, CI13XXX_PAGE_SIZE);
  2242. if (udc->qh_pool == NULL)
  2243. return -ENOMEM;
  2244. udc->td_pool = dma_pool_create("ci13xxx_td", &udc->gadget.dev,
  2245. sizeof(struct ci13xxx_td),
  2246. 64, CI13XXX_PAGE_SIZE);
  2247. if (udc->td_pool == NULL) {
  2248. dma_pool_destroy(udc->qh_pool);
  2249. udc->qh_pool = NULL;
  2250. return -ENOMEM;
  2251. }
  2252. spin_lock_irqsave(&udc->lock, flags);
  2253. info("hw_ep_max = %d", udc->hw_ep_max);
  2254. udc->gadget.dev.driver = NULL;
  2255. retval = 0;
  2256. for (i = 0; i < udc->hw_ep_max/2; i++) {
  2257. for (j = RX; j <= TX; j++) {
  2258. int k = i + j * udc->hw_ep_max/2;
  2259. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[k];
  2260. scnprintf(mEp->name, sizeof(mEp->name), "ep%i%s", i,
  2261. (j == TX) ? "in" : "out");
  2262. mEp->udc = udc;
  2263. mEp->lock = &udc->lock;
  2264. mEp->device = &udc->gadget.dev;
  2265. mEp->td_pool = udc->td_pool;
  2266. mEp->ep.name = mEp->name;
  2267. mEp->ep.ops = &usb_ep_ops;
  2268. mEp->ep.maxpacket = CTRL_PAYLOAD_MAX;
  2269. INIT_LIST_HEAD(&mEp->qh.queue);
  2270. spin_unlock_irqrestore(&udc->lock, flags);
  2271. mEp->qh.ptr = dma_pool_alloc(udc->qh_pool, GFP_KERNEL,
  2272. &mEp->qh.dma);
  2273. spin_lock_irqsave(&udc->lock, flags);
  2274. if (mEp->qh.ptr == NULL)
  2275. retval = -ENOMEM;
  2276. else
  2277. memset(mEp->qh.ptr, 0, sizeof(*mEp->qh.ptr));
  2278. /*
  2279. * set up shorthands for ep0 out and in endpoints,
  2280. * don't add to gadget's ep_list
  2281. */
  2282. if (i == 0) {
  2283. if (j == RX)
  2284. udc->ep0out = mEp;
  2285. else
  2286. udc->ep0in = mEp;
  2287. continue;
  2288. }
  2289. list_add_tail(&mEp->ep.ep_list, &udc->gadget.ep_list);
  2290. }
  2291. }
  2292. if (retval)
  2293. goto done;
  2294. spin_unlock_irqrestore(&udc->lock, flags);
  2295. udc->ep0out->ep.desc = &ctrl_endpt_out_desc;
  2296. retval = usb_ep_enable(&udc->ep0out->ep);
  2297. if (retval)
  2298. return retval;
  2299. udc->ep0in->ep.desc = &ctrl_endpt_in_desc;
  2300. retval = usb_ep_enable(&udc->ep0in->ep);
  2301. if (retval)
  2302. return retval;
  2303. spin_lock_irqsave(&udc->lock, flags);
  2304. udc->gadget.ep0 = &udc->ep0in->ep;
  2305. /* bind gadget */
  2306. driver->driver.bus = NULL;
  2307. udc->gadget.dev.driver = &driver->driver;
  2308. spin_unlock_irqrestore(&udc->lock, flags);
  2309. retval = bind(&udc->gadget); /* MAY SLEEP */
  2310. spin_lock_irqsave(&udc->lock, flags);
  2311. if (retval) {
  2312. udc->gadget.dev.driver = NULL;
  2313. goto done;
  2314. }
  2315. udc->driver = driver;
  2316. pm_runtime_get_sync(&udc->gadget.dev);
  2317. if (udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) {
  2318. if (udc->vbus_active) {
  2319. if (udc->udc_driver->flags & CI13XXX_REGS_SHARED)
  2320. hw_device_reset(udc);
  2321. } else {
  2322. pm_runtime_put_sync(&udc->gadget.dev);
  2323. goto done;
  2324. }
  2325. }
  2326. retval = hw_device_state(udc, udc->ep0out->qh.dma);
  2327. if (retval)
  2328. pm_runtime_put_sync(&udc->gadget.dev);
  2329. done:
  2330. spin_unlock_irqrestore(&udc->lock, flags);
  2331. return retval;
  2332. }
  2333. /**
  2334. * ci13xxx_stop: unregister a gadget driver
  2335. *
  2336. * Check usb_gadget_unregister_driver() at "usb_gadget.h" for details
  2337. */
  2338. static int ci13xxx_stop(struct usb_gadget_driver *driver)
  2339. {
  2340. struct ci13xxx *udc = _udc;
  2341. unsigned long i, flags;
  2342. trace("%p", driver);
  2343. if (driver == NULL ||
  2344. driver->unbind == NULL ||
  2345. driver->setup == NULL ||
  2346. driver->disconnect == NULL ||
  2347. driver != udc->driver)
  2348. return -EINVAL;
  2349. spin_lock_irqsave(&udc->lock, flags);
  2350. if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) ||
  2351. udc->vbus_active) {
  2352. hw_device_state(udc, 0);
  2353. if (udc->udc_driver->notify_event)
  2354. udc->udc_driver->notify_event(udc,
  2355. CI13XXX_CONTROLLER_STOPPED_EVENT);
  2356. spin_unlock_irqrestore(&udc->lock, flags);
  2357. _gadget_stop_activity(&udc->gadget);
  2358. spin_lock_irqsave(&udc->lock, flags);
  2359. pm_runtime_put(&udc->gadget.dev);
  2360. }
  2361. /* unbind gadget */
  2362. spin_unlock_irqrestore(&udc->lock, flags);
  2363. driver->unbind(&udc->gadget); /* MAY SLEEP */
  2364. spin_lock_irqsave(&udc->lock, flags);
  2365. udc->gadget.dev.driver = NULL;
  2366. /* free resources */
  2367. for (i = 0; i < udc->hw_ep_max; i++) {
  2368. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
  2369. if (mEp->num)
  2370. list_del_init(&mEp->ep.ep_list);
  2371. if (mEp->qh.ptr != NULL)
  2372. dma_pool_free(udc->qh_pool, mEp->qh.ptr, mEp->qh.dma);
  2373. }
  2374. udc->gadget.ep0 = NULL;
  2375. udc->driver = NULL;
  2376. spin_unlock_irqrestore(&udc->lock, flags);
  2377. if (udc->td_pool != NULL) {
  2378. dma_pool_destroy(udc->td_pool);
  2379. udc->td_pool = NULL;
  2380. }
  2381. if (udc->qh_pool != NULL) {
  2382. dma_pool_destroy(udc->qh_pool);
  2383. udc->qh_pool = NULL;
  2384. }
  2385. return 0;
  2386. }
  2387. /******************************************************************************
  2388. * BUS block
  2389. *****************************************************************************/
  2390. /**
  2391. * udc_irq: global interrupt handler
  2392. *
  2393. * This function returns IRQ_HANDLED if the IRQ has been handled
  2394. * It locks access to registers
  2395. */
  2396. static irqreturn_t udc_irq(int irq, void *data)
  2397. {
  2398. struct ci13xxx *udc = _udc;
  2399. irqreturn_t retval;
  2400. u32 intr;
  2401. trace();
  2402. if (udc == NULL) {
  2403. pr_err("ENODEV\n");
  2404. return IRQ_HANDLED;
  2405. }
  2406. spin_lock(&udc->lock);
  2407. if (udc->udc_driver->flags & CI13XXX_REGS_SHARED) {
  2408. if (hw_read(udc, OP_USBMODE, USBMODE_CM) !=
  2409. USBMODE_CM_DEVICE) {
  2410. spin_unlock(&udc->lock);
  2411. return IRQ_NONE;
  2412. }
  2413. }
  2414. intr = hw_test_and_clear_intr_active(udc);
  2415. if (intr) {
  2416. isr_statistics.hndl.buf[isr_statistics.hndl.idx++] = intr;
  2417. isr_statistics.hndl.idx &= ISR_MASK;
  2418. isr_statistics.hndl.cnt++;
  2419. /* order defines priority - do NOT change it */
  2420. if (USBi_URI & intr) {
  2421. isr_statistics.uri++;
  2422. isr_reset_handler(udc);
  2423. }
  2424. if (USBi_PCI & intr) {
  2425. isr_statistics.pci++;
  2426. udc->gadget.speed = hw_port_is_high_speed(udc) ?
  2427. USB_SPEED_HIGH : USB_SPEED_FULL;
  2428. if (udc->suspended && udc->driver->resume) {
  2429. spin_unlock(&udc->lock);
  2430. udc->driver->resume(&udc->gadget);
  2431. spin_lock(&udc->lock);
  2432. udc->suspended = 0;
  2433. }
  2434. }
  2435. if (USBi_UEI & intr)
  2436. isr_statistics.uei++;
  2437. if (USBi_UI & intr) {
  2438. isr_statistics.ui++;
  2439. isr_tr_complete_handler(udc);
  2440. }
  2441. if (USBi_SLI & intr) {
  2442. if (udc->gadget.speed != USB_SPEED_UNKNOWN &&
  2443. udc->driver->suspend) {
  2444. udc->suspended = 1;
  2445. spin_unlock(&udc->lock);
  2446. udc->driver->suspend(&udc->gadget);
  2447. spin_lock(&udc->lock);
  2448. }
  2449. isr_statistics.sli++;
  2450. }
  2451. retval = IRQ_HANDLED;
  2452. } else {
  2453. isr_statistics.none++;
  2454. retval = IRQ_NONE;
  2455. }
  2456. spin_unlock(&udc->lock);
  2457. return retval;
  2458. }
  2459. /**
  2460. * udc_release: driver release function
  2461. * @dev: device
  2462. *
  2463. * Currently does nothing
  2464. */
  2465. static void udc_release(struct device *dev)
  2466. {
  2467. trace("%p", dev);
  2468. if (dev == NULL)
  2469. pr_err("EINVAL\n");
  2470. }
  2471. /**
  2472. * udc_probe: parent probe must call this to initialize UDC
  2473. * @dev: parent device
  2474. * @regs: registers base address
  2475. * @name: driver name
  2476. *
  2477. * This function returns an error code
  2478. * No interrupts active, the IRQ has not been requested yet
  2479. * Kernel assumes 32-bit DMA operations by default, no need to dma_set_mask
  2480. */
  2481. static int udc_probe(struct ci13xxx_udc_driver *driver, struct device *dev,
  2482. void __iomem *regs)
  2483. {
  2484. struct ci13xxx *udc;
  2485. int retval = 0;
  2486. trace("%p, %p, %p", dev, regs, driver->name);
  2487. if (dev == NULL || regs == NULL || driver == NULL ||
  2488. driver->name == NULL)
  2489. return -EINVAL;
  2490. udc = kzalloc(sizeof(struct ci13xxx), GFP_KERNEL);
  2491. if (udc == NULL)
  2492. return -ENOMEM;
  2493. spin_lock_init(&udc->lock);
  2494. udc->regs = regs;
  2495. udc->udc_driver = driver;
  2496. udc->gadget.ops = &usb_gadget_ops;
  2497. udc->gadget.speed = USB_SPEED_UNKNOWN;
  2498. udc->gadget.max_speed = USB_SPEED_HIGH;
  2499. udc->gadget.is_otg = 0;
  2500. udc->gadget.name = driver->name;
  2501. INIT_LIST_HEAD(&udc->gadget.ep_list);
  2502. udc->gadget.ep0 = NULL;
  2503. dev_set_name(&udc->gadget.dev, "gadget");
  2504. udc->gadget.dev.dma_mask = dev->dma_mask;
  2505. udc->gadget.dev.coherent_dma_mask = dev->coherent_dma_mask;
  2506. udc->gadget.dev.parent = dev;
  2507. udc->gadget.dev.release = udc_release;
  2508. retval = hw_device_init(udc, regs, driver->capoffset);
  2509. if (retval < 0)
  2510. goto free_udc;
  2511. udc->transceiver = usb_get_transceiver();
  2512. if (udc->udc_driver->flags & CI13XXX_REQUIRE_TRANSCEIVER) {
  2513. if (udc->transceiver == NULL) {
  2514. retval = -ENODEV;
  2515. goto free_udc;
  2516. }
  2517. }
  2518. if (!(udc->udc_driver->flags & CI13XXX_REGS_SHARED)) {
  2519. retval = hw_device_reset(udc);
  2520. if (retval)
  2521. goto put_transceiver;
  2522. }
  2523. retval = device_register(&udc->gadget.dev);
  2524. if (retval) {
  2525. put_device(&udc->gadget.dev);
  2526. goto put_transceiver;
  2527. }
  2528. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2529. retval = dbg_create_files(&udc->gadget.dev);
  2530. #endif
  2531. if (retval)
  2532. goto unreg_device;
  2533. if (udc->transceiver) {
  2534. retval = otg_set_peripheral(udc->transceiver->otg,
  2535. &udc->gadget);
  2536. if (retval)
  2537. goto remove_dbg;
  2538. }
  2539. retval = usb_add_gadget_udc(dev, &udc->gadget);
  2540. if (retval)
  2541. goto remove_trans;
  2542. pm_runtime_no_callbacks(&udc->gadget.dev);
  2543. pm_runtime_enable(&udc->gadget.dev);
  2544. _udc = udc;
  2545. return retval;
  2546. remove_trans:
  2547. if (udc->transceiver) {
  2548. otg_set_peripheral(udc->transceiver->otg, &udc->gadget);
  2549. usb_put_transceiver(udc->transceiver);
  2550. }
  2551. dev_err(dev, "error = %i\n", retval);
  2552. remove_dbg:
  2553. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2554. dbg_remove_files(&udc->gadget.dev);
  2555. #endif
  2556. unreg_device:
  2557. device_unregister(&udc->gadget.dev);
  2558. put_transceiver:
  2559. if (udc->transceiver)
  2560. usb_put_transceiver(udc->transceiver);
  2561. free_udc:
  2562. kfree(udc);
  2563. _udc = NULL;
  2564. return retval;
  2565. }
  2566. /**
  2567. * udc_remove: parent remove must call this to remove UDC
  2568. *
  2569. * No interrupts active, the IRQ has been released
  2570. */
  2571. static void udc_remove(void)
  2572. {
  2573. struct ci13xxx *udc = _udc;
  2574. if (udc == NULL) {
  2575. pr_err("EINVAL\n");
  2576. return;
  2577. }
  2578. usb_del_gadget_udc(&udc->gadget);
  2579. if (udc->transceiver) {
  2580. otg_set_peripheral(udc->transceiver->otg, &udc->gadget);
  2581. usb_put_transceiver(udc->transceiver);
  2582. }
  2583. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2584. dbg_remove_files(&udc->gadget.dev);
  2585. #endif
  2586. device_unregister(&udc->gadget.dev);
  2587. kfree(udc->hw_bank.regmap);
  2588. kfree(udc);
  2589. _udc = NULL;
  2590. }
  2591. static int __devinit ci_udc_probe(struct platform_device *pdev)
  2592. {
  2593. struct device *dev = &pdev->dev;
  2594. struct ci13xxx_udc_driver *driver = dev->platform_data;
  2595. struct resource *res;
  2596. void __iomem *base;
  2597. int ret;
  2598. if (!driver) {
  2599. dev_err(dev, "platform data missing\n");
  2600. return -ENODEV;
  2601. }
  2602. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2603. if (!res) {
  2604. dev_err(dev, "missing resource\n");
  2605. return -ENODEV;
  2606. }
  2607. base = devm_request_and_ioremap(dev, res);
  2608. if (!res) {
  2609. dev_err(dev, "can't request and ioremap resource\n");
  2610. return -ENOMEM;
  2611. }
  2612. ret = udc_probe(driver, dev, base);
  2613. if (ret)
  2614. return ret;
  2615. _udc->irq = platform_get_irq(pdev, 0);
  2616. if (_udc->irq < 0) {
  2617. dev_err(dev, "missing IRQ\n");
  2618. ret = -ENODEV;
  2619. goto out;
  2620. }
  2621. ret = request_irq(_udc->irq, udc_irq, IRQF_SHARED, driver->name, _udc);
  2622. out:
  2623. if (ret)
  2624. udc_remove();
  2625. return ret;
  2626. }
  2627. static int __devexit ci_udc_remove(struct platform_device *pdev)
  2628. {
  2629. free_irq(_udc->irq, _udc);
  2630. udc_remove();
  2631. return 0;
  2632. }
  2633. static struct platform_driver ci_udc_driver = {
  2634. .probe = ci_udc_probe,
  2635. .remove = __devexit_p(ci_udc_remove),
  2636. .driver = {
  2637. .name = "ci_udc",
  2638. },
  2639. };
  2640. module_platform_driver(ci_udc_driver);
  2641. MODULE_ALIAS("platform:ci_udc");
  2642. MODULE_ALIAS("platform:ci13xxx");
  2643. MODULE_LICENSE("GPL v2");
  2644. MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
  2645. MODULE_DESCRIPTION("ChipIdea UDC Driver");