qeth_core_main.c 130 KB

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  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007, 2009
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #define KMSG_COMPONENT "qeth"
  11. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/string.h>
  15. #include <linux/errno.h>
  16. #include <linux/kernel.h>
  17. #include <linux/ip.h>
  18. #include <linux/tcp.h>
  19. #include <linux/mii.h>
  20. #include <linux/kthread.h>
  21. #include <linux/slab.h>
  22. #include <asm/ebcdic.h>
  23. #include <asm/io.h>
  24. #include "qeth_core.h"
  25. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  26. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  27. /* N P A M L V H */
  28. [QETH_DBF_SETUP] = {"qeth_setup",
  29. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  30. [QETH_DBF_MSG] = {"qeth_msg",
  31. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  32. [QETH_DBF_CTRL] = {"qeth_control",
  33. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  34. };
  35. EXPORT_SYMBOL_GPL(qeth_dbf);
  36. struct qeth_card_list_struct qeth_core_card_list;
  37. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  38. struct kmem_cache *qeth_core_header_cache;
  39. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  40. static struct device *qeth_core_root_dev;
  41. static unsigned int known_devices[][6] = QETH_MODELLIST_ARRAY;
  42. static struct lock_class_key qdio_out_skb_queue_key;
  43. static void qeth_send_control_data_cb(struct qeth_channel *,
  44. struct qeth_cmd_buffer *);
  45. static int qeth_issue_next_read(struct qeth_card *);
  46. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  47. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  48. static void qeth_free_buffer_pool(struct qeth_card *);
  49. static int qeth_qdio_establish(struct qeth_card *);
  50. static inline const char *qeth_get_cardname(struct qeth_card *card)
  51. {
  52. if (card->info.guestlan) {
  53. switch (card->info.type) {
  54. case QETH_CARD_TYPE_OSD:
  55. return " Guest LAN QDIO";
  56. case QETH_CARD_TYPE_IQD:
  57. return " Guest LAN Hiper";
  58. case QETH_CARD_TYPE_OSM:
  59. return " Guest LAN QDIO - OSM";
  60. case QETH_CARD_TYPE_OSX:
  61. return " Guest LAN QDIO - OSX";
  62. default:
  63. return " unknown";
  64. }
  65. } else {
  66. switch (card->info.type) {
  67. case QETH_CARD_TYPE_OSD:
  68. return " OSD Express";
  69. case QETH_CARD_TYPE_IQD:
  70. return " HiperSockets";
  71. case QETH_CARD_TYPE_OSN:
  72. return " OSN QDIO";
  73. case QETH_CARD_TYPE_OSM:
  74. return " OSM QDIO";
  75. case QETH_CARD_TYPE_OSX:
  76. return " OSX QDIO";
  77. default:
  78. return " unknown";
  79. }
  80. }
  81. return " n/a";
  82. }
  83. /* max length to be returned: 14 */
  84. const char *qeth_get_cardname_short(struct qeth_card *card)
  85. {
  86. if (card->info.guestlan) {
  87. switch (card->info.type) {
  88. case QETH_CARD_TYPE_OSD:
  89. return "GuestLAN QDIO";
  90. case QETH_CARD_TYPE_IQD:
  91. return "GuestLAN Hiper";
  92. case QETH_CARD_TYPE_OSM:
  93. return "GuestLAN OSM";
  94. case QETH_CARD_TYPE_OSX:
  95. return "GuestLAN OSX";
  96. default:
  97. return "unknown";
  98. }
  99. } else {
  100. switch (card->info.type) {
  101. case QETH_CARD_TYPE_OSD:
  102. switch (card->info.link_type) {
  103. case QETH_LINK_TYPE_FAST_ETH:
  104. return "OSD_100";
  105. case QETH_LINK_TYPE_HSTR:
  106. return "HSTR";
  107. case QETH_LINK_TYPE_GBIT_ETH:
  108. return "OSD_1000";
  109. case QETH_LINK_TYPE_10GBIT_ETH:
  110. return "OSD_10GIG";
  111. case QETH_LINK_TYPE_LANE_ETH100:
  112. return "OSD_FE_LANE";
  113. case QETH_LINK_TYPE_LANE_TR:
  114. return "OSD_TR_LANE";
  115. case QETH_LINK_TYPE_LANE_ETH1000:
  116. return "OSD_GbE_LANE";
  117. case QETH_LINK_TYPE_LANE:
  118. return "OSD_ATM_LANE";
  119. default:
  120. return "OSD_Express";
  121. }
  122. case QETH_CARD_TYPE_IQD:
  123. return "HiperSockets";
  124. case QETH_CARD_TYPE_OSN:
  125. return "OSN";
  126. case QETH_CARD_TYPE_OSM:
  127. return "OSM_1000";
  128. case QETH_CARD_TYPE_OSX:
  129. return "OSX_10GIG";
  130. default:
  131. return "unknown";
  132. }
  133. }
  134. return "n/a";
  135. }
  136. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  137. int clear_start_mask)
  138. {
  139. unsigned long flags;
  140. spin_lock_irqsave(&card->thread_mask_lock, flags);
  141. card->thread_allowed_mask = threads;
  142. if (clear_start_mask)
  143. card->thread_start_mask &= threads;
  144. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  145. wake_up(&card->wait_q);
  146. }
  147. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  148. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  149. {
  150. unsigned long flags;
  151. int rc = 0;
  152. spin_lock_irqsave(&card->thread_mask_lock, flags);
  153. rc = (card->thread_running_mask & threads);
  154. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  155. return rc;
  156. }
  157. EXPORT_SYMBOL_GPL(qeth_threads_running);
  158. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  159. {
  160. return wait_event_interruptible(card->wait_q,
  161. qeth_threads_running(card, threads) == 0);
  162. }
  163. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  164. void qeth_clear_working_pool_list(struct qeth_card *card)
  165. {
  166. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  167. QETH_CARD_TEXT(card, 5, "clwrklst");
  168. list_for_each_entry_safe(pool_entry, tmp,
  169. &card->qdio.in_buf_pool.entry_list, list){
  170. list_del(&pool_entry->list);
  171. }
  172. }
  173. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  174. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  175. {
  176. struct qeth_buffer_pool_entry *pool_entry;
  177. void *ptr;
  178. int i, j;
  179. QETH_CARD_TEXT(card, 5, "alocpool");
  180. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  181. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  182. if (!pool_entry) {
  183. qeth_free_buffer_pool(card);
  184. return -ENOMEM;
  185. }
  186. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  187. ptr = (void *) __get_free_page(GFP_KERNEL);
  188. if (!ptr) {
  189. while (j > 0)
  190. free_page((unsigned long)
  191. pool_entry->elements[--j]);
  192. kfree(pool_entry);
  193. qeth_free_buffer_pool(card);
  194. return -ENOMEM;
  195. }
  196. pool_entry->elements[j] = ptr;
  197. }
  198. list_add(&pool_entry->init_list,
  199. &card->qdio.init_pool.entry_list);
  200. }
  201. return 0;
  202. }
  203. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  204. {
  205. QETH_CARD_TEXT(card, 2, "realcbp");
  206. if ((card->state != CARD_STATE_DOWN) &&
  207. (card->state != CARD_STATE_RECOVER))
  208. return -EPERM;
  209. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  210. qeth_clear_working_pool_list(card);
  211. qeth_free_buffer_pool(card);
  212. card->qdio.in_buf_pool.buf_count = bufcnt;
  213. card->qdio.init_pool.buf_count = bufcnt;
  214. return qeth_alloc_buffer_pool(card);
  215. }
  216. EXPORT_SYMBOL_GPL(qeth_realloc_buffer_pool);
  217. static int qeth_issue_next_read(struct qeth_card *card)
  218. {
  219. int rc;
  220. struct qeth_cmd_buffer *iob;
  221. QETH_CARD_TEXT(card, 5, "issnxrd");
  222. if (card->read.state != CH_STATE_UP)
  223. return -EIO;
  224. iob = qeth_get_buffer(&card->read);
  225. if (!iob) {
  226. dev_warn(&card->gdev->dev, "The qeth device driver "
  227. "failed to recover an error on the device\n");
  228. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  229. "available\n", dev_name(&card->gdev->dev));
  230. return -ENOMEM;
  231. }
  232. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  233. QETH_CARD_TEXT(card, 6, "noirqpnd");
  234. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  235. (addr_t) iob, 0, 0);
  236. if (rc) {
  237. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  238. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  239. atomic_set(&card->read.irq_pending, 0);
  240. qeth_schedule_recovery(card);
  241. wake_up(&card->wait_q);
  242. }
  243. return rc;
  244. }
  245. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  246. {
  247. struct qeth_reply *reply;
  248. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  249. if (reply) {
  250. atomic_set(&reply->refcnt, 1);
  251. atomic_set(&reply->received, 0);
  252. reply->card = card;
  253. };
  254. return reply;
  255. }
  256. static void qeth_get_reply(struct qeth_reply *reply)
  257. {
  258. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  259. atomic_inc(&reply->refcnt);
  260. }
  261. static void qeth_put_reply(struct qeth_reply *reply)
  262. {
  263. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  264. if (atomic_dec_and_test(&reply->refcnt))
  265. kfree(reply);
  266. }
  267. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  268. struct qeth_card *card)
  269. {
  270. char *ipa_name;
  271. int com = cmd->hdr.command;
  272. ipa_name = qeth_get_ipa_cmd_name(com);
  273. if (rc)
  274. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
  275. ipa_name, com, QETH_CARD_IFNAME(card),
  276. rc, qeth_get_ipa_msg(rc));
  277. else
  278. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
  279. ipa_name, com, QETH_CARD_IFNAME(card));
  280. }
  281. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  282. struct qeth_cmd_buffer *iob)
  283. {
  284. struct qeth_ipa_cmd *cmd = NULL;
  285. QETH_CARD_TEXT(card, 5, "chkipad");
  286. if (IS_IPA(iob->data)) {
  287. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  288. if (IS_IPA_REPLY(cmd)) {
  289. if (cmd->hdr.command != IPA_CMD_SETCCID &&
  290. cmd->hdr.command != IPA_CMD_DELCCID &&
  291. cmd->hdr.command != IPA_CMD_MODCCID &&
  292. cmd->hdr.command != IPA_CMD_SET_DIAG_ASS)
  293. qeth_issue_ipa_msg(cmd,
  294. cmd->hdr.return_code, card);
  295. return cmd;
  296. } else {
  297. switch (cmd->hdr.command) {
  298. case IPA_CMD_STOPLAN:
  299. dev_warn(&card->gdev->dev,
  300. "The link for interface %s on CHPID"
  301. " 0x%X failed\n",
  302. QETH_CARD_IFNAME(card),
  303. card->info.chpid);
  304. card->lan_online = 0;
  305. if (card->dev && netif_carrier_ok(card->dev))
  306. netif_carrier_off(card->dev);
  307. return NULL;
  308. case IPA_CMD_STARTLAN:
  309. dev_info(&card->gdev->dev,
  310. "The link for %s on CHPID 0x%X has"
  311. " been restored\n",
  312. QETH_CARD_IFNAME(card),
  313. card->info.chpid);
  314. netif_carrier_on(card->dev);
  315. card->lan_online = 1;
  316. qeth_schedule_recovery(card);
  317. return NULL;
  318. case IPA_CMD_MODCCID:
  319. return cmd;
  320. case IPA_CMD_REGISTER_LOCAL_ADDR:
  321. QETH_CARD_TEXT(card, 3, "irla");
  322. break;
  323. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  324. QETH_CARD_TEXT(card, 3, "urla");
  325. break;
  326. default:
  327. QETH_DBF_MESSAGE(2, "Received data is IPA "
  328. "but not a reply!\n");
  329. break;
  330. }
  331. }
  332. }
  333. return cmd;
  334. }
  335. void qeth_clear_ipacmd_list(struct qeth_card *card)
  336. {
  337. struct qeth_reply *reply, *r;
  338. unsigned long flags;
  339. QETH_CARD_TEXT(card, 4, "clipalst");
  340. spin_lock_irqsave(&card->lock, flags);
  341. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  342. qeth_get_reply(reply);
  343. reply->rc = -EIO;
  344. atomic_inc(&reply->received);
  345. list_del_init(&reply->list);
  346. wake_up(&reply->wait_q);
  347. qeth_put_reply(reply);
  348. }
  349. spin_unlock_irqrestore(&card->lock, flags);
  350. }
  351. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  352. static int qeth_check_idx_response(struct qeth_card *card,
  353. unsigned char *buffer)
  354. {
  355. if (!buffer)
  356. return 0;
  357. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  358. if ((buffer[2] & 0xc0) == 0xc0) {
  359. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  360. "with cause code 0x%02x%s\n",
  361. buffer[4],
  362. ((buffer[4] == 0x22) ?
  363. " -- try another portname" : ""));
  364. QETH_CARD_TEXT(card, 2, "ckidxres");
  365. QETH_CARD_TEXT(card, 2, " idxterm");
  366. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  367. if (buffer[4] == 0xf6) {
  368. dev_err(&card->gdev->dev,
  369. "The qeth device is not configured "
  370. "for the OSI layer required by z/VM\n");
  371. return -EPERM;
  372. }
  373. return -EIO;
  374. }
  375. return 0;
  376. }
  377. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  378. __u32 len)
  379. {
  380. struct qeth_card *card;
  381. card = CARD_FROM_CDEV(channel->ccwdev);
  382. QETH_CARD_TEXT(card, 4, "setupccw");
  383. if (channel == &card->read)
  384. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  385. else
  386. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  387. channel->ccw.count = len;
  388. channel->ccw.cda = (__u32) __pa(iob);
  389. }
  390. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  391. {
  392. __u8 index;
  393. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "getbuff");
  394. index = channel->io_buf_no;
  395. do {
  396. if (channel->iob[index].state == BUF_STATE_FREE) {
  397. channel->iob[index].state = BUF_STATE_LOCKED;
  398. channel->io_buf_no = (channel->io_buf_no + 1) %
  399. QETH_CMD_BUFFER_NO;
  400. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  401. return channel->iob + index;
  402. }
  403. index = (index + 1) % QETH_CMD_BUFFER_NO;
  404. } while (index != channel->io_buf_no);
  405. return NULL;
  406. }
  407. void qeth_release_buffer(struct qeth_channel *channel,
  408. struct qeth_cmd_buffer *iob)
  409. {
  410. unsigned long flags;
  411. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "relbuff");
  412. spin_lock_irqsave(&channel->iob_lock, flags);
  413. memset(iob->data, 0, QETH_BUFSIZE);
  414. iob->state = BUF_STATE_FREE;
  415. iob->callback = qeth_send_control_data_cb;
  416. iob->rc = 0;
  417. spin_unlock_irqrestore(&channel->iob_lock, flags);
  418. }
  419. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  420. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  421. {
  422. struct qeth_cmd_buffer *buffer = NULL;
  423. unsigned long flags;
  424. spin_lock_irqsave(&channel->iob_lock, flags);
  425. buffer = __qeth_get_buffer(channel);
  426. spin_unlock_irqrestore(&channel->iob_lock, flags);
  427. return buffer;
  428. }
  429. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  430. {
  431. struct qeth_cmd_buffer *buffer;
  432. wait_event(channel->wait_q,
  433. ((buffer = qeth_get_buffer(channel)) != NULL));
  434. return buffer;
  435. }
  436. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  437. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  438. {
  439. int cnt;
  440. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  441. qeth_release_buffer(channel, &channel->iob[cnt]);
  442. channel->buf_no = 0;
  443. channel->io_buf_no = 0;
  444. }
  445. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  446. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  447. struct qeth_cmd_buffer *iob)
  448. {
  449. struct qeth_card *card;
  450. struct qeth_reply *reply, *r;
  451. struct qeth_ipa_cmd *cmd;
  452. unsigned long flags;
  453. int keep_reply;
  454. int rc = 0;
  455. card = CARD_FROM_CDEV(channel->ccwdev);
  456. QETH_CARD_TEXT(card, 4, "sndctlcb");
  457. rc = qeth_check_idx_response(card, iob->data);
  458. switch (rc) {
  459. case 0:
  460. break;
  461. case -EIO:
  462. qeth_clear_ipacmd_list(card);
  463. qeth_schedule_recovery(card);
  464. /* fall through */
  465. default:
  466. goto out;
  467. }
  468. cmd = qeth_check_ipa_data(card, iob);
  469. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  470. goto out;
  471. /*in case of OSN : check if cmd is set */
  472. if (card->info.type == QETH_CARD_TYPE_OSN &&
  473. cmd &&
  474. cmd->hdr.command != IPA_CMD_STARTLAN &&
  475. card->osn_info.assist_cb != NULL) {
  476. card->osn_info.assist_cb(card->dev, cmd);
  477. goto out;
  478. }
  479. spin_lock_irqsave(&card->lock, flags);
  480. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  481. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  482. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  483. qeth_get_reply(reply);
  484. list_del_init(&reply->list);
  485. spin_unlock_irqrestore(&card->lock, flags);
  486. keep_reply = 0;
  487. if (reply->callback != NULL) {
  488. if (cmd) {
  489. reply->offset = (__u16)((char *)cmd -
  490. (char *)iob->data);
  491. keep_reply = reply->callback(card,
  492. reply,
  493. (unsigned long)cmd);
  494. } else
  495. keep_reply = reply->callback(card,
  496. reply,
  497. (unsigned long)iob);
  498. }
  499. if (cmd)
  500. reply->rc = (u16) cmd->hdr.return_code;
  501. else if (iob->rc)
  502. reply->rc = iob->rc;
  503. if (keep_reply) {
  504. spin_lock_irqsave(&card->lock, flags);
  505. list_add_tail(&reply->list,
  506. &card->cmd_waiter_list);
  507. spin_unlock_irqrestore(&card->lock, flags);
  508. } else {
  509. atomic_inc(&reply->received);
  510. wake_up(&reply->wait_q);
  511. }
  512. qeth_put_reply(reply);
  513. goto out;
  514. }
  515. }
  516. spin_unlock_irqrestore(&card->lock, flags);
  517. out:
  518. memcpy(&card->seqno.pdu_hdr_ack,
  519. QETH_PDU_HEADER_SEQ_NO(iob->data),
  520. QETH_SEQ_NO_LENGTH);
  521. qeth_release_buffer(channel, iob);
  522. }
  523. static int qeth_setup_channel(struct qeth_channel *channel)
  524. {
  525. int cnt;
  526. QETH_DBF_TEXT(SETUP, 2, "setupch");
  527. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  528. channel->iob[cnt].data =
  529. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  530. if (channel->iob[cnt].data == NULL)
  531. break;
  532. channel->iob[cnt].state = BUF_STATE_FREE;
  533. channel->iob[cnt].channel = channel;
  534. channel->iob[cnt].callback = qeth_send_control_data_cb;
  535. channel->iob[cnt].rc = 0;
  536. }
  537. if (cnt < QETH_CMD_BUFFER_NO) {
  538. while (cnt-- > 0)
  539. kfree(channel->iob[cnt].data);
  540. return -ENOMEM;
  541. }
  542. channel->buf_no = 0;
  543. channel->io_buf_no = 0;
  544. atomic_set(&channel->irq_pending, 0);
  545. spin_lock_init(&channel->iob_lock);
  546. init_waitqueue_head(&channel->wait_q);
  547. return 0;
  548. }
  549. static int qeth_set_thread_start_bit(struct qeth_card *card,
  550. unsigned long thread)
  551. {
  552. unsigned long flags;
  553. spin_lock_irqsave(&card->thread_mask_lock, flags);
  554. if (!(card->thread_allowed_mask & thread) ||
  555. (card->thread_start_mask & thread)) {
  556. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  557. return -EPERM;
  558. }
  559. card->thread_start_mask |= thread;
  560. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  561. return 0;
  562. }
  563. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  564. {
  565. unsigned long flags;
  566. spin_lock_irqsave(&card->thread_mask_lock, flags);
  567. card->thread_start_mask &= ~thread;
  568. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  569. wake_up(&card->wait_q);
  570. }
  571. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  572. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  573. {
  574. unsigned long flags;
  575. spin_lock_irqsave(&card->thread_mask_lock, flags);
  576. card->thread_running_mask &= ~thread;
  577. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  578. wake_up(&card->wait_q);
  579. }
  580. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  581. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  582. {
  583. unsigned long flags;
  584. int rc = 0;
  585. spin_lock_irqsave(&card->thread_mask_lock, flags);
  586. if (card->thread_start_mask & thread) {
  587. if ((card->thread_allowed_mask & thread) &&
  588. !(card->thread_running_mask & thread)) {
  589. rc = 1;
  590. card->thread_start_mask &= ~thread;
  591. card->thread_running_mask |= thread;
  592. } else
  593. rc = -EPERM;
  594. }
  595. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  596. return rc;
  597. }
  598. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  599. {
  600. int rc = 0;
  601. wait_event(card->wait_q,
  602. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  603. return rc;
  604. }
  605. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  606. void qeth_schedule_recovery(struct qeth_card *card)
  607. {
  608. QETH_CARD_TEXT(card, 2, "startrec");
  609. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  610. schedule_work(&card->kernel_thread_starter);
  611. }
  612. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  613. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  614. {
  615. int dstat, cstat;
  616. char *sense;
  617. struct qeth_card *card;
  618. sense = (char *) irb->ecw;
  619. cstat = irb->scsw.cmd.cstat;
  620. dstat = irb->scsw.cmd.dstat;
  621. card = CARD_FROM_CDEV(cdev);
  622. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  623. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  624. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  625. QETH_CARD_TEXT(card, 2, "CGENCHK");
  626. dev_warn(&cdev->dev, "The qeth device driver "
  627. "failed to recover an error on the device\n");
  628. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x\n",
  629. dev_name(&cdev->dev), dstat, cstat);
  630. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  631. 16, 1, irb, 64, 1);
  632. return 1;
  633. }
  634. if (dstat & DEV_STAT_UNIT_CHECK) {
  635. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  636. SENSE_RESETTING_EVENT_FLAG) {
  637. QETH_CARD_TEXT(card, 2, "REVIND");
  638. return 1;
  639. }
  640. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  641. SENSE_COMMAND_REJECT_FLAG) {
  642. QETH_CARD_TEXT(card, 2, "CMDREJi");
  643. return 1;
  644. }
  645. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  646. QETH_CARD_TEXT(card, 2, "AFFE");
  647. return 1;
  648. }
  649. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  650. QETH_CARD_TEXT(card, 2, "ZEROSEN");
  651. return 0;
  652. }
  653. QETH_CARD_TEXT(card, 2, "DGENCHK");
  654. return 1;
  655. }
  656. return 0;
  657. }
  658. static long __qeth_check_irb_error(struct ccw_device *cdev,
  659. unsigned long intparm, struct irb *irb)
  660. {
  661. struct qeth_card *card;
  662. card = CARD_FROM_CDEV(cdev);
  663. if (!IS_ERR(irb))
  664. return 0;
  665. switch (PTR_ERR(irb)) {
  666. case -EIO:
  667. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  668. dev_name(&cdev->dev));
  669. QETH_CARD_TEXT(card, 2, "ckirberr");
  670. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  671. break;
  672. case -ETIMEDOUT:
  673. dev_warn(&cdev->dev, "A hardware operation timed out"
  674. " on the device\n");
  675. QETH_CARD_TEXT(card, 2, "ckirberr");
  676. QETH_CARD_TEXT_(card, 2, " rc%d", -ETIMEDOUT);
  677. if (intparm == QETH_RCD_PARM) {
  678. if (card && (card->data.ccwdev == cdev)) {
  679. card->data.state = CH_STATE_DOWN;
  680. wake_up(&card->wait_q);
  681. }
  682. }
  683. break;
  684. default:
  685. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  686. dev_name(&cdev->dev), PTR_ERR(irb));
  687. QETH_CARD_TEXT(card, 2, "ckirberr");
  688. QETH_CARD_TEXT(card, 2, " rc???");
  689. }
  690. return PTR_ERR(irb);
  691. }
  692. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  693. struct irb *irb)
  694. {
  695. int rc;
  696. int cstat, dstat;
  697. struct qeth_cmd_buffer *buffer;
  698. struct qeth_channel *channel;
  699. struct qeth_card *card;
  700. struct qeth_cmd_buffer *iob;
  701. __u8 index;
  702. if (__qeth_check_irb_error(cdev, intparm, irb))
  703. return;
  704. cstat = irb->scsw.cmd.cstat;
  705. dstat = irb->scsw.cmd.dstat;
  706. card = CARD_FROM_CDEV(cdev);
  707. if (!card)
  708. return;
  709. QETH_CARD_TEXT(card, 5, "irq");
  710. if (card->read.ccwdev == cdev) {
  711. channel = &card->read;
  712. QETH_CARD_TEXT(card, 5, "read");
  713. } else if (card->write.ccwdev == cdev) {
  714. channel = &card->write;
  715. QETH_CARD_TEXT(card, 5, "write");
  716. } else {
  717. channel = &card->data;
  718. QETH_CARD_TEXT(card, 5, "data");
  719. }
  720. atomic_set(&channel->irq_pending, 0);
  721. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  722. channel->state = CH_STATE_STOPPED;
  723. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  724. channel->state = CH_STATE_HALTED;
  725. /*let's wake up immediately on data channel*/
  726. if ((channel == &card->data) && (intparm != 0) &&
  727. (intparm != QETH_RCD_PARM))
  728. goto out;
  729. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  730. QETH_CARD_TEXT(card, 6, "clrchpar");
  731. /* we don't have to handle this further */
  732. intparm = 0;
  733. }
  734. if (intparm == QETH_HALT_CHANNEL_PARM) {
  735. QETH_CARD_TEXT(card, 6, "hltchpar");
  736. /* we don't have to handle this further */
  737. intparm = 0;
  738. }
  739. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  740. (dstat & DEV_STAT_UNIT_CHECK) ||
  741. (cstat)) {
  742. if (irb->esw.esw0.erw.cons) {
  743. dev_warn(&channel->ccwdev->dev,
  744. "The qeth device driver failed to recover "
  745. "an error on the device\n");
  746. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  747. "0x%X dstat 0x%X\n",
  748. dev_name(&channel->ccwdev->dev), cstat, dstat);
  749. print_hex_dump(KERN_WARNING, "qeth: irb ",
  750. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  751. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  752. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  753. }
  754. if (intparm == QETH_RCD_PARM) {
  755. channel->state = CH_STATE_DOWN;
  756. goto out;
  757. }
  758. rc = qeth_get_problem(cdev, irb);
  759. if (rc) {
  760. qeth_clear_ipacmd_list(card);
  761. qeth_schedule_recovery(card);
  762. goto out;
  763. }
  764. }
  765. if (intparm == QETH_RCD_PARM) {
  766. channel->state = CH_STATE_RCD_DONE;
  767. goto out;
  768. }
  769. if (intparm) {
  770. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  771. buffer->state = BUF_STATE_PROCESSED;
  772. }
  773. if (channel == &card->data)
  774. return;
  775. if (channel == &card->read &&
  776. channel->state == CH_STATE_UP)
  777. qeth_issue_next_read(card);
  778. iob = channel->iob;
  779. index = channel->buf_no;
  780. while (iob[index].state == BUF_STATE_PROCESSED) {
  781. if (iob[index].callback != NULL)
  782. iob[index].callback(channel, iob + index);
  783. index = (index + 1) % QETH_CMD_BUFFER_NO;
  784. }
  785. channel->buf_no = index;
  786. out:
  787. wake_up(&card->wait_q);
  788. return;
  789. }
  790. static void __qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  791. struct qeth_qdio_out_buffer *buf, unsigned int qeth_skip_skb)
  792. {
  793. int i;
  794. struct sk_buff *skb;
  795. /* is PCI flag set on buffer? */
  796. if (buf->buffer->element[0].flags & 0x40)
  797. atomic_dec(&queue->set_pci_flags_count);
  798. if (!qeth_skip_skb) {
  799. skb = skb_dequeue(&buf->skb_list);
  800. while (skb) {
  801. atomic_dec(&skb->users);
  802. dev_kfree_skb_any(skb);
  803. skb = skb_dequeue(&buf->skb_list);
  804. }
  805. }
  806. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  807. if (buf->buffer->element[i].addr && buf->is_header[i])
  808. kmem_cache_free(qeth_core_header_cache,
  809. buf->buffer->element[i].addr);
  810. buf->is_header[i] = 0;
  811. buf->buffer->element[i].length = 0;
  812. buf->buffer->element[i].addr = NULL;
  813. buf->buffer->element[i].flags = 0;
  814. }
  815. buf->buffer->element[15].flags = 0;
  816. buf->next_element_to_fill = 0;
  817. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  818. }
  819. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  820. struct qeth_qdio_out_buffer *buf)
  821. {
  822. __qeth_clear_output_buffer(queue, buf, 0);
  823. }
  824. void qeth_clear_qdio_buffers(struct qeth_card *card)
  825. {
  826. int i, j;
  827. QETH_CARD_TEXT(card, 2, "clearqdbf");
  828. /* clear outbound buffers to free skbs */
  829. for (i = 0; i < card->qdio.no_out_queues; ++i)
  830. if (card->qdio.out_qs[i]) {
  831. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  832. qeth_clear_output_buffer(card->qdio.out_qs[i],
  833. &card->qdio.out_qs[i]->bufs[j]);
  834. }
  835. }
  836. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  837. static void qeth_free_buffer_pool(struct qeth_card *card)
  838. {
  839. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  840. int i = 0;
  841. list_for_each_entry_safe(pool_entry, tmp,
  842. &card->qdio.init_pool.entry_list, init_list){
  843. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  844. free_page((unsigned long)pool_entry->elements[i]);
  845. list_del(&pool_entry->init_list);
  846. kfree(pool_entry);
  847. }
  848. }
  849. static void qeth_free_qdio_buffers(struct qeth_card *card)
  850. {
  851. int i, j;
  852. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  853. QETH_QDIO_UNINITIALIZED)
  854. return;
  855. kfree(card->qdio.in_q);
  856. card->qdio.in_q = NULL;
  857. /* inbound buffer pool */
  858. qeth_free_buffer_pool(card);
  859. /* free outbound qdio_qs */
  860. if (card->qdio.out_qs) {
  861. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  862. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  863. qeth_clear_output_buffer(card->qdio.out_qs[i],
  864. &card->qdio.out_qs[i]->bufs[j]);
  865. kfree(card->qdio.out_qs[i]);
  866. }
  867. kfree(card->qdio.out_qs);
  868. card->qdio.out_qs = NULL;
  869. }
  870. }
  871. static void qeth_clean_channel(struct qeth_channel *channel)
  872. {
  873. int cnt;
  874. QETH_DBF_TEXT(SETUP, 2, "freech");
  875. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  876. kfree(channel->iob[cnt].data);
  877. }
  878. static void qeth_get_channel_path_desc(struct qeth_card *card)
  879. {
  880. struct ccw_device *ccwdev;
  881. struct channelPath_dsc {
  882. u8 flags;
  883. u8 lsn;
  884. u8 desc;
  885. u8 chpid;
  886. u8 swla;
  887. u8 zeroes;
  888. u8 chla;
  889. u8 chpp;
  890. } *chp_dsc;
  891. QETH_DBF_TEXT(SETUP, 2, "chp_desc");
  892. ccwdev = card->data.ccwdev;
  893. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  894. if (chp_dsc != NULL) {
  895. /* CHPP field bit 6 == 1 -> single queue */
  896. if ((chp_dsc->chpp & 0x02) == 0x02)
  897. card->qdio.no_out_queues = 1;
  898. card->info.func_level = 0x4100 + chp_dsc->desc;
  899. kfree(chp_dsc);
  900. }
  901. if (card->qdio.no_out_queues == 1) {
  902. card->qdio.default_out_queue = 0;
  903. dev_info(&card->gdev->dev,
  904. "Priority Queueing not supported\n");
  905. }
  906. QETH_DBF_TEXT_(SETUP, 2, "nr:%x", card->qdio.no_out_queues);
  907. QETH_DBF_TEXT_(SETUP, 2, "lvl:%02x", card->info.func_level);
  908. return;
  909. }
  910. static void qeth_init_qdio_info(struct qeth_card *card)
  911. {
  912. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  913. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  914. /* inbound */
  915. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  916. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  917. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  918. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  919. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  920. }
  921. static void qeth_set_intial_options(struct qeth_card *card)
  922. {
  923. card->options.route4.type = NO_ROUTER;
  924. card->options.route6.type = NO_ROUTER;
  925. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  926. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  927. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  928. card->options.fake_broadcast = 0;
  929. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  930. card->options.performance_stats = 0;
  931. card->options.rx_sg_cb = QETH_RX_SG_CB;
  932. card->options.isolation = ISOLATION_MODE_NONE;
  933. }
  934. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  935. {
  936. unsigned long flags;
  937. int rc = 0;
  938. spin_lock_irqsave(&card->thread_mask_lock, flags);
  939. QETH_CARD_TEXT_(card, 4, " %02x%02x%02x",
  940. (u8) card->thread_start_mask,
  941. (u8) card->thread_allowed_mask,
  942. (u8) card->thread_running_mask);
  943. rc = (card->thread_start_mask & thread);
  944. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  945. return rc;
  946. }
  947. static void qeth_start_kernel_thread(struct work_struct *work)
  948. {
  949. struct qeth_card *card = container_of(work, struct qeth_card,
  950. kernel_thread_starter);
  951. QETH_CARD_TEXT(card , 2, "strthrd");
  952. if (card->read.state != CH_STATE_UP &&
  953. card->write.state != CH_STATE_UP)
  954. return;
  955. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  956. kthread_run(card->discipline.recover, (void *) card,
  957. "qeth_recover");
  958. }
  959. static int qeth_setup_card(struct qeth_card *card)
  960. {
  961. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  962. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  963. card->read.state = CH_STATE_DOWN;
  964. card->write.state = CH_STATE_DOWN;
  965. card->data.state = CH_STATE_DOWN;
  966. card->state = CARD_STATE_DOWN;
  967. card->lan_online = 0;
  968. card->use_hard_stop = 0;
  969. card->dev = NULL;
  970. spin_lock_init(&card->vlanlock);
  971. spin_lock_init(&card->mclock);
  972. card->vlangrp = NULL;
  973. spin_lock_init(&card->lock);
  974. spin_lock_init(&card->ip_lock);
  975. spin_lock_init(&card->thread_mask_lock);
  976. mutex_init(&card->conf_mutex);
  977. card->thread_start_mask = 0;
  978. card->thread_allowed_mask = 0;
  979. card->thread_running_mask = 0;
  980. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  981. INIT_LIST_HEAD(&card->ip_list);
  982. INIT_LIST_HEAD(card->ip_tbd_list);
  983. INIT_LIST_HEAD(&card->cmd_waiter_list);
  984. init_waitqueue_head(&card->wait_q);
  985. /* intial options */
  986. qeth_set_intial_options(card);
  987. /* IP address takeover */
  988. INIT_LIST_HEAD(&card->ipato.entries);
  989. card->ipato.enabled = 0;
  990. card->ipato.invert4 = 0;
  991. card->ipato.invert6 = 0;
  992. /* init QDIO stuff */
  993. qeth_init_qdio_info(card);
  994. return 0;
  995. }
  996. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  997. {
  998. struct qeth_card *card = container_of(slr, struct qeth_card,
  999. qeth_service_level);
  1000. if (card->info.mcl_level[0])
  1001. seq_printf(m, "qeth: %s firmware level %s\n",
  1002. CARD_BUS_ID(card), card->info.mcl_level);
  1003. }
  1004. static struct qeth_card *qeth_alloc_card(void)
  1005. {
  1006. struct qeth_card *card;
  1007. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1008. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1009. if (!card)
  1010. goto out;
  1011. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1012. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1013. if (!card->ip_tbd_list) {
  1014. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1015. goto out_card;
  1016. }
  1017. if (qeth_setup_channel(&card->read))
  1018. goto out_ip;
  1019. if (qeth_setup_channel(&card->write))
  1020. goto out_channel;
  1021. card->options.layer2 = -1;
  1022. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1023. register_service_level(&card->qeth_service_level);
  1024. return card;
  1025. out_channel:
  1026. qeth_clean_channel(&card->read);
  1027. out_ip:
  1028. kfree(card->ip_tbd_list);
  1029. out_card:
  1030. kfree(card);
  1031. out:
  1032. return NULL;
  1033. }
  1034. static int qeth_determine_card_type(struct qeth_card *card)
  1035. {
  1036. int i = 0;
  1037. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1038. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1039. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1040. while (known_devices[i][QETH_DEV_MODEL_IND]) {
  1041. if ((CARD_RDEV(card)->id.dev_type ==
  1042. known_devices[i][QETH_DEV_TYPE_IND]) &&
  1043. (CARD_RDEV(card)->id.dev_model ==
  1044. known_devices[i][QETH_DEV_MODEL_IND])) {
  1045. card->info.type = known_devices[i][QETH_DEV_MODEL_IND];
  1046. card->qdio.no_out_queues =
  1047. known_devices[i][QETH_QUEUE_NO_IND];
  1048. card->info.is_multicast_different =
  1049. known_devices[i][QETH_MULTICAST_IND];
  1050. qeth_get_channel_path_desc(card);
  1051. return 0;
  1052. }
  1053. i++;
  1054. }
  1055. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1056. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1057. "unknown type\n");
  1058. return -ENOENT;
  1059. }
  1060. static int qeth_clear_channel(struct qeth_channel *channel)
  1061. {
  1062. unsigned long flags;
  1063. struct qeth_card *card;
  1064. int rc;
  1065. card = CARD_FROM_CDEV(channel->ccwdev);
  1066. QETH_CARD_TEXT(card, 3, "clearch");
  1067. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1068. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1069. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1070. if (rc)
  1071. return rc;
  1072. rc = wait_event_interruptible_timeout(card->wait_q,
  1073. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1074. if (rc == -ERESTARTSYS)
  1075. return rc;
  1076. if (channel->state != CH_STATE_STOPPED)
  1077. return -ETIME;
  1078. channel->state = CH_STATE_DOWN;
  1079. return 0;
  1080. }
  1081. static int qeth_halt_channel(struct qeth_channel *channel)
  1082. {
  1083. unsigned long flags;
  1084. struct qeth_card *card;
  1085. int rc;
  1086. card = CARD_FROM_CDEV(channel->ccwdev);
  1087. QETH_CARD_TEXT(card, 3, "haltch");
  1088. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1089. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1090. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1091. if (rc)
  1092. return rc;
  1093. rc = wait_event_interruptible_timeout(card->wait_q,
  1094. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1095. if (rc == -ERESTARTSYS)
  1096. return rc;
  1097. if (channel->state != CH_STATE_HALTED)
  1098. return -ETIME;
  1099. return 0;
  1100. }
  1101. static int qeth_halt_channels(struct qeth_card *card)
  1102. {
  1103. int rc1 = 0, rc2 = 0, rc3 = 0;
  1104. QETH_CARD_TEXT(card, 3, "haltchs");
  1105. rc1 = qeth_halt_channel(&card->read);
  1106. rc2 = qeth_halt_channel(&card->write);
  1107. rc3 = qeth_halt_channel(&card->data);
  1108. if (rc1)
  1109. return rc1;
  1110. if (rc2)
  1111. return rc2;
  1112. return rc3;
  1113. }
  1114. static int qeth_clear_channels(struct qeth_card *card)
  1115. {
  1116. int rc1 = 0, rc2 = 0, rc3 = 0;
  1117. QETH_CARD_TEXT(card, 3, "clearchs");
  1118. rc1 = qeth_clear_channel(&card->read);
  1119. rc2 = qeth_clear_channel(&card->write);
  1120. rc3 = qeth_clear_channel(&card->data);
  1121. if (rc1)
  1122. return rc1;
  1123. if (rc2)
  1124. return rc2;
  1125. return rc3;
  1126. }
  1127. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1128. {
  1129. int rc = 0;
  1130. QETH_CARD_TEXT(card, 3, "clhacrd");
  1131. if (halt)
  1132. rc = qeth_halt_channels(card);
  1133. if (rc)
  1134. return rc;
  1135. return qeth_clear_channels(card);
  1136. }
  1137. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1138. {
  1139. int rc = 0;
  1140. QETH_CARD_TEXT(card, 3, "qdioclr");
  1141. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1142. QETH_QDIO_CLEANING)) {
  1143. case QETH_QDIO_ESTABLISHED:
  1144. if (card->info.type == QETH_CARD_TYPE_IQD)
  1145. rc = qdio_shutdown(CARD_DDEV(card),
  1146. QDIO_FLAG_CLEANUP_USING_HALT);
  1147. else
  1148. rc = qdio_shutdown(CARD_DDEV(card),
  1149. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1150. if (rc)
  1151. QETH_CARD_TEXT_(card, 3, "1err%d", rc);
  1152. qdio_free(CARD_DDEV(card));
  1153. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1154. break;
  1155. case QETH_QDIO_CLEANING:
  1156. return rc;
  1157. default:
  1158. break;
  1159. }
  1160. rc = qeth_clear_halt_card(card, use_halt);
  1161. if (rc)
  1162. QETH_CARD_TEXT_(card, 3, "2err%d", rc);
  1163. card->state = CARD_STATE_DOWN;
  1164. return rc;
  1165. }
  1166. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1167. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1168. int *length)
  1169. {
  1170. struct ciw *ciw;
  1171. char *rcd_buf;
  1172. int ret;
  1173. struct qeth_channel *channel = &card->data;
  1174. unsigned long flags;
  1175. /*
  1176. * scan for RCD command in extended SenseID data
  1177. */
  1178. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1179. if (!ciw || ciw->cmd == 0)
  1180. return -EOPNOTSUPP;
  1181. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1182. if (!rcd_buf)
  1183. return -ENOMEM;
  1184. channel->ccw.cmd_code = ciw->cmd;
  1185. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1186. channel->ccw.count = ciw->count;
  1187. channel->ccw.flags = CCW_FLAG_SLI;
  1188. channel->state = CH_STATE_RCD;
  1189. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1190. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1191. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1192. QETH_RCD_TIMEOUT);
  1193. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1194. if (!ret)
  1195. wait_event(card->wait_q,
  1196. (channel->state == CH_STATE_RCD_DONE ||
  1197. channel->state == CH_STATE_DOWN));
  1198. if (channel->state == CH_STATE_DOWN)
  1199. ret = -EIO;
  1200. else
  1201. channel->state = CH_STATE_DOWN;
  1202. if (ret) {
  1203. kfree(rcd_buf);
  1204. *buffer = NULL;
  1205. *length = 0;
  1206. } else {
  1207. *length = ciw->count;
  1208. *buffer = rcd_buf;
  1209. }
  1210. return ret;
  1211. }
  1212. static void qeth_configure_unitaddr(struct qeth_card *card, char *prcd)
  1213. {
  1214. QETH_DBF_TEXT(SETUP, 2, "cfgunit");
  1215. card->info.chpid = prcd[30];
  1216. card->info.unit_addr2 = prcd[31];
  1217. card->info.cula = prcd[63];
  1218. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1219. (prcd[0x11] == _ascebc['M']));
  1220. }
  1221. static void qeth_configure_blkt_default(struct qeth_card *card, char *prcd)
  1222. {
  1223. QETH_DBF_TEXT(SETUP, 2, "cfgblkt");
  1224. if (prcd[74] == 0xF0 && prcd[75] == 0xF0 && prcd[76] == 0xF5) {
  1225. card->info.blkt.time_total = 250;
  1226. card->info.blkt.inter_packet = 5;
  1227. card->info.blkt.inter_packet_jumbo = 15;
  1228. } else {
  1229. card->info.blkt.time_total = 0;
  1230. card->info.blkt.inter_packet = 0;
  1231. card->info.blkt.inter_packet_jumbo = 0;
  1232. }
  1233. }
  1234. static void qeth_init_tokens(struct qeth_card *card)
  1235. {
  1236. card->token.issuer_rm_w = 0x00010103UL;
  1237. card->token.cm_filter_w = 0x00010108UL;
  1238. card->token.cm_connection_w = 0x0001010aUL;
  1239. card->token.ulp_filter_w = 0x0001010bUL;
  1240. card->token.ulp_connection_w = 0x0001010dUL;
  1241. }
  1242. static void qeth_init_func_level(struct qeth_card *card)
  1243. {
  1244. switch (card->info.type) {
  1245. case QETH_CARD_TYPE_IQD:
  1246. card->info.func_level = QETH_IDX_FUNC_LEVEL_IQD;
  1247. break;
  1248. case QETH_CARD_TYPE_OSD:
  1249. case QETH_CARD_TYPE_OSN:
  1250. card->info.func_level = QETH_IDX_FUNC_LEVEL_OSD;
  1251. break;
  1252. default:
  1253. break;
  1254. }
  1255. }
  1256. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1257. void (*idx_reply_cb)(struct qeth_channel *,
  1258. struct qeth_cmd_buffer *))
  1259. {
  1260. struct qeth_cmd_buffer *iob;
  1261. unsigned long flags;
  1262. int rc;
  1263. struct qeth_card *card;
  1264. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1265. card = CARD_FROM_CDEV(channel->ccwdev);
  1266. iob = qeth_get_buffer(channel);
  1267. iob->callback = idx_reply_cb;
  1268. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1269. channel->ccw.count = QETH_BUFSIZE;
  1270. channel->ccw.cda = (__u32) __pa(iob->data);
  1271. wait_event(card->wait_q,
  1272. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1273. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1274. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1275. rc = ccw_device_start(channel->ccwdev,
  1276. &channel->ccw, (addr_t) iob, 0, 0);
  1277. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1278. if (rc) {
  1279. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1280. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1281. atomic_set(&channel->irq_pending, 0);
  1282. wake_up(&card->wait_q);
  1283. return rc;
  1284. }
  1285. rc = wait_event_interruptible_timeout(card->wait_q,
  1286. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1287. if (rc == -ERESTARTSYS)
  1288. return rc;
  1289. if (channel->state != CH_STATE_UP) {
  1290. rc = -ETIME;
  1291. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1292. qeth_clear_cmd_buffers(channel);
  1293. } else
  1294. rc = 0;
  1295. return rc;
  1296. }
  1297. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1298. void (*idx_reply_cb)(struct qeth_channel *,
  1299. struct qeth_cmd_buffer *))
  1300. {
  1301. struct qeth_card *card;
  1302. struct qeth_cmd_buffer *iob;
  1303. unsigned long flags;
  1304. __u16 temp;
  1305. __u8 tmp;
  1306. int rc;
  1307. struct ccw_dev_id temp_devid;
  1308. card = CARD_FROM_CDEV(channel->ccwdev);
  1309. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1310. iob = qeth_get_buffer(channel);
  1311. iob->callback = idx_reply_cb;
  1312. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1313. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1314. channel->ccw.cda = (__u32) __pa(iob->data);
  1315. if (channel == &card->write) {
  1316. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1317. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1318. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1319. card->seqno.trans_hdr++;
  1320. } else {
  1321. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1322. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1323. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1324. }
  1325. tmp = ((__u8)card->info.portno) | 0x80;
  1326. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1327. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1328. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1329. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1330. &card->info.func_level, sizeof(__u16));
  1331. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1332. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1333. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1334. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1335. wait_event(card->wait_q,
  1336. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1337. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1338. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1339. rc = ccw_device_start(channel->ccwdev,
  1340. &channel->ccw, (addr_t) iob, 0, 0);
  1341. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1342. if (rc) {
  1343. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1344. rc);
  1345. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1346. atomic_set(&channel->irq_pending, 0);
  1347. wake_up(&card->wait_q);
  1348. return rc;
  1349. }
  1350. rc = wait_event_interruptible_timeout(card->wait_q,
  1351. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1352. if (rc == -ERESTARTSYS)
  1353. return rc;
  1354. if (channel->state != CH_STATE_ACTIVATING) {
  1355. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1356. " failed to recover an error on the device\n");
  1357. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1358. dev_name(&channel->ccwdev->dev));
  1359. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1360. qeth_clear_cmd_buffers(channel);
  1361. return -ETIME;
  1362. }
  1363. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1364. }
  1365. static int qeth_peer_func_level(int level)
  1366. {
  1367. if ((level & 0xff) == 8)
  1368. return (level & 0xff) + 0x400;
  1369. if (((level >> 8) & 3) == 1)
  1370. return (level & 0xff) + 0x200;
  1371. return level;
  1372. }
  1373. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1374. struct qeth_cmd_buffer *iob)
  1375. {
  1376. struct qeth_card *card;
  1377. __u16 temp;
  1378. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1379. if (channel->state == CH_STATE_DOWN) {
  1380. channel->state = CH_STATE_ACTIVATING;
  1381. goto out;
  1382. }
  1383. card = CARD_FROM_CDEV(channel->ccwdev);
  1384. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1385. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == QETH_IDX_ACT_ERR_EXCL)
  1386. dev_err(&card->write.ccwdev->dev,
  1387. "The adapter is used exclusively by another "
  1388. "host\n");
  1389. else
  1390. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1391. " negative reply\n",
  1392. dev_name(&card->write.ccwdev->dev));
  1393. goto out;
  1394. }
  1395. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1396. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1397. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1398. "function level mismatch (sent: 0x%x, received: "
  1399. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1400. card->info.func_level, temp);
  1401. goto out;
  1402. }
  1403. channel->state = CH_STATE_UP;
  1404. out:
  1405. qeth_release_buffer(channel, iob);
  1406. }
  1407. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1408. struct qeth_cmd_buffer *iob)
  1409. {
  1410. struct qeth_card *card;
  1411. __u16 temp;
  1412. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1413. if (channel->state == CH_STATE_DOWN) {
  1414. channel->state = CH_STATE_ACTIVATING;
  1415. goto out;
  1416. }
  1417. card = CARD_FROM_CDEV(channel->ccwdev);
  1418. if (qeth_check_idx_response(card, iob->data))
  1419. goto out;
  1420. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1421. switch (QETH_IDX_ACT_CAUSE_CODE(iob->data)) {
  1422. case QETH_IDX_ACT_ERR_EXCL:
  1423. dev_err(&card->write.ccwdev->dev,
  1424. "The adapter is used exclusively by another "
  1425. "host\n");
  1426. break;
  1427. case QETH_IDX_ACT_ERR_AUTH:
  1428. case QETH_IDX_ACT_ERR_AUTH_USER:
  1429. dev_err(&card->read.ccwdev->dev,
  1430. "Setting the device online failed because of "
  1431. "insufficient authorization\n");
  1432. break;
  1433. default:
  1434. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1435. " negative reply\n",
  1436. dev_name(&card->read.ccwdev->dev));
  1437. }
  1438. QETH_CARD_TEXT_(card, 2, "idxread%c",
  1439. QETH_IDX_ACT_CAUSE_CODE(iob->data));
  1440. goto out;
  1441. }
  1442. /**
  1443. * * temporary fix for microcode bug
  1444. * * to revert it,replace OR by AND
  1445. * */
  1446. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1447. (card->info.type == QETH_CARD_TYPE_OSD))
  1448. card->info.portname_required = 1;
  1449. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1450. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1451. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1452. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1453. dev_name(&card->read.ccwdev->dev),
  1454. card->info.func_level, temp);
  1455. goto out;
  1456. }
  1457. memcpy(&card->token.issuer_rm_r,
  1458. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1459. QETH_MPC_TOKEN_LENGTH);
  1460. memcpy(&card->info.mcl_level[0],
  1461. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1462. channel->state = CH_STATE_UP;
  1463. out:
  1464. qeth_release_buffer(channel, iob);
  1465. }
  1466. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1467. struct qeth_cmd_buffer *iob)
  1468. {
  1469. qeth_setup_ccw(&card->write, iob->data, len);
  1470. iob->callback = qeth_release_buffer;
  1471. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1472. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1473. card->seqno.trans_hdr++;
  1474. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1475. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1476. card->seqno.pdu_hdr++;
  1477. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1478. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1479. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1480. }
  1481. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1482. int qeth_send_control_data(struct qeth_card *card, int len,
  1483. struct qeth_cmd_buffer *iob,
  1484. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1485. unsigned long),
  1486. void *reply_param)
  1487. {
  1488. int rc;
  1489. unsigned long flags;
  1490. struct qeth_reply *reply = NULL;
  1491. unsigned long timeout, event_timeout;
  1492. struct qeth_ipa_cmd *cmd;
  1493. QETH_CARD_TEXT(card, 2, "sendctl");
  1494. reply = qeth_alloc_reply(card);
  1495. if (!reply) {
  1496. return -ENOMEM;
  1497. }
  1498. reply->callback = reply_cb;
  1499. reply->param = reply_param;
  1500. if (card->state == CARD_STATE_DOWN)
  1501. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1502. else
  1503. reply->seqno = card->seqno.ipa++;
  1504. init_waitqueue_head(&reply->wait_q);
  1505. spin_lock_irqsave(&card->lock, flags);
  1506. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1507. spin_unlock_irqrestore(&card->lock, flags);
  1508. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1509. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1510. qeth_prepare_control_data(card, len, iob);
  1511. if (IS_IPA(iob->data))
  1512. event_timeout = QETH_IPA_TIMEOUT;
  1513. else
  1514. event_timeout = QETH_TIMEOUT;
  1515. timeout = jiffies + event_timeout;
  1516. QETH_CARD_TEXT(card, 6, "noirqpnd");
  1517. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1518. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1519. (addr_t) iob, 0, 0);
  1520. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1521. if (rc) {
  1522. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1523. "ccw_device_start rc = %i\n",
  1524. dev_name(&card->write.ccwdev->dev), rc);
  1525. QETH_CARD_TEXT_(card, 2, " err%d", rc);
  1526. spin_lock_irqsave(&card->lock, flags);
  1527. list_del_init(&reply->list);
  1528. qeth_put_reply(reply);
  1529. spin_unlock_irqrestore(&card->lock, flags);
  1530. qeth_release_buffer(iob->channel, iob);
  1531. atomic_set(&card->write.irq_pending, 0);
  1532. wake_up(&card->wait_q);
  1533. return rc;
  1534. }
  1535. /* we have only one long running ipassist, since we can ensure
  1536. process context of this command we can sleep */
  1537. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1538. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1539. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1540. if (!wait_event_timeout(reply->wait_q,
  1541. atomic_read(&reply->received), event_timeout))
  1542. goto time_err;
  1543. } else {
  1544. while (!atomic_read(&reply->received)) {
  1545. if (time_after(jiffies, timeout))
  1546. goto time_err;
  1547. cpu_relax();
  1548. };
  1549. }
  1550. rc = reply->rc;
  1551. qeth_put_reply(reply);
  1552. return rc;
  1553. time_err:
  1554. spin_lock_irqsave(&reply->card->lock, flags);
  1555. list_del_init(&reply->list);
  1556. spin_unlock_irqrestore(&reply->card->lock, flags);
  1557. reply->rc = -ETIME;
  1558. atomic_inc(&reply->received);
  1559. wake_up(&reply->wait_q);
  1560. rc = reply->rc;
  1561. qeth_put_reply(reply);
  1562. return rc;
  1563. }
  1564. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1565. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1566. unsigned long data)
  1567. {
  1568. struct qeth_cmd_buffer *iob;
  1569. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1570. iob = (struct qeth_cmd_buffer *) data;
  1571. memcpy(&card->token.cm_filter_r,
  1572. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1573. QETH_MPC_TOKEN_LENGTH);
  1574. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1575. return 0;
  1576. }
  1577. static int qeth_cm_enable(struct qeth_card *card)
  1578. {
  1579. int rc;
  1580. struct qeth_cmd_buffer *iob;
  1581. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1582. iob = qeth_wait_for_buffer(&card->write);
  1583. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1584. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1585. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1586. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1587. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1588. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1589. qeth_cm_enable_cb, NULL);
  1590. return rc;
  1591. }
  1592. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1593. unsigned long data)
  1594. {
  1595. struct qeth_cmd_buffer *iob;
  1596. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1597. iob = (struct qeth_cmd_buffer *) data;
  1598. memcpy(&card->token.cm_connection_r,
  1599. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1600. QETH_MPC_TOKEN_LENGTH);
  1601. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1602. return 0;
  1603. }
  1604. static int qeth_cm_setup(struct qeth_card *card)
  1605. {
  1606. int rc;
  1607. struct qeth_cmd_buffer *iob;
  1608. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1609. iob = qeth_wait_for_buffer(&card->write);
  1610. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1611. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1612. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1613. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1614. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1615. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1616. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1617. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1618. qeth_cm_setup_cb, NULL);
  1619. return rc;
  1620. }
  1621. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1622. {
  1623. switch (card->info.type) {
  1624. case QETH_CARD_TYPE_UNKNOWN:
  1625. return 1500;
  1626. case QETH_CARD_TYPE_IQD:
  1627. return card->info.max_mtu;
  1628. case QETH_CARD_TYPE_OSD:
  1629. switch (card->info.link_type) {
  1630. case QETH_LINK_TYPE_HSTR:
  1631. case QETH_LINK_TYPE_LANE_TR:
  1632. return 2000;
  1633. default:
  1634. return 1492;
  1635. }
  1636. case QETH_CARD_TYPE_OSM:
  1637. case QETH_CARD_TYPE_OSX:
  1638. return 1492;
  1639. default:
  1640. return 1500;
  1641. }
  1642. }
  1643. static inline int qeth_get_max_mtu_for_card(int cardtype)
  1644. {
  1645. switch (cardtype) {
  1646. case QETH_CARD_TYPE_UNKNOWN:
  1647. case QETH_CARD_TYPE_OSD:
  1648. case QETH_CARD_TYPE_OSN:
  1649. case QETH_CARD_TYPE_OSM:
  1650. case QETH_CARD_TYPE_OSX:
  1651. return 61440;
  1652. case QETH_CARD_TYPE_IQD:
  1653. return 57344;
  1654. default:
  1655. return 1500;
  1656. }
  1657. }
  1658. static inline int qeth_get_mtu_out_of_mpc(int cardtype)
  1659. {
  1660. switch (cardtype) {
  1661. case QETH_CARD_TYPE_IQD:
  1662. return 1;
  1663. default:
  1664. return 0;
  1665. }
  1666. }
  1667. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1668. {
  1669. switch (framesize) {
  1670. case 0x4000:
  1671. return 8192;
  1672. case 0x6000:
  1673. return 16384;
  1674. case 0xa000:
  1675. return 32768;
  1676. case 0xffff:
  1677. return 57344;
  1678. default:
  1679. return 0;
  1680. }
  1681. }
  1682. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1683. {
  1684. switch (card->info.type) {
  1685. case QETH_CARD_TYPE_OSD:
  1686. case QETH_CARD_TYPE_OSM:
  1687. case QETH_CARD_TYPE_OSX:
  1688. return ((mtu >= 576) && (mtu <= 61440));
  1689. case QETH_CARD_TYPE_IQD:
  1690. return ((mtu >= 576) &&
  1691. (mtu <= card->info.max_mtu + 4096 - 32));
  1692. case QETH_CARD_TYPE_OSN:
  1693. case QETH_CARD_TYPE_UNKNOWN:
  1694. default:
  1695. return 1;
  1696. }
  1697. }
  1698. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1699. unsigned long data)
  1700. {
  1701. __u16 mtu, framesize;
  1702. __u16 len;
  1703. __u8 link_type;
  1704. struct qeth_cmd_buffer *iob;
  1705. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1706. iob = (struct qeth_cmd_buffer *) data;
  1707. memcpy(&card->token.ulp_filter_r,
  1708. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1709. QETH_MPC_TOKEN_LENGTH);
  1710. if (qeth_get_mtu_out_of_mpc(card->info.type)) {
  1711. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1712. mtu = qeth_get_mtu_outof_framesize(framesize);
  1713. if (!mtu) {
  1714. iob->rc = -EINVAL;
  1715. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1716. return 0;
  1717. }
  1718. card->info.max_mtu = mtu;
  1719. card->info.initial_mtu = mtu;
  1720. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1721. } else {
  1722. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1723. card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
  1724. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1725. }
  1726. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1727. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1728. memcpy(&link_type,
  1729. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1730. card->info.link_type = link_type;
  1731. } else
  1732. card->info.link_type = 0;
  1733. QETH_DBF_TEXT_(SETUP, 2, "link%d", card->info.link_type);
  1734. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1735. return 0;
  1736. }
  1737. static int qeth_ulp_enable(struct qeth_card *card)
  1738. {
  1739. int rc;
  1740. char prot_type;
  1741. struct qeth_cmd_buffer *iob;
  1742. /*FIXME: trace view callbacks*/
  1743. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1744. iob = qeth_wait_for_buffer(&card->write);
  1745. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1746. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1747. (__u8) card->info.portno;
  1748. if (card->options.layer2)
  1749. if (card->info.type == QETH_CARD_TYPE_OSN)
  1750. prot_type = QETH_PROT_OSN2;
  1751. else
  1752. prot_type = QETH_PROT_LAYER2;
  1753. else
  1754. prot_type = QETH_PROT_TCPIP;
  1755. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1756. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1757. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1758. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1759. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1760. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1761. card->info.portname, 9);
  1762. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1763. qeth_ulp_enable_cb, NULL);
  1764. return rc;
  1765. }
  1766. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1767. unsigned long data)
  1768. {
  1769. struct qeth_cmd_buffer *iob;
  1770. int rc = 0;
  1771. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1772. iob = (struct qeth_cmd_buffer *) data;
  1773. memcpy(&card->token.ulp_connection_r,
  1774. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1775. QETH_MPC_TOKEN_LENGTH);
  1776. if (!strncmp("00S", QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1777. 3)) {
  1778. QETH_DBF_TEXT(SETUP, 2, "olmlimit");
  1779. dev_err(&card->gdev->dev, "A connection could not be "
  1780. "established because of an OLM limit\n");
  1781. rc = -EMLINK;
  1782. }
  1783. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1784. return rc;
  1785. }
  1786. static int qeth_ulp_setup(struct qeth_card *card)
  1787. {
  1788. int rc;
  1789. __u16 temp;
  1790. struct qeth_cmd_buffer *iob;
  1791. struct ccw_dev_id dev_id;
  1792. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1793. iob = qeth_wait_for_buffer(&card->write);
  1794. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1795. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1796. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1797. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1798. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1799. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1800. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1801. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1802. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1803. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1804. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1805. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1806. qeth_ulp_setup_cb, NULL);
  1807. return rc;
  1808. }
  1809. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1810. {
  1811. int i, j;
  1812. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1813. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1814. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1815. return 0;
  1816. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1817. GFP_KERNEL);
  1818. if (!card->qdio.in_q)
  1819. goto out_nomem;
  1820. QETH_DBF_TEXT(SETUP, 2, "inq");
  1821. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1822. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1823. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1824. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1825. card->qdio.in_q->bufs[i].buffer =
  1826. &card->qdio.in_q->qdio_bufs[i];
  1827. /* inbound buffer pool */
  1828. if (qeth_alloc_buffer_pool(card))
  1829. goto out_freeinq;
  1830. /* outbound */
  1831. card->qdio.out_qs =
  1832. kmalloc(card->qdio.no_out_queues *
  1833. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1834. if (!card->qdio.out_qs)
  1835. goto out_freepool;
  1836. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1837. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1838. GFP_KERNEL);
  1839. if (!card->qdio.out_qs[i])
  1840. goto out_freeoutq;
  1841. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1842. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1843. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1844. card->qdio.out_qs[i]->queue_no = i;
  1845. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1846. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1847. card->qdio.out_qs[i]->bufs[j].buffer =
  1848. &card->qdio.out_qs[i]->qdio_bufs[j];
  1849. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1850. skb_list);
  1851. lockdep_set_class(
  1852. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1853. &qdio_out_skb_queue_key);
  1854. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1855. }
  1856. }
  1857. return 0;
  1858. out_freeoutq:
  1859. while (i > 0)
  1860. kfree(card->qdio.out_qs[--i]);
  1861. kfree(card->qdio.out_qs);
  1862. card->qdio.out_qs = NULL;
  1863. out_freepool:
  1864. qeth_free_buffer_pool(card);
  1865. out_freeinq:
  1866. kfree(card->qdio.in_q);
  1867. card->qdio.in_q = NULL;
  1868. out_nomem:
  1869. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1870. return -ENOMEM;
  1871. }
  1872. static void qeth_create_qib_param_field(struct qeth_card *card,
  1873. char *param_field)
  1874. {
  1875. param_field[0] = _ascebc['P'];
  1876. param_field[1] = _ascebc['C'];
  1877. param_field[2] = _ascebc['I'];
  1878. param_field[3] = _ascebc['T'];
  1879. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1880. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1881. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1882. }
  1883. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1884. char *param_field)
  1885. {
  1886. param_field[16] = _ascebc['B'];
  1887. param_field[17] = _ascebc['L'];
  1888. param_field[18] = _ascebc['K'];
  1889. param_field[19] = _ascebc['T'];
  1890. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1891. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1892. *((unsigned int *) (&param_field[28])) =
  1893. card->info.blkt.inter_packet_jumbo;
  1894. }
  1895. static int qeth_qdio_activate(struct qeth_card *card)
  1896. {
  1897. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1898. return qdio_activate(CARD_DDEV(card));
  1899. }
  1900. static int qeth_dm_act(struct qeth_card *card)
  1901. {
  1902. int rc;
  1903. struct qeth_cmd_buffer *iob;
  1904. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1905. iob = qeth_wait_for_buffer(&card->write);
  1906. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1907. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1908. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1909. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1910. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1911. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1912. return rc;
  1913. }
  1914. static int qeth_mpc_initialize(struct qeth_card *card)
  1915. {
  1916. int rc;
  1917. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1918. rc = qeth_issue_next_read(card);
  1919. if (rc) {
  1920. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1921. return rc;
  1922. }
  1923. rc = qeth_cm_enable(card);
  1924. if (rc) {
  1925. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1926. goto out_qdio;
  1927. }
  1928. rc = qeth_cm_setup(card);
  1929. if (rc) {
  1930. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1931. goto out_qdio;
  1932. }
  1933. rc = qeth_ulp_enable(card);
  1934. if (rc) {
  1935. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1936. goto out_qdio;
  1937. }
  1938. rc = qeth_ulp_setup(card);
  1939. if (rc) {
  1940. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1941. goto out_qdio;
  1942. }
  1943. rc = qeth_alloc_qdio_buffers(card);
  1944. if (rc) {
  1945. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1946. goto out_qdio;
  1947. }
  1948. rc = qeth_qdio_establish(card);
  1949. if (rc) {
  1950. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1951. qeth_free_qdio_buffers(card);
  1952. goto out_qdio;
  1953. }
  1954. rc = qeth_qdio_activate(card);
  1955. if (rc) {
  1956. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  1957. goto out_qdio;
  1958. }
  1959. rc = qeth_dm_act(card);
  1960. if (rc) {
  1961. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  1962. goto out_qdio;
  1963. }
  1964. return 0;
  1965. out_qdio:
  1966. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1967. return rc;
  1968. }
  1969. static void qeth_print_status_with_portname(struct qeth_card *card)
  1970. {
  1971. char dbf_text[15];
  1972. int i;
  1973. sprintf(dbf_text, "%s", card->info.portname + 1);
  1974. for (i = 0; i < 8; i++)
  1975. dbf_text[i] =
  1976. (char) _ebcasc[(__u8) dbf_text[i]];
  1977. dbf_text[8] = 0;
  1978. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  1979. "with link type %s (portname: %s)\n",
  1980. qeth_get_cardname(card),
  1981. (card->info.mcl_level[0]) ? " (level: " : "",
  1982. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1983. (card->info.mcl_level[0]) ? ")" : "",
  1984. qeth_get_cardname_short(card),
  1985. dbf_text);
  1986. }
  1987. static void qeth_print_status_no_portname(struct qeth_card *card)
  1988. {
  1989. if (card->info.portname[0])
  1990. dev_info(&card->gdev->dev, "Device is a%s "
  1991. "card%s%s%s\nwith link type %s "
  1992. "(no portname needed by interface).\n",
  1993. qeth_get_cardname(card),
  1994. (card->info.mcl_level[0]) ? " (level: " : "",
  1995. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1996. (card->info.mcl_level[0]) ? ")" : "",
  1997. qeth_get_cardname_short(card));
  1998. else
  1999. dev_info(&card->gdev->dev, "Device is a%s "
  2000. "card%s%s%s\nwith link type %s.\n",
  2001. qeth_get_cardname(card),
  2002. (card->info.mcl_level[0]) ? " (level: " : "",
  2003. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2004. (card->info.mcl_level[0]) ? ")" : "",
  2005. qeth_get_cardname_short(card));
  2006. }
  2007. void qeth_print_status_message(struct qeth_card *card)
  2008. {
  2009. switch (card->info.type) {
  2010. case QETH_CARD_TYPE_OSD:
  2011. case QETH_CARD_TYPE_OSM:
  2012. case QETH_CARD_TYPE_OSX:
  2013. /* VM will use a non-zero first character
  2014. * to indicate a HiperSockets like reporting
  2015. * of the level OSA sets the first character to zero
  2016. * */
  2017. if (!card->info.mcl_level[0]) {
  2018. sprintf(card->info.mcl_level, "%02x%02x",
  2019. card->info.mcl_level[2],
  2020. card->info.mcl_level[3]);
  2021. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2022. break;
  2023. }
  2024. /* fallthrough */
  2025. case QETH_CARD_TYPE_IQD:
  2026. if ((card->info.guestlan) ||
  2027. (card->info.mcl_level[0] & 0x80)) {
  2028. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2029. card->info.mcl_level[0]];
  2030. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2031. card->info.mcl_level[1]];
  2032. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2033. card->info.mcl_level[2]];
  2034. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2035. card->info.mcl_level[3]];
  2036. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2037. }
  2038. break;
  2039. default:
  2040. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2041. }
  2042. if (card->info.portname_required)
  2043. qeth_print_status_with_portname(card);
  2044. else
  2045. qeth_print_status_no_portname(card);
  2046. }
  2047. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2048. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2049. {
  2050. struct qeth_buffer_pool_entry *entry;
  2051. QETH_CARD_TEXT(card, 5, "inwrklst");
  2052. list_for_each_entry(entry,
  2053. &card->qdio.init_pool.entry_list, init_list) {
  2054. qeth_put_buffer_pool_entry(card, entry);
  2055. }
  2056. }
  2057. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2058. struct qeth_card *card)
  2059. {
  2060. struct list_head *plh;
  2061. struct qeth_buffer_pool_entry *entry;
  2062. int i, free;
  2063. struct page *page;
  2064. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2065. return NULL;
  2066. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2067. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2068. free = 1;
  2069. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2070. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2071. free = 0;
  2072. break;
  2073. }
  2074. }
  2075. if (free) {
  2076. list_del_init(&entry->list);
  2077. return entry;
  2078. }
  2079. }
  2080. /* no free buffer in pool so take first one and swap pages */
  2081. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2082. struct qeth_buffer_pool_entry, list);
  2083. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2084. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2085. page = alloc_page(GFP_ATOMIC);
  2086. if (!page) {
  2087. return NULL;
  2088. } else {
  2089. free_page((unsigned long)entry->elements[i]);
  2090. entry->elements[i] = page_address(page);
  2091. if (card->options.performance_stats)
  2092. card->perf_stats.sg_alloc_page_rx++;
  2093. }
  2094. }
  2095. }
  2096. list_del_init(&entry->list);
  2097. return entry;
  2098. }
  2099. static int qeth_init_input_buffer(struct qeth_card *card,
  2100. struct qeth_qdio_buffer *buf)
  2101. {
  2102. struct qeth_buffer_pool_entry *pool_entry;
  2103. int i;
  2104. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2105. if (!pool_entry)
  2106. return 1;
  2107. /*
  2108. * since the buffer is accessed only from the input_tasklet
  2109. * there shouldn't be a need to synchronize; also, since we use
  2110. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2111. * buffers
  2112. */
  2113. buf->pool_entry = pool_entry;
  2114. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2115. buf->buffer->element[i].length = PAGE_SIZE;
  2116. buf->buffer->element[i].addr = pool_entry->elements[i];
  2117. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2118. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2119. else
  2120. buf->buffer->element[i].flags = 0;
  2121. }
  2122. return 0;
  2123. }
  2124. int qeth_init_qdio_queues(struct qeth_card *card)
  2125. {
  2126. int i, j;
  2127. int rc;
  2128. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2129. /* inbound queue */
  2130. memset(card->qdio.in_q->qdio_bufs, 0,
  2131. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2132. qeth_initialize_working_pool_list(card);
  2133. /*give only as many buffers to hardware as we have buffer pool entries*/
  2134. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2135. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2136. card->qdio.in_q->next_buf_to_init =
  2137. card->qdio.in_buf_pool.buf_count - 1;
  2138. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2139. card->qdio.in_buf_pool.buf_count - 1);
  2140. if (rc) {
  2141. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2142. return rc;
  2143. }
  2144. /* outbound queue */
  2145. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2146. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2147. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2148. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2149. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2150. &card->qdio.out_qs[i]->bufs[j]);
  2151. }
  2152. card->qdio.out_qs[i]->card = card;
  2153. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2154. card->qdio.out_qs[i]->do_pack = 0;
  2155. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2156. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2157. atomic_set(&card->qdio.out_qs[i]->state,
  2158. QETH_OUT_Q_UNLOCKED);
  2159. }
  2160. return 0;
  2161. }
  2162. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2163. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2164. {
  2165. switch (link_type) {
  2166. case QETH_LINK_TYPE_HSTR:
  2167. return 2;
  2168. default:
  2169. return 1;
  2170. }
  2171. }
  2172. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2173. struct qeth_ipa_cmd *cmd, __u8 command,
  2174. enum qeth_prot_versions prot)
  2175. {
  2176. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2177. cmd->hdr.command = command;
  2178. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2179. cmd->hdr.seqno = card->seqno.ipa;
  2180. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2181. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2182. if (card->options.layer2)
  2183. cmd->hdr.prim_version_no = 2;
  2184. else
  2185. cmd->hdr.prim_version_no = 1;
  2186. cmd->hdr.param_count = 1;
  2187. cmd->hdr.prot_version = prot;
  2188. cmd->hdr.ipa_supported = 0;
  2189. cmd->hdr.ipa_enabled = 0;
  2190. }
  2191. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2192. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2193. {
  2194. struct qeth_cmd_buffer *iob;
  2195. struct qeth_ipa_cmd *cmd;
  2196. iob = qeth_wait_for_buffer(&card->write);
  2197. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2198. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2199. return iob;
  2200. }
  2201. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2202. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2203. char prot_type)
  2204. {
  2205. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2206. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2207. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2208. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2209. }
  2210. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2211. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2212. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2213. unsigned long),
  2214. void *reply_param)
  2215. {
  2216. int rc;
  2217. char prot_type;
  2218. QETH_CARD_TEXT(card, 4, "sendipa");
  2219. if (card->options.layer2)
  2220. if (card->info.type == QETH_CARD_TYPE_OSN)
  2221. prot_type = QETH_PROT_OSN2;
  2222. else
  2223. prot_type = QETH_PROT_LAYER2;
  2224. else
  2225. prot_type = QETH_PROT_TCPIP;
  2226. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2227. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2228. iob, reply_cb, reply_param);
  2229. return rc;
  2230. }
  2231. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2232. static int qeth_send_startstoplan(struct qeth_card *card,
  2233. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2234. {
  2235. int rc;
  2236. struct qeth_cmd_buffer *iob;
  2237. iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
  2238. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2239. return rc;
  2240. }
  2241. int qeth_send_startlan(struct qeth_card *card)
  2242. {
  2243. int rc;
  2244. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2245. rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
  2246. return rc;
  2247. }
  2248. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2249. int qeth_send_stoplan(struct qeth_card *card)
  2250. {
  2251. int rc = 0;
  2252. /*
  2253. * TODO: according to the IPA format document page 14,
  2254. * TCP/IP (we!) never issue a STOPLAN
  2255. * is this right ?!?
  2256. */
  2257. QETH_DBF_TEXT(SETUP, 2, "stoplan");
  2258. rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
  2259. return rc;
  2260. }
  2261. EXPORT_SYMBOL_GPL(qeth_send_stoplan);
  2262. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2263. struct qeth_reply *reply, unsigned long data)
  2264. {
  2265. struct qeth_ipa_cmd *cmd;
  2266. QETH_CARD_TEXT(card, 4, "defadpcb");
  2267. cmd = (struct qeth_ipa_cmd *) data;
  2268. if (cmd->hdr.return_code == 0)
  2269. cmd->hdr.return_code =
  2270. cmd->data.setadapterparms.hdr.return_code;
  2271. return 0;
  2272. }
  2273. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2274. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2275. struct qeth_reply *reply, unsigned long data)
  2276. {
  2277. struct qeth_ipa_cmd *cmd;
  2278. QETH_CARD_TEXT(card, 3, "quyadpcb");
  2279. cmd = (struct qeth_ipa_cmd *) data;
  2280. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f) {
  2281. card->info.link_type =
  2282. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2283. QETH_DBF_TEXT_(SETUP, 2, "lnk %d", card->info.link_type);
  2284. }
  2285. card->options.adp.supported_funcs =
  2286. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2287. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2288. }
  2289. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2290. __u32 command, __u32 cmdlen)
  2291. {
  2292. struct qeth_cmd_buffer *iob;
  2293. struct qeth_ipa_cmd *cmd;
  2294. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2295. QETH_PROT_IPV4);
  2296. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2297. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2298. cmd->data.setadapterparms.hdr.command_code = command;
  2299. cmd->data.setadapterparms.hdr.used_total = 1;
  2300. cmd->data.setadapterparms.hdr.seq_no = 1;
  2301. return iob;
  2302. }
  2303. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2304. int qeth_query_setadapterparms(struct qeth_card *card)
  2305. {
  2306. int rc;
  2307. struct qeth_cmd_buffer *iob;
  2308. QETH_CARD_TEXT(card, 3, "queryadp");
  2309. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2310. sizeof(struct qeth_ipacmd_setadpparms));
  2311. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2312. return rc;
  2313. }
  2314. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2315. int qeth_check_qdio_errors(struct qeth_card *card, struct qdio_buffer *buf,
  2316. unsigned int qdio_error, const char *dbftext)
  2317. {
  2318. if (qdio_error) {
  2319. QETH_CARD_TEXT(card, 2, dbftext);
  2320. QETH_CARD_TEXT_(card, 2, " F15=%02X",
  2321. buf->element[15].flags & 0xff);
  2322. QETH_CARD_TEXT_(card, 2, " F14=%02X",
  2323. buf->element[14].flags & 0xff);
  2324. QETH_CARD_TEXT_(card, 2, " qerr=%X", qdio_error);
  2325. if ((buf->element[15].flags & 0xff) == 0x12) {
  2326. card->stats.rx_dropped++;
  2327. return 0;
  2328. } else
  2329. return 1;
  2330. }
  2331. return 0;
  2332. }
  2333. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2334. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2335. {
  2336. struct qeth_qdio_q *queue = card->qdio.in_q;
  2337. int count;
  2338. int i;
  2339. int rc;
  2340. int newcount = 0;
  2341. count = (index < queue->next_buf_to_init)?
  2342. card->qdio.in_buf_pool.buf_count -
  2343. (queue->next_buf_to_init - index) :
  2344. card->qdio.in_buf_pool.buf_count -
  2345. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2346. /* only requeue at a certain threshold to avoid SIGAs */
  2347. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2348. for (i = queue->next_buf_to_init;
  2349. i < queue->next_buf_to_init + count; ++i) {
  2350. if (qeth_init_input_buffer(card,
  2351. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2352. break;
  2353. } else {
  2354. newcount++;
  2355. }
  2356. }
  2357. if (newcount < count) {
  2358. /* we are in memory shortage so we switch back to
  2359. traditional skb allocation and drop packages */
  2360. atomic_set(&card->force_alloc_skb, 3);
  2361. count = newcount;
  2362. } else {
  2363. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2364. }
  2365. /*
  2366. * according to old code it should be avoided to requeue all
  2367. * 128 buffers in order to benefit from PCI avoidance.
  2368. * this function keeps at least one buffer (the buffer at
  2369. * 'index') un-requeued -> this buffer is the first buffer that
  2370. * will be requeued the next time
  2371. */
  2372. if (card->options.performance_stats) {
  2373. card->perf_stats.inbound_do_qdio_cnt++;
  2374. card->perf_stats.inbound_do_qdio_start_time =
  2375. qeth_get_micros();
  2376. }
  2377. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2378. queue->next_buf_to_init, count);
  2379. if (card->options.performance_stats)
  2380. card->perf_stats.inbound_do_qdio_time +=
  2381. qeth_get_micros() -
  2382. card->perf_stats.inbound_do_qdio_start_time;
  2383. if (rc) {
  2384. dev_warn(&card->gdev->dev,
  2385. "QDIO reported an error, rc=%i\n", rc);
  2386. QETH_CARD_TEXT(card, 2, "qinberr");
  2387. }
  2388. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2389. QDIO_MAX_BUFFERS_PER_Q;
  2390. }
  2391. }
  2392. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2393. static int qeth_handle_send_error(struct qeth_card *card,
  2394. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2395. {
  2396. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2397. QETH_CARD_TEXT(card, 6, "hdsnderr");
  2398. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2399. if (sbalf15 == 0) {
  2400. qdio_err = 0;
  2401. } else {
  2402. qdio_err = 1;
  2403. }
  2404. }
  2405. qeth_check_qdio_errors(card, buffer->buffer, qdio_err, "qouterr");
  2406. if (!qdio_err)
  2407. return QETH_SEND_ERROR_NONE;
  2408. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2409. return QETH_SEND_ERROR_RETRY;
  2410. QETH_CARD_TEXT(card, 1, "lnkfail");
  2411. QETH_CARD_TEXT_(card, 1, "%04x %02x",
  2412. (u16)qdio_err, (u8)sbalf15);
  2413. return QETH_SEND_ERROR_LINK_FAILURE;
  2414. }
  2415. /*
  2416. * Switched to packing state if the number of used buffers on a queue
  2417. * reaches a certain limit.
  2418. */
  2419. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2420. {
  2421. if (!queue->do_pack) {
  2422. if (atomic_read(&queue->used_buffers)
  2423. >= QETH_HIGH_WATERMARK_PACK){
  2424. /* switch non-PACKING -> PACKING */
  2425. QETH_CARD_TEXT(queue->card, 6, "np->pack");
  2426. if (queue->card->options.performance_stats)
  2427. queue->card->perf_stats.sc_dp_p++;
  2428. queue->do_pack = 1;
  2429. }
  2430. }
  2431. }
  2432. /*
  2433. * Switches from packing to non-packing mode. If there is a packing
  2434. * buffer on the queue this buffer will be prepared to be flushed.
  2435. * In that case 1 is returned to inform the caller. If no buffer
  2436. * has to be flushed, zero is returned.
  2437. */
  2438. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2439. {
  2440. struct qeth_qdio_out_buffer *buffer;
  2441. int flush_count = 0;
  2442. if (queue->do_pack) {
  2443. if (atomic_read(&queue->used_buffers)
  2444. <= QETH_LOW_WATERMARK_PACK) {
  2445. /* switch PACKING -> non-PACKING */
  2446. QETH_CARD_TEXT(queue->card, 6, "pack->np");
  2447. if (queue->card->options.performance_stats)
  2448. queue->card->perf_stats.sc_p_dp++;
  2449. queue->do_pack = 0;
  2450. /* flush packing buffers */
  2451. buffer = &queue->bufs[queue->next_buf_to_fill];
  2452. if ((atomic_read(&buffer->state) ==
  2453. QETH_QDIO_BUF_EMPTY) &&
  2454. (buffer->next_element_to_fill > 0)) {
  2455. atomic_set(&buffer->state,
  2456. QETH_QDIO_BUF_PRIMED);
  2457. flush_count++;
  2458. queue->next_buf_to_fill =
  2459. (queue->next_buf_to_fill + 1) %
  2460. QDIO_MAX_BUFFERS_PER_Q;
  2461. }
  2462. }
  2463. }
  2464. return flush_count;
  2465. }
  2466. /*
  2467. * Called to flush a packing buffer if no more pci flags are on the queue.
  2468. * Checks if there is a packing buffer and prepares it to be flushed.
  2469. * In that case returns 1, otherwise zero.
  2470. */
  2471. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2472. {
  2473. struct qeth_qdio_out_buffer *buffer;
  2474. buffer = &queue->bufs[queue->next_buf_to_fill];
  2475. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2476. (buffer->next_element_to_fill > 0)) {
  2477. /* it's a packing buffer */
  2478. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2479. queue->next_buf_to_fill =
  2480. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2481. return 1;
  2482. }
  2483. return 0;
  2484. }
  2485. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2486. int count)
  2487. {
  2488. struct qeth_qdio_out_buffer *buf;
  2489. int rc;
  2490. int i;
  2491. unsigned int qdio_flags;
  2492. for (i = index; i < index + count; ++i) {
  2493. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2494. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2495. SBAL_FLAGS_LAST_ENTRY;
  2496. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2497. continue;
  2498. if (!queue->do_pack) {
  2499. if ((atomic_read(&queue->used_buffers) >=
  2500. (QETH_HIGH_WATERMARK_PACK -
  2501. QETH_WATERMARK_PACK_FUZZ)) &&
  2502. !atomic_read(&queue->set_pci_flags_count)) {
  2503. /* it's likely that we'll go to packing
  2504. * mode soon */
  2505. atomic_inc(&queue->set_pci_flags_count);
  2506. buf->buffer->element[0].flags |= 0x40;
  2507. }
  2508. } else {
  2509. if (!atomic_read(&queue->set_pci_flags_count)) {
  2510. /*
  2511. * there's no outstanding PCI any more, so we
  2512. * have to request a PCI to be sure the the PCI
  2513. * will wake at some time in the future then we
  2514. * can flush packed buffers that might still be
  2515. * hanging around, which can happen if no
  2516. * further send was requested by the stack
  2517. */
  2518. atomic_inc(&queue->set_pci_flags_count);
  2519. buf->buffer->element[0].flags |= 0x40;
  2520. }
  2521. }
  2522. }
  2523. queue->sync_iqdio_error = 0;
  2524. queue->card->dev->trans_start = jiffies;
  2525. if (queue->card->options.performance_stats) {
  2526. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2527. queue->card->perf_stats.outbound_do_qdio_start_time =
  2528. qeth_get_micros();
  2529. }
  2530. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2531. if (atomic_read(&queue->set_pci_flags_count))
  2532. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2533. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2534. queue->queue_no, index, count);
  2535. if (queue->card->options.performance_stats)
  2536. queue->card->perf_stats.outbound_do_qdio_time +=
  2537. qeth_get_micros() -
  2538. queue->card->perf_stats.outbound_do_qdio_start_time;
  2539. if (rc > 0) {
  2540. if (!(rc & QDIO_ERROR_SIGA_BUSY))
  2541. queue->sync_iqdio_error = rc & 3;
  2542. }
  2543. if (rc) {
  2544. queue->card->stats.tx_errors += count;
  2545. /* ignore temporary SIGA errors without busy condition */
  2546. if (rc == QDIO_ERROR_SIGA_TARGET)
  2547. return;
  2548. QETH_CARD_TEXT(queue->card, 2, "flushbuf");
  2549. QETH_CARD_TEXT_(queue->card, 2, " err%d", rc);
  2550. /* this must not happen under normal circumstances. if it
  2551. * happens something is really wrong -> recover */
  2552. qeth_schedule_recovery(queue->card);
  2553. return;
  2554. }
  2555. atomic_add(count, &queue->used_buffers);
  2556. if (queue->card->options.performance_stats)
  2557. queue->card->perf_stats.bufs_sent += count;
  2558. }
  2559. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2560. {
  2561. int index;
  2562. int flush_cnt = 0;
  2563. int q_was_packing = 0;
  2564. /*
  2565. * check if weed have to switch to non-packing mode or if
  2566. * we have to get a pci flag out on the queue
  2567. */
  2568. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2569. !atomic_read(&queue->set_pci_flags_count)) {
  2570. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2571. QETH_OUT_Q_UNLOCKED) {
  2572. /*
  2573. * If we get in here, there was no action in
  2574. * do_send_packet. So, we check if there is a
  2575. * packing buffer to be flushed here.
  2576. */
  2577. netif_stop_queue(queue->card->dev);
  2578. index = queue->next_buf_to_fill;
  2579. q_was_packing = queue->do_pack;
  2580. /* queue->do_pack may change */
  2581. barrier();
  2582. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2583. if (!flush_cnt &&
  2584. !atomic_read(&queue->set_pci_flags_count))
  2585. flush_cnt +=
  2586. qeth_flush_buffers_on_no_pci(queue);
  2587. if (queue->card->options.performance_stats &&
  2588. q_was_packing)
  2589. queue->card->perf_stats.bufs_sent_pack +=
  2590. flush_cnt;
  2591. if (flush_cnt)
  2592. qeth_flush_buffers(queue, index, flush_cnt);
  2593. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2594. }
  2595. }
  2596. }
  2597. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  2598. unsigned int qdio_error, int __queue, int first_element,
  2599. int count, unsigned long card_ptr)
  2600. {
  2601. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2602. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2603. struct qeth_qdio_out_buffer *buffer;
  2604. int i;
  2605. unsigned qeth_send_err;
  2606. QETH_CARD_TEXT(card, 6, "qdouhdl");
  2607. if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
  2608. QETH_CARD_TEXT(card, 2, "achkcond");
  2609. netif_stop_queue(card->dev);
  2610. qeth_schedule_recovery(card);
  2611. return;
  2612. }
  2613. if (card->options.performance_stats) {
  2614. card->perf_stats.outbound_handler_cnt++;
  2615. card->perf_stats.outbound_handler_start_time =
  2616. qeth_get_micros();
  2617. }
  2618. for (i = first_element; i < (first_element + count); ++i) {
  2619. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2620. qeth_send_err = qeth_handle_send_error(card, buffer, qdio_error);
  2621. __qeth_clear_output_buffer(queue, buffer,
  2622. (qeth_send_err == QETH_SEND_ERROR_RETRY) ? 1 : 0);
  2623. }
  2624. atomic_sub(count, &queue->used_buffers);
  2625. /* check if we need to do something on this outbound queue */
  2626. if (card->info.type != QETH_CARD_TYPE_IQD)
  2627. qeth_check_outbound_queue(queue);
  2628. netif_wake_queue(queue->card->dev);
  2629. if (card->options.performance_stats)
  2630. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2631. card->perf_stats.outbound_handler_start_time;
  2632. }
  2633. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2634. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2635. int ipv, int cast_type)
  2636. {
  2637. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSD ||
  2638. card->info.type == QETH_CARD_TYPE_OSX))
  2639. return card->qdio.default_out_queue;
  2640. switch (card->qdio.no_out_queues) {
  2641. case 4:
  2642. if (cast_type && card->info.is_multicast_different)
  2643. return card->info.is_multicast_different &
  2644. (card->qdio.no_out_queues - 1);
  2645. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2646. const u8 tos = ip_hdr(skb)->tos;
  2647. if (card->qdio.do_prio_queueing ==
  2648. QETH_PRIO_Q_ING_TOS) {
  2649. if (tos & IP_TOS_NOTIMPORTANT)
  2650. return 3;
  2651. if (tos & IP_TOS_HIGHRELIABILITY)
  2652. return 2;
  2653. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2654. return 1;
  2655. if (tos & IP_TOS_LOWDELAY)
  2656. return 0;
  2657. }
  2658. if (card->qdio.do_prio_queueing ==
  2659. QETH_PRIO_Q_ING_PREC)
  2660. return 3 - (tos >> 6);
  2661. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2662. /* TODO: IPv6!!! */
  2663. }
  2664. return card->qdio.default_out_queue;
  2665. case 1: /* fallthrough for single-out-queue 1920-device */
  2666. default:
  2667. return card->qdio.default_out_queue;
  2668. }
  2669. }
  2670. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2671. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2672. struct sk_buff *skb, int elems)
  2673. {
  2674. int dlen = skb->len - skb->data_len;
  2675. int elements_needed = PFN_UP((unsigned long)skb->data + dlen - 1) -
  2676. PFN_DOWN((unsigned long)skb->data);
  2677. elements_needed += skb_shinfo(skb)->nr_frags;
  2678. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2679. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  2680. "(Number=%d / Length=%d). Discarded.\n",
  2681. (elements_needed+elems), skb->len);
  2682. return 0;
  2683. }
  2684. return elements_needed;
  2685. }
  2686. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2687. int qeth_hdr_chk_and_bounce(struct sk_buff *skb, int len)
  2688. {
  2689. int hroom, inpage, rest;
  2690. if (((unsigned long)skb->data & PAGE_MASK) !=
  2691. (((unsigned long)skb->data + len - 1) & PAGE_MASK)) {
  2692. hroom = skb_headroom(skb);
  2693. inpage = PAGE_SIZE - ((unsigned long) skb->data % PAGE_SIZE);
  2694. rest = len - inpage;
  2695. if (rest > hroom)
  2696. return 1;
  2697. memmove(skb->data - rest, skb->data, skb->len - skb->data_len);
  2698. skb->data -= rest;
  2699. QETH_DBF_MESSAGE(2, "skb bounce len: %d rest: %d\n", len, rest);
  2700. }
  2701. return 0;
  2702. }
  2703. EXPORT_SYMBOL_GPL(qeth_hdr_chk_and_bounce);
  2704. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  2705. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  2706. int offset)
  2707. {
  2708. int length = skb->len - skb->data_len;
  2709. int length_here;
  2710. int element;
  2711. char *data;
  2712. int first_lap, cnt;
  2713. struct skb_frag_struct *frag;
  2714. element = *next_element_to_fill;
  2715. data = skb->data;
  2716. first_lap = (is_tso == 0 ? 1 : 0);
  2717. if (offset >= 0) {
  2718. data = skb->data + offset;
  2719. length -= offset;
  2720. first_lap = 0;
  2721. }
  2722. while (length > 0) {
  2723. /* length_here is the remaining amount of data in this page */
  2724. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2725. if (length < length_here)
  2726. length_here = length;
  2727. buffer->element[element].addr = data;
  2728. buffer->element[element].length = length_here;
  2729. length -= length_here;
  2730. if (!length) {
  2731. if (first_lap)
  2732. if (skb_shinfo(skb)->nr_frags)
  2733. buffer->element[element].flags =
  2734. SBAL_FLAGS_FIRST_FRAG;
  2735. else
  2736. buffer->element[element].flags = 0;
  2737. else
  2738. buffer->element[element].flags =
  2739. SBAL_FLAGS_MIDDLE_FRAG;
  2740. } else {
  2741. if (first_lap)
  2742. buffer->element[element].flags =
  2743. SBAL_FLAGS_FIRST_FRAG;
  2744. else
  2745. buffer->element[element].flags =
  2746. SBAL_FLAGS_MIDDLE_FRAG;
  2747. }
  2748. data += length_here;
  2749. element++;
  2750. first_lap = 0;
  2751. }
  2752. for (cnt = 0; cnt < skb_shinfo(skb)->nr_frags; cnt++) {
  2753. frag = &skb_shinfo(skb)->frags[cnt];
  2754. buffer->element[element].addr = (char *)page_to_phys(frag->page)
  2755. + frag->page_offset;
  2756. buffer->element[element].length = frag->size;
  2757. buffer->element[element].flags = SBAL_FLAGS_MIDDLE_FRAG;
  2758. element++;
  2759. }
  2760. if (buffer->element[element - 1].flags)
  2761. buffer->element[element - 1].flags = SBAL_FLAGS_LAST_FRAG;
  2762. *next_element_to_fill = element;
  2763. }
  2764. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2765. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  2766. struct qeth_hdr *hdr, int offset, int hd_len)
  2767. {
  2768. struct qdio_buffer *buffer;
  2769. int flush_cnt = 0, hdr_len, large_send = 0;
  2770. buffer = buf->buffer;
  2771. atomic_inc(&skb->users);
  2772. skb_queue_tail(&buf->skb_list, skb);
  2773. /*check first on TSO ....*/
  2774. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2775. int element = buf->next_element_to_fill;
  2776. hdr_len = sizeof(struct qeth_hdr_tso) +
  2777. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  2778. /*fill first buffer entry only with header information */
  2779. buffer->element[element].addr = skb->data;
  2780. buffer->element[element].length = hdr_len;
  2781. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2782. buf->next_element_to_fill++;
  2783. skb->data += hdr_len;
  2784. skb->len -= hdr_len;
  2785. large_send = 1;
  2786. }
  2787. if (offset >= 0) {
  2788. int element = buf->next_element_to_fill;
  2789. buffer->element[element].addr = hdr;
  2790. buffer->element[element].length = sizeof(struct qeth_hdr) +
  2791. hd_len;
  2792. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2793. buf->is_header[element] = 1;
  2794. buf->next_element_to_fill++;
  2795. }
  2796. __qeth_fill_buffer(skb, buffer, large_send,
  2797. (int *)&buf->next_element_to_fill, offset);
  2798. if (!queue->do_pack) {
  2799. QETH_CARD_TEXT(queue->card, 6, "fillbfnp");
  2800. /* set state to PRIMED -> will be flushed */
  2801. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2802. flush_cnt = 1;
  2803. } else {
  2804. QETH_CARD_TEXT(queue->card, 6, "fillbfpa");
  2805. if (queue->card->options.performance_stats)
  2806. queue->card->perf_stats.skbs_sent_pack++;
  2807. if (buf->next_element_to_fill >=
  2808. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2809. /*
  2810. * packed buffer if full -> set state PRIMED
  2811. * -> will be flushed
  2812. */
  2813. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2814. flush_cnt = 1;
  2815. }
  2816. }
  2817. return flush_cnt;
  2818. }
  2819. int qeth_do_send_packet_fast(struct qeth_card *card,
  2820. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2821. struct qeth_hdr *hdr, int elements_needed,
  2822. int offset, int hd_len)
  2823. {
  2824. struct qeth_qdio_out_buffer *buffer;
  2825. struct sk_buff *skb1;
  2826. struct qeth_skb_data *retry_ctrl;
  2827. int index;
  2828. int rc;
  2829. /* spin until we get the queue ... */
  2830. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2831. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2832. /* ... now we've got the queue */
  2833. index = queue->next_buf_to_fill;
  2834. buffer = &queue->bufs[queue->next_buf_to_fill];
  2835. /*
  2836. * check if buffer is empty to make sure that we do not 'overtake'
  2837. * ourselves and try to fill a buffer that is already primed
  2838. */
  2839. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2840. goto out;
  2841. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2842. QDIO_MAX_BUFFERS_PER_Q;
  2843. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2844. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  2845. qeth_flush_buffers(queue, index, 1);
  2846. if (queue->sync_iqdio_error == 2) {
  2847. skb1 = skb_dequeue(&buffer->skb_list);
  2848. while (skb1) {
  2849. atomic_dec(&skb1->users);
  2850. skb1 = skb_dequeue(&buffer->skb_list);
  2851. }
  2852. retry_ctrl = (struct qeth_skb_data *) &skb->cb[16];
  2853. if (retry_ctrl->magic != QETH_SKB_MAGIC) {
  2854. retry_ctrl->magic = QETH_SKB_MAGIC;
  2855. retry_ctrl->count = 0;
  2856. }
  2857. if (retry_ctrl->count < QETH_SIGA_CC2_RETRIES) {
  2858. retry_ctrl->count++;
  2859. rc = dev_queue_xmit(skb);
  2860. } else {
  2861. dev_kfree_skb_any(skb);
  2862. QETH_CARD_TEXT(card, 2, "qrdrop");
  2863. }
  2864. }
  2865. return 0;
  2866. out:
  2867. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2868. return -EBUSY;
  2869. }
  2870. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2871. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2872. struct sk_buff *skb, struct qeth_hdr *hdr,
  2873. int elements_needed)
  2874. {
  2875. struct qeth_qdio_out_buffer *buffer;
  2876. int start_index;
  2877. int flush_count = 0;
  2878. int do_pack = 0;
  2879. int tmp;
  2880. int rc = 0;
  2881. /* spin until we get the queue ... */
  2882. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2883. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2884. start_index = queue->next_buf_to_fill;
  2885. buffer = &queue->bufs[queue->next_buf_to_fill];
  2886. /*
  2887. * check if buffer is empty to make sure that we do not 'overtake'
  2888. * ourselves and try to fill a buffer that is already primed
  2889. */
  2890. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2891. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2892. return -EBUSY;
  2893. }
  2894. /* check if we need to switch packing state of this queue */
  2895. qeth_switch_to_packing_if_needed(queue);
  2896. if (queue->do_pack) {
  2897. do_pack = 1;
  2898. /* does packet fit in current buffer? */
  2899. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2900. buffer->next_element_to_fill) < elements_needed) {
  2901. /* ... no -> set state PRIMED */
  2902. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2903. flush_count++;
  2904. queue->next_buf_to_fill =
  2905. (queue->next_buf_to_fill + 1) %
  2906. QDIO_MAX_BUFFERS_PER_Q;
  2907. buffer = &queue->bufs[queue->next_buf_to_fill];
  2908. /* we did a step forward, so check buffer state
  2909. * again */
  2910. if (atomic_read(&buffer->state) !=
  2911. QETH_QDIO_BUF_EMPTY) {
  2912. qeth_flush_buffers(queue, start_index,
  2913. flush_count);
  2914. atomic_set(&queue->state,
  2915. QETH_OUT_Q_UNLOCKED);
  2916. return -EBUSY;
  2917. }
  2918. }
  2919. }
  2920. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  2921. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  2922. QDIO_MAX_BUFFERS_PER_Q;
  2923. flush_count += tmp;
  2924. if (flush_count)
  2925. qeth_flush_buffers(queue, start_index, flush_count);
  2926. else if (!atomic_read(&queue->set_pci_flags_count))
  2927. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  2928. /*
  2929. * queue->state will go from LOCKED -> UNLOCKED or from
  2930. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  2931. * (switch packing state or flush buffer to get another pci flag out).
  2932. * In that case we will enter this loop
  2933. */
  2934. while (atomic_dec_return(&queue->state)) {
  2935. flush_count = 0;
  2936. start_index = queue->next_buf_to_fill;
  2937. /* check if we can go back to non-packing state */
  2938. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  2939. /*
  2940. * check if we need to flush a packing buffer to get a pci
  2941. * flag out on the queue
  2942. */
  2943. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  2944. flush_count += qeth_flush_buffers_on_no_pci(queue);
  2945. if (flush_count)
  2946. qeth_flush_buffers(queue, start_index, flush_count);
  2947. }
  2948. /* at this point the queue is UNLOCKED again */
  2949. if (queue->card->options.performance_stats && do_pack)
  2950. queue->card->perf_stats.bufs_sent_pack += flush_count;
  2951. return rc;
  2952. }
  2953. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  2954. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  2955. struct qeth_reply *reply, unsigned long data)
  2956. {
  2957. struct qeth_ipa_cmd *cmd;
  2958. struct qeth_ipacmd_setadpparms *setparms;
  2959. QETH_CARD_TEXT(card, 4, "prmadpcb");
  2960. cmd = (struct qeth_ipa_cmd *) data;
  2961. setparms = &(cmd->data.setadapterparms);
  2962. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2963. if (cmd->hdr.return_code) {
  2964. QETH_CARD_TEXT_(card, 4, "prmrc%2.2x", cmd->hdr.return_code);
  2965. setparms->data.mode = SET_PROMISC_MODE_OFF;
  2966. }
  2967. card->info.promisc_mode = setparms->data.mode;
  2968. return 0;
  2969. }
  2970. void qeth_setadp_promisc_mode(struct qeth_card *card)
  2971. {
  2972. enum qeth_ipa_promisc_modes mode;
  2973. struct net_device *dev = card->dev;
  2974. struct qeth_cmd_buffer *iob;
  2975. struct qeth_ipa_cmd *cmd;
  2976. QETH_CARD_TEXT(card, 4, "setprom");
  2977. if (((dev->flags & IFF_PROMISC) &&
  2978. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  2979. (!(dev->flags & IFF_PROMISC) &&
  2980. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  2981. return;
  2982. mode = SET_PROMISC_MODE_OFF;
  2983. if (dev->flags & IFF_PROMISC)
  2984. mode = SET_PROMISC_MODE_ON;
  2985. QETH_CARD_TEXT_(card, 4, "mode:%x", mode);
  2986. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  2987. sizeof(struct qeth_ipacmd_setadpparms));
  2988. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  2989. cmd->data.setadapterparms.data.mode = mode;
  2990. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  2991. }
  2992. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  2993. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  2994. {
  2995. struct qeth_card *card;
  2996. char dbf_text[15];
  2997. card = dev->ml_priv;
  2998. QETH_CARD_TEXT(card, 4, "chgmtu");
  2999. sprintf(dbf_text, "%8x", new_mtu);
  3000. QETH_CARD_TEXT(card, 4, dbf_text);
  3001. if (new_mtu < 64)
  3002. return -EINVAL;
  3003. if (new_mtu > 65535)
  3004. return -EINVAL;
  3005. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3006. (!qeth_mtu_is_valid(card, new_mtu)))
  3007. return -EINVAL;
  3008. dev->mtu = new_mtu;
  3009. return 0;
  3010. }
  3011. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3012. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3013. {
  3014. struct qeth_card *card;
  3015. card = dev->ml_priv;
  3016. QETH_CARD_TEXT(card, 5, "getstat");
  3017. return &card->stats;
  3018. }
  3019. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3020. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3021. struct qeth_reply *reply, unsigned long data)
  3022. {
  3023. struct qeth_ipa_cmd *cmd;
  3024. QETH_CARD_TEXT(card, 4, "chgmaccb");
  3025. cmd = (struct qeth_ipa_cmd *) data;
  3026. if (!card->options.layer2 ||
  3027. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3028. memcpy(card->dev->dev_addr,
  3029. &cmd->data.setadapterparms.data.change_addr.addr,
  3030. OSA_ADDR_LEN);
  3031. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3032. }
  3033. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3034. return 0;
  3035. }
  3036. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3037. {
  3038. int rc;
  3039. struct qeth_cmd_buffer *iob;
  3040. struct qeth_ipa_cmd *cmd;
  3041. QETH_CARD_TEXT(card, 4, "chgmac");
  3042. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3043. sizeof(struct qeth_ipacmd_setadpparms));
  3044. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3045. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3046. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3047. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3048. card->dev->dev_addr, OSA_ADDR_LEN);
  3049. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3050. NULL);
  3051. return rc;
  3052. }
  3053. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3054. static int qeth_setadpparms_set_access_ctrl_cb(struct qeth_card *card,
  3055. struct qeth_reply *reply, unsigned long data)
  3056. {
  3057. struct qeth_ipa_cmd *cmd;
  3058. struct qeth_set_access_ctrl *access_ctrl_req;
  3059. int rc;
  3060. QETH_CARD_TEXT(card, 4, "setaccb");
  3061. cmd = (struct qeth_ipa_cmd *) data;
  3062. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3063. QETH_DBF_TEXT_(SETUP, 2, "setaccb");
  3064. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3065. QETH_DBF_TEXT_(SETUP, 2, "rc=%d",
  3066. cmd->data.setadapterparms.hdr.return_code);
  3067. switch (cmd->data.setadapterparms.hdr.return_code) {
  3068. case SET_ACCESS_CTRL_RC_SUCCESS:
  3069. case SET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED:
  3070. case SET_ACCESS_CTRL_RC_ALREADY_ISOLATED:
  3071. {
  3072. card->options.isolation = access_ctrl_req->subcmd_code;
  3073. if (card->options.isolation == ISOLATION_MODE_NONE) {
  3074. dev_info(&card->gdev->dev,
  3075. "QDIO data connection isolation is deactivated\n");
  3076. } else {
  3077. dev_info(&card->gdev->dev,
  3078. "QDIO data connection isolation is activated\n");
  3079. }
  3080. QETH_DBF_MESSAGE(3, "OK:SET_ACCESS_CTRL(%s, %d)==%d\n",
  3081. card->gdev->dev.kobj.name,
  3082. access_ctrl_req->subcmd_code,
  3083. cmd->data.setadapterparms.hdr.return_code);
  3084. rc = 0;
  3085. break;
  3086. }
  3087. case SET_ACCESS_CTRL_RC_NOT_SUPPORTED:
  3088. {
  3089. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_CTRL(%s,%d)==%d\n",
  3090. card->gdev->dev.kobj.name,
  3091. access_ctrl_req->subcmd_code,
  3092. cmd->data.setadapterparms.hdr.return_code);
  3093. dev_err(&card->gdev->dev, "Adapter does not "
  3094. "support QDIO data connection isolation\n");
  3095. /* ensure isolation mode is "none" */
  3096. card->options.isolation = ISOLATION_MODE_NONE;
  3097. rc = -EOPNOTSUPP;
  3098. break;
  3099. }
  3100. case SET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER:
  3101. {
  3102. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3103. card->gdev->dev.kobj.name,
  3104. access_ctrl_req->subcmd_code,
  3105. cmd->data.setadapterparms.hdr.return_code);
  3106. dev_err(&card->gdev->dev,
  3107. "Adapter is dedicated. "
  3108. "QDIO data connection isolation not supported\n");
  3109. /* ensure isolation mode is "none" */
  3110. card->options.isolation = ISOLATION_MODE_NONE;
  3111. rc = -EOPNOTSUPP;
  3112. break;
  3113. }
  3114. case SET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF:
  3115. {
  3116. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3117. card->gdev->dev.kobj.name,
  3118. access_ctrl_req->subcmd_code,
  3119. cmd->data.setadapterparms.hdr.return_code);
  3120. dev_err(&card->gdev->dev,
  3121. "TSO does not permit QDIO data connection isolation\n");
  3122. /* ensure isolation mode is "none" */
  3123. card->options.isolation = ISOLATION_MODE_NONE;
  3124. rc = -EPERM;
  3125. break;
  3126. }
  3127. default:
  3128. {
  3129. /* this should never happen */
  3130. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d"
  3131. "==UNKNOWN\n",
  3132. card->gdev->dev.kobj.name,
  3133. access_ctrl_req->subcmd_code,
  3134. cmd->data.setadapterparms.hdr.return_code);
  3135. /* ensure isolation mode is "none" */
  3136. card->options.isolation = ISOLATION_MODE_NONE;
  3137. rc = 0;
  3138. break;
  3139. }
  3140. }
  3141. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3142. return rc;
  3143. }
  3144. static int qeth_setadpparms_set_access_ctrl(struct qeth_card *card,
  3145. enum qeth_ipa_isolation_modes isolation)
  3146. {
  3147. int rc;
  3148. struct qeth_cmd_buffer *iob;
  3149. struct qeth_ipa_cmd *cmd;
  3150. struct qeth_set_access_ctrl *access_ctrl_req;
  3151. QETH_CARD_TEXT(card, 4, "setacctl");
  3152. QETH_DBF_TEXT_(SETUP, 2, "setacctl");
  3153. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3154. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,
  3155. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3156. sizeof(struct qeth_set_access_ctrl));
  3157. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3158. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3159. access_ctrl_req->subcmd_code = isolation;
  3160. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_set_access_ctrl_cb,
  3161. NULL);
  3162. QETH_DBF_TEXT_(SETUP, 2, "rc=%d", rc);
  3163. return rc;
  3164. }
  3165. int qeth_set_access_ctrl_online(struct qeth_card *card)
  3166. {
  3167. int rc = 0;
  3168. QETH_CARD_TEXT(card, 4, "setactlo");
  3169. if ((card->info.type == QETH_CARD_TYPE_OSD ||
  3170. card->info.type == QETH_CARD_TYPE_OSX) &&
  3171. qeth_adp_supported(card, IPA_SETADP_SET_ACCESS_CONTROL)) {
  3172. rc = qeth_setadpparms_set_access_ctrl(card,
  3173. card->options.isolation);
  3174. if (rc) {
  3175. QETH_DBF_MESSAGE(3,
  3176. "IPA(SET_ACCESS_CTRL,%s,%d) sent failed\n",
  3177. card->gdev->dev.kobj.name,
  3178. rc);
  3179. }
  3180. } else if (card->options.isolation != ISOLATION_MODE_NONE) {
  3181. card->options.isolation = ISOLATION_MODE_NONE;
  3182. dev_err(&card->gdev->dev, "Adapter does not "
  3183. "support QDIO data connection isolation\n");
  3184. rc = -EOPNOTSUPP;
  3185. }
  3186. return rc;
  3187. }
  3188. EXPORT_SYMBOL_GPL(qeth_set_access_ctrl_online);
  3189. void qeth_tx_timeout(struct net_device *dev)
  3190. {
  3191. struct qeth_card *card;
  3192. card = dev->ml_priv;
  3193. QETH_CARD_TEXT(card, 4, "txtimeo");
  3194. card->stats.tx_errors++;
  3195. qeth_schedule_recovery(card);
  3196. }
  3197. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3198. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3199. {
  3200. struct qeth_card *card = dev->ml_priv;
  3201. int rc = 0;
  3202. switch (regnum) {
  3203. case MII_BMCR: /* Basic mode control register */
  3204. rc = BMCR_FULLDPLX;
  3205. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3206. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3207. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3208. rc |= BMCR_SPEED100;
  3209. break;
  3210. case MII_BMSR: /* Basic mode status register */
  3211. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3212. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3213. BMSR_100BASE4;
  3214. break;
  3215. case MII_PHYSID1: /* PHYS ID 1 */
  3216. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3217. dev->dev_addr[2];
  3218. rc = (rc >> 5) & 0xFFFF;
  3219. break;
  3220. case MII_PHYSID2: /* PHYS ID 2 */
  3221. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3222. break;
  3223. case MII_ADVERTISE: /* Advertisement control reg */
  3224. rc = ADVERTISE_ALL;
  3225. break;
  3226. case MII_LPA: /* Link partner ability reg */
  3227. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3228. LPA_100BASE4 | LPA_LPACK;
  3229. break;
  3230. case MII_EXPANSION: /* Expansion register */
  3231. break;
  3232. case MII_DCOUNTER: /* disconnect counter */
  3233. break;
  3234. case MII_FCSCOUNTER: /* false carrier counter */
  3235. break;
  3236. case MII_NWAYTEST: /* N-way auto-neg test register */
  3237. break;
  3238. case MII_RERRCOUNTER: /* rx error counter */
  3239. rc = card->stats.rx_errors;
  3240. break;
  3241. case MII_SREVISION: /* silicon revision */
  3242. break;
  3243. case MII_RESV1: /* reserved 1 */
  3244. break;
  3245. case MII_LBRERROR: /* loopback, rx, bypass error */
  3246. break;
  3247. case MII_PHYADDR: /* physical address */
  3248. break;
  3249. case MII_RESV2: /* reserved 2 */
  3250. break;
  3251. case MII_TPISTATUS: /* TPI status for 10mbps */
  3252. break;
  3253. case MII_NCONFIG: /* network interface config */
  3254. break;
  3255. default:
  3256. break;
  3257. }
  3258. return rc;
  3259. }
  3260. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3261. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3262. struct qeth_cmd_buffer *iob, int len,
  3263. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3264. unsigned long),
  3265. void *reply_param)
  3266. {
  3267. u16 s1, s2;
  3268. QETH_CARD_TEXT(card, 4, "sendsnmp");
  3269. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3270. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3271. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3272. /* adjust PDU length fields in IPA_PDU_HEADER */
  3273. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3274. s2 = (u32) len;
  3275. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3276. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3277. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3278. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3279. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3280. reply_cb, reply_param);
  3281. }
  3282. static int qeth_snmp_command_cb(struct qeth_card *card,
  3283. struct qeth_reply *reply, unsigned long sdata)
  3284. {
  3285. struct qeth_ipa_cmd *cmd;
  3286. struct qeth_arp_query_info *qinfo;
  3287. struct qeth_snmp_cmd *snmp;
  3288. unsigned char *data;
  3289. __u16 data_len;
  3290. QETH_CARD_TEXT(card, 3, "snpcmdcb");
  3291. cmd = (struct qeth_ipa_cmd *) sdata;
  3292. data = (unsigned char *)((char *)cmd - reply->offset);
  3293. qinfo = (struct qeth_arp_query_info *) reply->param;
  3294. snmp = &cmd->data.setadapterparms.data.snmp;
  3295. if (cmd->hdr.return_code) {
  3296. QETH_CARD_TEXT_(card, 4, "scer1%i", cmd->hdr.return_code);
  3297. return 0;
  3298. }
  3299. if (cmd->data.setadapterparms.hdr.return_code) {
  3300. cmd->hdr.return_code =
  3301. cmd->data.setadapterparms.hdr.return_code;
  3302. QETH_CARD_TEXT_(card, 4, "scer2%i", cmd->hdr.return_code);
  3303. return 0;
  3304. }
  3305. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3306. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3307. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3308. else
  3309. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3310. /* check if there is enough room in userspace */
  3311. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3312. QETH_CARD_TEXT_(card, 4, "scer3%i", -ENOMEM);
  3313. cmd->hdr.return_code = -ENOMEM;
  3314. return 0;
  3315. }
  3316. QETH_CARD_TEXT_(card, 4, "snore%i",
  3317. cmd->data.setadapterparms.hdr.used_total);
  3318. QETH_CARD_TEXT_(card, 4, "sseqn%i",
  3319. cmd->data.setadapterparms.hdr.seq_no);
  3320. /*copy entries to user buffer*/
  3321. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3322. memcpy(qinfo->udata + qinfo->udata_offset,
  3323. (char *)snmp,
  3324. data_len + offsetof(struct qeth_snmp_cmd, data));
  3325. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3326. } else {
  3327. memcpy(qinfo->udata + qinfo->udata_offset,
  3328. (char *)&snmp->request, data_len);
  3329. }
  3330. qinfo->udata_offset += data_len;
  3331. /* check if all replies received ... */
  3332. QETH_CARD_TEXT_(card, 4, "srtot%i",
  3333. cmd->data.setadapterparms.hdr.used_total);
  3334. QETH_CARD_TEXT_(card, 4, "srseq%i",
  3335. cmd->data.setadapterparms.hdr.seq_no);
  3336. if (cmd->data.setadapterparms.hdr.seq_no <
  3337. cmd->data.setadapterparms.hdr.used_total)
  3338. return 1;
  3339. return 0;
  3340. }
  3341. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3342. {
  3343. struct qeth_cmd_buffer *iob;
  3344. struct qeth_ipa_cmd *cmd;
  3345. struct qeth_snmp_ureq *ureq;
  3346. int req_len;
  3347. struct qeth_arp_query_info qinfo = {0, };
  3348. int rc = 0;
  3349. QETH_CARD_TEXT(card, 3, "snmpcmd");
  3350. if (card->info.guestlan)
  3351. return -EOPNOTSUPP;
  3352. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3353. (!card->options.layer2)) {
  3354. return -EOPNOTSUPP;
  3355. }
  3356. /* skip 4 bytes (data_len struct member) to get req_len */
  3357. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3358. return -EFAULT;
  3359. ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
  3360. if (!ureq) {
  3361. QETH_CARD_TEXT(card, 2, "snmpnome");
  3362. return -ENOMEM;
  3363. }
  3364. if (copy_from_user(ureq, udata,
  3365. req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
  3366. kfree(ureq);
  3367. return -EFAULT;
  3368. }
  3369. qinfo.udata_len = ureq->hdr.data_len;
  3370. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3371. if (!qinfo.udata) {
  3372. kfree(ureq);
  3373. return -ENOMEM;
  3374. }
  3375. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3376. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3377. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3378. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3379. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3380. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3381. qeth_snmp_command_cb, (void *)&qinfo);
  3382. if (rc)
  3383. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3384. QETH_CARD_IFNAME(card), rc);
  3385. else {
  3386. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3387. rc = -EFAULT;
  3388. }
  3389. kfree(ureq);
  3390. kfree(qinfo.udata);
  3391. return rc;
  3392. }
  3393. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3394. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3395. {
  3396. switch (card->info.type) {
  3397. case QETH_CARD_TYPE_IQD:
  3398. return 2;
  3399. default:
  3400. return 0;
  3401. }
  3402. }
  3403. static int qeth_qdio_establish(struct qeth_card *card)
  3404. {
  3405. struct qdio_initialize init_data;
  3406. char *qib_param_field;
  3407. struct qdio_buffer **in_sbal_ptrs;
  3408. struct qdio_buffer **out_sbal_ptrs;
  3409. int i, j, k;
  3410. int rc = 0;
  3411. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3412. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3413. GFP_KERNEL);
  3414. if (!qib_param_field)
  3415. return -ENOMEM;
  3416. qeth_create_qib_param_field(card, qib_param_field);
  3417. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3418. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3419. GFP_KERNEL);
  3420. if (!in_sbal_ptrs) {
  3421. kfree(qib_param_field);
  3422. return -ENOMEM;
  3423. }
  3424. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3425. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3426. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3427. out_sbal_ptrs =
  3428. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3429. sizeof(void *), GFP_KERNEL);
  3430. if (!out_sbal_ptrs) {
  3431. kfree(in_sbal_ptrs);
  3432. kfree(qib_param_field);
  3433. return -ENOMEM;
  3434. }
  3435. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3436. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3437. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3438. card->qdio.out_qs[i]->bufs[j].buffer);
  3439. }
  3440. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3441. init_data.cdev = CARD_DDEV(card);
  3442. init_data.q_format = qeth_get_qdio_q_format(card);
  3443. init_data.qib_param_field_format = 0;
  3444. init_data.qib_param_field = qib_param_field;
  3445. init_data.no_input_qs = 1;
  3446. init_data.no_output_qs = card->qdio.no_out_queues;
  3447. init_data.input_handler = card->discipline.input_handler;
  3448. init_data.output_handler = card->discipline.output_handler;
  3449. init_data.int_parm = (unsigned long) card;
  3450. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3451. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3452. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3453. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3454. rc = qdio_allocate(&init_data);
  3455. if (rc) {
  3456. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3457. goto out;
  3458. }
  3459. rc = qdio_establish(&init_data);
  3460. if (rc) {
  3461. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3462. qdio_free(CARD_DDEV(card));
  3463. }
  3464. }
  3465. out:
  3466. kfree(out_sbal_ptrs);
  3467. kfree(in_sbal_ptrs);
  3468. kfree(qib_param_field);
  3469. return rc;
  3470. }
  3471. static void qeth_core_free_card(struct qeth_card *card)
  3472. {
  3473. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3474. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3475. qeth_clean_channel(&card->read);
  3476. qeth_clean_channel(&card->write);
  3477. if (card->dev)
  3478. free_netdev(card->dev);
  3479. kfree(card->ip_tbd_list);
  3480. qeth_free_qdio_buffers(card);
  3481. unregister_service_level(&card->qeth_service_level);
  3482. kfree(card);
  3483. }
  3484. static struct ccw_device_id qeth_ids[] = {
  3485. {CCW_DEVICE_DEVTYPE(0x1731, 0x01, 0x1732, 0x01),
  3486. .driver_info = QETH_CARD_TYPE_OSD},
  3487. {CCW_DEVICE_DEVTYPE(0x1731, 0x05, 0x1732, 0x05),
  3488. .driver_info = QETH_CARD_TYPE_IQD},
  3489. {CCW_DEVICE_DEVTYPE(0x1731, 0x06, 0x1732, 0x06),
  3490. .driver_info = QETH_CARD_TYPE_OSN},
  3491. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x03),
  3492. .driver_info = QETH_CARD_TYPE_OSM},
  3493. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x02),
  3494. .driver_info = QETH_CARD_TYPE_OSX},
  3495. {},
  3496. };
  3497. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3498. static struct ccw_driver qeth_ccw_driver = {
  3499. .name = "qeth",
  3500. .ids = qeth_ids,
  3501. .probe = ccwgroup_probe_ccwdev,
  3502. .remove = ccwgroup_remove_ccwdev,
  3503. };
  3504. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3505. unsigned long driver_id)
  3506. {
  3507. return ccwgroup_create_from_string(root_dev, driver_id,
  3508. &qeth_ccw_driver, 3, buf);
  3509. }
  3510. int qeth_core_hardsetup_card(struct qeth_card *card)
  3511. {
  3512. int retries = 0;
  3513. int rc;
  3514. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3515. atomic_set(&card->force_alloc_skb, 0);
  3516. retry:
  3517. if (retries)
  3518. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  3519. dev_name(&card->gdev->dev));
  3520. ccw_device_set_offline(CARD_DDEV(card));
  3521. ccw_device_set_offline(CARD_WDEV(card));
  3522. ccw_device_set_offline(CARD_RDEV(card));
  3523. rc = ccw_device_set_online(CARD_RDEV(card));
  3524. if (rc)
  3525. goto retriable;
  3526. rc = ccw_device_set_online(CARD_WDEV(card));
  3527. if (rc)
  3528. goto retriable;
  3529. rc = ccw_device_set_online(CARD_DDEV(card));
  3530. if (rc)
  3531. goto retriable;
  3532. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3533. retriable:
  3534. if (rc == -ERESTARTSYS) {
  3535. QETH_DBF_TEXT(SETUP, 2, "break1");
  3536. return rc;
  3537. } else if (rc) {
  3538. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3539. if (++retries > 3)
  3540. goto out;
  3541. else
  3542. goto retry;
  3543. }
  3544. qeth_init_tokens(card);
  3545. qeth_init_func_level(card);
  3546. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3547. if (rc == -ERESTARTSYS) {
  3548. QETH_DBF_TEXT(SETUP, 2, "break2");
  3549. return rc;
  3550. } else if (rc) {
  3551. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3552. if (--retries < 0)
  3553. goto out;
  3554. else
  3555. goto retry;
  3556. }
  3557. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3558. if (rc == -ERESTARTSYS) {
  3559. QETH_DBF_TEXT(SETUP, 2, "break3");
  3560. return rc;
  3561. } else if (rc) {
  3562. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3563. if (--retries < 0)
  3564. goto out;
  3565. else
  3566. goto retry;
  3567. }
  3568. rc = qeth_mpc_initialize(card);
  3569. if (rc) {
  3570. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3571. goto out;
  3572. }
  3573. return 0;
  3574. out:
  3575. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  3576. "an error on the device\n");
  3577. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  3578. dev_name(&card->gdev->dev), rc);
  3579. return rc;
  3580. }
  3581. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3582. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3583. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3584. {
  3585. struct page *page = virt_to_page(element->addr);
  3586. if (*pskb == NULL) {
  3587. /* the upper protocol layers assume that there is data in the
  3588. * skb itself. Copy a small amount (64 bytes) to make them
  3589. * happy. */
  3590. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3591. if (!(*pskb))
  3592. return -ENOMEM;
  3593. skb_reserve(*pskb, ETH_HLEN);
  3594. if (data_len <= 64) {
  3595. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3596. data_len);
  3597. } else {
  3598. get_page(page);
  3599. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3600. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3601. data_len - 64);
  3602. (*pskb)->data_len += data_len - 64;
  3603. (*pskb)->len += data_len - 64;
  3604. (*pskb)->truesize += data_len - 64;
  3605. (*pfrag)++;
  3606. }
  3607. } else {
  3608. get_page(page);
  3609. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3610. (*pskb)->data_len += data_len;
  3611. (*pskb)->len += data_len;
  3612. (*pskb)->truesize += data_len;
  3613. (*pfrag)++;
  3614. }
  3615. return 0;
  3616. }
  3617. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3618. struct qdio_buffer *buffer,
  3619. struct qdio_buffer_element **__element, int *__offset,
  3620. struct qeth_hdr **hdr)
  3621. {
  3622. struct qdio_buffer_element *element = *__element;
  3623. int offset = *__offset;
  3624. struct sk_buff *skb = NULL;
  3625. int skb_len = 0;
  3626. void *data_ptr;
  3627. int data_len;
  3628. int headroom = 0;
  3629. int use_rx_sg = 0;
  3630. int frag = 0;
  3631. /* qeth_hdr must not cross element boundaries */
  3632. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3633. if (qeth_is_last_sbale(element))
  3634. return NULL;
  3635. element++;
  3636. offset = 0;
  3637. if (element->length < sizeof(struct qeth_hdr))
  3638. return NULL;
  3639. }
  3640. *hdr = element->addr + offset;
  3641. offset += sizeof(struct qeth_hdr);
  3642. switch ((*hdr)->hdr.l2.id) {
  3643. case QETH_HEADER_TYPE_LAYER2:
  3644. skb_len = (*hdr)->hdr.l2.pkt_length;
  3645. break;
  3646. case QETH_HEADER_TYPE_LAYER3:
  3647. skb_len = (*hdr)->hdr.l3.length;
  3648. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3649. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3650. headroom = TR_HLEN;
  3651. else
  3652. headroom = ETH_HLEN;
  3653. break;
  3654. case QETH_HEADER_TYPE_OSN:
  3655. skb_len = (*hdr)->hdr.osn.pdu_length;
  3656. headroom = sizeof(struct qeth_hdr);
  3657. break;
  3658. default:
  3659. break;
  3660. }
  3661. if (!skb_len)
  3662. return NULL;
  3663. if ((skb_len >= card->options.rx_sg_cb) &&
  3664. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3665. (!atomic_read(&card->force_alloc_skb))) {
  3666. use_rx_sg = 1;
  3667. } else {
  3668. skb = dev_alloc_skb(skb_len + headroom);
  3669. if (!skb)
  3670. goto no_mem;
  3671. if (headroom)
  3672. skb_reserve(skb, headroom);
  3673. }
  3674. data_ptr = element->addr + offset;
  3675. while (skb_len) {
  3676. data_len = min(skb_len, (int)(element->length - offset));
  3677. if (data_len) {
  3678. if (use_rx_sg) {
  3679. if (qeth_create_skb_frag(element, &skb, offset,
  3680. &frag, data_len))
  3681. goto no_mem;
  3682. } else {
  3683. memcpy(skb_put(skb, data_len), data_ptr,
  3684. data_len);
  3685. }
  3686. }
  3687. skb_len -= data_len;
  3688. if (skb_len) {
  3689. if (qeth_is_last_sbale(element)) {
  3690. QETH_CARD_TEXT(card, 4, "unexeob");
  3691. QETH_CARD_HEX(card, 2, buffer, sizeof(void *));
  3692. dev_kfree_skb_any(skb);
  3693. card->stats.rx_errors++;
  3694. return NULL;
  3695. }
  3696. element++;
  3697. offset = 0;
  3698. data_ptr = element->addr;
  3699. } else {
  3700. offset += data_len;
  3701. }
  3702. }
  3703. *__element = element;
  3704. *__offset = offset;
  3705. if (use_rx_sg && card->options.performance_stats) {
  3706. card->perf_stats.sg_skbs_rx++;
  3707. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3708. }
  3709. return skb;
  3710. no_mem:
  3711. if (net_ratelimit()) {
  3712. QETH_CARD_TEXT(card, 2, "noskbmem");
  3713. }
  3714. card->stats.rx_dropped++;
  3715. return NULL;
  3716. }
  3717. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3718. static void qeth_unregister_dbf_views(void)
  3719. {
  3720. int x;
  3721. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3722. debug_unregister(qeth_dbf[x].id);
  3723. qeth_dbf[x].id = NULL;
  3724. }
  3725. }
  3726. void qeth_dbf_longtext(debug_info_t *id, int level, char *fmt, ...)
  3727. {
  3728. char dbf_txt_buf[32];
  3729. va_list args;
  3730. if (level > id->level)
  3731. return;
  3732. va_start(args, fmt);
  3733. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  3734. va_end(args);
  3735. debug_text_event(id, level, dbf_txt_buf);
  3736. }
  3737. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  3738. static int qeth_register_dbf_views(void)
  3739. {
  3740. int ret;
  3741. int x;
  3742. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3743. /* register the areas */
  3744. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3745. qeth_dbf[x].pages,
  3746. qeth_dbf[x].areas,
  3747. qeth_dbf[x].len);
  3748. if (qeth_dbf[x].id == NULL) {
  3749. qeth_unregister_dbf_views();
  3750. return -ENOMEM;
  3751. }
  3752. /* register a view */
  3753. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3754. if (ret) {
  3755. qeth_unregister_dbf_views();
  3756. return ret;
  3757. }
  3758. /* set a passing level */
  3759. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3760. }
  3761. return 0;
  3762. }
  3763. int qeth_core_load_discipline(struct qeth_card *card,
  3764. enum qeth_discipline_id discipline)
  3765. {
  3766. int rc = 0;
  3767. switch (discipline) {
  3768. case QETH_DISCIPLINE_LAYER3:
  3769. card->discipline.ccwgdriver = try_then_request_module(
  3770. symbol_get(qeth_l3_ccwgroup_driver),
  3771. "qeth_l3");
  3772. break;
  3773. case QETH_DISCIPLINE_LAYER2:
  3774. card->discipline.ccwgdriver = try_then_request_module(
  3775. symbol_get(qeth_l2_ccwgroup_driver),
  3776. "qeth_l2");
  3777. break;
  3778. }
  3779. if (!card->discipline.ccwgdriver) {
  3780. dev_err(&card->gdev->dev, "There is no kernel module to "
  3781. "support discipline %d\n", discipline);
  3782. rc = -EINVAL;
  3783. }
  3784. return rc;
  3785. }
  3786. void qeth_core_free_discipline(struct qeth_card *card)
  3787. {
  3788. if (card->options.layer2)
  3789. symbol_put(qeth_l2_ccwgroup_driver);
  3790. else
  3791. symbol_put(qeth_l3_ccwgroup_driver);
  3792. card->discipline.ccwgdriver = NULL;
  3793. }
  3794. static void qeth_determine_capabilities(struct qeth_card *card)
  3795. {
  3796. int rc;
  3797. int length;
  3798. char *prcd;
  3799. QETH_DBF_TEXT(SETUP, 2, "detcapab");
  3800. rc = ccw_device_set_online(CARD_DDEV(card));
  3801. if (rc) {
  3802. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3803. goto out;
  3804. }
  3805. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  3806. if (rc) {
  3807. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  3808. dev_name(&card->gdev->dev), rc);
  3809. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3810. goto out_offline;
  3811. }
  3812. qeth_configure_unitaddr(card, prcd);
  3813. qeth_configure_blkt_default(card, prcd);
  3814. kfree(prcd);
  3815. rc = qdio_get_ssqd_desc(CARD_DDEV(card), &card->ssqd);
  3816. if (rc)
  3817. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  3818. out_offline:
  3819. ccw_device_set_offline(CARD_DDEV(card));
  3820. out:
  3821. return;
  3822. }
  3823. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3824. {
  3825. struct qeth_card *card;
  3826. struct device *dev;
  3827. int rc;
  3828. unsigned long flags;
  3829. char dbf_name[20];
  3830. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3831. dev = &gdev->dev;
  3832. if (!get_device(dev))
  3833. return -ENODEV;
  3834. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  3835. card = qeth_alloc_card();
  3836. if (!card) {
  3837. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3838. rc = -ENOMEM;
  3839. goto err_dev;
  3840. }
  3841. snprintf(dbf_name, sizeof(dbf_name), "qeth_card_%s",
  3842. dev_name(&gdev->dev));
  3843. card->debug = debug_register(dbf_name, 2, 1, 8);
  3844. if (!card->debug) {
  3845. QETH_DBF_TEXT_(SETUP, 2, "%s", "qcdbf");
  3846. rc = -ENOMEM;
  3847. goto err_card;
  3848. }
  3849. debug_register_view(card->debug, &debug_hex_ascii_view);
  3850. card->read.ccwdev = gdev->cdev[0];
  3851. card->write.ccwdev = gdev->cdev[1];
  3852. card->data.ccwdev = gdev->cdev[2];
  3853. dev_set_drvdata(&gdev->dev, card);
  3854. card->gdev = gdev;
  3855. gdev->cdev[0]->handler = qeth_irq;
  3856. gdev->cdev[1]->handler = qeth_irq;
  3857. gdev->cdev[2]->handler = qeth_irq;
  3858. rc = qeth_determine_card_type(card);
  3859. if (rc) {
  3860. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3861. goto err_dbf;
  3862. }
  3863. rc = qeth_setup_card(card);
  3864. if (rc) {
  3865. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3866. goto err_dbf;
  3867. }
  3868. if (card->info.type == QETH_CARD_TYPE_OSN)
  3869. rc = qeth_core_create_osn_attributes(dev);
  3870. else
  3871. rc = qeth_core_create_device_attributes(dev);
  3872. if (rc)
  3873. goto err_dbf;
  3874. switch (card->info.type) {
  3875. case QETH_CARD_TYPE_OSN:
  3876. case QETH_CARD_TYPE_OSM:
  3877. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3878. if (rc)
  3879. goto err_attr;
  3880. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3881. if (rc)
  3882. goto err_disc;
  3883. case QETH_CARD_TYPE_OSD:
  3884. case QETH_CARD_TYPE_OSX:
  3885. default:
  3886. break;
  3887. }
  3888. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3889. list_add_tail(&card->list, &qeth_core_card_list.list);
  3890. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3891. qeth_determine_capabilities(card);
  3892. return 0;
  3893. err_disc:
  3894. qeth_core_free_discipline(card);
  3895. err_attr:
  3896. if (card->info.type == QETH_CARD_TYPE_OSN)
  3897. qeth_core_remove_osn_attributes(dev);
  3898. else
  3899. qeth_core_remove_device_attributes(dev);
  3900. err_dbf:
  3901. debug_unregister(card->debug);
  3902. err_card:
  3903. qeth_core_free_card(card);
  3904. err_dev:
  3905. put_device(dev);
  3906. return rc;
  3907. }
  3908. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3909. {
  3910. unsigned long flags;
  3911. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3912. QETH_DBF_TEXT(SETUP, 2, "removedv");
  3913. if (card->discipline.ccwgdriver) {
  3914. card->discipline.ccwgdriver->remove(gdev);
  3915. qeth_core_free_discipline(card);
  3916. }
  3917. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3918. qeth_core_remove_osn_attributes(&gdev->dev);
  3919. } else {
  3920. qeth_core_remove_device_attributes(&gdev->dev);
  3921. }
  3922. debug_unregister(card->debug);
  3923. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3924. list_del(&card->list);
  3925. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3926. qeth_core_free_card(card);
  3927. dev_set_drvdata(&gdev->dev, NULL);
  3928. put_device(&gdev->dev);
  3929. return;
  3930. }
  3931. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3932. {
  3933. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3934. int rc = 0;
  3935. int def_discipline;
  3936. if (!card->discipline.ccwgdriver) {
  3937. if (card->info.type == QETH_CARD_TYPE_IQD)
  3938. def_discipline = QETH_DISCIPLINE_LAYER3;
  3939. else
  3940. def_discipline = QETH_DISCIPLINE_LAYER2;
  3941. rc = qeth_core_load_discipline(card, def_discipline);
  3942. if (rc)
  3943. goto err;
  3944. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3945. if (rc)
  3946. goto err;
  3947. }
  3948. rc = card->discipline.ccwgdriver->set_online(gdev);
  3949. err:
  3950. return rc;
  3951. }
  3952. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3953. {
  3954. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3955. return card->discipline.ccwgdriver->set_offline(gdev);
  3956. }
  3957. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3958. {
  3959. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3960. if (card->discipline.ccwgdriver &&
  3961. card->discipline.ccwgdriver->shutdown)
  3962. card->discipline.ccwgdriver->shutdown(gdev);
  3963. }
  3964. static int qeth_core_prepare(struct ccwgroup_device *gdev)
  3965. {
  3966. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3967. if (card->discipline.ccwgdriver &&
  3968. card->discipline.ccwgdriver->prepare)
  3969. return card->discipline.ccwgdriver->prepare(gdev);
  3970. return 0;
  3971. }
  3972. static void qeth_core_complete(struct ccwgroup_device *gdev)
  3973. {
  3974. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3975. if (card->discipline.ccwgdriver &&
  3976. card->discipline.ccwgdriver->complete)
  3977. card->discipline.ccwgdriver->complete(gdev);
  3978. }
  3979. static int qeth_core_freeze(struct ccwgroup_device *gdev)
  3980. {
  3981. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3982. if (card->discipline.ccwgdriver &&
  3983. card->discipline.ccwgdriver->freeze)
  3984. return card->discipline.ccwgdriver->freeze(gdev);
  3985. return 0;
  3986. }
  3987. static int qeth_core_thaw(struct ccwgroup_device *gdev)
  3988. {
  3989. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3990. if (card->discipline.ccwgdriver &&
  3991. card->discipline.ccwgdriver->thaw)
  3992. return card->discipline.ccwgdriver->thaw(gdev);
  3993. return 0;
  3994. }
  3995. static int qeth_core_restore(struct ccwgroup_device *gdev)
  3996. {
  3997. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3998. if (card->discipline.ccwgdriver &&
  3999. card->discipline.ccwgdriver->restore)
  4000. return card->discipline.ccwgdriver->restore(gdev);
  4001. return 0;
  4002. }
  4003. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  4004. .owner = THIS_MODULE,
  4005. .name = "qeth",
  4006. .driver_id = 0xD8C5E3C8,
  4007. .probe = qeth_core_probe_device,
  4008. .remove = qeth_core_remove_device,
  4009. .set_online = qeth_core_set_online,
  4010. .set_offline = qeth_core_set_offline,
  4011. .shutdown = qeth_core_shutdown,
  4012. .prepare = qeth_core_prepare,
  4013. .complete = qeth_core_complete,
  4014. .freeze = qeth_core_freeze,
  4015. .thaw = qeth_core_thaw,
  4016. .restore = qeth_core_restore,
  4017. };
  4018. static ssize_t
  4019. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  4020. size_t count)
  4021. {
  4022. int err;
  4023. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  4024. qeth_core_ccwgroup_driver.driver_id);
  4025. if (err)
  4026. return err;
  4027. else
  4028. return count;
  4029. }
  4030. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  4031. static struct {
  4032. const char str[ETH_GSTRING_LEN];
  4033. } qeth_ethtool_stats_keys[] = {
  4034. /* 0 */{"rx skbs"},
  4035. {"rx buffers"},
  4036. {"tx skbs"},
  4037. {"tx buffers"},
  4038. {"tx skbs no packing"},
  4039. {"tx buffers no packing"},
  4040. {"tx skbs packing"},
  4041. {"tx buffers packing"},
  4042. {"tx sg skbs"},
  4043. {"tx sg frags"},
  4044. /* 10 */{"rx sg skbs"},
  4045. {"rx sg frags"},
  4046. {"rx sg page allocs"},
  4047. {"tx large kbytes"},
  4048. {"tx large count"},
  4049. {"tx pk state ch n->p"},
  4050. {"tx pk state ch p->n"},
  4051. {"tx pk watermark low"},
  4052. {"tx pk watermark high"},
  4053. {"queue 0 buffer usage"},
  4054. /* 20 */{"queue 1 buffer usage"},
  4055. {"queue 2 buffer usage"},
  4056. {"queue 3 buffer usage"},
  4057. {"rx handler time"},
  4058. {"rx handler count"},
  4059. {"rx do_QDIO time"},
  4060. {"rx do_QDIO count"},
  4061. {"tx handler time"},
  4062. {"tx handler count"},
  4063. {"tx time"},
  4064. /* 30 */{"tx count"},
  4065. {"tx do_QDIO time"},
  4066. {"tx do_QDIO count"},
  4067. {"tx csum"},
  4068. {"tx lin"},
  4069. };
  4070. int qeth_core_get_sset_count(struct net_device *dev, int stringset)
  4071. {
  4072. switch (stringset) {
  4073. case ETH_SS_STATS:
  4074. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  4075. default:
  4076. return -EINVAL;
  4077. }
  4078. }
  4079. EXPORT_SYMBOL_GPL(qeth_core_get_sset_count);
  4080. void qeth_core_get_ethtool_stats(struct net_device *dev,
  4081. struct ethtool_stats *stats, u64 *data)
  4082. {
  4083. struct qeth_card *card = dev->ml_priv;
  4084. data[0] = card->stats.rx_packets -
  4085. card->perf_stats.initial_rx_packets;
  4086. data[1] = card->perf_stats.bufs_rec;
  4087. data[2] = card->stats.tx_packets -
  4088. card->perf_stats.initial_tx_packets;
  4089. data[3] = card->perf_stats.bufs_sent;
  4090. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  4091. - card->perf_stats.skbs_sent_pack;
  4092. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  4093. data[6] = card->perf_stats.skbs_sent_pack;
  4094. data[7] = card->perf_stats.bufs_sent_pack;
  4095. data[8] = card->perf_stats.sg_skbs_sent;
  4096. data[9] = card->perf_stats.sg_frags_sent;
  4097. data[10] = card->perf_stats.sg_skbs_rx;
  4098. data[11] = card->perf_stats.sg_frags_rx;
  4099. data[12] = card->perf_stats.sg_alloc_page_rx;
  4100. data[13] = (card->perf_stats.large_send_bytes >> 10);
  4101. data[14] = card->perf_stats.large_send_cnt;
  4102. data[15] = card->perf_stats.sc_dp_p;
  4103. data[16] = card->perf_stats.sc_p_dp;
  4104. data[17] = QETH_LOW_WATERMARK_PACK;
  4105. data[18] = QETH_HIGH_WATERMARK_PACK;
  4106. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  4107. data[20] = (card->qdio.no_out_queues > 1) ?
  4108. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  4109. data[21] = (card->qdio.no_out_queues > 2) ?
  4110. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  4111. data[22] = (card->qdio.no_out_queues > 3) ?
  4112. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  4113. data[23] = card->perf_stats.inbound_time;
  4114. data[24] = card->perf_stats.inbound_cnt;
  4115. data[25] = card->perf_stats.inbound_do_qdio_time;
  4116. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  4117. data[27] = card->perf_stats.outbound_handler_time;
  4118. data[28] = card->perf_stats.outbound_handler_cnt;
  4119. data[29] = card->perf_stats.outbound_time;
  4120. data[30] = card->perf_stats.outbound_cnt;
  4121. data[31] = card->perf_stats.outbound_do_qdio_time;
  4122. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  4123. data[33] = card->perf_stats.tx_csum;
  4124. data[34] = card->perf_stats.tx_lin;
  4125. }
  4126. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  4127. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4128. {
  4129. switch (stringset) {
  4130. case ETH_SS_STATS:
  4131. memcpy(data, &qeth_ethtool_stats_keys,
  4132. sizeof(qeth_ethtool_stats_keys));
  4133. break;
  4134. default:
  4135. WARN_ON(1);
  4136. break;
  4137. }
  4138. }
  4139. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  4140. void qeth_core_get_drvinfo(struct net_device *dev,
  4141. struct ethtool_drvinfo *info)
  4142. {
  4143. struct qeth_card *card = dev->ml_priv;
  4144. if (card->options.layer2)
  4145. strcpy(info->driver, "qeth_l2");
  4146. else
  4147. strcpy(info->driver, "qeth_l3");
  4148. strcpy(info->version, "1.0");
  4149. strcpy(info->fw_version, card->info.mcl_level);
  4150. sprintf(info->bus_info, "%s/%s/%s",
  4151. CARD_RDEV_ID(card),
  4152. CARD_WDEV_ID(card),
  4153. CARD_DDEV_ID(card));
  4154. }
  4155. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  4156. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  4157. struct ethtool_cmd *ecmd)
  4158. {
  4159. struct qeth_card *card = netdev->ml_priv;
  4160. enum qeth_link_types link_type;
  4161. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  4162. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  4163. else
  4164. link_type = card->info.link_type;
  4165. ecmd->transceiver = XCVR_INTERNAL;
  4166. ecmd->supported = SUPPORTED_Autoneg;
  4167. ecmd->advertising = ADVERTISED_Autoneg;
  4168. ecmd->duplex = DUPLEX_FULL;
  4169. ecmd->autoneg = AUTONEG_ENABLE;
  4170. switch (link_type) {
  4171. case QETH_LINK_TYPE_FAST_ETH:
  4172. case QETH_LINK_TYPE_LANE_ETH100:
  4173. ecmd->supported |= SUPPORTED_10baseT_Half |
  4174. SUPPORTED_10baseT_Full |
  4175. SUPPORTED_100baseT_Half |
  4176. SUPPORTED_100baseT_Full |
  4177. SUPPORTED_TP;
  4178. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4179. ADVERTISED_10baseT_Full |
  4180. ADVERTISED_100baseT_Half |
  4181. ADVERTISED_100baseT_Full |
  4182. ADVERTISED_TP;
  4183. ecmd->speed = SPEED_100;
  4184. ecmd->port = PORT_TP;
  4185. break;
  4186. case QETH_LINK_TYPE_GBIT_ETH:
  4187. case QETH_LINK_TYPE_LANE_ETH1000:
  4188. ecmd->supported |= SUPPORTED_10baseT_Half |
  4189. SUPPORTED_10baseT_Full |
  4190. SUPPORTED_100baseT_Half |
  4191. SUPPORTED_100baseT_Full |
  4192. SUPPORTED_1000baseT_Half |
  4193. SUPPORTED_1000baseT_Full |
  4194. SUPPORTED_FIBRE;
  4195. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4196. ADVERTISED_10baseT_Full |
  4197. ADVERTISED_100baseT_Half |
  4198. ADVERTISED_100baseT_Full |
  4199. ADVERTISED_1000baseT_Half |
  4200. ADVERTISED_1000baseT_Full |
  4201. ADVERTISED_FIBRE;
  4202. ecmd->speed = SPEED_1000;
  4203. ecmd->port = PORT_FIBRE;
  4204. break;
  4205. case QETH_LINK_TYPE_10GBIT_ETH:
  4206. ecmd->supported |= SUPPORTED_10baseT_Half |
  4207. SUPPORTED_10baseT_Full |
  4208. SUPPORTED_100baseT_Half |
  4209. SUPPORTED_100baseT_Full |
  4210. SUPPORTED_1000baseT_Half |
  4211. SUPPORTED_1000baseT_Full |
  4212. SUPPORTED_10000baseT_Full |
  4213. SUPPORTED_FIBRE;
  4214. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4215. ADVERTISED_10baseT_Full |
  4216. ADVERTISED_100baseT_Half |
  4217. ADVERTISED_100baseT_Full |
  4218. ADVERTISED_1000baseT_Half |
  4219. ADVERTISED_1000baseT_Full |
  4220. ADVERTISED_10000baseT_Full |
  4221. ADVERTISED_FIBRE;
  4222. ecmd->speed = SPEED_10000;
  4223. ecmd->port = PORT_FIBRE;
  4224. break;
  4225. default:
  4226. ecmd->supported |= SUPPORTED_10baseT_Half |
  4227. SUPPORTED_10baseT_Full |
  4228. SUPPORTED_TP;
  4229. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4230. ADVERTISED_10baseT_Full |
  4231. ADVERTISED_TP;
  4232. ecmd->speed = SPEED_10;
  4233. ecmd->port = PORT_TP;
  4234. }
  4235. return 0;
  4236. }
  4237. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4238. static int __init qeth_core_init(void)
  4239. {
  4240. int rc;
  4241. pr_info("loading core functions\n");
  4242. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4243. rwlock_init(&qeth_core_card_list.rwlock);
  4244. rc = qeth_register_dbf_views();
  4245. if (rc)
  4246. goto out_err;
  4247. rc = ccw_driver_register(&qeth_ccw_driver);
  4248. if (rc)
  4249. goto ccw_err;
  4250. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4251. if (rc)
  4252. goto ccwgroup_err;
  4253. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4254. &driver_attr_group);
  4255. if (rc)
  4256. goto driver_err;
  4257. qeth_core_root_dev = root_device_register("qeth");
  4258. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4259. if (rc)
  4260. goto register_err;
  4261. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4262. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4263. if (!qeth_core_header_cache) {
  4264. rc = -ENOMEM;
  4265. goto slab_err;
  4266. }
  4267. return 0;
  4268. slab_err:
  4269. root_device_unregister(qeth_core_root_dev);
  4270. register_err:
  4271. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4272. &driver_attr_group);
  4273. driver_err:
  4274. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4275. ccwgroup_err:
  4276. ccw_driver_unregister(&qeth_ccw_driver);
  4277. ccw_err:
  4278. QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc);
  4279. qeth_unregister_dbf_views();
  4280. out_err:
  4281. pr_err("Initializing the qeth device driver failed\n");
  4282. return rc;
  4283. }
  4284. static void __exit qeth_core_exit(void)
  4285. {
  4286. root_device_unregister(qeth_core_root_dev);
  4287. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4288. &driver_attr_group);
  4289. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4290. ccw_driver_unregister(&qeth_ccw_driver);
  4291. kmem_cache_destroy(qeth_core_header_cache);
  4292. qeth_unregister_dbf_views();
  4293. pr_info("core functions removed\n");
  4294. }
  4295. module_init(qeth_core_init);
  4296. module_exit(qeth_core_exit);
  4297. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4298. MODULE_DESCRIPTION("qeth core functions");
  4299. MODULE_LICENSE("GPL");