main.c 52 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. static u8 parse_mpdudensity(u8 mpdudensity)
  21. {
  22. /*
  23. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  24. * 0 for no restriction
  25. * 1 for 1/4 us
  26. * 2 for 1/2 us
  27. * 3 for 1 us
  28. * 4 for 2 us
  29. * 5 for 4 us
  30. * 6 for 8 us
  31. * 7 for 16 us
  32. */
  33. switch (mpdudensity) {
  34. case 0:
  35. return 0;
  36. case 1:
  37. case 2:
  38. case 3:
  39. /* Our lower layer calculations limit our precision to
  40. 1 microsecond */
  41. return 1;
  42. case 4:
  43. return 2;
  44. case 5:
  45. return 4;
  46. case 6:
  47. return 8;
  48. case 7:
  49. return 16;
  50. default:
  51. return 0;
  52. }
  53. }
  54. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  55. {
  56. bool pending = false;
  57. spin_lock_bh(&txq->axq_lock);
  58. if (txq->axq_depth || !list_empty(&txq->axq_acq))
  59. pending = true;
  60. spin_unlock_bh(&txq->axq_lock);
  61. return pending;
  62. }
  63. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  64. {
  65. unsigned long flags;
  66. bool ret;
  67. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  68. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  69. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  70. return ret;
  71. }
  72. void ath9k_ps_wakeup(struct ath_softc *sc)
  73. {
  74. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  75. unsigned long flags;
  76. enum ath9k_power_mode power_mode;
  77. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  78. if (++sc->ps_usecount != 1)
  79. goto unlock;
  80. power_mode = sc->sc_ah->power_mode;
  81. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  82. /*
  83. * While the hardware is asleep, the cycle counters contain no
  84. * useful data. Better clear them now so that they don't mess up
  85. * survey data results.
  86. */
  87. if (power_mode != ATH9K_PM_AWAKE) {
  88. spin_lock(&common->cc_lock);
  89. ath_hw_cycle_counters_update(common);
  90. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  91. memset(&common->cc_ani, 0, sizeof(common->cc_ani));
  92. spin_unlock(&common->cc_lock);
  93. }
  94. unlock:
  95. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  96. }
  97. void ath9k_ps_restore(struct ath_softc *sc)
  98. {
  99. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  100. enum ath9k_power_mode mode;
  101. unsigned long flags;
  102. bool reset;
  103. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  104. if (--sc->ps_usecount != 0)
  105. goto unlock;
  106. if (sc->ps_idle) {
  107. ath9k_hw_setrxabort(sc->sc_ah, 1);
  108. ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  109. mode = ATH9K_PM_FULL_SLEEP;
  110. } else if (sc->ps_enabled &&
  111. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  112. PS_WAIT_FOR_CAB |
  113. PS_WAIT_FOR_PSPOLL_DATA |
  114. PS_WAIT_FOR_TX_ACK))) {
  115. mode = ATH9K_PM_NETWORK_SLEEP;
  116. } else {
  117. goto unlock;
  118. }
  119. spin_lock(&common->cc_lock);
  120. ath_hw_cycle_counters_update(common);
  121. spin_unlock(&common->cc_lock);
  122. ath9k_hw_setpower(sc->sc_ah, mode);
  123. unlock:
  124. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  125. }
  126. static void __ath_cancel_work(struct ath_softc *sc)
  127. {
  128. cancel_work_sync(&sc->paprd_work);
  129. cancel_work_sync(&sc->hw_check_work);
  130. cancel_delayed_work_sync(&sc->tx_complete_work);
  131. cancel_delayed_work_sync(&sc->hw_pll_work);
  132. }
  133. static void ath_cancel_work(struct ath_softc *sc)
  134. {
  135. __ath_cancel_work(sc);
  136. cancel_work_sync(&sc->hw_reset_work);
  137. }
  138. static void ath_restart_work(struct ath_softc *sc)
  139. {
  140. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  141. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  142. if (AR_SREV_9485(sc->sc_ah) || AR_SREV_9340(sc->sc_ah))
  143. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
  144. msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
  145. ath_start_rx_poll(sc, 3);
  146. if (!common->disable_ani)
  147. ath_start_ani(common);
  148. }
  149. static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
  150. {
  151. struct ath_hw *ah = sc->sc_ah;
  152. struct ath_common *common = ath9k_hw_common(ah);
  153. bool ret = true;
  154. ieee80211_stop_queues(sc->hw);
  155. sc->hw_busy_count = 0;
  156. del_timer_sync(&common->ani.timer);
  157. del_timer_sync(&sc->rx_poll_timer);
  158. ath9k_debug_samp_bb_mac(sc);
  159. ath9k_hw_disable_interrupts(ah);
  160. if (!ath_stoprecv(sc))
  161. ret = false;
  162. if (!ath_drain_all_txq(sc, retry_tx))
  163. ret = false;
  164. if (!flush) {
  165. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  166. ath_rx_tasklet(sc, 1, true);
  167. ath_rx_tasklet(sc, 1, false);
  168. } else {
  169. ath_flushrecv(sc);
  170. }
  171. return ret;
  172. }
  173. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  174. {
  175. struct ath_hw *ah = sc->sc_ah;
  176. struct ath_common *common = ath9k_hw_common(ah);
  177. unsigned long flags;
  178. if (ath_startrecv(sc) != 0) {
  179. ath_err(common, "Unable to restart recv logic\n");
  180. return false;
  181. }
  182. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  183. sc->config.txpowlimit, &sc->curtxpow);
  184. clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
  185. ath9k_hw_set_interrupts(ah);
  186. ath9k_hw_enable_interrupts(ah);
  187. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
  188. if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
  189. goto work;
  190. ath_set_beacon(sc);
  191. if (ah->opmode == NL80211_IFTYPE_STATION &&
  192. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  193. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  194. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  195. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  196. }
  197. work:
  198. ath_restart_work(sc);
  199. }
  200. if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
  201. ath_ant_comb_update(sc);
  202. ieee80211_wake_queues(sc->hw);
  203. return true;
  204. }
  205. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
  206. bool retry_tx)
  207. {
  208. struct ath_hw *ah = sc->sc_ah;
  209. struct ath_common *common = ath9k_hw_common(ah);
  210. struct ath9k_hw_cal_data *caldata = NULL;
  211. bool fastcc = true;
  212. bool flush = false;
  213. int r;
  214. __ath_cancel_work(sc);
  215. spin_lock_bh(&sc->sc_pcu_lock);
  216. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
  217. fastcc = false;
  218. caldata = &sc->caldata;
  219. }
  220. if (!hchan) {
  221. fastcc = false;
  222. flush = true;
  223. hchan = ah->curchan;
  224. }
  225. if (!ath_prepare_reset(sc, retry_tx, flush))
  226. fastcc = false;
  227. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  228. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  229. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  230. if (r) {
  231. ath_err(common,
  232. "Unable to reset channel, reset status %d\n", r);
  233. goto out;
  234. }
  235. if (!ath_complete_reset(sc, true))
  236. r = -EIO;
  237. out:
  238. spin_unlock_bh(&sc->sc_pcu_lock);
  239. return r;
  240. }
  241. /*
  242. * Set/change channels. If the channel is really being changed, it's done
  243. * by reseting the chip. To accomplish this we must first cleanup any pending
  244. * DMA, then restart stuff.
  245. */
  246. static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  247. struct ath9k_channel *hchan)
  248. {
  249. int r;
  250. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  251. return -EIO;
  252. r = ath_reset_internal(sc, hchan, false);
  253. return r;
  254. }
  255. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  256. struct ieee80211_vif *vif)
  257. {
  258. struct ath_node *an;
  259. an = (struct ath_node *)sta->drv_priv;
  260. #ifdef CONFIG_ATH9K_DEBUGFS
  261. spin_lock(&sc->nodes_lock);
  262. list_add(&an->list, &sc->nodes);
  263. spin_unlock(&sc->nodes_lock);
  264. #endif
  265. an->sta = sta;
  266. an->vif = vif;
  267. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
  268. ath_tx_node_init(sc, an);
  269. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  270. sta->ht_cap.ampdu_factor);
  271. an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
  272. }
  273. }
  274. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  275. {
  276. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  277. #ifdef CONFIG_ATH9K_DEBUGFS
  278. spin_lock(&sc->nodes_lock);
  279. list_del(&an->list);
  280. spin_unlock(&sc->nodes_lock);
  281. an->sta = NULL;
  282. #endif
  283. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  284. ath_tx_node_cleanup(sc, an);
  285. }
  286. void ath9k_tasklet(unsigned long data)
  287. {
  288. struct ath_softc *sc = (struct ath_softc *)data;
  289. struct ath_hw *ah = sc->sc_ah;
  290. struct ath_common *common = ath9k_hw_common(ah);
  291. unsigned long flags;
  292. u32 status = sc->intrstatus;
  293. u32 rxmask;
  294. ath9k_ps_wakeup(sc);
  295. spin_lock(&sc->sc_pcu_lock);
  296. if ((status & ATH9K_INT_FATAL) ||
  297. (status & ATH9K_INT_BB_WATCHDOG)) {
  298. #ifdef CONFIG_ATH9K_DEBUGFS
  299. enum ath_reset_type type;
  300. if (status & ATH9K_INT_FATAL)
  301. type = RESET_TYPE_FATAL_INT;
  302. else
  303. type = RESET_TYPE_BB_WATCHDOG;
  304. RESET_STAT_INC(sc, type);
  305. #endif
  306. set_bit(SC_OP_HW_RESET, &sc->sc_flags);
  307. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  308. goto out;
  309. }
  310. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  311. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  312. /*
  313. * TSF sync does not look correct; remain awake to sync with
  314. * the next Beacon.
  315. */
  316. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  317. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  318. }
  319. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  320. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  321. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  322. ATH9K_INT_RXORN);
  323. else
  324. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  325. if (status & rxmask) {
  326. /* Check for high priority Rx first */
  327. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  328. (status & ATH9K_INT_RXHP))
  329. ath_rx_tasklet(sc, 0, true);
  330. ath_rx_tasklet(sc, 0, false);
  331. }
  332. if (status & ATH9K_INT_TX) {
  333. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  334. ath_tx_edma_tasklet(sc);
  335. else
  336. ath_tx_tasklet(sc);
  337. }
  338. ath9k_btcoex_handle_interrupt(sc, status);
  339. out:
  340. /* re-enable hardware interrupt */
  341. ath9k_hw_enable_interrupts(ah);
  342. spin_unlock(&sc->sc_pcu_lock);
  343. ath9k_ps_restore(sc);
  344. }
  345. irqreturn_t ath_isr(int irq, void *dev)
  346. {
  347. #define SCHED_INTR ( \
  348. ATH9K_INT_FATAL | \
  349. ATH9K_INT_BB_WATCHDOG | \
  350. ATH9K_INT_RXORN | \
  351. ATH9K_INT_RXEOL | \
  352. ATH9K_INT_RX | \
  353. ATH9K_INT_RXLP | \
  354. ATH9K_INT_RXHP | \
  355. ATH9K_INT_TX | \
  356. ATH9K_INT_BMISS | \
  357. ATH9K_INT_CST | \
  358. ATH9K_INT_TSFOOR | \
  359. ATH9K_INT_GENTIMER | \
  360. ATH9K_INT_MCI)
  361. struct ath_softc *sc = dev;
  362. struct ath_hw *ah = sc->sc_ah;
  363. struct ath_common *common = ath9k_hw_common(ah);
  364. enum ath9k_int status;
  365. bool sched = false;
  366. /*
  367. * The hardware is not ready/present, don't
  368. * touch anything. Note this can happen early
  369. * on if the IRQ is shared.
  370. */
  371. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  372. return IRQ_NONE;
  373. /* shared irq, not for us */
  374. if (!ath9k_hw_intrpend(ah))
  375. return IRQ_NONE;
  376. if(test_bit(SC_OP_HW_RESET, &sc->sc_flags))
  377. return IRQ_HANDLED;
  378. /*
  379. * Figure out the reason(s) for the interrupt. Note
  380. * that the hal returns a pseudo-ISR that may include
  381. * bits we haven't explicitly enabled so we mask the
  382. * value to insure we only process bits we requested.
  383. */
  384. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  385. status &= ah->imask; /* discard unasked-for bits */
  386. /*
  387. * If there are no status bits set, then this interrupt was not
  388. * for me (should have been caught above).
  389. */
  390. if (!status)
  391. return IRQ_NONE;
  392. /* Cache the status */
  393. sc->intrstatus = status;
  394. if (status & SCHED_INTR)
  395. sched = true;
  396. /*
  397. * If a FATAL or RXORN interrupt is received, we have to reset the
  398. * chip immediately.
  399. */
  400. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  401. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  402. goto chip_reset;
  403. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  404. (status & ATH9K_INT_BB_WATCHDOG)) {
  405. spin_lock(&common->cc_lock);
  406. ath_hw_cycle_counters_update(common);
  407. ar9003_hw_bb_watchdog_dbg_info(ah);
  408. spin_unlock(&common->cc_lock);
  409. goto chip_reset;
  410. }
  411. if (status & ATH9K_INT_SWBA)
  412. tasklet_schedule(&sc->bcon_tasklet);
  413. if (status & ATH9K_INT_TXURN)
  414. ath9k_hw_updatetxtriglevel(ah, true);
  415. if (status & ATH9K_INT_RXEOL) {
  416. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  417. ath9k_hw_set_interrupts(ah);
  418. }
  419. if (status & ATH9K_INT_MIB) {
  420. /*
  421. * Disable interrupts until we service the MIB
  422. * interrupt; otherwise it will continue to
  423. * fire.
  424. */
  425. ath9k_hw_disable_interrupts(ah);
  426. /*
  427. * Let the hal handle the event. We assume
  428. * it will clear whatever condition caused
  429. * the interrupt.
  430. */
  431. spin_lock(&common->cc_lock);
  432. ath9k_hw_proc_mib_event(ah);
  433. spin_unlock(&common->cc_lock);
  434. ath9k_hw_enable_interrupts(ah);
  435. }
  436. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  437. if (status & ATH9K_INT_TIM_TIMER) {
  438. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  439. goto chip_reset;
  440. /* Clear RxAbort bit so that we can
  441. * receive frames */
  442. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  443. spin_lock(&sc->sc_pm_lock);
  444. ath9k_hw_setrxabort(sc->sc_ah, 0);
  445. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  446. spin_unlock(&sc->sc_pm_lock);
  447. }
  448. chip_reset:
  449. ath_debug_stat_interrupt(sc, status);
  450. if (sched) {
  451. /* turn off every interrupt */
  452. ath9k_hw_disable_interrupts(ah);
  453. tasklet_schedule(&sc->intr_tq);
  454. }
  455. return IRQ_HANDLED;
  456. #undef SCHED_INTR
  457. }
  458. static int ath_reset(struct ath_softc *sc, bool retry_tx)
  459. {
  460. int r;
  461. ath9k_ps_wakeup(sc);
  462. r = ath_reset_internal(sc, NULL, retry_tx);
  463. if (retry_tx) {
  464. int i;
  465. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  466. if (ATH_TXQ_SETUP(sc, i)) {
  467. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  468. ath_txq_schedule(sc, &sc->tx.txq[i]);
  469. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  470. }
  471. }
  472. }
  473. ath9k_ps_restore(sc);
  474. return r;
  475. }
  476. void ath_reset_work(struct work_struct *work)
  477. {
  478. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  479. ath_reset(sc, true);
  480. }
  481. /**********************/
  482. /* mac80211 callbacks */
  483. /**********************/
  484. static int ath9k_start(struct ieee80211_hw *hw)
  485. {
  486. struct ath_softc *sc = hw->priv;
  487. struct ath_hw *ah = sc->sc_ah;
  488. struct ath_common *common = ath9k_hw_common(ah);
  489. struct ieee80211_channel *curchan = hw->conf.channel;
  490. struct ath9k_channel *init_channel;
  491. int r;
  492. ath_dbg(common, CONFIG,
  493. "Starting driver with initial channel: %d MHz\n",
  494. curchan->center_freq);
  495. ath9k_ps_wakeup(sc);
  496. mutex_lock(&sc->mutex);
  497. init_channel = ath9k_cmn_get_curchannel(hw, ah);
  498. /* Reset SERDES registers */
  499. ath9k_hw_configpcipowersave(ah, false);
  500. /*
  501. * The basic interface to setting the hardware in a good
  502. * state is ``reset''. On return the hardware is known to
  503. * be powered up and with interrupts disabled. This must
  504. * be followed by initialization of the appropriate bits
  505. * and then setup of the interrupt mask.
  506. */
  507. spin_lock_bh(&sc->sc_pcu_lock);
  508. atomic_set(&ah->intr_ref_cnt, -1);
  509. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  510. if (r) {
  511. ath_err(common,
  512. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  513. r, curchan->center_freq);
  514. spin_unlock_bh(&sc->sc_pcu_lock);
  515. goto mutex_unlock;
  516. }
  517. /* Setup our intr mask. */
  518. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  519. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  520. ATH9K_INT_GLOBAL;
  521. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  522. ah->imask |= ATH9K_INT_RXHP |
  523. ATH9K_INT_RXLP |
  524. ATH9K_INT_BB_WATCHDOG;
  525. else
  526. ah->imask |= ATH9K_INT_RX;
  527. ah->imask |= ATH9K_INT_GTT;
  528. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  529. ah->imask |= ATH9K_INT_CST;
  530. ath_mci_enable(sc);
  531. clear_bit(SC_OP_INVALID, &sc->sc_flags);
  532. sc->sc_ah->is_monitoring = false;
  533. if (!ath_complete_reset(sc, false)) {
  534. r = -EIO;
  535. spin_unlock_bh(&sc->sc_pcu_lock);
  536. goto mutex_unlock;
  537. }
  538. if (ah->led_pin >= 0) {
  539. ath9k_hw_cfg_output(ah, ah->led_pin,
  540. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  541. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  542. }
  543. /*
  544. * Reset key cache to sane defaults (all entries cleared) instead of
  545. * semi-random values after suspend/resume.
  546. */
  547. ath9k_cmn_init_crypto(sc->sc_ah);
  548. spin_unlock_bh(&sc->sc_pcu_lock);
  549. ath9k_start_btcoex(sc);
  550. if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
  551. common->bus_ops->extn_synch_en(common);
  552. mutex_unlock:
  553. mutex_unlock(&sc->mutex);
  554. ath9k_ps_restore(sc);
  555. return r;
  556. }
  557. static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  558. {
  559. struct ath_softc *sc = hw->priv;
  560. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  561. struct ath_tx_control txctl;
  562. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  563. unsigned long flags;
  564. if (sc->ps_enabled) {
  565. /*
  566. * mac80211 does not set PM field for normal data frames, so we
  567. * need to update that based on the current PS mode.
  568. */
  569. if (ieee80211_is_data(hdr->frame_control) &&
  570. !ieee80211_is_nullfunc(hdr->frame_control) &&
  571. !ieee80211_has_pm(hdr->frame_control)) {
  572. ath_dbg(common, PS,
  573. "Add PM=1 for a TX frame while in PS mode\n");
  574. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  575. }
  576. }
  577. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
  578. /*
  579. * We are using PS-Poll and mac80211 can request TX while in
  580. * power save mode. Need to wake up hardware for the TX to be
  581. * completed and if needed, also for RX of buffered frames.
  582. */
  583. ath9k_ps_wakeup(sc);
  584. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  585. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  586. ath9k_hw_setrxabort(sc->sc_ah, 0);
  587. if (ieee80211_is_pspoll(hdr->frame_control)) {
  588. ath_dbg(common, PS,
  589. "Sending PS-Poll to pick a buffered frame\n");
  590. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  591. } else {
  592. ath_dbg(common, PS, "Wake up to complete TX\n");
  593. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  594. }
  595. /*
  596. * The actual restore operation will happen only after
  597. * the ps_flags bit is cleared. We are just dropping
  598. * the ps_usecount here.
  599. */
  600. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  601. ath9k_ps_restore(sc);
  602. }
  603. /*
  604. * Cannot tx while the hardware is in full sleep, it first needs a full
  605. * chip reset to recover from that
  606. */
  607. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
  608. ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
  609. goto exit;
  610. }
  611. memset(&txctl, 0, sizeof(struct ath_tx_control));
  612. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  613. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  614. if (ath_tx_start(hw, skb, &txctl) != 0) {
  615. ath_dbg(common, XMIT, "TX failed\n");
  616. TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
  617. goto exit;
  618. }
  619. return;
  620. exit:
  621. dev_kfree_skb_any(skb);
  622. }
  623. static void ath9k_stop(struct ieee80211_hw *hw)
  624. {
  625. struct ath_softc *sc = hw->priv;
  626. struct ath_hw *ah = sc->sc_ah;
  627. struct ath_common *common = ath9k_hw_common(ah);
  628. bool prev_idle;
  629. mutex_lock(&sc->mutex);
  630. ath_cancel_work(sc);
  631. del_timer_sync(&sc->rx_poll_timer);
  632. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  633. ath_dbg(common, ANY, "Device not present\n");
  634. mutex_unlock(&sc->mutex);
  635. return;
  636. }
  637. /* Ensure HW is awake when we try to shut it down. */
  638. ath9k_ps_wakeup(sc);
  639. ath9k_stop_btcoex(sc);
  640. spin_lock_bh(&sc->sc_pcu_lock);
  641. /* prevent tasklets to enable interrupts once we disable them */
  642. ah->imask &= ~ATH9K_INT_GLOBAL;
  643. /* make sure h/w will not generate any interrupt
  644. * before setting the invalid flag. */
  645. ath9k_hw_disable_interrupts(ah);
  646. spin_unlock_bh(&sc->sc_pcu_lock);
  647. /* we can now sync irq and kill any running tasklets, since we already
  648. * disabled interrupts and not holding a spin lock */
  649. synchronize_irq(sc->irq);
  650. tasklet_kill(&sc->intr_tq);
  651. tasklet_kill(&sc->bcon_tasklet);
  652. prev_idle = sc->ps_idle;
  653. sc->ps_idle = true;
  654. spin_lock_bh(&sc->sc_pcu_lock);
  655. if (ah->led_pin >= 0) {
  656. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  657. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  658. }
  659. ath_prepare_reset(sc, false, true);
  660. if (sc->rx.frag) {
  661. dev_kfree_skb_any(sc->rx.frag);
  662. sc->rx.frag = NULL;
  663. }
  664. if (!ah->curchan)
  665. ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
  666. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  667. ath9k_hw_phy_disable(ah);
  668. ath9k_hw_configpcipowersave(ah, true);
  669. spin_unlock_bh(&sc->sc_pcu_lock);
  670. ath9k_ps_restore(sc);
  671. set_bit(SC_OP_INVALID, &sc->sc_flags);
  672. sc->ps_idle = prev_idle;
  673. mutex_unlock(&sc->mutex);
  674. ath_dbg(common, CONFIG, "Driver halt\n");
  675. }
  676. bool ath9k_uses_beacons(int type)
  677. {
  678. switch (type) {
  679. case NL80211_IFTYPE_AP:
  680. case NL80211_IFTYPE_ADHOC:
  681. case NL80211_IFTYPE_MESH_POINT:
  682. return true;
  683. default:
  684. return false;
  685. }
  686. }
  687. static void ath9k_reclaim_beacon(struct ath_softc *sc,
  688. struct ieee80211_vif *vif)
  689. {
  690. struct ath_vif *avp = (void *)vif->drv_priv;
  691. ath9k_set_beaconing_status(sc, false);
  692. ath_beacon_return(sc, avp);
  693. ath9k_set_beaconing_status(sc, true);
  694. }
  695. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  696. {
  697. struct ath9k_vif_iter_data *iter_data = data;
  698. int i;
  699. if (iter_data->hw_macaddr)
  700. for (i = 0; i < ETH_ALEN; i++)
  701. iter_data->mask[i] &=
  702. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  703. switch (vif->type) {
  704. case NL80211_IFTYPE_AP:
  705. iter_data->naps++;
  706. break;
  707. case NL80211_IFTYPE_STATION:
  708. iter_data->nstations++;
  709. break;
  710. case NL80211_IFTYPE_ADHOC:
  711. iter_data->nadhocs++;
  712. break;
  713. case NL80211_IFTYPE_MESH_POINT:
  714. iter_data->nmeshes++;
  715. break;
  716. case NL80211_IFTYPE_WDS:
  717. iter_data->nwds++;
  718. break;
  719. default:
  720. break;
  721. }
  722. }
  723. /* Called with sc->mutex held. */
  724. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  725. struct ieee80211_vif *vif,
  726. struct ath9k_vif_iter_data *iter_data)
  727. {
  728. struct ath_softc *sc = hw->priv;
  729. struct ath_hw *ah = sc->sc_ah;
  730. struct ath_common *common = ath9k_hw_common(ah);
  731. /*
  732. * Use the hardware MAC address as reference, the hardware uses it
  733. * together with the BSSID mask when matching addresses.
  734. */
  735. memset(iter_data, 0, sizeof(*iter_data));
  736. iter_data->hw_macaddr = common->macaddr;
  737. memset(&iter_data->mask, 0xff, ETH_ALEN);
  738. if (vif)
  739. ath9k_vif_iter(iter_data, vif->addr, vif);
  740. /* Get list of all active MAC addresses */
  741. ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
  742. iter_data);
  743. }
  744. /* Called with sc->mutex held. */
  745. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  746. struct ieee80211_vif *vif)
  747. {
  748. struct ath_softc *sc = hw->priv;
  749. struct ath_hw *ah = sc->sc_ah;
  750. struct ath_common *common = ath9k_hw_common(ah);
  751. struct ath9k_vif_iter_data iter_data;
  752. ath9k_calculate_iter_data(hw, vif, &iter_data);
  753. /* Set BSSID mask. */
  754. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  755. ath_hw_setbssidmask(common);
  756. /* Set op-mode & TSF */
  757. if (iter_data.naps > 0) {
  758. ath9k_hw_set_tsfadjust(ah, 1);
  759. set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
  760. ah->opmode = NL80211_IFTYPE_AP;
  761. } else {
  762. ath9k_hw_set_tsfadjust(ah, 0);
  763. clear_bit(SC_OP_TSF_RESET, &sc->sc_flags);
  764. if (iter_data.nmeshes)
  765. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  766. else if (iter_data.nwds)
  767. ah->opmode = NL80211_IFTYPE_AP;
  768. else if (iter_data.nadhocs)
  769. ah->opmode = NL80211_IFTYPE_ADHOC;
  770. else
  771. ah->opmode = NL80211_IFTYPE_STATION;
  772. }
  773. /*
  774. * Enable MIB interrupts when there are hardware phy counters.
  775. */
  776. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
  777. if (ah->config.enable_ani)
  778. ah->imask |= ATH9K_INT_MIB;
  779. ah->imask |= ATH9K_INT_TSFOOR;
  780. } else {
  781. ah->imask &= ~ATH9K_INT_MIB;
  782. ah->imask &= ~ATH9K_INT_TSFOOR;
  783. }
  784. ath9k_hw_set_interrupts(ah);
  785. /* Set up ANI */
  786. if (iter_data.naps > 0) {
  787. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  788. if (!common->disable_ani) {
  789. set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  790. ath_start_ani(common);
  791. }
  792. } else {
  793. clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  794. del_timer_sync(&common->ani.timer);
  795. }
  796. }
  797. /* Called with sc->mutex held, vif counts set up properly. */
  798. static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
  799. struct ieee80211_vif *vif)
  800. {
  801. struct ath_softc *sc = hw->priv;
  802. ath9k_calculate_summary_state(hw, vif);
  803. if (ath9k_uses_beacons(vif->type)) {
  804. /* Reserve a beacon slot for the vif */
  805. ath9k_set_beaconing_status(sc, false);
  806. ath_beacon_alloc(sc, vif);
  807. ath9k_set_beaconing_status(sc, true);
  808. }
  809. }
  810. static int ath9k_add_interface(struct ieee80211_hw *hw,
  811. struct ieee80211_vif *vif)
  812. {
  813. struct ath_softc *sc = hw->priv;
  814. struct ath_hw *ah = sc->sc_ah;
  815. struct ath_common *common = ath9k_hw_common(ah);
  816. int ret = 0;
  817. ath9k_ps_wakeup(sc);
  818. mutex_lock(&sc->mutex);
  819. switch (vif->type) {
  820. case NL80211_IFTYPE_STATION:
  821. case NL80211_IFTYPE_WDS:
  822. case NL80211_IFTYPE_ADHOC:
  823. case NL80211_IFTYPE_AP:
  824. case NL80211_IFTYPE_MESH_POINT:
  825. break;
  826. default:
  827. ath_err(common, "Interface type %d not yet supported\n",
  828. vif->type);
  829. ret = -EOPNOTSUPP;
  830. goto out;
  831. }
  832. if (ath9k_uses_beacons(vif->type)) {
  833. if (sc->nbcnvifs >= ATH_BCBUF) {
  834. ath_err(common, "Not enough beacon buffers when adding"
  835. " new interface of type: %i\n",
  836. vif->type);
  837. ret = -ENOBUFS;
  838. goto out;
  839. }
  840. }
  841. if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
  842. ((vif->type == NL80211_IFTYPE_ADHOC) &&
  843. sc->nvifs > 0)) {
  844. ath_err(common, "Cannot create ADHOC interface when other"
  845. " interfaces already exist.\n");
  846. ret = -EINVAL;
  847. goto out;
  848. }
  849. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  850. sc->nvifs++;
  851. ath9k_do_vif_add_setup(hw, vif);
  852. out:
  853. mutex_unlock(&sc->mutex);
  854. ath9k_ps_restore(sc);
  855. return ret;
  856. }
  857. static int ath9k_change_interface(struct ieee80211_hw *hw,
  858. struct ieee80211_vif *vif,
  859. enum nl80211_iftype new_type,
  860. bool p2p)
  861. {
  862. struct ath_softc *sc = hw->priv;
  863. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  864. int ret = 0;
  865. ath_dbg(common, CONFIG, "Change Interface\n");
  866. mutex_lock(&sc->mutex);
  867. ath9k_ps_wakeup(sc);
  868. /* See if new interface type is valid. */
  869. if ((new_type == NL80211_IFTYPE_ADHOC) &&
  870. (sc->nvifs > 1)) {
  871. ath_err(common, "When using ADHOC, it must be the only"
  872. " interface.\n");
  873. ret = -EINVAL;
  874. goto out;
  875. }
  876. if (ath9k_uses_beacons(new_type) &&
  877. !ath9k_uses_beacons(vif->type)) {
  878. if (sc->nbcnvifs >= ATH_BCBUF) {
  879. ath_err(common, "No beacon slot available\n");
  880. ret = -ENOBUFS;
  881. goto out;
  882. }
  883. }
  884. /* Clean up old vif stuff */
  885. if (ath9k_uses_beacons(vif->type))
  886. ath9k_reclaim_beacon(sc, vif);
  887. /* Add new settings */
  888. vif->type = new_type;
  889. vif->p2p = p2p;
  890. ath9k_do_vif_add_setup(hw, vif);
  891. out:
  892. ath9k_ps_restore(sc);
  893. mutex_unlock(&sc->mutex);
  894. return ret;
  895. }
  896. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  897. struct ieee80211_vif *vif)
  898. {
  899. struct ath_softc *sc = hw->priv;
  900. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  901. ath_dbg(common, CONFIG, "Detach Interface\n");
  902. ath9k_ps_wakeup(sc);
  903. mutex_lock(&sc->mutex);
  904. sc->nvifs--;
  905. /* Reclaim beacon resources */
  906. if (ath9k_uses_beacons(vif->type))
  907. ath9k_reclaim_beacon(sc, vif);
  908. ath9k_calculate_summary_state(hw, NULL);
  909. mutex_unlock(&sc->mutex);
  910. ath9k_ps_restore(sc);
  911. }
  912. static void ath9k_enable_ps(struct ath_softc *sc)
  913. {
  914. struct ath_hw *ah = sc->sc_ah;
  915. struct ath_common *common = ath9k_hw_common(ah);
  916. sc->ps_enabled = true;
  917. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  918. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  919. ah->imask |= ATH9K_INT_TIM_TIMER;
  920. ath9k_hw_set_interrupts(ah);
  921. }
  922. ath9k_hw_setrxabort(ah, 1);
  923. }
  924. ath_dbg(common, PS, "PowerSave enabled\n");
  925. }
  926. static void ath9k_disable_ps(struct ath_softc *sc)
  927. {
  928. struct ath_hw *ah = sc->sc_ah;
  929. struct ath_common *common = ath9k_hw_common(ah);
  930. sc->ps_enabled = false;
  931. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  932. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  933. ath9k_hw_setrxabort(ah, 0);
  934. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  935. PS_WAIT_FOR_CAB |
  936. PS_WAIT_FOR_PSPOLL_DATA |
  937. PS_WAIT_FOR_TX_ACK);
  938. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  939. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  940. ath9k_hw_set_interrupts(ah);
  941. }
  942. }
  943. ath_dbg(common, PS, "PowerSave disabled\n");
  944. }
  945. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  946. {
  947. struct ath_softc *sc = hw->priv;
  948. struct ath_hw *ah = sc->sc_ah;
  949. struct ath_common *common = ath9k_hw_common(ah);
  950. struct ieee80211_conf *conf = &hw->conf;
  951. bool reset_channel = false;
  952. ath9k_ps_wakeup(sc);
  953. mutex_lock(&sc->mutex);
  954. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  955. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  956. if (sc->ps_idle)
  957. ath_cancel_work(sc);
  958. else
  959. /*
  960. * The chip needs a reset to properly wake up from
  961. * full sleep
  962. */
  963. reset_channel = ah->chip_fullsleep;
  964. }
  965. /*
  966. * We just prepare to enable PS. We have to wait until our AP has
  967. * ACK'd our null data frame to disable RX otherwise we'll ignore
  968. * those ACKs and end up retransmitting the same null data frames.
  969. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  970. */
  971. if (changed & IEEE80211_CONF_CHANGE_PS) {
  972. unsigned long flags;
  973. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  974. if (conf->flags & IEEE80211_CONF_PS)
  975. ath9k_enable_ps(sc);
  976. else
  977. ath9k_disable_ps(sc);
  978. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  979. }
  980. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  981. if (conf->flags & IEEE80211_CONF_MONITOR) {
  982. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  983. sc->sc_ah->is_monitoring = true;
  984. } else {
  985. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  986. sc->sc_ah->is_monitoring = false;
  987. }
  988. }
  989. if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
  990. struct ieee80211_channel *curchan = hw->conf.channel;
  991. int pos = curchan->hw_value;
  992. int old_pos = -1;
  993. unsigned long flags;
  994. if (ah->curchan)
  995. old_pos = ah->curchan - &ah->channels[0];
  996. ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
  997. curchan->center_freq, conf->channel_type);
  998. /* update survey stats for the old channel before switching */
  999. spin_lock_irqsave(&common->cc_lock, flags);
  1000. ath_update_survey_stats(sc);
  1001. spin_unlock_irqrestore(&common->cc_lock, flags);
  1002. /*
  1003. * Preserve the current channel values, before updating
  1004. * the same channel
  1005. */
  1006. if (ah->curchan && (old_pos == pos))
  1007. ath9k_hw_getnf(ah, ah->curchan);
  1008. ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
  1009. curchan, conf->channel_type);
  1010. /*
  1011. * If the operating channel changes, change the survey in-use flags
  1012. * along with it.
  1013. * Reset the survey data for the new channel, unless we're switching
  1014. * back to the operating channel from an off-channel operation.
  1015. */
  1016. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  1017. sc->cur_survey != &sc->survey[pos]) {
  1018. if (sc->cur_survey)
  1019. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  1020. sc->cur_survey = &sc->survey[pos];
  1021. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  1022. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  1023. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  1024. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  1025. }
  1026. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1027. ath_err(common, "Unable to set channel\n");
  1028. mutex_unlock(&sc->mutex);
  1029. return -EINVAL;
  1030. }
  1031. /*
  1032. * The most recent snapshot of channel->noisefloor for the old
  1033. * channel is only available after the hardware reset. Copy it to
  1034. * the survey stats now.
  1035. */
  1036. if (old_pos >= 0)
  1037. ath_update_survey_nf(sc, old_pos);
  1038. }
  1039. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1040. ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
  1041. sc->config.txpowlimit = 2 * conf->power_level;
  1042. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  1043. sc->config.txpowlimit, &sc->curtxpow);
  1044. }
  1045. mutex_unlock(&sc->mutex);
  1046. ath9k_ps_restore(sc);
  1047. return 0;
  1048. }
  1049. #define SUPPORTED_FILTERS \
  1050. (FIF_PROMISC_IN_BSS | \
  1051. FIF_ALLMULTI | \
  1052. FIF_CONTROL | \
  1053. FIF_PSPOLL | \
  1054. FIF_OTHER_BSS | \
  1055. FIF_BCN_PRBRESP_PROMISC | \
  1056. FIF_PROBE_REQ | \
  1057. FIF_FCSFAIL)
  1058. /* FIXME: sc->sc_full_reset ? */
  1059. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1060. unsigned int changed_flags,
  1061. unsigned int *total_flags,
  1062. u64 multicast)
  1063. {
  1064. struct ath_softc *sc = hw->priv;
  1065. u32 rfilt;
  1066. changed_flags &= SUPPORTED_FILTERS;
  1067. *total_flags &= SUPPORTED_FILTERS;
  1068. sc->rx.rxfilter = *total_flags;
  1069. ath9k_ps_wakeup(sc);
  1070. rfilt = ath_calcrxfilter(sc);
  1071. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1072. ath9k_ps_restore(sc);
  1073. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1074. rfilt);
  1075. }
  1076. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1077. struct ieee80211_vif *vif,
  1078. struct ieee80211_sta *sta)
  1079. {
  1080. struct ath_softc *sc = hw->priv;
  1081. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1082. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1083. struct ieee80211_key_conf ps_key = { };
  1084. ath_node_attach(sc, sta, vif);
  1085. if (vif->type != NL80211_IFTYPE_AP &&
  1086. vif->type != NL80211_IFTYPE_AP_VLAN)
  1087. return 0;
  1088. an->ps_key = ath_key_config(common, vif, sta, &ps_key);
  1089. return 0;
  1090. }
  1091. static void ath9k_del_ps_key(struct ath_softc *sc,
  1092. struct ieee80211_vif *vif,
  1093. struct ieee80211_sta *sta)
  1094. {
  1095. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1096. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1097. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1098. if (!an->ps_key)
  1099. return;
  1100. ath_key_delete(common, &ps_key);
  1101. }
  1102. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1103. struct ieee80211_vif *vif,
  1104. struct ieee80211_sta *sta)
  1105. {
  1106. struct ath_softc *sc = hw->priv;
  1107. ath9k_del_ps_key(sc, vif, sta);
  1108. ath_node_detach(sc, sta);
  1109. return 0;
  1110. }
  1111. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1112. struct ieee80211_vif *vif,
  1113. enum sta_notify_cmd cmd,
  1114. struct ieee80211_sta *sta)
  1115. {
  1116. struct ath_softc *sc = hw->priv;
  1117. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1118. if (!sta->ht_cap.ht_supported)
  1119. return;
  1120. switch (cmd) {
  1121. case STA_NOTIFY_SLEEP:
  1122. an->sleeping = true;
  1123. ath_tx_aggr_sleep(sta, sc, an);
  1124. break;
  1125. case STA_NOTIFY_AWAKE:
  1126. an->sleeping = false;
  1127. ath_tx_aggr_wakeup(sc, an);
  1128. break;
  1129. }
  1130. }
  1131. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1132. struct ieee80211_vif *vif, u16 queue,
  1133. const struct ieee80211_tx_queue_params *params)
  1134. {
  1135. struct ath_softc *sc = hw->priv;
  1136. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1137. struct ath_txq *txq;
  1138. struct ath9k_tx_queue_info qi;
  1139. int ret = 0;
  1140. if (queue >= WME_NUM_AC)
  1141. return 0;
  1142. txq = sc->tx.txq_map[queue];
  1143. ath9k_ps_wakeup(sc);
  1144. mutex_lock(&sc->mutex);
  1145. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1146. qi.tqi_aifs = params->aifs;
  1147. qi.tqi_cwmin = params->cw_min;
  1148. qi.tqi_cwmax = params->cw_max;
  1149. qi.tqi_burstTime = params->txop;
  1150. ath_dbg(common, CONFIG,
  1151. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1152. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1153. params->cw_max, params->txop);
  1154. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1155. if (ret)
  1156. ath_err(common, "TXQ Update failed\n");
  1157. if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
  1158. if (queue == WME_AC_BE && !ret)
  1159. ath_beaconq_config(sc);
  1160. mutex_unlock(&sc->mutex);
  1161. ath9k_ps_restore(sc);
  1162. return ret;
  1163. }
  1164. static int ath9k_set_key(struct ieee80211_hw *hw,
  1165. enum set_key_cmd cmd,
  1166. struct ieee80211_vif *vif,
  1167. struct ieee80211_sta *sta,
  1168. struct ieee80211_key_conf *key)
  1169. {
  1170. struct ath_softc *sc = hw->priv;
  1171. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1172. int ret = 0;
  1173. if (ath9k_modparam_nohwcrypt)
  1174. return -ENOSPC;
  1175. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1176. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1177. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1178. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1179. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1180. /*
  1181. * For now, disable hw crypto for the RSN IBSS group keys. This
  1182. * could be optimized in the future to use a modified key cache
  1183. * design to support per-STA RX GTK, but until that gets
  1184. * implemented, use of software crypto for group addressed
  1185. * frames is a acceptable to allow RSN IBSS to be used.
  1186. */
  1187. return -EOPNOTSUPP;
  1188. }
  1189. mutex_lock(&sc->mutex);
  1190. ath9k_ps_wakeup(sc);
  1191. ath_dbg(common, CONFIG, "Set HW Key\n");
  1192. switch (cmd) {
  1193. case SET_KEY:
  1194. if (sta)
  1195. ath9k_del_ps_key(sc, vif, sta);
  1196. ret = ath_key_config(common, vif, sta, key);
  1197. if (ret >= 0) {
  1198. key->hw_key_idx = ret;
  1199. /* push IV and Michael MIC generation to stack */
  1200. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1201. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1202. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1203. if (sc->sc_ah->sw_mgmt_crypto &&
  1204. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1205. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1206. ret = 0;
  1207. }
  1208. break;
  1209. case DISABLE_KEY:
  1210. ath_key_delete(common, key);
  1211. break;
  1212. default:
  1213. ret = -EINVAL;
  1214. }
  1215. ath9k_ps_restore(sc);
  1216. mutex_unlock(&sc->mutex);
  1217. return ret;
  1218. }
  1219. static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1220. {
  1221. struct ath_softc *sc = data;
  1222. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1223. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1224. struct ath_vif *avp = (void *)vif->drv_priv;
  1225. unsigned long flags;
  1226. /*
  1227. * Skip iteration if primary station vif's bss info
  1228. * was not changed
  1229. */
  1230. if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
  1231. return;
  1232. if (bss_conf->assoc) {
  1233. set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1234. avp->primary_sta_vif = true;
  1235. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1236. common->curaid = bss_conf->aid;
  1237. ath9k_hw_write_associd(sc->sc_ah);
  1238. ath_dbg(common, CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
  1239. bss_conf->aid, common->curbssid);
  1240. ath_beacon_config(sc, vif);
  1241. /*
  1242. * Request a re-configuration of Beacon related timers
  1243. * on the receipt of the first Beacon frame (i.e.,
  1244. * after time sync with the AP).
  1245. */
  1246. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1247. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  1248. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1249. /* Reset rssi stats */
  1250. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1251. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1252. ath_start_rx_poll(sc, 3);
  1253. if (!common->disable_ani) {
  1254. set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1255. ath_start_ani(common);
  1256. }
  1257. }
  1258. }
  1259. static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
  1260. {
  1261. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1262. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1263. struct ath_vif *avp = (void *)vif->drv_priv;
  1264. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  1265. return;
  1266. /* Reconfigure bss info */
  1267. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1268. ath_dbg(common, CONFIG, "Bss Info DISASSOC %d, bssid %pM\n",
  1269. common->curaid, common->curbssid);
  1270. clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1271. clear_bit(SC_OP_BEACONS, &sc->sc_flags);
  1272. avp->primary_sta_vif = false;
  1273. memset(common->curbssid, 0, ETH_ALEN);
  1274. common->curaid = 0;
  1275. }
  1276. ieee80211_iterate_active_interfaces_atomic(
  1277. sc->hw, ath9k_bss_iter, sc);
  1278. /*
  1279. * None of station vifs are associated.
  1280. * Clear bssid & aid
  1281. */
  1282. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  1283. ath9k_hw_write_associd(sc->sc_ah);
  1284. clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1285. del_timer_sync(&common->ani.timer);
  1286. del_timer_sync(&sc->rx_poll_timer);
  1287. memset(&sc->caldata, 0, sizeof(sc->caldata));
  1288. }
  1289. }
  1290. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1291. struct ieee80211_vif *vif,
  1292. struct ieee80211_bss_conf *bss_conf,
  1293. u32 changed)
  1294. {
  1295. struct ath_softc *sc = hw->priv;
  1296. struct ath_hw *ah = sc->sc_ah;
  1297. struct ath_common *common = ath9k_hw_common(ah);
  1298. struct ath_vif *avp = (void *)vif->drv_priv;
  1299. int slottime;
  1300. ath9k_ps_wakeup(sc);
  1301. mutex_lock(&sc->mutex);
  1302. if (changed & BSS_CHANGED_ASSOC) {
  1303. ath9k_config_bss(sc, vif);
  1304. ath_dbg(common, CONFIG, "BSSID: %pM aid: 0x%x\n",
  1305. common->curbssid, common->curaid);
  1306. }
  1307. if (changed & BSS_CHANGED_IBSS) {
  1308. /* There can be only one vif available */
  1309. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1310. common->curaid = bss_conf->aid;
  1311. ath9k_hw_write_associd(sc->sc_ah);
  1312. if (bss_conf->ibss_joined) {
  1313. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1314. if (!common->disable_ani) {
  1315. set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1316. ath_start_ani(common);
  1317. }
  1318. } else {
  1319. clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1320. del_timer_sync(&common->ani.timer);
  1321. del_timer_sync(&sc->rx_poll_timer);
  1322. }
  1323. }
  1324. /*
  1325. * In case of AP mode, the HW TSF has to be reset
  1326. * when the beacon interval changes.
  1327. */
  1328. if ((changed & BSS_CHANGED_BEACON_INT) &&
  1329. (vif->type == NL80211_IFTYPE_AP))
  1330. set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
  1331. /* Configure beaconing (AP, IBSS, MESH) */
  1332. if (ath9k_uses_beacons(vif->type) &&
  1333. ((changed & BSS_CHANGED_BEACON) ||
  1334. (changed & BSS_CHANGED_BEACON_ENABLED) ||
  1335. (changed & BSS_CHANGED_BEACON_INT))) {
  1336. ath9k_set_beaconing_status(sc, false);
  1337. if (bss_conf->enable_beacon)
  1338. ath_beacon_alloc(sc, vif);
  1339. else
  1340. avp->is_bslot_active = false;
  1341. ath_beacon_config(sc, vif);
  1342. ath9k_set_beaconing_status(sc, true);
  1343. }
  1344. if (changed & BSS_CHANGED_ERP_SLOT) {
  1345. if (bss_conf->use_short_slot)
  1346. slottime = 9;
  1347. else
  1348. slottime = 20;
  1349. if (vif->type == NL80211_IFTYPE_AP) {
  1350. /*
  1351. * Defer update, so that connected stations can adjust
  1352. * their settings at the same time.
  1353. * See beacon.c for more details
  1354. */
  1355. sc->beacon.slottime = slottime;
  1356. sc->beacon.updateslot = UPDATE;
  1357. } else {
  1358. ah->slottime = slottime;
  1359. ath9k_hw_init_global_settings(ah);
  1360. }
  1361. }
  1362. mutex_unlock(&sc->mutex);
  1363. ath9k_ps_restore(sc);
  1364. }
  1365. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1366. {
  1367. struct ath_softc *sc = hw->priv;
  1368. u64 tsf;
  1369. mutex_lock(&sc->mutex);
  1370. ath9k_ps_wakeup(sc);
  1371. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1372. ath9k_ps_restore(sc);
  1373. mutex_unlock(&sc->mutex);
  1374. return tsf;
  1375. }
  1376. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1377. struct ieee80211_vif *vif,
  1378. u64 tsf)
  1379. {
  1380. struct ath_softc *sc = hw->priv;
  1381. mutex_lock(&sc->mutex);
  1382. ath9k_ps_wakeup(sc);
  1383. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1384. ath9k_ps_restore(sc);
  1385. mutex_unlock(&sc->mutex);
  1386. }
  1387. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1388. {
  1389. struct ath_softc *sc = hw->priv;
  1390. mutex_lock(&sc->mutex);
  1391. ath9k_ps_wakeup(sc);
  1392. ath9k_hw_reset_tsf(sc->sc_ah);
  1393. ath9k_ps_restore(sc);
  1394. mutex_unlock(&sc->mutex);
  1395. }
  1396. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1397. struct ieee80211_vif *vif,
  1398. enum ieee80211_ampdu_mlme_action action,
  1399. struct ieee80211_sta *sta,
  1400. u16 tid, u16 *ssn, u8 buf_size)
  1401. {
  1402. struct ath_softc *sc = hw->priv;
  1403. int ret = 0;
  1404. local_bh_disable();
  1405. switch (action) {
  1406. case IEEE80211_AMPDU_RX_START:
  1407. break;
  1408. case IEEE80211_AMPDU_RX_STOP:
  1409. break;
  1410. case IEEE80211_AMPDU_TX_START:
  1411. ath9k_ps_wakeup(sc);
  1412. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1413. if (!ret)
  1414. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1415. ath9k_ps_restore(sc);
  1416. break;
  1417. case IEEE80211_AMPDU_TX_STOP:
  1418. ath9k_ps_wakeup(sc);
  1419. ath_tx_aggr_stop(sc, sta, tid);
  1420. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1421. ath9k_ps_restore(sc);
  1422. break;
  1423. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1424. ath9k_ps_wakeup(sc);
  1425. ath_tx_aggr_resume(sc, sta, tid);
  1426. ath9k_ps_restore(sc);
  1427. break;
  1428. default:
  1429. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1430. }
  1431. local_bh_enable();
  1432. return ret;
  1433. }
  1434. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1435. struct survey_info *survey)
  1436. {
  1437. struct ath_softc *sc = hw->priv;
  1438. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1439. struct ieee80211_supported_band *sband;
  1440. struct ieee80211_channel *chan;
  1441. unsigned long flags;
  1442. int pos;
  1443. spin_lock_irqsave(&common->cc_lock, flags);
  1444. if (idx == 0)
  1445. ath_update_survey_stats(sc);
  1446. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1447. if (sband && idx >= sband->n_channels) {
  1448. idx -= sband->n_channels;
  1449. sband = NULL;
  1450. }
  1451. if (!sband)
  1452. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1453. if (!sband || idx >= sband->n_channels) {
  1454. spin_unlock_irqrestore(&common->cc_lock, flags);
  1455. return -ENOENT;
  1456. }
  1457. chan = &sband->channels[idx];
  1458. pos = chan->hw_value;
  1459. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1460. survey->channel = chan;
  1461. spin_unlock_irqrestore(&common->cc_lock, flags);
  1462. return 0;
  1463. }
  1464. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1465. {
  1466. struct ath_softc *sc = hw->priv;
  1467. struct ath_hw *ah = sc->sc_ah;
  1468. mutex_lock(&sc->mutex);
  1469. ah->coverage_class = coverage_class;
  1470. ath9k_ps_wakeup(sc);
  1471. ath9k_hw_init_global_settings(ah);
  1472. ath9k_ps_restore(sc);
  1473. mutex_unlock(&sc->mutex);
  1474. }
  1475. static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
  1476. {
  1477. struct ath_softc *sc = hw->priv;
  1478. struct ath_hw *ah = sc->sc_ah;
  1479. struct ath_common *common = ath9k_hw_common(ah);
  1480. int timeout = 200; /* ms */
  1481. int i, j;
  1482. bool drain_txq;
  1483. mutex_lock(&sc->mutex);
  1484. cancel_delayed_work_sync(&sc->tx_complete_work);
  1485. if (ah->ah_flags & AH_UNPLUGGED) {
  1486. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1487. mutex_unlock(&sc->mutex);
  1488. return;
  1489. }
  1490. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1491. ath_dbg(common, ANY, "Device not present\n");
  1492. mutex_unlock(&sc->mutex);
  1493. return;
  1494. }
  1495. for (j = 0; j < timeout; j++) {
  1496. bool npend = false;
  1497. if (j)
  1498. usleep_range(1000, 2000);
  1499. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1500. if (!ATH_TXQ_SETUP(sc, i))
  1501. continue;
  1502. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1503. if (npend)
  1504. break;
  1505. }
  1506. if (!npend)
  1507. break;
  1508. }
  1509. if (drop) {
  1510. ath9k_ps_wakeup(sc);
  1511. spin_lock_bh(&sc->sc_pcu_lock);
  1512. drain_txq = ath_drain_all_txq(sc, false);
  1513. spin_unlock_bh(&sc->sc_pcu_lock);
  1514. if (!drain_txq)
  1515. ath_reset(sc, false);
  1516. ath9k_ps_restore(sc);
  1517. ieee80211_wake_queues(hw);
  1518. }
  1519. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1520. mutex_unlock(&sc->mutex);
  1521. }
  1522. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1523. {
  1524. struct ath_softc *sc = hw->priv;
  1525. int i;
  1526. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1527. if (!ATH_TXQ_SETUP(sc, i))
  1528. continue;
  1529. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1530. return true;
  1531. }
  1532. return false;
  1533. }
  1534. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1535. {
  1536. struct ath_softc *sc = hw->priv;
  1537. struct ath_hw *ah = sc->sc_ah;
  1538. struct ieee80211_vif *vif;
  1539. struct ath_vif *avp;
  1540. struct ath_buf *bf;
  1541. struct ath_tx_status ts;
  1542. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1543. int status;
  1544. vif = sc->beacon.bslot[0];
  1545. if (!vif)
  1546. return 0;
  1547. avp = (void *)vif->drv_priv;
  1548. if (!avp->is_bslot_active)
  1549. return 0;
  1550. if (!sc->beacon.tx_processed && !edma) {
  1551. tasklet_disable(&sc->bcon_tasklet);
  1552. bf = avp->av_bcbuf;
  1553. if (!bf || !bf->bf_mpdu)
  1554. goto skip;
  1555. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1556. if (status == -EINPROGRESS)
  1557. goto skip;
  1558. sc->beacon.tx_processed = true;
  1559. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1560. skip:
  1561. tasklet_enable(&sc->bcon_tasklet);
  1562. }
  1563. return sc->beacon.tx_last;
  1564. }
  1565. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1566. struct ieee80211_low_level_stats *stats)
  1567. {
  1568. struct ath_softc *sc = hw->priv;
  1569. struct ath_hw *ah = sc->sc_ah;
  1570. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1571. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1572. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1573. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1574. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1575. return 0;
  1576. }
  1577. static u32 fill_chainmask(u32 cap, u32 new)
  1578. {
  1579. u32 filled = 0;
  1580. int i;
  1581. for (i = 0; cap && new; i++, cap >>= 1) {
  1582. if (!(cap & BIT(0)))
  1583. continue;
  1584. if (new & BIT(0))
  1585. filled |= BIT(i);
  1586. new >>= 1;
  1587. }
  1588. return filled;
  1589. }
  1590. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  1591. {
  1592. struct ath_softc *sc = hw->priv;
  1593. struct ath_hw *ah = sc->sc_ah;
  1594. if (!rx_ant || !tx_ant)
  1595. return -EINVAL;
  1596. sc->ant_rx = rx_ant;
  1597. sc->ant_tx = tx_ant;
  1598. if (ah->caps.rx_chainmask == 1)
  1599. return 0;
  1600. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1601. if (AR_SREV_9100(ah))
  1602. ah->rxchainmask = 0x7;
  1603. else
  1604. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1605. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1606. ath9k_reload_chainmask_settings(sc);
  1607. return 0;
  1608. }
  1609. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  1610. {
  1611. struct ath_softc *sc = hw->priv;
  1612. *tx_ant = sc->ant_tx;
  1613. *rx_ant = sc->ant_rx;
  1614. return 0;
  1615. }
  1616. #ifdef CONFIG_ATH9K_DEBUGFS
  1617. /* Ethtool support for get-stats */
  1618. #define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO"
  1619. static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = {
  1620. "tx_pkts_nic",
  1621. "tx_bytes_nic",
  1622. "rx_pkts_nic",
  1623. "rx_bytes_nic",
  1624. AMKSTR(d_tx_pkts),
  1625. AMKSTR(d_tx_bytes),
  1626. AMKSTR(d_tx_mpdus_queued),
  1627. AMKSTR(d_tx_mpdus_completed),
  1628. AMKSTR(d_tx_mpdu_xretries),
  1629. AMKSTR(d_tx_aggregates),
  1630. AMKSTR(d_tx_ampdus_queued_hw),
  1631. AMKSTR(d_tx_ampdus_queued_sw),
  1632. AMKSTR(d_tx_ampdus_completed),
  1633. AMKSTR(d_tx_ampdu_retries),
  1634. AMKSTR(d_tx_ampdu_xretries),
  1635. AMKSTR(d_tx_fifo_underrun),
  1636. AMKSTR(d_tx_op_exceeded),
  1637. AMKSTR(d_tx_timer_expiry),
  1638. AMKSTR(d_tx_desc_cfg_err),
  1639. AMKSTR(d_tx_data_underrun),
  1640. AMKSTR(d_tx_delim_underrun),
  1641. "d_rx_decrypt_crc_err",
  1642. "d_rx_phy_err",
  1643. "d_rx_mic_err",
  1644. "d_rx_pre_delim_crc_err",
  1645. "d_rx_post_delim_crc_err",
  1646. "d_rx_decrypt_busy_err",
  1647. "d_rx_phyerr_radar",
  1648. "d_rx_phyerr_ofdm_timing",
  1649. "d_rx_phyerr_cck_timing",
  1650. };
  1651. #define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats)
  1652. static void ath9k_get_et_strings(struct ieee80211_hw *hw,
  1653. struct ieee80211_vif *vif,
  1654. u32 sset, u8 *data)
  1655. {
  1656. if (sset == ETH_SS_STATS)
  1657. memcpy(data, *ath9k_gstrings_stats,
  1658. sizeof(ath9k_gstrings_stats));
  1659. }
  1660. static int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
  1661. struct ieee80211_vif *vif, int sset)
  1662. {
  1663. if (sset == ETH_SS_STATS)
  1664. return ATH9K_SSTATS_LEN;
  1665. return 0;
  1666. }
  1667. #define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum)
  1668. #define AWDATA(elem) \
  1669. do { \
  1670. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem; \
  1671. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem; \
  1672. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem; \
  1673. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem; \
  1674. } while (0)
  1675. #define AWDATA_RX(elem) \
  1676. do { \
  1677. data[i++] = sc->debug.stats.rxstats.elem; \
  1678. } while (0)
  1679. static void ath9k_get_et_stats(struct ieee80211_hw *hw,
  1680. struct ieee80211_vif *vif,
  1681. struct ethtool_stats *stats, u64 *data)
  1682. {
  1683. struct ath_softc *sc = hw->priv;
  1684. int i = 0;
  1685. data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_pkts_all +
  1686. sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_pkts_all +
  1687. sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_pkts_all +
  1688. sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_pkts_all);
  1689. data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_bytes_all +
  1690. sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_bytes_all +
  1691. sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_bytes_all +
  1692. sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_bytes_all);
  1693. AWDATA_RX(rx_pkts_all);
  1694. AWDATA_RX(rx_bytes_all);
  1695. AWDATA(tx_pkts_all);
  1696. AWDATA(tx_bytes_all);
  1697. AWDATA(queued);
  1698. AWDATA(completed);
  1699. AWDATA(xretries);
  1700. AWDATA(a_aggr);
  1701. AWDATA(a_queued_hw);
  1702. AWDATA(a_queued_sw);
  1703. AWDATA(a_completed);
  1704. AWDATA(a_retries);
  1705. AWDATA(a_xretries);
  1706. AWDATA(fifo_underrun);
  1707. AWDATA(xtxop);
  1708. AWDATA(timer_exp);
  1709. AWDATA(desc_cfg_err);
  1710. AWDATA(data_underrun);
  1711. AWDATA(delim_underrun);
  1712. AWDATA_RX(decrypt_crc_err);
  1713. AWDATA_RX(phy_err);
  1714. AWDATA_RX(mic_err);
  1715. AWDATA_RX(pre_delim_crc_err);
  1716. AWDATA_RX(post_delim_crc_err);
  1717. AWDATA_RX(decrypt_busy_err);
  1718. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]);
  1719. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]);
  1720. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]);
  1721. WARN_ON(i != ATH9K_SSTATS_LEN);
  1722. }
  1723. /* End of ethtool get-stats functions */
  1724. #endif
  1725. struct ieee80211_ops ath9k_ops = {
  1726. .tx = ath9k_tx,
  1727. .start = ath9k_start,
  1728. .stop = ath9k_stop,
  1729. .add_interface = ath9k_add_interface,
  1730. .change_interface = ath9k_change_interface,
  1731. .remove_interface = ath9k_remove_interface,
  1732. .config = ath9k_config,
  1733. .configure_filter = ath9k_configure_filter,
  1734. .sta_add = ath9k_sta_add,
  1735. .sta_remove = ath9k_sta_remove,
  1736. .sta_notify = ath9k_sta_notify,
  1737. .conf_tx = ath9k_conf_tx,
  1738. .bss_info_changed = ath9k_bss_info_changed,
  1739. .set_key = ath9k_set_key,
  1740. .get_tsf = ath9k_get_tsf,
  1741. .set_tsf = ath9k_set_tsf,
  1742. .reset_tsf = ath9k_reset_tsf,
  1743. .ampdu_action = ath9k_ampdu_action,
  1744. .get_survey = ath9k_get_survey,
  1745. .rfkill_poll = ath9k_rfkill_poll_state,
  1746. .set_coverage_class = ath9k_set_coverage_class,
  1747. .flush = ath9k_flush,
  1748. .tx_frames_pending = ath9k_tx_frames_pending,
  1749. .tx_last_beacon = ath9k_tx_last_beacon,
  1750. .get_stats = ath9k_get_stats,
  1751. .set_antenna = ath9k_set_antenna,
  1752. .get_antenna = ath9k_get_antenna,
  1753. #ifdef CONFIG_ATH9K_DEBUGFS
  1754. .get_et_sset_count = ath9k_get_et_sset_count,
  1755. .get_et_stats = ath9k_get_et_stats,
  1756. .get_et_strings = ath9k_get_et_strings,
  1757. #endif
  1758. };