setup.c 14 KB

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  1. /*
  2. * linux/arch/sh/boards/se/7724/setup.c
  3. *
  4. * Copyright (C) 2009 Renesas Solutions Corp.
  5. *
  6. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License. See the file "COPYING" in the main directory of this archive
  10. * for more details.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/device.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/mtd/physmap.h>
  17. #include <linux/delay.h>
  18. #include <linux/smc91x.h>
  19. #include <linux/gpio.h>
  20. #include <linux/input.h>
  21. #include <linux/usb/r8a66597.h>
  22. #include <video/sh_mobile_lcdc.h>
  23. #include <media/sh_mobile_ceu.h>
  24. #include <asm/io.h>
  25. #include <asm/heartbeat.h>
  26. #include <asm/sh_eth.h>
  27. #include <asm/clock.h>
  28. #include <asm/sh_keysc.h>
  29. #include <cpu/sh7724.h>
  30. #include <mach-se/mach/se7724.h>
  31. /*
  32. * SWx 1234 5678
  33. * ------------------------------------
  34. * SW31 : 1001 1100 : default
  35. * SW32 : 0111 1111 : use on board flash
  36. *
  37. * SW41 : abxx xxxx -> a = 0 : Analog monitor
  38. * 1 : Digital monitor
  39. * b = 0 : VGA
  40. * 1 : SVGA
  41. */
  42. /* Heartbeat */
  43. static struct heartbeat_data heartbeat_data = {
  44. .regsize = 16,
  45. };
  46. static struct resource heartbeat_resources[] = {
  47. [0] = {
  48. .start = PA_LED,
  49. .end = PA_LED,
  50. .flags = IORESOURCE_MEM,
  51. },
  52. };
  53. static struct platform_device heartbeat_device = {
  54. .name = "heartbeat",
  55. .id = -1,
  56. .dev = {
  57. .platform_data = &heartbeat_data,
  58. },
  59. .num_resources = ARRAY_SIZE(heartbeat_resources),
  60. .resource = heartbeat_resources,
  61. };
  62. /* LAN91C111 */
  63. static struct smc91x_platdata smc91x_info = {
  64. .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
  65. };
  66. static struct resource smc91x_eth_resources[] = {
  67. [0] = {
  68. .name = "SMC91C111" ,
  69. .start = 0x1a300300,
  70. .end = 0x1a30030f,
  71. .flags = IORESOURCE_MEM,
  72. },
  73. [1] = {
  74. .start = IRQ0_SMC,
  75. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  76. },
  77. };
  78. static struct platform_device smc91x_eth_device = {
  79. .name = "smc91x",
  80. .num_resources = ARRAY_SIZE(smc91x_eth_resources),
  81. .resource = smc91x_eth_resources,
  82. .dev = {
  83. .platform_data = &smc91x_info,
  84. },
  85. };
  86. /* MTD */
  87. static struct mtd_partition nor_flash_partitions[] = {
  88. {
  89. .name = "uboot",
  90. .offset = 0,
  91. .size = (1 * 1024 * 1024),
  92. .mask_flags = MTD_WRITEABLE, /* Read-only */
  93. }, {
  94. .name = "kernel",
  95. .offset = MTDPART_OFS_APPEND,
  96. .size = (2 * 1024 * 1024),
  97. }, {
  98. .name = "free-area",
  99. .offset = MTDPART_OFS_APPEND,
  100. .size = MTDPART_SIZ_FULL,
  101. },
  102. };
  103. static struct physmap_flash_data nor_flash_data = {
  104. .width = 2,
  105. .parts = nor_flash_partitions,
  106. .nr_parts = ARRAY_SIZE(nor_flash_partitions),
  107. };
  108. static struct resource nor_flash_resources[] = {
  109. [0] = {
  110. .name = "NOR Flash",
  111. .start = 0x00000000,
  112. .end = 0x01ffffff,
  113. .flags = IORESOURCE_MEM,
  114. }
  115. };
  116. static struct platform_device nor_flash_device = {
  117. .name = "physmap-flash",
  118. .resource = nor_flash_resources,
  119. .num_resources = ARRAY_SIZE(nor_flash_resources),
  120. .dev = {
  121. .platform_data = &nor_flash_data,
  122. },
  123. };
  124. /* LCDC */
  125. static struct sh_mobile_lcdc_info lcdc_info = {
  126. .clock_source = LCDC_CLK_EXTERNAL,
  127. .ch[0] = {
  128. .chan = LCDC_CHAN_MAINLCD,
  129. .bpp = 16,
  130. .clock_divider = 1,
  131. .lcd_cfg = {
  132. .name = "LB070WV1",
  133. .sync = 0, /* hsync and vsync are active low */
  134. },
  135. .lcd_size_cfg = { /* 7.0 inch */
  136. .width = 152,
  137. .height = 91,
  138. },
  139. .board_cfg = {
  140. },
  141. }
  142. };
  143. static struct resource lcdc_resources[] = {
  144. [0] = {
  145. .name = "LCDC",
  146. .start = 0xfe940000,
  147. .end = 0xfe941fff,
  148. .flags = IORESOURCE_MEM,
  149. },
  150. [1] = {
  151. .start = 106,
  152. .flags = IORESOURCE_IRQ,
  153. },
  154. };
  155. static struct platform_device lcdc_device = {
  156. .name = "sh_mobile_lcdc_fb",
  157. .num_resources = ARRAY_SIZE(lcdc_resources),
  158. .resource = lcdc_resources,
  159. .dev = {
  160. .platform_data = &lcdc_info,
  161. },
  162. };
  163. /* CEU0 */
  164. static struct sh_mobile_ceu_info sh_mobile_ceu0_info = {
  165. .flags = SH_CEU_FLAG_USE_8BIT_BUS,
  166. };
  167. static struct resource ceu0_resources[] = {
  168. [0] = {
  169. .name = "CEU0",
  170. .start = 0xfe910000,
  171. .end = 0xfe91009f,
  172. .flags = IORESOURCE_MEM,
  173. },
  174. [1] = {
  175. .start = 52,
  176. .flags = IORESOURCE_IRQ,
  177. },
  178. [2] = {
  179. /* place holder for contiguous memory */
  180. },
  181. };
  182. static struct platform_device ceu0_device = {
  183. .name = "sh_mobile_ceu",
  184. .id = 0, /* "ceu0" clock */
  185. .num_resources = ARRAY_SIZE(ceu0_resources),
  186. .resource = ceu0_resources,
  187. .dev = {
  188. .platform_data = &sh_mobile_ceu0_info,
  189. },
  190. };
  191. /* CEU1 */
  192. static struct sh_mobile_ceu_info sh_mobile_ceu1_info = {
  193. .flags = SH_CEU_FLAG_USE_8BIT_BUS,
  194. };
  195. static struct resource ceu1_resources[] = {
  196. [0] = {
  197. .name = "CEU1",
  198. .start = 0xfe914000,
  199. .end = 0xfe91409f,
  200. .flags = IORESOURCE_MEM,
  201. },
  202. [1] = {
  203. .start = 63,
  204. .flags = IORESOURCE_IRQ,
  205. },
  206. [2] = {
  207. /* place holder for contiguous memory */
  208. },
  209. };
  210. static struct platform_device ceu1_device = {
  211. .name = "sh_mobile_ceu",
  212. .id = 1, /* "ceu1" clock */
  213. .num_resources = ARRAY_SIZE(ceu1_resources),
  214. .resource = ceu1_resources,
  215. .dev = {
  216. .platform_data = &sh_mobile_ceu1_info,
  217. },
  218. };
  219. /* KEYSC */
  220. static struct sh_keysc_info keysc_info = {
  221. .mode = SH_KEYSC_MODE_1,
  222. .scan_timing = 10,
  223. .delay = 50,
  224. .keycodes = {
  225. KEY_1, KEY_2, KEY_3, KEY_4, KEY_5,
  226. KEY_6, KEY_7, KEY_8, KEY_9, KEY_A,
  227. KEY_B, KEY_C, KEY_D, KEY_E, KEY_F,
  228. KEY_G, KEY_H, KEY_I, KEY_K, KEY_L,
  229. KEY_M, KEY_N, KEY_O, KEY_P, KEY_Q,
  230. KEY_R, KEY_S, KEY_T, KEY_U, KEY_V,
  231. },
  232. };
  233. static struct resource keysc_resources[] = {
  234. [0] = {
  235. .start = 0x1a204000,
  236. .end = 0x1a20400f,
  237. .flags = IORESOURCE_MEM,
  238. },
  239. [1] = {
  240. .start = IRQ0_KEY,
  241. .flags = IORESOURCE_IRQ,
  242. },
  243. };
  244. static struct platform_device keysc_device = {
  245. .name = "sh_keysc",
  246. .id = 0, /* "keysc0" clock */
  247. .num_resources = ARRAY_SIZE(keysc_resources),
  248. .resource = keysc_resources,
  249. .dev = {
  250. .platform_data = &keysc_info,
  251. },
  252. };
  253. /* SH Eth */
  254. static struct resource sh_eth_resources[] = {
  255. [0] = {
  256. .start = SH_ETH_ADDR,
  257. .end = SH_ETH_ADDR + 0x1FC,
  258. .flags = IORESOURCE_MEM,
  259. },
  260. [1] = {
  261. .start = 91,
  262. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  263. },
  264. };
  265. struct sh_eth_plat_data sh_eth_plat = {
  266. .phy = 0x1f, /* SMSC LAN8187 */
  267. .edmac_endian = EDMAC_LITTLE_ENDIAN,
  268. };
  269. static struct platform_device sh_eth_device = {
  270. .name = "sh-eth",
  271. .id = 0,
  272. .dev = {
  273. .platform_data = &sh_eth_plat,
  274. },
  275. .num_resources = ARRAY_SIZE(sh_eth_resources),
  276. .resource = sh_eth_resources,
  277. };
  278. static struct r8a66597_platdata sh7724_usb0_host_data = {
  279. };
  280. static struct resource sh7724_usb0_host_resources[] = {
  281. [0] = {
  282. .start = 0xa4d80000,
  283. .end = 0xa4d800ff,
  284. .flags = IORESOURCE_MEM,
  285. },
  286. [1] = {
  287. .start = 65,
  288. .end = 65,
  289. .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
  290. },
  291. };
  292. static struct platform_device sh7724_usb0_host_device = {
  293. .name = "r8a66597_hcd",
  294. .id = 0,
  295. .dev = {
  296. .dma_mask = NULL, /* not use dma */
  297. .coherent_dma_mask = 0xffffffff,
  298. .platform_data = &sh7724_usb0_host_data,
  299. },
  300. .num_resources = ARRAY_SIZE(sh7724_usb0_host_resources),
  301. .resource = sh7724_usb0_host_resources,
  302. };
  303. static struct platform_device *ms7724se_devices[] __initdata = {
  304. &heartbeat_device,
  305. &smc91x_eth_device,
  306. &lcdc_device,
  307. &nor_flash_device,
  308. &ceu0_device,
  309. &ceu1_device,
  310. &keysc_device,
  311. &sh_eth_device,
  312. &sh7724_usb0_host_device,
  313. };
  314. #define EEPROM_OP 0xBA206000
  315. #define EEPROM_ADR 0xBA206004
  316. #define EEPROM_DATA 0xBA20600C
  317. #define EEPROM_STAT 0xBA206010
  318. #define EEPROM_STRT 0xBA206014
  319. static int __init sh_eth_is_eeprom_ready(void)
  320. {
  321. int t = 10000;
  322. while (t--) {
  323. if (!ctrl_inw(EEPROM_STAT))
  324. return 1;
  325. cpu_relax();
  326. }
  327. printk(KERN_ERR "ms7724se can not access to eeprom\n");
  328. return 0;
  329. }
  330. static void __init sh_eth_init(void)
  331. {
  332. int i;
  333. u16 mac[3];
  334. /* check EEPROM status */
  335. if (!sh_eth_is_eeprom_ready())
  336. return;
  337. /* read MAC addr from EEPROM */
  338. for (i = 0 ; i < 3 ; i++) {
  339. ctrl_outw(0x0, EEPROM_OP); /* read */
  340. ctrl_outw(i*2, EEPROM_ADR);
  341. ctrl_outw(0x1, EEPROM_STRT);
  342. if (!sh_eth_is_eeprom_ready())
  343. return;
  344. mac[i] = ctrl_inw(EEPROM_DATA);
  345. mac[i] = ((mac[i] & 0xFF) << 8) | (mac[i] >> 8); /* swap */
  346. }
  347. /* reset sh-eth */
  348. ctrl_outl(0x1, SH_ETH_ADDR + 0x0);
  349. /* set MAC addr */
  350. ctrl_outl(((mac[0] << 16) | (mac[1])), SH_ETH_MAHR);
  351. ctrl_outl((mac[2]), SH_ETH_MALR);
  352. }
  353. #define SW4140 0xBA201000
  354. #define FPGA_OUT 0xBA200400
  355. #define PORT_HIZA 0xA4050158
  356. #define PORT_MSELCRB 0xA4050182
  357. #define SW41_A 0x0100
  358. #define SW41_B 0x0200
  359. #define SW41_C 0x0400
  360. #define SW41_D 0x0800
  361. #define SW41_E 0x1000
  362. #define SW41_F 0x2000
  363. #define SW41_G 0x4000
  364. #define SW41_H 0x8000
  365. static int __init devices_setup(void)
  366. {
  367. u16 sw = ctrl_inw(SW4140); /* select camera, monitor */
  368. /* Reset Release */
  369. ctrl_outw(ctrl_inw(FPGA_OUT) &
  370. ~((1 << 1) | /* LAN */
  371. (1 << 6) | /* VIDEO DAC */
  372. (1 << 12) | /* USB0 */
  373. (1 << 14)), /* RMII */
  374. FPGA_OUT);
  375. /* turn on USB clocks, use external clock */
  376. ctrl_outw((ctrl_inw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
  377. /* enable USB0 port */
  378. ctrl_outw(0x0600, 0xa40501d4);
  379. /* enable IRQ 0,1,2 */
  380. gpio_request(GPIO_FN_INTC_IRQ0, NULL);
  381. gpio_request(GPIO_FN_INTC_IRQ1, NULL);
  382. gpio_request(GPIO_FN_INTC_IRQ2, NULL);
  383. /* enable SCIFA3 */
  384. gpio_request(GPIO_FN_SCIF3_I_SCK, NULL);
  385. gpio_request(GPIO_FN_SCIF3_I_RXD, NULL);
  386. gpio_request(GPIO_FN_SCIF3_I_TXD, NULL);
  387. gpio_request(GPIO_FN_SCIF3_I_CTS, NULL);
  388. gpio_request(GPIO_FN_SCIF3_I_RTS, NULL);
  389. /* enable LCDC */
  390. gpio_request(GPIO_FN_LCDD23, NULL);
  391. gpio_request(GPIO_FN_LCDD22, NULL);
  392. gpio_request(GPIO_FN_LCDD21, NULL);
  393. gpio_request(GPIO_FN_LCDD20, NULL);
  394. gpio_request(GPIO_FN_LCDD19, NULL);
  395. gpio_request(GPIO_FN_LCDD18, NULL);
  396. gpio_request(GPIO_FN_LCDD17, NULL);
  397. gpio_request(GPIO_FN_LCDD16, NULL);
  398. gpio_request(GPIO_FN_LCDD15, NULL);
  399. gpio_request(GPIO_FN_LCDD14, NULL);
  400. gpio_request(GPIO_FN_LCDD13, NULL);
  401. gpio_request(GPIO_FN_LCDD12, NULL);
  402. gpio_request(GPIO_FN_LCDD11, NULL);
  403. gpio_request(GPIO_FN_LCDD10, NULL);
  404. gpio_request(GPIO_FN_LCDD9, NULL);
  405. gpio_request(GPIO_FN_LCDD8, NULL);
  406. gpio_request(GPIO_FN_LCDD7, NULL);
  407. gpio_request(GPIO_FN_LCDD6, NULL);
  408. gpio_request(GPIO_FN_LCDD5, NULL);
  409. gpio_request(GPIO_FN_LCDD4, NULL);
  410. gpio_request(GPIO_FN_LCDD3, NULL);
  411. gpio_request(GPIO_FN_LCDD2, NULL);
  412. gpio_request(GPIO_FN_LCDD1, NULL);
  413. gpio_request(GPIO_FN_LCDD0, NULL);
  414. gpio_request(GPIO_FN_LCDDISP, NULL);
  415. gpio_request(GPIO_FN_LCDHSYN, NULL);
  416. gpio_request(GPIO_FN_LCDDCK, NULL);
  417. gpio_request(GPIO_FN_LCDVSYN, NULL);
  418. gpio_request(GPIO_FN_LCDDON, NULL);
  419. gpio_request(GPIO_FN_LCDVEPWC, NULL);
  420. gpio_request(GPIO_FN_LCDVCPWC, NULL);
  421. gpio_request(GPIO_FN_LCDRD, NULL);
  422. gpio_request(GPIO_FN_LCDLCLK, NULL);
  423. ctrl_outw((ctrl_inw(PORT_HIZA) & ~0x0001), PORT_HIZA);
  424. /* enable CEU0 */
  425. gpio_request(GPIO_FN_VIO0_D15, NULL);
  426. gpio_request(GPIO_FN_VIO0_D14, NULL);
  427. gpio_request(GPIO_FN_VIO0_D13, NULL);
  428. gpio_request(GPIO_FN_VIO0_D12, NULL);
  429. gpio_request(GPIO_FN_VIO0_D11, NULL);
  430. gpio_request(GPIO_FN_VIO0_D10, NULL);
  431. gpio_request(GPIO_FN_VIO0_D9, NULL);
  432. gpio_request(GPIO_FN_VIO0_D8, NULL);
  433. gpio_request(GPIO_FN_VIO0_D7, NULL);
  434. gpio_request(GPIO_FN_VIO0_D6, NULL);
  435. gpio_request(GPIO_FN_VIO0_D5, NULL);
  436. gpio_request(GPIO_FN_VIO0_D4, NULL);
  437. gpio_request(GPIO_FN_VIO0_D3, NULL);
  438. gpio_request(GPIO_FN_VIO0_D2, NULL);
  439. gpio_request(GPIO_FN_VIO0_D1, NULL);
  440. gpio_request(GPIO_FN_VIO0_D0, NULL);
  441. gpio_request(GPIO_FN_VIO0_VD, NULL);
  442. gpio_request(GPIO_FN_VIO0_CLK, NULL);
  443. gpio_request(GPIO_FN_VIO0_FLD, NULL);
  444. gpio_request(GPIO_FN_VIO0_HD, NULL);
  445. platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20);
  446. /* enable CEU1 */
  447. gpio_request(GPIO_FN_VIO1_D7, NULL);
  448. gpio_request(GPIO_FN_VIO1_D6, NULL);
  449. gpio_request(GPIO_FN_VIO1_D5, NULL);
  450. gpio_request(GPIO_FN_VIO1_D4, NULL);
  451. gpio_request(GPIO_FN_VIO1_D3, NULL);
  452. gpio_request(GPIO_FN_VIO1_D2, NULL);
  453. gpio_request(GPIO_FN_VIO1_D1, NULL);
  454. gpio_request(GPIO_FN_VIO1_D0, NULL);
  455. gpio_request(GPIO_FN_VIO1_FLD, NULL);
  456. gpio_request(GPIO_FN_VIO1_HD, NULL);
  457. gpio_request(GPIO_FN_VIO1_VD, NULL);
  458. gpio_request(GPIO_FN_VIO1_CLK, NULL);
  459. platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20);
  460. /* KEYSC */
  461. gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
  462. gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
  463. gpio_request(GPIO_FN_KEYIN4, NULL);
  464. gpio_request(GPIO_FN_KEYIN3, NULL);
  465. gpio_request(GPIO_FN_KEYIN2, NULL);
  466. gpio_request(GPIO_FN_KEYIN1, NULL);
  467. gpio_request(GPIO_FN_KEYIN0, NULL);
  468. gpio_request(GPIO_FN_KEYOUT3, NULL);
  469. gpio_request(GPIO_FN_KEYOUT2, NULL);
  470. gpio_request(GPIO_FN_KEYOUT1, NULL);
  471. gpio_request(GPIO_FN_KEYOUT0, NULL);
  472. /*
  473. * enable SH-Eth
  474. *
  475. * please remove J33 pin from your board !!
  476. *
  477. * ms7724 board should not use GPIO_FN_LNKSTA pin
  478. * So, This time PTX5 is set to input pin
  479. */
  480. gpio_request(GPIO_FN_RMII_RXD0, NULL);
  481. gpio_request(GPIO_FN_RMII_RXD1, NULL);
  482. gpio_request(GPIO_FN_RMII_TXD0, NULL);
  483. gpio_request(GPIO_FN_RMII_TXD1, NULL);
  484. gpio_request(GPIO_FN_RMII_REF_CLK, NULL);
  485. gpio_request(GPIO_FN_RMII_TX_EN, NULL);
  486. gpio_request(GPIO_FN_RMII_RX_ER, NULL);
  487. gpio_request(GPIO_FN_RMII_CRS_DV, NULL);
  488. gpio_request(GPIO_FN_MDIO, NULL);
  489. gpio_request(GPIO_FN_MDC, NULL);
  490. gpio_request(GPIO_PTX5, NULL);
  491. gpio_direction_input(GPIO_PTX5);
  492. sh_eth_init();
  493. if (sw & SW41_B) {
  494. /* SVGA */
  495. lcdc_info.ch[0].lcd_cfg.xres = 800;
  496. lcdc_info.ch[0].lcd_cfg.yres = 600;
  497. lcdc_info.ch[0].lcd_cfg.left_margin = 142;
  498. lcdc_info.ch[0].lcd_cfg.right_margin = 52;
  499. lcdc_info.ch[0].lcd_cfg.hsync_len = 96;
  500. lcdc_info.ch[0].lcd_cfg.upper_margin = 24;
  501. lcdc_info.ch[0].lcd_cfg.lower_margin = 2;
  502. lcdc_info.ch[0].lcd_cfg.vsync_len = 2;
  503. } else {
  504. /* VGA */
  505. lcdc_info.ch[0].lcd_cfg.xres = 640;
  506. lcdc_info.ch[0].lcd_cfg.yres = 480;
  507. lcdc_info.ch[0].lcd_cfg.left_margin = 105;
  508. lcdc_info.ch[0].lcd_cfg.right_margin = 50;
  509. lcdc_info.ch[0].lcd_cfg.hsync_len = 96;
  510. lcdc_info.ch[0].lcd_cfg.upper_margin = 33;
  511. lcdc_info.ch[0].lcd_cfg.lower_margin = 10;
  512. lcdc_info.ch[0].lcd_cfg.vsync_len = 2;
  513. }
  514. if (sw & SW41_A) {
  515. /* Digital monitor */
  516. lcdc_info.ch[0].interface_type = RGB18;
  517. lcdc_info.ch[0].flags = 0;
  518. } else {
  519. /* Analog monitor */
  520. lcdc_info.ch[0].interface_type = RGB24;
  521. lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
  522. }
  523. return platform_add_devices(ms7724se_devices,
  524. ARRAY_SIZE(ms7724se_devices));
  525. }
  526. device_initcall(devices_setup);
  527. static struct sh_machine_vector mv_ms7724se __initmv = {
  528. .mv_name = "ms7724se",
  529. .mv_init_irq = init_se7724_IRQ,
  530. .mv_nr_irqs = SE7724_FPGA_IRQ_BASE + SE7724_FPGA_IRQ_NR,
  531. };