mmu_context.h 3.2 KB

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  1. /*
  2. * arch/arm/include/asm/mmu_context.h
  3. *
  4. * Copyright (C) 1996 Russell King.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Changelog:
  11. * 27-06-1996 RMK Created
  12. */
  13. #ifndef __ASM_ARM_MMU_CONTEXT_H
  14. #define __ASM_ARM_MMU_CONTEXT_H
  15. #include <linux/compiler.h>
  16. #include <linux/sched.h>
  17. #include <asm/cacheflush.h>
  18. #include <asm/cachetype.h>
  19. #include <asm/proc-fns.h>
  20. #include <asm/smp_plat.h>
  21. #include <asm-generic/mm_hooks.h>
  22. void __check_vmalloc_seq(struct mm_struct *mm);
  23. #ifdef CONFIG_CPU_HAS_ASID
  24. void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk);
  25. #define init_new_context(tsk,mm) ({ atomic64_set(&mm->context.id, 0); 0; })
  26. DECLARE_PER_CPU(atomic64_t, active_asids);
  27. #else /* !CONFIG_CPU_HAS_ASID */
  28. #ifdef CONFIG_MMU
  29. static inline void check_and_switch_context(struct mm_struct *mm,
  30. struct task_struct *tsk)
  31. {
  32. if (unlikely(mm->context.vmalloc_seq != init_mm.context.vmalloc_seq))
  33. __check_vmalloc_seq(mm);
  34. if (irqs_disabled())
  35. /*
  36. * cpu_switch_mm() needs to flush the VIVT caches. To avoid
  37. * high interrupt latencies, defer the call and continue
  38. * running with the old mm. Since we only support UP systems
  39. * on non-ASID CPUs, the old mm will remain valid until the
  40. * finish_arch_post_lock_switch() call.
  41. */
  42. set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM);
  43. else
  44. cpu_switch_mm(mm->pgd, mm);
  45. }
  46. #define finish_arch_post_lock_switch \
  47. finish_arch_post_lock_switch
  48. static inline void finish_arch_post_lock_switch(void)
  49. {
  50. if (test_and_clear_thread_flag(TIF_SWITCH_MM)) {
  51. struct mm_struct *mm = current->mm;
  52. cpu_switch_mm(mm->pgd, mm);
  53. }
  54. }
  55. #endif /* CONFIG_MMU */
  56. #define init_new_context(tsk,mm) 0
  57. #endif /* CONFIG_CPU_HAS_ASID */
  58. #define destroy_context(mm) do { } while(0)
  59. #define activate_mm(prev,next) switch_mm(prev, next, NULL)
  60. /*
  61. * This is called when "tsk" is about to enter lazy TLB mode.
  62. *
  63. * mm: describes the currently active mm context
  64. * tsk: task which is entering lazy tlb
  65. * cpu: cpu number which is entering lazy tlb
  66. *
  67. * tsk->mm will be NULL
  68. */
  69. static inline void
  70. enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
  71. {
  72. }
  73. /*
  74. * This is the actual mm switch as far as the scheduler
  75. * is concerned. No registers are touched. We avoid
  76. * calling the CPU specific function when the mm hasn't
  77. * actually changed.
  78. */
  79. static inline void
  80. switch_mm(struct mm_struct *prev, struct mm_struct *next,
  81. struct task_struct *tsk)
  82. {
  83. #ifdef CONFIG_MMU
  84. unsigned int cpu = smp_processor_id();
  85. /*
  86. * __sync_icache_dcache doesn't broadcast the I-cache invalidation,
  87. * so check for possible thread migration and invalidate the I-cache
  88. * if we're new to this CPU.
  89. */
  90. if (cache_ops_need_broadcast() &&
  91. !cpumask_empty(mm_cpumask(next)) &&
  92. !cpumask_test_cpu(cpu, mm_cpumask(next)))
  93. __flush_icache_all();
  94. if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) {
  95. check_and_switch_context(next, tsk);
  96. if (cache_is_vivt())
  97. cpumask_clear_cpu(cpu, mm_cpumask(prev));
  98. }
  99. #endif
  100. }
  101. #define deactivate_mm(tsk,mm) do { } while (0)
  102. #endif