cpsw-phy-sel.c 4.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161
  1. /* Texas Instruments Ethernet Switch Driver
  2. *
  3. * Copyright (C) 2013 Texas Instruments
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * version 2 as published by the Free Software Foundation.
  8. *
  9. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  10. * kind, whether express or implied; without even the implied warranty
  11. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. */
  14. #include <linux/platform_device.h>
  15. #include <linux/module.h>
  16. #include <linux/netdevice.h>
  17. #include <linux/phy.h>
  18. #include <linux/of.h>
  19. #include <linux/of_device.h>
  20. #include "cpsw.h"
  21. /* AM33xx SoC specific definitions for the CONTROL port */
  22. #define AM33XX_GMII_SEL_MODE_MII 0
  23. #define AM33XX_GMII_SEL_MODE_RMII 1
  24. #define AM33XX_GMII_SEL_MODE_RGMII 2
  25. #define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7)
  26. #define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6)
  27. struct cpsw_phy_sel_priv {
  28. struct device *dev;
  29. u32 __iomem *gmii_sel;
  30. bool rmii_clock_external;
  31. void (*cpsw_phy_sel)(struct cpsw_phy_sel_priv *priv,
  32. phy_interface_t phy_mode, int slave);
  33. };
  34. static void cpsw_gmii_sel_am3352(struct cpsw_phy_sel_priv *priv,
  35. phy_interface_t phy_mode, int slave)
  36. {
  37. u32 reg;
  38. u32 mask;
  39. u32 mode = 0;
  40. reg = readl(priv->gmii_sel);
  41. switch (phy_mode) {
  42. case PHY_INTERFACE_MODE_RMII:
  43. mode = AM33XX_GMII_SEL_MODE_RMII;
  44. break;
  45. case PHY_INTERFACE_MODE_RGMII:
  46. case PHY_INTERFACE_MODE_RGMII_ID:
  47. case PHY_INTERFACE_MODE_RGMII_RXID:
  48. case PHY_INTERFACE_MODE_RGMII_TXID:
  49. mode = AM33XX_GMII_SEL_MODE_RGMII;
  50. break;
  51. case PHY_INTERFACE_MODE_MII:
  52. default:
  53. mode = AM33XX_GMII_SEL_MODE_MII;
  54. break;
  55. };
  56. mask = 0x3 << (slave * 2) | BIT(slave + 6);
  57. mode <<= slave * 2;
  58. if (priv->rmii_clock_external) {
  59. if (slave == 0)
  60. mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN;
  61. else
  62. mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN;
  63. }
  64. reg &= ~mask;
  65. reg |= mode;
  66. writel(reg, priv->gmii_sel);
  67. }
  68. static struct platform_driver cpsw_phy_sel_driver;
  69. static int match(struct device *dev, void *data)
  70. {
  71. struct device_node *node = (struct device_node *)data;
  72. return dev->of_node == node &&
  73. dev->driver == &cpsw_phy_sel_driver.driver;
  74. }
  75. void cpsw_phy_sel(struct device *dev, phy_interface_t phy_mode, int slave)
  76. {
  77. struct device_node *node;
  78. struct cpsw_phy_sel_priv *priv;
  79. node = of_get_child_by_name(dev->of_node, "cpsw-phy-sel");
  80. if (!node) {
  81. dev_err(dev, "Phy mode driver DT not found\n");
  82. return;
  83. }
  84. dev = bus_find_device(&platform_bus_type, NULL, node, match);
  85. priv = dev_get_drvdata(dev);
  86. priv->cpsw_phy_sel(priv, phy_mode, slave);
  87. }
  88. EXPORT_SYMBOL_GPL(cpsw_phy_sel);
  89. static const struct of_device_id cpsw_phy_sel_id_table[] = {
  90. {
  91. .compatible = "ti,am3352-cpsw-phy-sel",
  92. .data = &cpsw_gmii_sel_am3352,
  93. },
  94. {}
  95. };
  96. MODULE_DEVICE_TABLE(of, cpsw_phy_sel_id_table);
  97. static int cpsw_phy_sel_probe(struct platform_device *pdev)
  98. {
  99. struct resource *res;
  100. const struct of_device_id *of_id;
  101. struct cpsw_phy_sel_priv *priv;
  102. of_id = of_match_node(cpsw_phy_sel_id_table, pdev->dev.of_node);
  103. if (!of_id)
  104. return -EINVAL;
  105. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  106. if (!priv) {
  107. dev_err(&pdev->dev, "unable to alloc memory for cpsw phy sel\n");
  108. return -ENOMEM;
  109. }
  110. priv->cpsw_phy_sel = of_id->data;
  111. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gmii-sel");
  112. priv->gmii_sel = devm_ioremap_resource(&pdev->dev, res);
  113. if (IS_ERR(priv->gmii_sel))
  114. return PTR_ERR(priv->gmii_sel);
  115. if (of_find_property(pdev->dev.of_node, "rmii-clock-ext", NULL))
  116. priv->rmii_clock_external = true;
  117. dev_set_drvdata(&pdev->dev, priv);
  118. return 0;
  119. }
  120. static struct platform_driver cpsw_phy_sel_driver = {
  121. .probe = cpsw_phy_sel_probe,
  122. .driver = {
  123. .name = "cpsw-phy-sel",
  124. .owner = THIS_MODULE,
  125. .of_match_table = of_match_ptr(cpsw_phy_sel_id_table),
  126. },
  127. };
  128. module_platform_driver(cpsw_phy_sel_driver);
  129. MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
  130. MODULE_LICENSE("GPL v2");