main.c 26 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162
  1. /*
  2. * Sonics Silicon Backplane
  3. * Subsystem core
  4. *
  5. * Copyright 2005, Broadcom Corporation
  6. * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
  7. *
  8. * Licensed under the GNU/GPL. See COPYING for details.
  9. */
  10. #include "ssb_private.h"
  11. #include <linux/delay.h>
  12. #include <linux/ssb/ssb.h>
  13. #include <linux/ssb/ssb_regs.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/pci.h>
  16. #include <pcmcia/cs_types.h>
  17. #include <pcmcia/cs.h>
  18. #include <pcmcia/cistpl.h>
  19. #include <pcmcia/ds.h>
  20. MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
  21. MODULE_LICENSE("GPL");
  22. /* Temporary list of yet-to-be-attached buses */
  23. static LIST_HEAD(attach_queue);
  24. /* List if running buses */
  25. static LIST_HEAD(buses);
  26. /* Software ID counter */
  27. static unsigned int next_busnumber;
  28. /* buses_mutes locks the two buslists and the next_busnumber.
  29. * Don't lock this directly, but use ssb_buses_[un]lock() below. */
  30. static DEFINE_MUTEX(buses_mutex);
  31. /* There are differences in the codeflow, if the bus is
  32. * initialized from early boot, as various needed services
  33. * are not available early. This is a mechanism to delay
  34. * these initializations to after early boot has finished.
  35. * It's also used to avoid mutex locking, as that's not
  36. * available and needed early. */
  37. static bool ssb_is_early_boot = 1;
  38. static void ssb_buses_lock(void);
  39. static void ssb_buses_unlock(void);
  40. #ifdef CONFIG_SSB_PCIHOST
  41. struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev)
  42. {
  43. struct ssb_bus *bus;
  44. ssb_buses_lock();
  45. list_for_each_entry(bus, &buses, list) {
  46. if (bus->bustype == SSB_BUSTYPE_PCI &&
  47. bus->host_pci == pdev)
  48. goto found;
  49. }
  50. bus = NULL;
  51. found:
  52. ssb_buses_unlock();
  53. return bus;
  54. }
  55. #endif /* CONFIG_SSB_PCIHOST */
  56. static struct ssb_device *ssb_device_get(struct ssb_device *dev)
  57. {
  58. if (dev)
  59. get_device(dev->dev);
  60. return dev;
  61. }
  62. static void ssb_device_put(struct ssb_device *dev)
  63. {
  64. if (dev)
  65. put_device(dev->dev);
  66. }
  67. static int ssb_bus_resume(struct ssb_bus *bus)
  68. {
  69. int err;
  70. ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
  71. err = ssb_pcmcia_init(bus);
  72. if (err) {
  73. /* No need to disable XTAL, as we don't have one on PCMCIA. */
  74. return err;
  75. }
  76. ssb_chipco_resume(&bus->chipco);
  77. return 0;
  78. }
  79. static int ssb_device_resume(struct device *dev)
  80. {
  81. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  82. struct ssb_driver *ssb_drv;
  83. struct ssb_bus *bus;
  84. int err = 0;
  85. bus = ssb_dev->bus;
  86. if (bus->suspend_cnt == bus->nr_devices) {
  87. err = ssb_bus_resume(bus);
  88. if (err)
  89. return err;
  90. }
  91. bus->suspend_cnt--;
  92. if (dev->driver) {
  93. ssb_drv = drv_to_ssb_drv(dev->driver);
  94. if (ssb_drv && ssb_drv->resume)
  95. err = ssb_drv->resume(ssb_dev);
  96. if (err)
  97. goto out;
  98. }
  99. out:
  100. return err;
  101. }
  102. static void ssb_bus_suspend(struct ssb_bus *bus, pm_message_t state)
  103. {
  104. ssb_chipco_suspend(&bus->chipco, state);
  105. ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  106. /* Reset HW state information in memory, so that HW is
  107. * completely reinitialized on resume. */
  108. bus->mapped_device = NULL;
  109. #ifdef CONFIG_SSB_DRIVER_PCICORE
  110. bus->pcicore.setup_done = 0;
  111. #endif
  112. #ifdef CONFIG_SSB_DEBUG
  113. bus->powered_up = 0;
  114. #endif
  115. }
  116. static int ssb_device_suspend(struct device *dev, pm_message_t state)
  117. {
  118. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  119. struct ssb_driver *ssb_drv;
  120. struct ssb_bus *bus;
  121. int err = 0;
  122. if (dev->driver) {
  123. ssb_drv = drv_to_ssb_drv(dev->driver);
  124. if (ssb_drv && ssb_drv->suspend)
  125. err = ssb_drv->suspend(ssb_dev, state);
  126. if (err)
  127. goto out;
  128. }
  129. bus = ssb_dev->bus;
  130. bus->suspend_cnt++;
  131. if (bus->suspend_cnt == bus->nr_devices) {
  132. /* All devices suspended. Shutdown the bus. */
  133. ssb_bus_suspend(bus, state);
  134. }
  135. out:
  136. return err;
  137. }
  138. #ifdef CONFIG_SSB_PCIHOST
  139. int ssb_devices_freeze(struct ssb_bus *bus)
  140. {
  141. struct ssb_device *dev;
  142. struct ssb_driver *drv;
  143. int err = 0;
  144. int i;
  145. pm_message_t state = PMSG_FREEZE;
  146. /* First check that we are capable to freeze all devices. */
  147. for (i = 0; i < bus->nr_devices; i++) {
  148. dev = &(bus->devices[i]);
  149. if (!dev->dev ||
  150. !dev->dev->driver ||
  151. !device_is_registered(dev->dev))
  152. continue;
  153. drv = drv_to_ssb_drv(dev->dev->driver);
  154. if (!drv)
  155. continue;
  156. if (!drv->suspend) {
  157. /* Nope, can't suspend this one. */
  158. return -EOPNOTSUPP;
  159. }
  160. }
  161. /* Now suspend all devices */
  162. for (i = 0; i < bus->nr_devices; i++) {
  163. dev = &(bus->devices[i]);
  164. if (!dev->dev ||
  165. !dev->dev->driver ||
  166. !device_is_registered(dev->dev))
  167. continue;
  168. drv = drv_to_ssb_drv(dev->dev->driver);
  169. if (!drv)
  170. continue;
  171. err = drv->suspend(dev, state);
  172. if (err) {
  173. ssb_printk(KERN_ERR PFX "Failed to freeze device %s\n",
  174. dev->dev->bus_id);
  175. goto err_unwind;
  176. }
  177. }
  178. return 0;
  179. err_unwind:
  180. for (i--; i >= 0; i--) {
  181. dev = &(bus->devices[i]);
  182. if (!dev->dev ||
  183. !dev->dev->driver ||
  184. !device_is_registered(dev->dev))
  185. continue;
  186. drv = drv_to_ssb_drv(dev->dev->driver);
  187. if (!drv)
  188. continue;
  189. if (drv->resume)
  190. drv->resume(dev);
  191. }
  192. return err;
  193. }
  194. int ssb_devices_thaw(struct ssb_bus *bus)
  195. {
  196. struct ssb_device *dev;
  197. struct ssb_driver *drv;
  198. int err;
  199. int i;
  200. for (i = 0; i < bus->nr_devices; i++) {
  201. dev = &(bus->devices[i]);
  202. if (!dev->dev ||
  203. !dev->dev->driver ||
  204. !device_is_registered(dev->dev))
  205. continue;
  206. drv = drv_to_ssb_drv(dev->dev->driver);
  207. if (!drv)
  208. continue;
  209. if (SSB_WARN_ON(!drv->resume))
  210. continue;
  211. err = drv->resume(dev);
  212. if (err) {
  213. ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
  214. dev->dev->bus_id);
  215. }
  216. }
  217. return 0;
  218. }
  219. #endif /* CONFIG_SSB_PCIHOST */
  220. static void ssb_device_shutdown(struct device *dev)
  221. {
  222. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  223. struct ssb_driver *ssb_drv;
  224. if (!dev->driver)
  225. return;
  226. ssb_drv = drv_to_ssb_drv(dev->driver);
  227. if (ssb_drv && ssb_drv->shutdown)
  228. ssb_drv->shutdown(ssb_dev);
  229. }
  230. static int ssb_device_remove(struct device *dev)
  231. {
  232. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  233. struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
  234. if (ssb_drv && ssb_drv->remove)
  235. ssb_drv->remove(ssb_dev);
  236. ssb_device_put(ssb_dev);
  237. return 0;
  238. }
  239. static int ssb_device_probe(struct device *dev)
  240. {
  241. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  242. struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
  243. int err = 0;
  244. ssb_device_get(ssb_dev);
  245. if (ssb_drv && ssb_drv->probe)
  246. err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
  247. if (err)
  248. ssb_device_put(ssb_dev);
  249. return err;
  250. }
  251. static int ssb_match_devid(const struct ssb_device_id *tabid,
  252. const struct ssb_device_id *devid)
  253. {
  254. if ((tabid->vendor != devid->vendor) &&
  255. tabid->vendor != SSB_ANY_VENDOR)
  256. return 0;
  257. if ((tabid->coreid != devid->coreid) &&
  258. tabid->coreid != SSB_ANY_ID)
  259. return 0;
  260. if ((tabid->revision != devid->revision) &&
  261. tabid->revision != SSB_ANY_REV)
  262. return 0;
  263. return 1;
  264. }
  265. static int ssb_bus_match(struct device *dev, struct device_driver *drv)
  266. {
  267. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  268. struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
  269. const struct ssb_device_id *id;
  270. for (id = ssb_drv->id_table;
  271. id->vendor || id->coreid || id->revision;
  272. id++) {
  273. if (ssb_match_devid(id, &ssb_dev->id))
  274. return 1; /* found */
  275. }
  276. return 0;
  277. }
  278. static int ssb_device_uevent(struct device *dev, char **envp, int num_envp,
  279. char *buffer, int buffer_size)
  280. {
  281. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  282. int ret, i = 0, length = 0;
  283. if (!dev)
  284. return -ENODEV;
  285. ret = add_uevent_var(envp, num_envp, &i,
  286. buffer, buffer_size, &length,
  287. "MODALIAS=ssb:v%04Xid%04Xrev%02X",
  288. ssb_dev->id.vendor, ssb_dev->id.coreid,
  289. ssb_dev->id.revision);
  290. envp[i] = NULL;
  291. return ret;
  292. }
  293. static struct bus_type ssb_bustype = {
  294. .name = "ssb",
  295. .match = ssb_bus_match,
  296. .probe = ssb_device_probe,
  297. .remove = ssb_device_remove,
  298. .shutdown = ssb_device_shutdown,
  299. .suspend = ssb_device_suspend,
  300. .resume = ssb_device_resume,
  301. .uevent = ssb_device_uevent,
  302. };
  303. static void ssb_buses_lock(void)
  304. {
  305. /* See the comment at the ssb_is_early_boot definition */
  306. if (!ssb_is_early_boot)
  307. mutex_lock(&buses_mutex);
  308. }
  309. static void ssb_buses_unlock(void)
  310. {
  311. /* See the comment at the ssb_is_early_boot definition */
  312. if (!ssb_is_early_boot)
  313. mutex_unlock(&buses_mutex);
  314. }
  315. static void ssb_devices_unregister(struct ssb_bus *bus)
  316. {
  317. struct ssb_device *sdev;
  318. int i;
  319. for (i = bus->nr_devices - 1; i >= 0; i--) {
  320. sdev = &(bus->devices[i]);
  321. if (sdev->dev)
  322. device_unregister(sdev->dev);
  323. }
  324. }
  325. void ssb_bus_unregister(struct ssb_bus *bus)
  326. {
  327. ssb_buses_lock();
  328. ssb_devices_unregister(bus);
  329. list_del(&bus->list);
  330. ssb_buses_unlock();
  331. /* ssb_pcmcia_exit(bus); */
  332. ssb_pci_exit(bus);
  333. ssb_iounmap(bus);
  334. }
  335. EXPORT_SYMBOL(ssb_bus_unregister);
  336. static void ssb_release_dev(struct device *dev)
  337. {
  338. struct __ssb_dev_wrapper *devwrap;
  339. devwrap = container_of(dev, struct __ssb_dev_wrapper, dev);
  340. kfree(devwrap);
  341. }
  342. static int ssb_devices_register(struct ssb_bus *bus)
  343. {
  344. struct ssb_device *sdev;
  345. struct device *dev;
  346. struct __ssb_dev_wrapper *devwrap;
  347. int i, err = 0;
  348. int dev_idx = 0;
  349. for (i = 0; i < bus->nr_devices; i++) {
  350. sdev = &(bus->devices[i]);
  351. /* We don't register SSB-system devices to the kernel,
  352. * as the drivers for them are built into SSB. */
  353. switch (sdev->id.coreid) {
  354. case SSB_DEV_CHIPCOMMON:
  355. case SSB_DEV_PCI:
  356. case SSB_DEV_PCIE:
  357. case SSB_DEV_PCMCIA:
  358. case SSB_DEV_MIPS:
  359. case SSB_DEV_MIPS_3302:
  360. case SSB_DEV_EXTIF:
  361. continue;
  362. }
  363. devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
  364. if (!devwrap) {
  365. ssb_printk(KERN_ERR PFX
  366. "Could not allocate device\n");
  367. err = -ENOMEM;
  368. goto error;
  369. }
  370. dev = &devwrap->dev;
  371. devwrap->sdev = sdev;
  372. dev->release = ssb_release_dev;
  373. dev->bus = &ssb_bustype;
  374. snprintf(dev->bus_id, sizeof(dev->bus_id),
  375. "ssb%u:%d", bus->busnumber, dev_idx);
  376. switch (bus->bustype) {
  377. case SSB_BUSTYPE_PCI:
  378. #ifdef CONFIG_SSB_PCIHOST
  379. sdev->irq = bus->host_pci->irq;
  380. dev->parent = &bus->host_pci->dev;
  381. #endif
  382. break;
  383. case SSB_BUSTYPE_PCMCIA:
  384. #ifdef CONFIG_SSB_PCMCIAHOST
  385. dev->parent = &bus->host_pcmcia->dev;
  386. #endif
  387. break;
  388. case SSB_BUSTYPE_SSB:
  389. break;
  390. }
  391. sdev->dev = dev;
  392. err = device_register(dev);
  393. if (err) {
  394. ssb_printk(KERN_ERR PFX
  395. "Could not register %s\n",
  396. dev->bus_id);
  397. /* Set dev to NULL to not unregister
  398. * dev on error unwinding. */
  399. sdev->dev = NULL;
  400. kfree(devwrap);
  401. goto error;
  402. }
  403. dev_idx++;
  404. }
  405. return 0;
  406. error:
  407. /* Unwind the already registered devices. */
  408. ssb_devices_unregister(bus);
  409. return err;
  410. }
  411. /* Needs ssb_buses_lock() */
  412. static int ssb_attach_queued_buses(void)
  413. {
  414. struct ssb_bus *bus, *n;
  415. int err = 0;
  416. int drop_them_all = 0;
  417. list_for_each_entry_safe(bus, n, &attach_queue, list) {
  418. if (drop_them_all) {
  419. list_del(&bus->list);
  420. continue;
  421. }
  422. /* Can't init the PCIcore in ssb_bus_register(), as that
  423. * is too early in boot for embedded systems
  424. * (no udelay() available). So do it here in attach stage.
  425. */
  426. err = ssb_bus_powerup(bus, 0);
  427. if (err)
  428. goto error;
  429. ssb_pcicore_init(&bus->pcicore);
  430. ssb_bus_may_powerdown(bus);
  431. err = ssb_devices_register(bus);
  432. error:
  433. if (err) {
  434. drop_them_all = 1;
  435. list_del(&bus->list);
  436. continue;
  437. }
  438. list_move_tail(&bus->list, &buses);
  439. }
  440. return err;
  441. }
  442. static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
  443. {
  444. struct ssb_bus *bus = dev->bus;
  445. offset += dev->core_index * SSB_CORE_SIZE;
  446. return readw(bus->mmio + offset);
  447. }
  448. static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset)
  449. {
  450. struct ssb_bus *bus = dev->bus;
  451. offset += dev->core_index * SSB_CORE_SIZE;
  452. return readl(bus->mmio + offset);
  453. }
  454. static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
  455. {
  456. struct ssb_bus *bus = dev->bus;
  457. offset += dev->core_index * SSB_CORE_SIZE;
  458. writew(value, bus->mmio + offset);
  459. }
  460. static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
  461. {
  462. struct ssb_bus *bus = dev->bus;
  463. offset += dev->core_index * SSB_CORE_SIZE;
  464. writel(value, bus->mmio + offset);
  465. }
  466. /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
  467. static const struct ssb_bus_ops ssb_ssb_ops = {
  468. .read16 = ssb_ssb_read16,
  469. .read32 = ssb_ssb_read32,
  470. .write16 = ssb_ssb_write16,
  471. .write32 = ssb_ssb_write32,
  472. };
  473. static int ssb_fetch_invariants(struct ssb_bus *bus,
  474. ssb_invariants_func_t get_invariants)
  475. {
  476. struct ssb_init_invariants iv;
  477. int err;
  478. memset(&iv, 0, sizeof(iv));
  479. err = get_invariants(bus, &iv);
  480. if (err)
  481. goto out;
  482. memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
  483. memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
  484. out:
  485. return err;
  486. }
  487. static int ssb_bus_register(struct ssb_bus *bus,
  488. ssb_invariants_func_t get_invariants,
  489. unsigned long baseaddr)
  490. {
  491. int err;
  492. spin_lock_init(&bus->bar_lock);
  493. INIT_LIST_HEAD(&bus->list);
  494. /* Powerup the bus */
  495. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
  496. if (err)
  497. goto out;
  498. ssb_buses_lock();
  499. bus->busnumber = next_busnumber;
  500. /* Scan for devices (cores) */
  501. err = ssb_bus_scan(bus, baseaddr);
  502. if (err)
  503. goto err_disable_xtal;
  504. /* Init PCI-host device (if any) */
  505. err = ssb_pci_init(bus);
  506. if (err)
  507. goto err_unmap;
  508. /* Init PCMCIA-host device (if any) */
  509. err = ssb_pcmcia_init(bus);
  510. if (err)
  511. goto err_pci_exit;
  512. /* Initialize basic system devices (if available) */
  513. err = ssb_bus_powerup(bus, 0);
  514. if (err)
  515. goto err_pcmcia_exit;
  516. ssb_chipcommon_init(&bus->chipco);
  517. ssb_mipscore_init(&bus->mipscore);
  518. err = ssb_fetch_invariants(bus, get_invariants);
  519. if (err) {
  520. ssb_bus_may_powerdown(bus);
  521. goto err_pcmcia_exit;
  522. }
  523. ssb_bus_may_powerdown(bus);
  524. /* Queue it for attach.
  525. * See the comment at the ssb_is_early_boot definition. */
  526. list_add_tail(&bus->list, &attach_queue);
  527. if (!ssb_is_early_boot) {
  528. /* This is not early boot, so we must attach the bus now */
  529. err = ssb_attach_queued_buses();
  530. if (err)
  531. goto err_dequeue;
  532. }
  533. next_busnumber++;
  534. ssb_buses_unlock();
  535. out:
  536. return err;
  537. err_dequeue:
  538. list_del(&bus->list);
  539. err_pcmcia_exit:
  540. /* ssb_pcmcia_exit(bus); */
  541. err_pci_exit:
  542. ssb_pci_exit(bus);
  543. err_unmap:
  544. ssb_iounmap(bus);
  545. err_disable_xtal:
  546. ssb_buses_unlock();
  547. ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  548. return err;
  549. }
  550. #ifdef CONFIG_SSB_PCIHOST
  551. int ssb_bus_pcibus_register(struct ssb_bus *bus,
  552. struct pci_dev *host_pci)
  553. {
  554. int err;
  555. bus->bustype = SSB_BUSTYPE_PCI;
  556. bus->host_pci = host_pci;
  557. bus->ops = &ssb_pci_ops;
  558. err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
  559. if (!err) {
  560. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
  561. "PCI device %s\n", host_pci->dev.bus_id);
  562. }
  563. return err;
  564. }
  565. EXPORT_SYMBOL(ssb_bus_pcibus_register);
  566. #endif /* CONFIG_SSB_PCIHOST */
  567. #ifdef CONFIG_SSB_PCMCIAHOST
  568. int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
  569. struct pcmcia_device *pcmcia_dev,
  570. unsigned long baseaddr)
  571. {
  572. int err;
  573. bus->bustype = SSB_BUSTYPE_PCMCIA;
  574. bus->host_pcmcia = pcmcia_dev;
  575. bus->ops = &ssb_pcmcia_ops;
  576. err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
  577. if (!err) {
  578. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
  579. "PCMCIA device %s\n", pcmcia_dev->devname);
  580. }
  581. return err;
  582. }
  583. EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
  584. #endif /* CONFIG_SSB_PCMCIAHOST */
  585. int ssb_bus_ssbbus_register(struct ssb_bus *bus,
  586. unsigned long baseaddr,
  587. ssb_invariants_func_t get_invariants)
  588. {
  589. int err;
  590. bus->bustype = SSB_BUSTYPE_SSB;
  591. bus->ops = &ssb_ssb_ops;
  592. err = ssb_bus_register(bus, get_invariants, baseaddr);
  593. if (!err) {
  594. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at "
  595. "address 0x%08lX\n", baseaddr);
  596. }
  597. return err;
  598. }
  599. int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
  600. {
  601. drv->drv.name = drv->name;
  602. drv->drv.bus = &ssb_bustype;
  603. drv->drv.owner = owner;
  604. return driver_register(&drv->drv);
  605. }
  606. EXPORT_SYMBOL(__ssb_driver_register);
  607. void ssb_driver_unregister(struct ssb_driver *drv)
  608. {
  609. driver_unregister(&drv->drv);
  610. }
  611. EXPORT_SYMBOL(ssb_driver_unregister);
  612. void ssb_set_devtypedata(struct ssb_device *dev, void *data)
  613. {
  614. struct ssb_bus *bus = dev->bus;
  615. struct ssb_device *ent;
  616. int i;
  617. for (i = 0; i < bus->nr_devices; i++) {
  618. ent = &(bus->devices[i]);
  619. if (ent->id.vendor != dev->id.vendor)
  620. continue;
  621. if (ent->id.coreid != dev->id.coreid)
  622. continue;
  623. ent->devtypedata = data;
  624. }
  625. }
  626. EXPORT_SYMBOL(ssb_set_devtypedata);
  627. static u32 clkfactor_f6_resolve(u32 v)
  628. {
  629. /* map the magic values */
  630. switch (v) {
  631. case SSB_CHIPCO_CLK_F6_2:
  632. return 2;
  633. case SSB_CHIPCO_CLK_F6_3:
  634. return 3;
  635. case SSB_CHIPCO_CLK_F6_4:
  636. return 4;
  637. case SSB_CHIPCO_CLK_F6_5:
  638. return 5;
  639. case SSB_CHIPCO_CLK_F6_6:
  640. return 6;
  641. case SSB_CHIPCO_CLK_F6_7:
  642. return 7;
  643. }
  644. return 0;
  645. }
  646. /* Calculate the speed the backplane would run at a given set of clockcontrol values */
  647. u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
  648. {
  649. u32 n1, n2, clock, m1, m2, m3, mc;
  650. n1 = (n & SSB_CHIPCO_CLK_N1);
  651. n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
  652. switch (plltype) {
  653. case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
  654. if (m & SSB_CHIPCO_CLK_T6_MMASK)
  655. return SSB_CHIPCO_CLK_T6_M0;
  656. return SSB_CHIPCO_CLK_T6_M1;
  657. case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
  658. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  659. case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
  660. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  661. n1 = clkfactor_f6_resolve(n1);
  662. n2 += SSB_CHIPCO_CLK_F5_BIAS;
  663. break;
  664. case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
  665. n1 += SSB_CHIPCO_CLK_T2_BIAS;
  666. n2 += SSB_CHIPCO_CLK_T2_BIAS;
  667. SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7)));
  668. SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23)));
  669. break;
  670. case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
  671. return 100000000;
  672. default:
  673. SSB_WARN_ON(1);
  674. }
  675. switch (plltype) {
  676. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  677. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  678. clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
  679. break;
  680. default:
  681. clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
  682. }
  683. if (!clock)
  684. return 0;
  685. m1 = (m & SSB_CHIPCO_CLK_M1);
  686. m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
  687. m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
  688. mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
  689. switch (plltype) {
  690. case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
  691. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  692. case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
  693. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  694. m1 = clkfactor_f6_resolve(m1);
  695. if ((plltype == SSB_PLLTYPE_1) ||
  696. (plltype == SSB_PLLTYPE_3))
  697. m2 += SSB_CHIPCO_CLK_F5_BIAS;
  698. else
  699. m2 = clkfactor_f6_resolve(m2);
  700. m3 = clkfactor_f6_resolve(m3);
  701. switch (mc) {
  702. case SSB_CHIPCO_CLK_MC_BYPASS:
  703. return clock;
  704. case SSB_CHIPCO_CLK_MC_M1:
  705. return (clock / m1);
  706. case SSB_CHIPCO_CLK_MC_M1M2:
  707. return (clock / (m1 * m2));
  708. case SSB_CHIPCO_CLK_MC_M1M2M3:
  709. return (clock / (m1 * m2 * m3));
  710. case SSB_CHIPCO_CLK_MC_M1M3:
  711. return (clock / (m1 * m3));
  712. }
  713. return 0;
  714. case SSB_PLLTYPE_2:
  715. m1 += SSB_CHIPCO_CLK_T2_BIAS;
  716. m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
  717. m3 += SSB_CHIPCO_CLK_T2_BIAS;
  718. SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7)));
  719. SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10)));
  720. SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7)));
  721. if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
  722. clock /= m1;
  723. if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
  724. clock /= m2;
  725. if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
  726. clock /= m3;
  727. return clock;
  728. default:
  729. SSB_WARN_ON(1);
  730. }
  731. return 0;
  732. }
  733. /* Get the current speed the backplane is running at */
  734. u32 ssb_clockspeed(struct ssb_bus *bus)
  735. {
  736. u32 rate;
  737. u32 plltype;
  738. u32 clkctl_n, clkctl_m;
  739. if (ssb_extif_available(&bus->extif))
  740. ssb_extif_get_clockcontrol(&bus->extif, &plltype,
  741. &clkctl_n, &clkctl_m);
  742. else if (bus->chipco.dev)
  743. ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
  744. &clkctl_n, &clkctl_m);
  745. else
  746. return 0;
  747. if (bus->chip_id == 0x5365) {
  748. rate = 100000000;
  749. } else {
  750. rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
  751. if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
  752. rate /= 2;
  753. }
  754. return rate;
  755. }
  756. EXPORT_SYMBOL(ssb_clockspeed);
  757. static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
  758. {
  759. /* The REJECT bit changed position in TMSLOW between
  760. * Backplane revisions. */
  761. switch (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV) {
  762. case SSB_IDLOW_SSBREV_22:
  763. return SSB_TMSLOW_REJECT_22;
  764. case SSB_IDLOW_SSBREV_23:
  765. return SSB_TMSLOW_REJECT_23;
  766. default:
  767. WARN_ON(1);
  768. }
  769. return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
  770. }
  771. int ssb_device_is_enabled(struct ssb_device *dev)
  772. {
  773. u32 val;
  774. u32 reject;
  775. reject = ssb_tmslow_reject_bitmask(dev);
  776. val = ssb_read32(dev, SSB_TMSLOW);
  777. val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject;
  778. return (val == SSB_TMSLOW_CLOCK);
  779. }
  780. EXPORT_SYMBOL(ssb_device_is_enabled);
  781. static void ssb_flush_tmslow(struct ssb_device *dev)
  782. {
  783. /* Make _really_ sure the device has finished the TMSLOW
  784. * register write transaction, as we risk running into
  785. * a machine check exception otherwise.
  786. * Do this by reading the register back to commit the
  787. * PCI write and delay an additional usec for the device
  788. * to react to the change. */
  789. ssb_read32(dev, SSB_TMSLOW);
  790. udelay(1);
  791. }
  792. void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
  793. {
  794. u32 val;
  795. ssb_device_disable(dev, core_specific_flags);
  796. ssb_write32(dev, SSB_TMSLOW,
  797. SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
  798. SSB_TMSLOW_FGC | core_specific_flags);
  799. ssb_flush_tmslow(dev);
  800. /* Clear SERR if set. This is a hw bug workaround. */
  801. if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
  802. ssb_write32(dev, SSB_TMSHIGH, 0);
  803. val = ssb_read32(dev, SSB_IMSTATE);
  804. if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
  805. val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
  806. ssb_write32(dev, SSB_IMSTATE, val);
  807. }
  808. ssb_write32(dev, SSB_TMSLOW,
  809. SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
  810. core_specific_flags);
  811. ssb_flush_tmslow(dev);
  812. ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
  813. core_specific_flags);
  814. ssb_flush_tmslow(dev);
  815. }
  816. EXPORT_SYMBOL(ssb_device_enable);
  817. /* Wait for a bit in a register to get set or unset.
  818. * timeout is in units of ten-microseconds */
  819. static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
  820. int timeout, int set)
  821. {
  822. int i;
  823. u32 val;
  824. for (i = 0; i < timeout; i++) {
  825. val = ssb_read32(dev, reg);
  826. if (set) {
  827. if (val & bitmask)
  828. return 0;
  829. } else {
  830. if (!(val & bitmask))
  831. return 0;
  832. }
  833. udelay(10);
  834. }
  835. printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
  836. "register %04X to %s.\n",
  837. bitmask, reg, (set ? "set" : "clear"));
  838. return -ETIMEDOUT;
  839. }
  840. void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
  841. {
  842. u32 reject;
  843. if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
  844. return;
  845. reject = ssb_tmslow_reject_bitmask(dev);
  846. ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
  847. ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
  848. ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
  849. ssb_write32(dev, SSB_TMSLOW,
  850. SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
  851. reject | SSB_TMSLOW_RESET |
  852. core_specific_flags);
  853. ssb_flush_tmslow(dev);
  854. ssb_write32(dev, SSB_TMSLOW,
  855. reject | SSB_TMSLOW_RESET |
  856. core_specific_flags);
  857. ssb_flush_tmslow(dev);
  858. }
  859. EXPORT_SYMBOL(ssb_device_disable);
  860. u32 ssb_dma_translation(struct ssb_device *dev)
  861. {
  862. switch (dev->bus->bustype) {
  863. case SSB_BUSTYPE_SSB:
  864. return 0;
  865. case SSB_BUSTYPE_PCI:
  866. case SSB_BUSTYPE_PCMCIA:
  867. return SSB_PCI_DMA;
  868. }
  869. return 0;
  870. }
  871. EXPORT_SYMBOL(ssb_dma_translation);
  872. int ssb_dma_set_mask(struct ssb_device *ssb_dev, u64 mask)
  873. {
  874. struct device *dev = ssb_dev->dev;
  875. #ifdef CONFIG_SSB_PCIHOST
  876. if (ssb_dev->bus->bustype == SSB_BUSTYPE_PCI &&
  877. !dma_supported(dev, mask))
  878. return -EIO;
  879. #endif
  880. dev->coherent_dma_mask = mask;
  881. dev->dma_mask = &dev->coherent_dma_mask;
  882. return 0;
  883. }
  884. EXPORT_SYMBOL(ssb_dma_set_mask);
  885. int ssb_bus_may_powerdown(struct ssb_bus *bus)
  886. {
  887. struct ssb_chipcommon *cc;
  888. int err = 0;
  889. /* On buses where more than one core may be working
  890. * at a time, we must not powerdown stuff if there are
  891. * still cores that may want to run. */
  892. if (bus->bustype == SSB_BUSTYPE_SSB)
  893. goto out;
  894. cc = &bus->chipco;
  895. ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
  896. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  897. if (err)
  898. goto error;
  899. out:
  900. #ifdef CONFIG_SSB_DEBUG
  901. bus->powered_up = 0;
  902. #endif
  903. return err;
  904. error:
  905. ssb_printk(KERN_ERR PFX "Bus powerdown failed\n");
  906. goto out;
  907. }
  908. EXPORT_SYMBOL(ssb_bus_may_powerdown);
  909. int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
  910. {
  911. struct ssb_chipcommon *cc;
  912. int err;
  913. enum ssb_clkmode mode;
  914. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
  915. if (err)
  916. goto error;
  917. cc = &bus->chipco;
  918. mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
  919. ssb_chipco_set_clockmode(cc, mode);
  920. #ifdef CONFIG_SSB_DEBUG
  921. bus->powered_up = 1;
  922. #endif
  923. return 0;
  924. error:
  925. ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
  926. return err;
  927. }
  928. EXPORT_SYMBOL(ssb_bus_powerup);
  929. u32 ssb_admatch_base(u32 adm)
  930. {
  931. u32 base = 0;
  932. switch (adm & SSB_ADM_TYPE) {
  933. case SSB_ADM_TYPE0:
  934. base = (adm & SSB_ADM_BASE0);
  935. break;
  936. case SSB_ADM_TYPE1:
  937. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  938. base = (adm & SSB_ADM_BASE1);
  939. break;
  940. case SSB_ADM_TYPE2:
  941. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  942. base = (adm & SSB_ADM_BASE2);
  943. break;
  944. default:
  945. SSB_WARN_ON(1);
  946. }
  947. return base;
  948. }
  949. EXPORT_SYMBOL(ssb_admatch_base);
  950. u32 ssb_admatch_size(u32 adm)
  951. {
  952. u32 size = 0;
  953. switch (adm & SSB_ADM_TYPE) {
  954. case SSB_ADM_TYPE0:
  955. size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
  956. break;
  957. case SSB_ADM_TYPE1:
  958. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  959. size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
  960. break;
  961. case SSB_ADM_TYPE2:
  962. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  963. size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
  964. break;
  965. default:
  966. SSB_WARN_ON(1);
  967. }
  968. size = (1 << (size + 1));
  969. return size;
  970. }
  971. EXPORT_SYMBOL(ssb_admatch_size);
  972. static int __init ssb_modinit(void)
  973. {
  974. int err;
  975. /* See the comment at the ssb_is_early_boot definition */
  976. ssb_is_early_boot = 0;
  977. err = bus_register(&ssb_bustype);
  978. if (err)
  979. return err;
  980. /* Maybe we already registered some buses at early boot.
  981. * Check for this and attach them
  982. */
  983. ssb_buses_lock();
  984. err = ssb_attach_queued_buses();
  985. ssb_buses_unlock();
  986. if (err)
  987. bus_unregister(&ssb_bustype);
  988. err = b43_pci_ssb_bridge_init();
  989. if (err) {
  990. ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
  991. "initialization failed");
  992. /* don't fail SSB init because of this */
  993. err = 0;
  994. }
  995. return err;
  996. }
  997. subsys_initcall(ssb_modinit);
  998. static void __exit ssb_modexit(void)
  999. {
  1000. b43_pci_ssb_bridge_exit();
  1001. bus_unregister(&ssb_bustype);
  1002. }
  1003. module_exit(ssb_modexit)