intel_idle.c 11 KB

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  1. /*
  2. * intel_idle.c - native hardware idle loop for modern Intel processors
  3. *
  4. * Copyright (c) 2010, Intel Corporation.
  5. * Len Brown <len.brown@intel.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms and conditions of the GNU General Public License,
  9. * version 2, as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program; if not, write to the Free Software Foundation, Inc.,
  18. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19. */
  20. /*
  21. * intel_idle is a cpuidle driver that loads on specific Intel processors
  22. * in lieu of the legacy ACPI processor_idle driver. The intent is to
  23. * make Linux more efficient on these processors, as intel_idle knows
  24. * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
  25. */
  26. /*
  27. * Design Assumptions
  28. *
  29. * All CPUs have same idle states as boot CPU
  30. *
  31. * Chipset BM_STS (bus master status) bit is a NOP
  32. * for preventing entry into deep C-stats
  33. */
  34. /*
  35. * Known limitations
  36. *
  37. * The driver currently initializes for_each_online_cpu() upon modprobe.
  38. * It it unaware of subsequent processors hot-added to the system.
  39. * This means that if you boot with maxcpus=n and later online
  40. * processors above n, those processors will use C1 only.
  41. *
  42. * ACPI has a .suspend hack to turn off deep c-statees during suspend
  43. * to avoid complications with the lapic timer workaround.
  44. * Have not seen issues with suspend, but may need same workaround here.
  45. *
  46. * There is currently no kernel-based automatic probing/loading mechanism
  47. * if the driver is built as a module.
  48. */
  49. /* un-comment DEBUG to enable pr_debug() statements */
  50. #define DEBUG
  51. #include <linux/kernel.h>
  52. #include <linux/cpuidle.h>
  53. #include <linux/clockchips.h>
  54. #include <linux/hrtimer.h> /* ktime_get_real() */
  55. #include <trace/events/power.h>
  56. #include <linux/sched.h>
  57. #include <asm/mwait.h>
  58. #define INTEL_IDLE_VERSION "0.4"
  59. #define PREFIX "intel_idle: "
  60. static struct cpuidle_driver intel_idle_driver = {
  61. .name = "intel_idle",
  62. .owner = THIS_MODULE,
  63. };
  64. /* intel_idle.max_cstate=0 disables driver */
  65. static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1;
  66. static unsigned int mwait_substates;
  67. /* Reliable LAPIC Timer States, bit 1 for C1 etc. */
  68. static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */
  69. static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
  70. static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state);
  71. static struct cpuidle_state *cpuidle_state_table;
  72. /*
  73. * States are indexed by the cstate number,
  74. * which is also the index into the MWAIT hint array.
  75. * Thus C0 is a dummy.
  76. */
  77. static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
  78. { /* MWAIT C0 */ },
  79. { /* MWAIT C1 */
  80. .name = "NHM-C1",
  81. .desc = "MWAIT 0x00",
  82. .driver_data = (void *) 0x00,
  83. .flags = CPUIDLE_FLAG_TIME_VALID,
  84. .exit_latency = 3,
  85. .target_residency = 6,
  86. .enter = &intel_idle },
  87. { /* MWAIT C2 */
  88. .name = "NHM-C3",
  89. .desc = "MWAIT 0x10",
  90. .driver_data = (void *) 0x10,
  91. .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
  92. .exit_latency = 20,
  93. .target_residency = 80,
  94. .enter = &intel_idle },
  95. { /* MWAIT C3 */
  96. .name = "NHM-C6",
  97. .desc = "MWAIT 0x20",
  98. .driver_data = (void *) 0x20,
  99. .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
  100. .exit_latency = 200,
  101. .target_residency = 800,
  102. .enter = &intel_idle },
  103. };
  104. static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
  105. { /* MWAIT C0 */ },
  106. { /* MWAIT C1 */
  107. .name = "SNB-C1",
  108. .desc = "MWAIT 0x00",
  109. .driver_data = (void *) 0x00,
  110. .flags = CPUIDLE_FLAG_TIME_VALID,
  111. .exit_latency = 1,
  112. .target_residency = 4,
  113. .enter = &intel_idle },
  114. { /* MWAIT C2 */
  115. .name = "SNB-C3",
  116. .desc = "MWAIT 0x10",
  117. .driver_data = (void *) 0x10,
  118. .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
  119. .exit_latency = 80,
  120. .target_residency = 160,
  121. .enter = &intel_idle },
  122. { /* MWAIT C3 */
  123. .name = "SNB-C6",
  124. .desc = "MWAIT 0x20",
  125. .driver_data = (void *) 0x20,
  126. .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
  127. .exit_latency = 104,
  128. .target_residency = 208,
  129. .enter = &intel_idle },
  130. { /* MWAIT C4 */
  131. .name = "SNB-C7",
  132. .desc = "MWAIT 0x30",
  133. .driver_data = (void *) 0x30,
  134. .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
  135. .exit_latency = 109,
  136. .target_residency = 300,
  137. .enter = &intel_idle },
  138. };
  139. static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
  140. { /* MWAIT C0 */ },
  141. { /* MWAIT C1 */
  142. .name = "ATM-C1",
  143. .desc = "MWAIT 0x00",
  144. .driver_data = (void *) 0x00,
  145. .flags = CPUIDLE_FLAG_TIME_VALID,
  146. .exit_latency = 1,
  147. .target_residency = 4,
  148. .enter = &intel_idle },
  149. { /* MWAIT C2 */
  150. .name = "ATM-C2",
  151. .desc = "MWAIT 0x10",
  152. .driver_data = (void *) 0x10,
  153. .flags = CPUIDLE_FLAG_TIME_VALID,
  154. .exit_latency = 20,
  155. .target_residency = 80,
  156. .enter = &intel_idle },
  157. { /* MWAIT C3 */ },
  158. { /* MWAIT C4 */
  159. .name = "ATM-C4",
  160. .desc = "MWAIT 0x30",
  161. .driver_data = (void *) 0x30,
  162. .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
  163. .exit_latency = 100,
  164. .target_residency = 400,
  165. .enter = &intel_idle },
  166. { /* MWAIT C5 */ },
  167. { /* MWAIT C6 */
  168. .name = "ATM-C6",
  169. .desc = "MWAIT 0x52",
  170. .driver_data = (void *) 0x52,
  171. .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
  172. .exit_latency = 140,
  173. .target_residency = 560,
  174. .enter = &intel_idle },
  175. };
  176. /**
  177. * intel_idle
  178. * @dev: cpuidle_device
  179. * @state: cpuidle state
  180. *
  181. */
  182. static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state)
  183. {
  184. unsigned long ecx = 1; /* break on interrupt flag */
  185. unsigned long eax = (unsigned long)cpuidle_get_statedata(state);
  186. unsigned int cstate;
  187. ktime_t kt_before, kt_after;
  188. s64 usec_delta;
  189. int cpu = smp_processor_id();
  190. cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
  191. local_irq_disable();
  192. /*
  193. * leave_mm() to avoid costly and often unnecessary wakeups
  194. * for flushing the user TLB's associated with the active mm.
  195. */
  196. if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
  197. leave_mm(cpu);
  198. if (!(lapic_timer_reliable_states & (1 << (cstate))))
  199. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
  200. kt_before = ktime_get_real();
  201. stop_critical_timings();
  202. trace_power_start(POWER_CSTATE, (eax >> 4) + 1, cpu);
  203. if (!need_resched()) {
  204. __monitor((void *)&current_thread_info()->flags, 0, 0);
  205. smp_mb();
  206. if (!need_resched())
  207. __mwait(eax, ecx);
  208. }
  209. start_critical_timings();
  210. kt_after = ktime_get_real();
  211. usec_delta = ktime_to_us(ktime_sub(kt_after, kt_before));
  212. local_irq_enable();
  213. if (!(lapic_timer_reliable_states & (1 << (cstate))))
  214. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
  215. return usec_delta;
  216. }
  217. /*
  218. * intel_idle_probe()
  219. */
  220. static int intel_idle_probe(void)
  221. {
  222. unsigned int eax, ebx, ecx;
  223. if (max_cstate == 0) {
  224. pr_debug(PREFIX "disabled\n");
  225. return -EPERM;
  226. }
  227. if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
  228. return -ENODEV;
  229. if (!boot_cpu_has(X86_FEATURE_MWAIT))
  230. return -ENODEV;
  231. if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
  232. return -ENODEV;
  233. cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
  234. if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
  235. !(ecx & CPUID5_ECX_INTERRUPT_BREAK))
  236. return -ENODEV;
  237. pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
  238. if (boot_cpu_data.x86 != 6) /* family 6 */
  239. return -ENODEV;
  240. switch (boot_cpu_data.x86_model) {
  241. case 0x1A: /* Core i7, Xeon 5500 series */
  242. case 0x1E: /* Core i7 and i5 Processor - Lynnfield Jasper Forest */
  243. case 0x1F: /* Core i7 and i5 Processor - Nehalem */
  244. case 0x2E: /* Nehalem-EX Xeon */
  245. case 0x2F: /* Westmere-EX Xeon */
  246. case 0x25: /* Westmere */
  247. case 0x2C: /* Westmere */
  248. cpuidle_state_table = nehalem_cstates;
  249. break;
  250. case 0x1C: /* 28 - Atom Processor */
  251. case 0x26: /* 38 - Lincroft Atom Processor */
  252. cpuidle_state_table = atom_cstates;
  253. break;
  254. case 0x2A: /* SNB */
  255. case 0x2D: /* SNB Xeon */
  256. cpuidle_state_table = snb_cstates;
  257. break;
  258. default:
  259. pr_debug(PREFIX "does not run on family %d model %d\n",
  260. boot_cpu_data.x86, boot_cpu_data.x86_model);
  261. return -ENODEV;
  262. }
  263. if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
  264. lapic_timer_reliable_states = 0xFFFFFFFF;
  265. pr_debug(PREFIX "v" INTEL_IDLE_VERSION
  266. " model 0x%X\n", boot_cpu_data.x86_model);
  267. pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
  268. lapic_timer_reliable_states);
  269. return 0;
  270. }
  271. /*
  272. * intel_idle_cpuidle_devices_uninit()
  273. * unregister, free cpuidle_devices
  274. */
  275. static void intel_idle_cpuidle_devices_uninit(void)
  276. {
  277. int i;
  278. struct cpuidle_device *dev;
  279. for_each_online_cpu(i) {
  280. dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
  281. cpuidle_unregister_device(dev);
  282. }
  283. free_percpu(intel_idle_cpuidle_devices);
  284. return;
  285. }
  286. /*
  287. * intel_idle_cpuidle_devices_init()
  288. * allocate, initialize, register cpuidle_devices
  289. */
  290. static int intel_idle_cpuidle_devices_init(void)
  291. {
  292. int i, cstate;
  293. struct cpuidle_device *dev;
  294. intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
  295. if (intel_idle_cpuidle_devices == NULL)
  296. return -ENOMEM;
  297. for_each_online_cpu(i) {
  298. dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
  299. dev->state_count = 1;
  300. for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
  301. int num_substates;
  302. if (cstate > max_cstate) {
  303. printk(PREFIX "max_cstate %d reached\n",
  304. max_cstate);
  305. break;
  306. }
  307. /* does the state exist in CPUID.MWAIT? */
  308. num_substates = (mwait_substates >> ((cstate) * 4))
  309. & MWAIT_SUBSTATE_MASK;
  310. if (num_substates == 0)
  311. continue;
  312. /* is the state not enabled? */
  313. if (cpuidle_state_table[cstate].enter == NULL) {
  314. /* does the driver not know about the state? */
  315. if (*cpuidle_state_table[cstate].name == '\0')
  316. pr_debug(PREFIX "unaware of model 0x%x"
  317. " MWAIT %d please"
  318. " contact lenb@kernel.org",
  319. boot_cpu_data.x86_model, cstate);
  320. continue;
  321. }
  322. if ((cstate > 2) &&
  323. !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
  324. mark_tsc_unstable("TSC halts in idle"
  325. " states deeper than C2");
  326. dev->states[dev->state_count] = /* structure copy */
  327. cpuidle_state_table[cstate];
  328. dev->state_count += 1;
  329. }
  330. dev->cpu = i;
  331. if (cpuidle_register_device(dev)) {
  332. pr_debug(PREFIX "cpuidle_register_device %d failed!\n",
  333. i);
  334. intel_idle_cpuidle_devices_uninit();
  335. return -EIO;
  336. }
  337. }
  338. return 0;
  339. }
  340. static int __init intel_idle_init(void)
  341. {
  342. int retval;
  343. retval = intel_idle_probe();
  344. if (retval)
  345. return retval;
  346. retval = cpuidle_register_driver(&intel_idle_driver);
  347. if (retval) {
  348. printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
  349. cpuidle_get_driver()->name);
  350. return retval;
  351. }
  352. retval = intel_idle_cpuidle_devices_init();
  353. if (retval) {
  354. cpuidle_unregister_driver(&intel_idle_driver);
  355. return retval;
  356. }
  357. return 0;
  358. }
  359. static void __exit intel_idle_exit(void)
  360. {
  361. intel_idle_cpuidle_devices_uninit();
  362. cpuidle_unregister_driver(&intel_idle_driver);
  363. return;
  364. }
  365. module_init(intel_idle_init);
  366. module_exit(intel_idle_exit);
  367. module_param(max_cstate, int, 0444);
  368. MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
  369. MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
  370. MODULE_LICENSE("GPL");