video1394.c 41 KB

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  1. /*
  2. * video1394.c - video driver for OHCI 1394 boards
  3. * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
  4. * Peter Schlaile <udbz@rz.uni-karlsruhe.de>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software Foundation,
  18. * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19. *
  20. * NOTES:
  21. *
  22. * jds -- add private data to file to keep track of iso contexts associated
  23. * with each open -- so release won't kill all iso transfers.
  24. *
  25. * Damien Douxchamps: Fix failure when the number of DMA pages per frame is
  26. * one.
  27. *
  28. * ioctl return codes:
  29. * EFAULT is only for invalid address for the argp
  30. * EINVAL for out of range values
  31. * EBUSY when trying to use an already used resource
  32. * ESRCH when trying to free/stop a not used resource
  33. * EAGAIN for resource allocation failure that could perhaps succeed later
  34. * ENOTTY for unsupported ioctl request
  35. *
  36. */
  37. #include <linux/config.h>
  38. #include <linux/kernel.h>
  39. #include <linux/list.h>
  40. #include <linux/slab.h>
  41. #include <linux/interrupt.h>
  42. #include <linux/wait.h>
  43. #include <linux/errno.h>
  44. #include <linux/module.h>
  45. #include <linux/init.h>
  46. #include <linux/pci.h>
  47. #include <linux/fs.h>
  48. #include <linux/poll.h>
  49. #include <linux/smp_lock.h>
  50. #include <linux/delay.h>
  51. #include <linux/devfs_fs_kernel.h>
  52. #include <linux/bitops.h>
  53. #include <linux/types.h>
  54. #include <linux/vmalloc.h>
  55. #include <linux/timex.h>
  56. #include <linux/mm.h>
  57. #include <linux/ioctl32.h>
  58. #include <linux/compat.h>
  59. #include <linux/cdev.h>
  60. #include "ieee1394.h"
  61. #include "ieee1394_types.h"
  62. #include "hosts.h"
  63. #include "ieee1394_core.h"
  64. #include "highlevel.h"
  65. #include "video1394.h"
  66. #include "nodemgr.h"
  67. #include "dma.h"
  68. #include "ohci1394.h"
  69. #define ISO_CHANNELS 64
  70. #ifndef virt_to_page
  71. #define virt_to_page(x) MAP_NR(x)
  72. #endif
  73. #ifndef vmalloc_32
  74. #define vmalloc_32(x) vmalloc(x)
  75. #endif
  76. struct it_dma_prg {
  77. struct dma_cmd begin;
  78. quadlet_t data[4];
  79. struct dma_cmd end;
  80. quadlet_t pad[4]; /* FIXME: quick hack for memory alignment */
  81. };
  82. struct dma_iso_ctx {
  83. struct ti_ohci *ohci;
  84. int type; /* OHCI_ISO_TRANSMIT or OHCI_ISO_RECEIVE */
  85. struct ohci1394_iso_tasklet iso_tasklet;
  86. int channel;
  87. int ctx;
  88. int last_buffer;
  89. int * next_buffer; /* For ISO Transmit of video packets
  90. to write the correct SYT field
  91. into the next block */
  92. unsigned int num_desc;
  93. unsigned int buf_size;
  94. unsigned int frame_size;
  95. unsigned int packet_size;
  96. unsigned int left_size;
  97. unsigned int nb_cmd;
  98. struct dma_region dma;
  99. struct dma_prog_region *prg_reg;
  100. struct dma_cmd **ir_prg;
  101. struct it_dma_prg **it_prg;
  102. unsigned int *buffer_status;
  103. struct timeval *buffer_time; /* time when the buffer was received */
  104. unsigned int *last_used_cmd; /* For ISO Transmit with
  105. variable sized packets only ! */
  106. int ctrlClear;
  107. int ctrlSet;
  108. int cmdPtr;
  109. int ctxMatch;
  110. wait_queue_head_t waitq;
  111. spinlock_t lock;
  112. unsigned int syt_offset;
  113. int flags;
  114. struct list_head link;
  115. };
  116. struct file_ctx {
  117. struct ti_ohci *ohci;
  118. struct list_head context_list;
  119. struct dma_iso_ctx *current_ctx;
  120. };
  121. #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
  122. #define VIDEO1394_DEBUG
  123. #endif
  124. #ifdef DBGMSG
  125. #undef DBGMSG
  126. #endif
  127. #ifdef VIDEO1394_DEBUG
  128. #define DBGMSG(card, fmt, args...) \
  129. printk(KERN_INFO "video1394_%d: " fmt "\n" , card , ## args)
  130. #else
  131. #define DBGMSG(card, fmt, args...)
  132. #endif
  133. /* print general (card independent) information */
  134. #define PRINT_G(level, fmt, args...) \
  135. printk(level "video1394: " fmt "\n" , ## args)
  136. /* print card specific information */
  137. #define PRINT(level, card, fmt, args...) \
  138. printk(level "video1394_%d: " fmt "\n" , card , ## args)
  139. static void wakeup_dma_ir_ctx(unsigned long l);
  140. static void wakeup_dma_it_ctx(unsigned long l);
  141. static struct hpsb_highlevel video1394_highlevel;
  142. static int free_dma_iso_ctx(struct dma_iso_ctx *d)
  143. {
  144. int i;
  145. DBGMSG(d->ohci->host->id, "Freeing dma_iso_ctx %d", d->ctx);
  146. ohci1394_stop_context(d->ohci, d->ctrlClear, NULL);
  147. if (d->iso_tasklet.link.next != NULL)
  148. ohci1394_unregister_iso_tasklet(d->ohci, &d->iso_tasklet);
  149. dma_region_free(&d->dma);
  150. if (d->prg_reg) {
  151. for (i = 0; i < d->num_desc; i++)
  152. dma_prog_region_free(&d->prg_reg[i]);
  153. kfree(d->prg_reg);
  154. }
  155. kfree(d->ir_prg);
  156. kfree(d->it_prg);
  157. kfree(d->buffer_status);
  158. kfree(d->buffer_time);
  159. kfree(d->last_used_cmd);
  160. kfree(d->next_buffer);
  161. list_del(&d->link);
  162. kfree(d);
  163. return 0;
  164. }
  165. static struct dma_iso_ctx *
  166. alloc_dma_iso_ctx(struct ti_ohci *ohci, int type, int num_desc,
  167. int buf_size, int channel, unsigned int packet_size)
  168. {
  169. struct dma_iso_ctx *d;
  170. int i;
  171. d = kmalloc(sizeof(struct dma_iso_ctx), GFP_KERNEL);
  172. if (d == NULL) {
  173. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma_iso_ctx");
  174. return NULL;
  175. }
  176. memset(d, 0, sizeof *d);
  177. d->ohci = ohci;
  178. d->type = type;
  179. d->channel = channel;
  180. d->num_desc = num_desc;
  181. d->frame_size = buf_size;
  182. d->buf_size = PAGE_ALIGN(buf_size);
  183. d->last_buffer = -1;
  184. INIT_LIST_HEAD(&d->link);
  185. init_waitqueue_head(&d->waitq);
  186. /* Init the regions for easy cleanup */
  187. dma_region_init(&d->dma);
  188. if (dma_region_alloc(&d->dma, d->num_desc * d->buf_size, ohci->dev,
  189. PCI_DMA_BIDIRECTIONAL)) {
  190. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma buffer");
  191. free_dma_iso_ctx(d);
  192. return NULL;
  193. }
  194. if (type == OHCI_ISO_RECEIVE)
  195. ohci1394_init_iso_tasklet(&d->iso_tasklet, type,
  196. wakeup_dma_ir_ctx,
  197. (unsigned long) d);
  198. else
  199. ohci1394_init_iso_tasklet(&d->iso_tasklet, type,
  200. wakeup_dma_it_ctx,
  201. (unsigned long) d);
  202. if (ohci1394_register_iso_tasklet(ohci, &d->iso_tasklet) < 0) {
  203. PRINT(KERN_ERR, ohci->host->id, "no free iso %s contexts",
  204. type == OHCI_ISO_RECEIVE ? "receive" : "transmit");
  205. free_dma_iso_ctx(d);
  206. return NULL;
  207. }
  208. d->ctx = d->iso_tasklet.context;
  209. d->prg_reg = kmalloc(d->num_desc * sizeof(struct dma_prog_region),
  210. GFP_KERNEL);
  211. if (d->prg_reg == NULL) {
  212. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate ir prg regs");
  213. free_dma_iso_ctx(d);
  214. return NULL;
  215. }
  216. /* Makes for easier cleanup */
  217. for (i = 0; i < d->num_desc; i++)
  218. dma_prog_region_init(&d->prg_reg[i]);
  219. if (type == OHCI_ISO_RECEIVE) {
  220. d->ctrlSet = OHCI1394_IsoRcvContextControlSet+32*d->ctx;
  221. d->ctrlClear = OHCI1394_IsoRcvContextControlClear+32*d->ctx;
  222. d->cmdPtr = OHCI1394_IsoRcvCommandPtr+32*d->ctx;
  223. d->ctxMatch = OHCI1394_IsoRcvContextMatch+32*d->ctx;
  224. d->ir_prg = kmalloc(d->num_desc * sizeof(struct dma_cmd *),
  225. GFP_KERNEL);
  226. if (d->ir_prg == NULL) {
  227. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma ir prg");
  228. free_dma_iso_ctx(d);
  229. return NULL;
  230. }
  231. memset(d->ir_prg, 0, d->num_desc * sizeof(struct dma_cmd *));
  232. d->nb_cmd = d->buf_size / PAGE_SIZE + 1;
  233. d->left_size = (d->frame_size % PAGE_SIZE) ?
  234. d->frame_size % PAGE_SIZE : PAGE_SIZE;
  235. for (i = 0;i < d->num_desc; i++) {
  236. if (dma_prog_region_alloc(&d->prg_reg[i], d->nb_cmd *
  237. sizeof(struct dma_cmd), ohci->dev)) {
  238. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma ir prg");
  239. free_dma_iso_ctx(d);
  240. return NULL;
  241. }
  242. d->ir_prg[i] = (struct dma_cmd *)d->prg_reg[i].kvirt;
  243. }
  244. } else { /* OHCI_ISO_TRANSMIT */
  245. d->ctrlSet = OHCI1394_IsoXmitContextControlSet+16*d->ctx;
  246. d->ctrlClear = OHCI1394_IsoXmitContextControlClear+16*d->ctx;
  247. d->cmdPtr = OHCI1394_IsoXmitCommandPtr+16*d->ctx;
  248. d->it_prg = kmalloc(d->num_desc * sizeof(struct it_dma_prg *),
  249. GFP_KERNEL);
  250. if (d->it_prg == NULL) {
  251. PRINT(KERN_ERR, ohci->host->id,
  252. "Failed to allocate dma it prg");
  253. free_dma_iso_ctx(d);
  254. return NULL;
  255. }
  256. memset(d->it_prg, 0, d->num_desc*sizeof(struct it_dma_prg *));
  257. d->packet_size = packet_size;
  258. if (PAGE_SIZE % packet_size || packet_size>4096) {
  259. PRINT(KERN_ERR, ohci->host->id,
  260. "Packet size %d (page_size: %ld) "
  261. "not yet supported\n",
  262. packet_size, PAGE_SIZE);
  263. free_dma_iso_ctx(d);
  264. return NULL;
  265. }
  266. d->nb_cmd = d->frame_size / d->packet_size;
  267. if (d->frame_size % d->packet_size) {
  268. d->nb_cmd++;
  269. d->left_size = d->frame_size % d->packet_size;
  270. } else
  271. d->left_size = d->packet_size;
  272. for (i = 0; i < d->num_desc; i++) {
  273. if (dma_prog_region_alloc(&d->prg_reg[i], d->nb_cmd *
  274. sizeof(struct it_dma_prg), ohci->dev)) {
  275. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma it prg");
  276. free_dma_iso_ctx(d);
  277. return NULL;
  278. }
  279. d->it_prg[i] = (struct it_dma_prg *)d->prg_reg[i].kvirt;
  280. }
  281. }
  282. d->buffer_status = kmalloc(d->num_desc * sizeof(unsigned int),
  283. GFP_KERNEL);
  284. d->buffer_time = kmalloc(d->num_desc * sizeof(struct timeval),
  285. GFP_KERNEL);
  286. d->last_used_cmd = kmalloc(d->num_desc * sizeof(unsigned int),
  287. GFP_KERNEL);
  288. d->next_buffer = kmalloc(d->num_desc * sizeof(int),
  289. GFP_KERNEL);
  290. if (d->buffer_status == NULL) {
  291. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate buffer_status");
  292. free_dma_iso_ctx(d);
  293. return NULL;
  294. }
  295. if (d->buffer_time == NULL) {
  296. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate buffer_time");
  297. free_dma_iso_ctx(d);
  298. return NULL;
  299. }
  300. if (d->last_used_cmd == NULL) {
  301. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate last_used_cmd");
  302. free_dma_iso_ctx(d);
  303. return NULL;
  304. }
  305. if (d->next_buffer == NULL) {
  306. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate next_buffer");
  307. free_dma_iso_ctx(d);
  308. return NULL;
  309. }
  310. memset(d->buffer_status, 0, d->num_desc * sizeof(unsigned int));
  311. memset(d->buffer_time, 0, d->num_desc * sizeof(struct timeval));
  312. memset(d->last_used_cmd, 0, d->num_desc * sizeof(unsigned int));
  313. memset(d->next_buffer, -1, d->num_desc * sizeof(int));
  314. spin_lock_init(&d->lock);
  315. PRINT(KERN_INFO, ohci->host->id, "Iso %s DMA: %d buffers "
  316. "of size %d allocated for a frame size %d, each with %d prgs",
  317. (type == OHCI_ISO_RECEIVE) ? "receive" : "transmit",
  318. d->num_desc, d->buf_size, d->frame_size, d->nb_cmd);
  319. return d;
  320. }
  321. static void reset_ir_status(struct dma_iso_ctx *d, int n)
  322. {
  323. int i;
  324. d->ir_prg[n][0].status = cpu_to_le32(4);
  325. d->ir_prg[n][1].status = cpu_to_le32(PAGE_SIZE-4);
  326. for (i = 2; i < d->nb_cmd - 1; i++)
  327. d->ir_prg[n][i].status = cpu_to_le32(PAGE_SIZE);
  328. d->ir_prg[n][i].status = cpu_to_le32(d->left_size);
  329. }
  330. static void initialize_dma_ir_prg(struct dma_iso_ctx *d, int n, int flags)
  331. {
  332. struct dma_cmd *ir_prg = d->ir_prg[n];
  333. struct dma_prog_region *ir_reg = &d->prg_reg[n];
  334. unsigned long buf = (unsigned long)d->dma.kvirt + n * d->buf_size;
  335. int i;
  336. /* the first descriptor will read only 4 bytes */
  337. ir_prg[0].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  338. DMA_CTL_BRANCH | 4);
  339. /* set the sync flag */
  340. if (flags & VIDEO1394_SYNC_FRAMES)
  341. ir_prg[0].control |= cpu_to_le32(DMA_CTL_WAIT);
  342. ir_prg[0].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, buf -
  343. (unsigned long)d->dma.kvirt));
  344. ir_prg[0].branchAddress = cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
  345. 1 * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
  346. /* If there is *not* only one DMA page per frame (hence, d->nb_cmd==2) */
  347. if (d->nb_cmd > 2) {
  348. /* The second descriptor will read PAGE_SIZE-4 bytes */
  349. ir_prg[1].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  350. DMA_CTL_BRANCH | (PAGE_SIZE-4));
  351. ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, (buf + 4) -
  352. (unsigned long)d->dma.kvirt));
  353. ir_prg[1].branchAddress = cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
  354. 2 * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
  355. for (i = 2; i < d->nb_cmd - 1; i++) {
  356. ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  357. DMA_CTL_BRANCH | PAGE_SIZE);
  358. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  359. (buf+(i-1)*PAGE_SIZE) -
  360. (unsigned long)d->dma.kvirt));
  361. ir_prg[i].branchAddress =
  362. cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
  363. (i + 1) * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
  364. }
  365. /* The last descriptor will generate an interrupt */
  366. ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  367. DMA_CTL_IRQ | DMA_CTL_BRANCH | d->left_size);
  368. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  369. (buf+(i-1)*PAGE_SIZE) -
  370. (unsigned long)d->dma.kvirt));
  371. } else {
  372. /* Only one DMA page is used. Read d->left_size immediately and */
  373. /* generate an interrupt as this is also the last page. */
  374. ir_prg[1].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  375. DMA_CTL_IRQ | DMA_CTL_BRANCH | (d->left_size-4));
  376. ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  377. (buf + 4) - (unsigned long)d->dma.kvirt));
  378. }
  379. }
  380. static void initialize_dma_ir_ctx(struct dma_iso_ctx *d, int tag, int flags)
  381. {
  382. struct ti_ohci *ohci = (struct ti_ohci *)d->ohci;
  383. int i;
  384. d->flags = flags;
  385. ohci1394_stop_context(ohci, d->ctrlClear, NULL);
  386. for (i=0;i<d->num_desc;i++) {
  387. initialize_dma_ir_prg(d, i, flags);
  388. reset_ir_status(d, i);
  389. }
  390. /* reset the ctrl register */
  391. reg_write(ohci, d->ctrlClear, 0xf0000000);
  392. /* Set bufferFill */
  393. reg_write(ohci, d->ctrlSet, 0x80000000);
  394. /* Set isoch header */
  395. if (flags & VIDEO1394_INCLUDE_ISO_HEADERS)
  396. reg_write(ohci, d->ctrlSet, 0x40000000);
  397. /* Set the context match register to match on all tags,
  398. sync for sync tag, and listen to d->channel */
  399. reg_write(ohci, d->ctxMatch, 0xf0000000|((tag&0xf)<<8)|d->channel);
  400. /* Set up isoRecvIntMask to generate interrupts */
  401. reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1<<d->ctx);
  402. }
  403. /* find which context is listening to this channel */
  404. static struct dma_iso_ctx *
  405. find_ctx(struct list_head *list, int type, int channel)
  406. {
  407. struct dma_iso_ctx *ctx;
  408. list_for_each_entry(ctx, list, link) {
  409. if (ctx->type == type && ctx->channel == channel)
  410. return ctx;
  411. }
  412. return NULL;
  413. }
  414. static void wakeup_dma_ir_ctx(unsigned long l)
  415. {
  416. struct dma_iso_ctx *d = (struct dma_iso_ctx *) l;
  417. int i;
  418. spin_lock(&d->lock);
  419. for (i = 0; i < d->num_desc; i++) {
  420. if (d->ir_prg[i][d->nb_cmd-1].status & cpu_to_le32(0xFFFF0000)) {
  421. reset_ir_status(d, i);
  422. d->buffer_status[i] = VIDEO1394_BUFFER_READY;
  423. do_gettimeofday(&d->buffer_time[i]);
  424. }
  425. }
  426. spin_unlock(&d->lock);
  427. if (waitqueue_active(&d->waitq))
  428. wake_up_interruptible(&d->waitq);
  429. }
  430. static inline void put_timestamp(struct ti_ohci *ohci, struct dma_iso_ctx * d,
  431. int n)
  432. {
  433. unsigned char* buf = d->dma.kvirt + n * d->buf_size;
  434. u32 cycleTimer;
  435. u32 timeStamp;
  436. if (n == -1) {
  437. return;
  438. }
  439. cycleTimer = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
  440. timeStamp = ((cycleTimer & 0x0fff) + d->syt_offset); /* 11059 = 450 us */
  441. timeStamp = (timeStamp % 3072 + ((timeStamp / 3072) << 12)
  442. + (cycleTimer & 0xf000)) & 0xffff;
  443. buf[6] = timeStamp >> 8;
  444. buf[7] = timeStamp & 0xff;
  445. /* if first packet is empty packet, then put timestamp into the next full one too */
  446. if ( (le32_to_cpu(d->it_prg[n][0].data[1]) >>16) == 0x008) {
  447. buf += d->packet_size;
  448. buf[6] = timeStamp >> 8;
  449. buf[7] = timeStamp & 0xff;
  450. }
  451. /* do the next buffer frame too in case of irq latency */
  452. n = d->next_buffer[n];
  453. if (n == -1) {
  454. return;
  455. }
  456. buf = d->dma.kvirt + n * d->buf_size;
  457. timeStamp += (d->last_used_cmd[n] << 12) & 0xffff;
  458. buf[6] = timeStamp >> 8;
  459. buf[7] = timeStamp & 0xff;
  460. /* if first packet is empty packet, then put timestamp into the next full one too */
  461. if ( (le32_to_cpu(d->it_prg[n][0].data[1]) >>16) == 0x008) {
  462. buf += d->packet_size;
  463. buf[6] = timeStamp >> 8;
  464. buf[7] = timeStamp & 0xff;
  465. }
  466. #if 0
  467. printk("curr: %d, next: %d, cycleTimer: %08x timeStamp: %08x\n",
  468. curr, n, cycleTimer, timeStamp);
  469. #endif
  470. }
  471. static void wakeup_dma_it_ctx(unsigned long l)
  472. {
  473. struct dma_iso_ctx *d = (struct dma_iso_ctx *) l;
  474. struct ti_ohci *ohci = d->ohci;
  475. int i;
  476. spin_lock(&d->lock);
  477. for (i = 0; i < d->num_desc; i++) {
  478. if (d->it_prg[i][d->last_used_cmd[i]].end.status &
  479. cpu_to_le32(0xFFFF0000)) {
  480. int next = d->next_buffer[i];
  481. put_timestamp(ohci, d, next);
  482. d->it_prg[i][d->last_used_cmd[i]].end.status = 0;
  483. d->buffer_status[i] = VIDEO1394_BUFFER_READY;
  484. }
  485. }
  486. spin_unlock(&d->lock);
  487. if (waitqueue_active(&d->waitq))
  488. wake_up_interruptible(&d->waitq);
  489. }
  490. static void initialize_dma_it_prg(struct dma_iso_ctx *d, int n, int sync_tag)
  491. {
  492. struct it_dma_prg *it_prg = d->it_prg[n];
  493. struct dma_prog_region *it_reg = &d->prg_reg[n];
  494. unsigned long buf = (unsigned long)d->dma.kvirt + n * d->buf_size;
  495. int i;
  496. d->last_used_cmd[n] = d->nb_cmd - 1;
  497. for (i=0;i<d->nb_cmd;i++) {
  498. it_prg[i].begin.control = cpu_to_le32(DMA_CTL_OUTPUT_MORE |
  499. DMA_CTL_IMMEDIATE | 8) ;
  500. it_prg[i].begin.address = 0;
  501. it_prg[i].begin.status = 0;
  502. it_prg[i].data[0] = cpu_to_le32(
  503. (IEEE1394_SPEED_100 << 16)
  504. | (/* tag */ 1 << 14)
  505. | (d->channel << 8)
  506. | (TCODE_ISO_DATA << 4));
  507. if (i==0) it_prg[i].data[0] |= cpu_to_le32(sync_tag);
  508. it_prg[i].data[1] = cpu_to_le32(d->packet_size << 16);
  509. it_prg[i].data[2] = 0;
  510. it_prg[i].data[3] = 0;
  511. it_prg[i].end.control = cpu_to_le32(DMA_CTL_OUTPUT_LAST |
  512. DMA_CTL_BRANCH);
  513. it_prg[i].end.address =
  514. cpu_to_le32(dma_region_offset_to_bus(&d->dma, (buf+i*d->packet_size) -
  515. (unsigned long)d->dma.kvirt));
  516. if (i<d->nb_cmd-1) {
  517. it_prg[i].end.control |= cpu_to_le32(d->packet_size);
  518. it_prg[i].begin.branchAddress =
  519. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  520. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  521. it_prg[i].end.branchAddress =
  522. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  523. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  524. } else {
  525. /* the last prg generates an interrupt */
  526. it_prg[i].end.control |= cpu_to_le32(DMA_CTL_UPDATE |
  527. DMA_CTL_IRQ | d->left_size);
  528. /* the last prg doesn't branch */
  529. it_prg[i].begin.branchAddress = 0;
  530. it_prg[i].end.branchAddress = 0;
  531. }
  532. it_prg[i].end.status = 0;
  533. }
  534. }
  535. static void initialize_dma_it_prg_var_packet_queue(
  536. struct dma_iso_ctx *d, int n, unsigned int * packet_sizes,
  537. struct ti_ohci *ohci)
  538. {
  539. struct it_dma_prg *it_prg = d->it_prg[n];
  540. struct dma_prog_region *it_reg = &d->prg_reg[n];
  541. int i;
  542. #if 0
  543. if (n != -1) {
  544. put_timestamp(ohci, d, n);
  545. }
  546. #endif
  547. d->last_used_cmd[n] = d->nb_cmd - 1;
  548. for (i = 0; i < d->nb_cmd; i++) {
  549. unsigned int size;
  550. if (packet_sizes[i] > d->packet_size) {
  551. size = d->packet_size;
  552. } else {
  553. size = packet_sizes[i];
  554. }
  555. it_prg[i].data[1] = cpu_to_le32(size << 16);
  556. it_prg[i].end.control = cpu_to_le32(DMA_CTL_OUTPUT_LAST | DMA_CTL_BRANCH);
  557. if (i < d->nb_cmd-1 && packet_sizes[i+1] != 0) {
  558. it_prg[i].end.control |= cpu_to_le32(size);
  559. it_prg[i].begin.branchAddress =
  560. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  561. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  562. it_prg[i].end.branchAddress =
  563. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  564. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  565. } else {
  566. /* the last prg generates an interrupt */
  567. it_prg[i].end.control |= cpu_to_le32(DMA_CTL_UPDATE |
  568. DMA_CTL_IRQ | size);
  569. /* the last prg doesn't branch */
  570. it_prg[i].begin.branchAddress = 0;
  571. it_prg[i].end.branchAddress = 0;
  572. d->last_used_cmd[n] = i;
  573. break;
  574. }
  575. }
  576. }
  577. static void initialize_dma_it_ctx(struct dma_iso_ctx *d, int sync_tag,
  578. unsigned int syt_offset, int flags)
  579. {
  580. struct ti_ohci *ohci = (struct ti_ohci *)d->ohci;
  581. int i;
  582. d->flags = flags;
  583. d->syt_offset = (syt_offset == 0 ? 11000 : syt_offset);
  584. ohci1394_stop_context(ohci, d->ctrlClear, NULL);
  585. for (i=0;i<d->num_desc;i++)
  586. initialize_dma_it_prg(d, i, sync_tag);
  587. /* Set up isoRecvIntMask to generate interrupts */
  588. reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1<<d->ctx);
  589. }
  590. static inline unsigned video1394_buffer_state(struct dma_iso_ctx *d,
  591. unsigned int buffer)
  592. {
  593. unsigned long flags;
  594. unsigned int ret;
  595. spin_lock_irqsave(&d->lock, flags);
  596. ret = d->buffer_status[buffer];
  597. spin_unlock_irqrestore(&d->lock, flags);
  598. return ret;
  599. }
  600. static int __video1394_ioctl(struct file *file,
  601. unsigned int cmd, unsigned long arg)
  602. {
  603. struct file_ctx *ctx = (struct file_ctx *)file->private_data;
  604. struct ti_ohci *ohci = ctx->ohci;
  605. unsigned long flags;
  606. void __user *argp = (void __user *)arg;
  607. switch(cmd)
  608. {
  609. case VIDEO1394_IOC_LISTEN_CHANNEL:
  610. case VIDEO1394_IOC_TALK_CHANNEL:
  611. {
  612. struct video1394_mmap v;
  613. u64 mask;
  614. struct dma_iso_ctx *d;
  615. int i;
  616. if (copy_from_user(&v, argp, sizeof(v)))
  617. return -EFAULT;
  618. /* if channel < 0, find lowest available one */
  619. if (v.channel < 0) {
  620. mask = (u64)0x1;
  621. for (i=0; ; i++) {
  622. if (i == ISO_CHANNELS) {
  623. PRINT(KERN_ERR, ohci->host->id,
  624. "No free channel found");
  625. return EAGAIN;
  626. }
  627. if (!(ohci->ISO_channel_usage & mask)) {
  628. v.channel = i;
  629. PRINT(KERN_INFO, ohci->host->id, "Found free channel %d", i);
  630. break;
  631. }
  632. mask = mask << 1;
  633. }
  634. } else if (v.channel >= ISO_CHANNELS) {
  635. PRINT(KERN_ERR, ohci->host->id,
  636. "Iso channel %d out of bounds", v.channel);
  637. return -EINVAL;
  638. } else {
  639. mask = (u64)0x1<<v.channel;
  640. }
  641. PRINT(KERN_INFO, ohci->host->id, "mask: %08X%08X usage: %08X%08X\n",
  642. (u32)(mask>>32),(u32)(mask&0xffffffff),
  643. (u32)(ohci->ISO_channel_usage>>32),
  644. (u32)(ohci->ISO_channel_usage&0xffffffff));
  645. if (ohci->ISO_channel_usage & mask) {
  646. PRINT(KERN_ERR, ohci->host->id,
  647. "Channel %d is already taken", v.channel);
  648. return -EBUSY;
  649. }
  650. if (v.buf_size == 0 || v.buf_size > VIDEO1394_MAX_SIZE) {
  651. PRINT(KERN_ERR, ohci->host->id,
  652. "Invalid %d length buffer requested",v.buf_size);
  653. return -EINVAL;
  654. }
  655. if (v.nb_buffers == 0 || v.nb_buffers > VIDEO1394_MAX_SIZE) {
  656. PRINT(KERN_ERR, ohci->host->id,
  657. "Invalid %d buffers requested",v.nb_buffers);
  658. return -EINVAL;
  659. }
  660. if (v.nb_buffers * v.buf_size > VIDEO1394_MAX_SIZE) {
  661. PRINT(KERN_ERR, ohci->host->id,
  662. "%d buffers of size %d bytes is too big",
  663. v.nb_buffers, v.buf_size);
  664. return -EINVAL;
  665. }
  666. if (cmd == VIDEO1394_IOC_LISTEN_CHANNEL) {
  667. d = alloc_dma_iso_ctx(ohci, OHCI_ISO_RECEIVE,
  668. v.nb_buffers, v.buf_size,
  669. v.channel, 0);
  670. if (d == NULL) {
  671. PRINT(KERN_ERR, ohci->host->id,
  672. "Couldn't allocate ir context");
  673. return -EAGAIN;
  674. }
  675. initialize_dma_ir_ctx(d, v.sync_tag, v.flags);
  676. ctx->current_ctx = d;
  677. v.buf_size = d->buf_size;
  678. list_add_tail(&d->link, &ctx->context_list);
  679. PRINT(KERN_INFO, ohci->host->id,
  680. "iso context %d listen on channel %d",
  681. d->ctx, v.channel);
  682. }
  683. else {
  684. d = alloc_dma_iso_ctx(ohci, OHCI_ISO_TRANSMIT,
  685. v.nb_buffers, v.buf_size,
  686. v.channel, v.packet_size);
  687. if (d == NULL) {
  688. PRINT(KERN_ERR, ohci->host->id,
  689. "Couldn't allocate it context");
  690. return -EAGAIN;
  691. }
  692. initialize_dma_it_ctx(d, v.sync_tag,
  693. v.syt_offset, v.flags);
  694. ctx->current_ctx = d;
  695. v.buf_size = d->buf_size;
  696. list_add_tail(&d->link, &ctx->context_list);
  697. PRINT(KERN_INFO, ohci->host->id,
  698. "Iso context %d talk on channel %d", d->ctx,
  699. v.channel);
  700. }
  701. if (copy_to_user((void *)arg, &v, sizeof(v))) {
  702. /* FIXME : free allocated dma resources */
  703. return -EFAULT;
  704. }
  705. ohci->ISO_channel_usage |= mask;
  706. return 0;
  707. }
  708. case VIDEO1394_IOC_UNLISTEN_CHANNEL:
  709. case VIDEO1394_IOC_UNTALK_CHANNEL:
  710. {
  711. int channel;
  712. u64 mask;
  713. struct dma_iso_ctx *d;
  714. if (copy_from_user(&channel, argp, sizeof(int)))
  715. return -EFAULT;
  716. if (channel < 0 || channel >= ISO_CHANNELS) {
  717. PRINT(KERN_ERR, ohci->host->id,
  718. "Iso channel %d out of bound", channel);
  719. return -EINVAL;
  720. }
  721. mask = (u64)0x1<<channel;
  722. if (!(ohci->ISO_channel_usage & mask)) {
  723. PRINT(KERN_ERR, ohci->host->id,
  724. "Channel %d is not being used", channel);
  725. return -ESRCH;
  726. }
  727. /* Mark this channel as unused */
  728. ohci->ISO_channel_usage &= ~mask;
  729. if (cmd == VIDEO1394_IOC_UNLISTEN_CHANNEL)
  730. d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, channel);
  731. else
  732. d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, channel);
  733. if (d == NULL) return -ESRCH;
  734. PRINT(KERN_INFO, ohci->host->id, "Iso context %d "
  735. "stop talking on channel %d", d->ctx, channel);
  736. free_dma_iso_ctx(d);
  737. return 0;
  738. }
  739. case VIDEO1394_IOC_LISTEN_QUEUE_BUFFER:
  740. {
  741. struct video1394_wait v;
  742. struct dma_iso_ctx *d;
  743. if (copy_from_user(&v, argp, sizeof(v)))
  744. return -EFAULT;
  745. d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, v.channel);
  746. if (d == NULL) return -EFAULT;
  747. if ((v.buffer<0) || (v.buffer>d->num_desc)) {
  748. PRINT(KERN_ERR, ohci->host->id,
  749. "Buffer %d out of range",v.buffer);
  750. return -EINVAL;
  751. }
  752. spin_lock_irqsave(&d->lock,flags);
  753. if (d->buffer_status[v.buffer]==VIDEO1394_BUFFER_QUEUED) {
  754. PRINT(KERN_ERR, ohci->host->id,
  755. "Buffer %d is already used",v.buffer);
  756. spin_unlock_irqrestore(&d->lock,flags);
  757. return -EBUSY;
  758. }
  759. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_QUEUED;
  760. if (d->last_buffer>=0)
  761. d->ir_prg[d->last_buffer][d->nb_cmd-1].branchAddress =
  762. cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[v.buffer], 0)
  763. & 0xfffffff0) | 0x1);
  764. d->last_buffer = v.buffer;
  765. d->ir_prg[d->last_buffer][d->nb_cmd-1].branchAddress = 0;
  766. spin_unlock_irqrestore(&d->lock,flags);
  767. if (!(reg_read(ohci, d->ctrlSet) & 0x8000))
  768. {
  769. DBGMSG(ohci->host->id, "Starting iso DMA ctx=%d",d->ctx);
  770. /* Tell the controller where the first program is */
  771. reg_write(ohci, d->cmdPtr,
  772. dma_prog_region_offset_to_bus(&d->prg_reg[v.buffer], 0) | 0x1);
  773. /* Run IR context */
  774. reg_write(ohci, d->ctrlSet, 0x8000);
  775. }
  776. else {
  777. /* Wake up dma context if necessary */
  778. if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
  779. PRINT(KERN_INFO, ohci->host->id,
  780. "Waking up iso dma ctx=%d", d->ctx);
  781. reg_write(ohci, d->ctrlSet, 0x1000);
  782. }
  783. }
  784. return 0;
  785. }
  786. case VIDEO1394_IOC_LISTEN_WAIT_BUFFER:
  787. case VIDEO1394_IOC_LISTEN_POLL_BUFFER:
  788. {
  789. struct video1394_wait v;
  790. struct dma_iso_ctx *d;
  791. int i;
  792. if (copy_from_user(&v, argp, sizeof(v)))
  793. return -EFAULT;
  794. d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, v.channel);
  795. if (d == NULL) return -EFAULT;
  796. if ((v.buffer<0) || (v.buffer>d->num_desc)) {
  797. PRINT(KERN_ERR, ohci->host->id,
  798. "Buffer %d out of range",v.buffer);
  799. return -EINVAL;
  800. }
  801. /*
  802. * I change the way it works so that it returns
  803. * the last received frame.
  804. */
  805. spin_lock_irqsave(&d->lock, flags);
  806. switch(d->buffer_status[v.buffer]) {
  807. case VIDEO1394_BUFFER_READY:
  808. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  809. break;
  810. case VIDEO1394_BUFFER_QUEUED:
  811. if (cmd == VIDEO1394_IOC_LISTEN_POLL_BUFFER) {
  812. /* for polling, return error code EINTR */
  813. spin_unlock_irqrestore(&d->lock, flags);
  814. return -EINTR;
  815. }
  816. spin_unlock_irqrestore(&d->lock, flags);
  817. wait_event_interruptible(d->waitq,
  818. video1394_buffer_state(d, v.buffer) ==
  819. VIDEO1394_BUFFER_READY);
  820. if (signal_pending(current))
  821. return -EINTR;
  822. spin_lock_irqsave(&d->lock, flags);
  823. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  824. break;
  825. default:
  826. PRINT(KERN_ERR, ohci->host->id,
  827. "Buffer %d is not queued",v.buffer);
  828. spin_unlock_irqrestore(&d->lock, flags);
  829. return -ESRCH;
  830. }
  831. /* set time of buffer */
  832. v.filltime = d->buffer_time[v.buffer];
  833. // printk("Buffer %d time %d\n", v.buffer, (d->buffer_time[v.buffer]).tv_usec);
  834. /*
  835. * Look ahead to see how many more buffers have been received
  836. */
  837. i=0;
  838. while (d->buffer_status[(v.buffer+1)%d->num_desc]==
  839. VIDEO1394_BUFFER_READY) {
  840. v.buffer=(v.buffer+1)%d->num_desc;
  841. i++;
  842. }
  843. spin_unlock_irqrestore(&d->lock, flags);
  844. v.buffer=i;
  845. if (copy_to_user(argp, &v, sizeof(v)))
  846. return -EFAULT;
  847. return 0;
  848. }
  849. case VIDEO1394_IOC_TALK_QUEUE_BUFFER:
  850. {
  851. struct video1394_wait v;
  852. unsigned int *psizes = NULL;
  853. struct dma_iso_ctx *d;
  854. if (copy_from_user(&v, argp, sizeof(v)))
  855. return -EFAULT;
  856. d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, v.channel);
  857. if (d == NULL) return -EFAULT;
  858. if ((v.buffer<0) || (v.buffer>d->num_desc)) {
  859. PRINT(KERN_ERR, ohci->host->id,
  860. "Buffer %d out of range",v.buffer);
  861. return -EINVAL;
  862. }
  863. if (d->flags & VIDEO1394_VARIABLE_PACKET_SIZE) {
  864. int buf_size = d->nb_cmd * sizeof(unsigned int);
  865. struct video1394_queue_variable __user *p = argp;
  866. unsigned int __user *qv;
  867. if (get_user(qv, &p->packet_sizes))
  868. return -EFAULT;
  869. psizes = kmalloc(buf_size, GFP_KERNEL);
  870. if (!psizes)
  871. return -ENOMEM;
  872. if (copy_from_user(psizes, qv, buf_size)) {
  873. kfree(psizes);
  874. return -EFAULT;
  875. }
  876. }
  877. spin_lock_irqsave(&d->lock,flags);
  878. if (d->buffer_status[v.buffer]!=VIDEO1394_BUFFER_FREE) {
  879. PRINT(KERN_ERR, ohci->host->id,
  880. "Buffer %d is already used",v.buffer);
  881. spin_unlock_irqrestore(&d->lock,flags);
  882. kfree(psizes);
  883. return -EBUSY;
  884. }
  885. if (d->flags & VIDEO1394_VARIABLE_PACKET_SIZE) {
  886. initialize_dma_it_prg_var_packet_queue(
  887. d, v.buffer, psizes,
  888. ohci);
  889. }
  890. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_QUEUED;
  891. if (d->last_buffer >= 0) {
  892. d->it_prg[d->last_buffer]
  893. [ d->last_used_cmd[d->last_buffer] ].end.branchAddress =
  894. cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[v.buffer],
  895. 0) & 0xfffffff0) | 0x3);
  896. d->it_prg[d->last_buffer]
  897. [ d->last_used_cmd[d->last_buffer] ].begin.branchAddress =
  898. cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[v.buffer],
  899. 0) & 0xfffffff0) | 0x3);
  900. d->next_buffer[d->last_buffer] = v.buffer;
  901. }
  902. d->last_buffer = v.buffer;
  903. d->next_buffer[d->last_buffer] = -1;
  904. d->it_prg[d->last_buffer][d->last_used_cmd[d->last_buffer]].end.branchAddress = 0;
  905. spin_unlock_irqrestore(&d->lock,flags);
  906. if (!(reg_read(ohci, d->ctrlSet) & 0x8000))
  907. {
  908. DBGMSG(ohci->host->id, "Starting iso transmit DMA ctx=%d",
  909. d->ctx);
  910. put_timestamp(ohci, d, d->last_buffer);
  911. /* Tell the controller where the first program is */
  912. reg_write(ohci, d->cmdPtr,
  913. dma_prog_region_offset_to_bus(&d->prg_reg[v.buffer], 0) | 0x3);
  914. /* Run IT context */
  915. reg_write(ohci, d->ctrlSet, 0x8000);
  916. }
  917. else {
  918. /* Wake up dma context if necessary */
  919. if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
  920. PRINT(KERN_INFO, ohci->host->id,
  921. "Waking up iso transmit dma ctx=%d",
  922. d->ctx);
  923. put_timestamp(ohci, d, d->last_buffer);
  924. reg_write(ohci, d->ctrlSet, 0x1000);
  925. }
  926. }
  927. kfree(psizes);
  928. return 0;
  929. }
  930. case VIDEO1394_IOC_TALK_WAIT_BUFFER:
  931. {
  932. struct video1394_wait v;
  933. struct dma_iso_ctx *d;
  934. if (copy_from_user(&v, argp, sizeof(v)))
  935. return -EFAULT;
  936. d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, v.channel);
  937. if (d == NULL) return -EFAULT;
  938. if ((v.buffer<0) || (v.buffer>d->num_desc)) {
  939. PRINT(KERN_ERR, ohci->host->id,
  940. "Buffer %d out of range",v.buffer);
  941. return -EINVAL;
  942. }
  943. switch(d->buffer_status[v.buffer]) {
  944. case VIDEO1394_BUFFER_READY:
  945. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  946. return 0;
  947. case VIDEO1394_BUFFER_QUEUED:
  948. wait_event_interruptible(d->waitq,
  949. (d->buffer_status[v.buffer] == VIDEO1394_BUFFER_READY));
  950. if (signal_pending(current))
  951. return -EINTR;
  952. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  953. return 0;
  954. default:
  955. PRINT(KERN_ERR, ohci->host->id,
  956. "Buffer %d is not queued",v.buffer);
  957. return -ESRCH;
  958. }
  959. }
  960. default:
  961. return -ENOTTY;
  962. }
  963. }
  964. static long video1394_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
  965. {
  966. int err;
  967. lock_kernel();
  968. err = __video1394_ioctl(file, cmd, arg);
  969. unlock_kernel();
  970. return err;
  971. }
  972. /*
  973. * This maps the vmalloced and reserved buffer to user space.
  974. *
  975. * FIXME:
  976. * - PAGE_READONLY should suffice!?
  977. * - remap_pfn_range is kind of inefficient for page by page remapping.
  978. * But e.g. pte_alloc() does not work in modules ... :-(
  979. */
  980. static int video1394_mmap(struct file *file, struct vm_area_struct *vma)
  981. {
  982. struct file_ctx *ctx = (struct file_ctx *)file->private_data;
  983. int res = -EINVAL;
  984. lock_kernel();
  985. if (ctx->current_ctx == NULL) {
  986. PRINT(KERN_ERR, ctx->ohci->host->id, "Current iso context not set");
  987. } else
  988. res = dma_region_mmap(&ctx->current_ctx->dma, file, vma);
  989. unlock_kernel();
  990. return res;
  991. }
  992. static int video1394_open(struct inode *inode, struct file *file)
  993. {
  994. int i = ieee1394_file_to_instance(file);
  995. struct ti_ohci *ohci;
  996. struct file_ctx *ctx;
  997. ohci = hpsb_get_hostinfo_bykey(&video1394_highlevel, i);
  998. if (ohci == NULL)
  999. return -EIO;
  1000. ctx = kmalloc(sizeof(struct file_ctx), GFP_KERNEL);
  1001. if (ctx == NULL) {
  1002. PRINT(KERN_ERR, ohci->host->id, "Cannot malloc file_ctx");
  1003. return -ENOMEM;
  1004. }
  1005. memset(ctx, 0, sizeof(struct file_ctx));
  1006. ctx->ohci = ohci;
  1007. INIT_LIST_HEAD(&ctx->context_list);
  1008. ctx->current_ctx = NULL;
  1009. file->private_data = ctx;
  1010. return 0;
  1011. }
  1012. static int video1394_release(struct inode *inode, struct file *file)
  1013. {
  1014. struct file_ctx *ctx = (struct file_ctx *)file->private_data;
  1015. struct ti_ohci *ohci = ctx->ohci;
  1016. struct list_head *lh, *next;
  1017. u64 mask;
  1018. lock_kernel();
  1019. list_for_each_safe(lh, next, &ctx->context_list) {
  1020. struct dma_iso_ctx *d;
  1021. d = list_entry(lh, struct dma_iso_ctx, link);
  1022. mask = (u64) 1 << d->channel;
  1023. if (!(ohci->ISO_channel_usage & mask))
  1024. PRINT(KERN_ERR, ohci->host->id, "On release: Channel %d "
  1025. "is not being used", d->channel);
  1026. else
  1027. ohci->ISO_channel_usage &= ~mask;
  1028. PRINT(KERN_INFO, ohci->host->id, "On release: Iso %s context "
  1029. "%d stop listening on channel %d",
  1030. d->type == OHCI_ISO_RECEIVE ? "receive" : "transmit",
  1031. d->ctx, d->channel);
  1032. free_dma_iso_ctx(d);
  1033. }
  1034. kfree(ctx);
  1035. file->private_data = NULL;
  1036. unlock_kernel();
  1037. return 0;
  1038. }
  1039. #ifdef CONFIG_COMPAT
  1040. static long video1394_compat_ioctl(struct file *f, unsigned cmd, unsigned long arg);
  1041. #endif
  1042. static struct cdev video1394_cdev;
  1043. static struct file_operations video1394_fops=
  1044. {
  1045. .owner = THIS_MODULE,
  1046. .unlocked_ioctl = video1394_ioctl,
  1047. #ifdef CONFIG_COMPAT
  1048. .compat_ioctl = video1394_compat_ioctl,
  1049. #endif
  1050. .mmap = video1394_mmap,
  1051. .open = video1394_open,
  1052. .release = video1394_release
  1053. };
  1054. /*** HOTPLUG STUFF **********************************************************/
  1055. /*
  1056. * Export information about protocols/devices supported by this driver.
  1057. */
  1058. static struct ieee1394_device_id video1394_id_table[] = {
  1059. {
  1060. .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
  1061. .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
  1062. .version = CAMERA_SW_VERSION_ENTRY & 0xffffff
  1063. },
  1064. {
  1065. .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
  1066. .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
  1067. .version = (CAMERA_SW_VERSION_ENTRY + 1) & 0xffffff
  1068. },
  1069. {
  1070. .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
  1071. .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
  1072. .version = (CAMERA_SW_VERSION_ENTRY + 2) & 0xffffff
  1073. },
  1074. { }
  1075. };
  1076. MODULE_DEVICE_TABLE(ieee1394, video1394_id_table);
  1077. static struct hpsb_protocol_driver video1394_driver = {
  1078. .name = "1394 Digital Camera Driver",
  1079. .id_table = video1394_id_table,
  1080. .driver = {
  1081. .name = VIDEO1394_DRIVER_NAME,
  1082. .bus = &ieee1394_bus_type,
  1083. },
  1084. };
  1085. static void video1394_add_host (struct hpsb_host *host)
  1086. {
  1087. struct ti_ohci *ohci;
  1088. int minor;
  1089. /* We only work with the OHCI-1394 driver */
  1090. if (strcmp(host->driver->name, OHCI1394_DRIVER_NAME))
  1091. return;
  1092. ohci = (struct ti_ohci *)host->hostdata;
  1093. if (!hpsb_create_hostinfo(&video1394_highlevel, host, 0)) {
  1094. PRINT(KERN_ERR, ohci->host->id, "Cannot allocate hostinfo");
  1095. return;
  1096. }
  1097. hpsb_set_hostinfo(&video1394_highlevel, host, ohci);
  1098. hpsb_set_hostinfo_key(&video1394_highlevel, host, ohci->host->id);
  1099. minor = IEEE1394_MINOR_BLOCK_VIDEO1394 * 16 + ohci->host->id;
  1100. class_simple_device_add(hpsb_protocol_class, MKDEV(
  1101. IEEE1394_MAJOR, minor),
  1102. NULL, "%s-%d", VIDEO1394_DRIVER_NAME, ohci->host->id);
  1103. devfs_mk_cdev(MKDEV(IEEE1394_MAJOR, minor),
  1104. S_IFCHR | S_IRUSR | S_IWUSR,
  1105. "%s/%d", VIDEO1394_DRIVER_NAME, ohci->host->id);
  1106. }
  1107. static void video1394_remove_host (struct hpsb_host *host)
  1108. {
  1109. struct ti_ohci *ohci = hpsb_get_hostinfo(&video1394_highlevel, host);
  1110. if (ohci) {
  1111. class_simple_device_remove(MKDEV(IEEE1394_MAJOR,
  1112. IEEE1394_MINOR_BLOCK_VIDEO1394 * 16 + ohci->host->id));
  1113. devfs_remove("%s/%d", VIDEO1394_DRIVER_NAME, ohci->host->id);
  1114. }
  1115. return;
  1116. }
  1117. static struct hpsb_highlevel video1394_highlevel = {
  1118. .name = VIDEO1394_DRIVER_NAME,
  1119. .add_host = video1394_add_host,
  1120. .remove_host = video1394_remove_host,
  1121. };
  1122. MODULE_AUTHOR("Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>");
  1123. MODULE_DESCRIPTION("driver for digital video on OHCI board");
  1124. MODULE_SUPPORTED_DEVICE(VIDEO1394_DRIVER_NAME);
  1125. MODULE_LICENSE("GPL");
  1126. #ifdef CONFIG_COMPAT
  1127. #define VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER \
  1128. _IOW ('#', 0x12, struct video1394_wait32)
  1129. #define VIDEO1394_IOC32_LISTEN_WAIT_BUFFER \
  1130. _IOWR('#', 0x13, struct video1394_wait32)
  1131. #define VIDEO1394_IOC32_TALK_WAIT_BUFFER \
  1132. _IOW ('#', 0x17, struct video1394_wait32)
  1133. #define VIDEO1394_IOC32_LISTEN_POLL_BUFFER \
  1134. _IOWR('#', 0x18, struct video1394_wait32)
  1135. struct video1394_wait32 {
  1136. u32 channel;
  1137. u32 buffer;
  1138. struct compat_timeval filltime;
  1139. };
  1140. static int video1394_wr_wait32(struct file *file, unsigned int cmd, unsigned long arg)
  1141. {
  1142. struct video1394_wait32 __user *argp = (void __user *)arg;
  1143. struct video1394_wait32 wait32;
  1144. struct video1394_wait wait;
  1145. mm_segment_t old_fs;
  1146. int ret;
  1147. if (copy_from_user(&wait32, argp, sizeof(wait32)))
  1148. return -EFAULT;
  1149. wait.channel = wait32.channel;
  1150. wait.buffer = wait32.buffer;
  1151. wait.filltime.tv_sec = (time_t)wait32.filltime.tv_sec;
  1152. wait.filltime.tv_usec = (suseconds_t)wait32.filltime.tv_usec;
  1153. old_fs = get_fs();
  1154. set_fs(KERNEL_DS);
  1155. if (cmd == VIDEO1394_IOC32_LISTEN_WAIT_BUFFER)
  1156. ret = video1394_ioctl(file,
  1157. VIDEO1394_IOC_LISTEN_WAIT_BUFFER,
  1158. (unsigned long) &wait);
  1159. else
  1160. ret = video1394_ioctl(file,
  1161. VIDEO1394_IOC_LISTEN_POLL_BUFFER,
  1162. (unsigned long) &wait);
  1163. set_fs(old_fs);
  1164. if (!ret) {
  1165. wait32.channel = wait.channel;
  1166. wait32.buffer = wait.buffer;
  1167. wait32.filltime.tv_sec = (int)wait.filltime.tv_sec;
  1168. wait32.filltime.tv_usec = (int)wait.filltime.tv_usec;
  1169. if (copy_to_user(argp, &wait32, sizeof(wait32)))
  1170. ret = -EFAULT;
  1171. }
  1172. return ret;
  1173. }
  1174. static int video1394_w_wait32(struct file *file, unsigned int cmd, unsigned long arg)
  1175. {
  1176. struct video1394_wait32 wait32;
  1177. struct video1394_wait wait;
  1178. mm_segment_t old_fs;
  1179. int ret;
  1180. if (copy_from_user(&wait32, (void __user *)arg, sizeof(wait32)))
  1181. return -EFAULT;
  1182. wait.channel = wait32.channel;
  1183. wait.buffer = wait32.buffer;
  1184. wait.filltime.tv_sec = (time_t)wait32.filltime.tv_sec;
  1185. wait.filltime.tv_usec = (suseconds_t)wait32.filltime.tv_usec;
  1186. old_fs = get_fs();
  1187. set_fs(KERNEL_DS);
  1188. if (cmd == VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER)
  1189. ret = video1394_ioctl(file,
  1190. VIDEO1394_IOC_LISTEN_QUEUE_BUFFER,
  1191. (unsigned long) &wait);
  1192. else
  1193. ret = video1394_ioctl(file,
  1194. VIDEO1394_IOC_TALK_WAIT_BUFFER,
  1195. (unsigned long) &wait);
  1196. set_fs(old_fs);
  1197. return ret;
  1198. }
  1199. static int video1394_queue_buf32(struct file *file, unsigned int cmd, unsigned long arg)
  1200. {
  1201. return -EFAULT; /* ??? was there before. */
  1202. return video1394_ioctl(file,
  1203. VIDEO1394_IOC_TALK_QUEUE_BUFFER, arg);
  1204. }
  1205. static long video1394_compat_ioctl(struct file *f, unsigned cmd, unsigned long arg)
  1206. {
  1207. switch (cmd) {
  1208. case VIDEO1394_IOC_LISTEN_CHANNEL:
  1209. case VIDEO1394_IOC_UNLISTEN_CHANNEL:
  1210. case VIDEO1394_IOC_TALK_CHANNEL:
  1211. case VIDEO1394_IOC_UNTALK_CHANNEL:
  1212. return video1394_ioctl(f, cmd, arg);
  1213. case VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER:
  1214. return video1394_w_wait32(f, cmd, arg);
  1215. case VIDEO1394_IOC32_LISTEN_WAIT_BUFFER:
  1216. return video1394_wr_wait32(f, cmd, arg);
  1217. case VIDEO1394_IOC_TALK_QUEUE_BUFFER:
  1218. return video1394_queue_buf32(f, cmd, arg);
  1219. case VIDEO1394_IOC32_TALK_WAIT_BUFFER:
  1220. return video1394_w_wait32(f, cmd, arg);
  1221. case VIDEO1394_IOC32_LISTEN_POLL_BUFFER:
  1222. return video1394_wr_wait32(f, cmd, arg);
  1223. default:
  1224. return -ENOIOCTLCMD;
  1225. }
  1226. }
  1227. #endif /* CONFIG_COMPAT */
  1228. static void __exit video1394_exit_module (void)
  1229. {
  1230. hpsb_unregister_protocol(&video1394_driver);
  1231. hpsb_unregister_highlevel(&video1394_highlevel);
  1232. devfs_remove(VIDEO1394_DRIVER_NAME);
  1233. cdev_del(&video1394_cdev);
  1234. PRINT_G(KERN_INFO, "Removed " VIDEO1394_DRIVER_NAME " module");
  1235. }
  1236. static int __init video1394_init_module (void)
  1237. {
  1238. int ret;
  1239. cdev_init(&video1394_cdev, &video1394_fops);
  1240. video1394_cdev.owner = THIS_MODULE;
  1241. kobject_set_name(&video1394_cdev.kobj, VIDEO1394_DRIVER_NAME);
  1242. ret = cdev_add(&video1394_cdev, IEEE1394_VIDEO1394_DEV, 16);
  1243. if (ret) {
  1244. PRINT_G(KERN_ERR, "video1394: unable to get minor device block");
  1245. return ret;
  1246. }
  1247. devfs_mk_dir(VIDEO1394_DRIVER_NAME);
  1248. hpsb_register_highlevel(&video1394_highlevel);
  1249. ret = hpsb_register_protocol(&video1394_driver);
  1250. if (ret) {
  1251. PRINT_G(KERN_ERR, "video1394: failed to register protocol");
  1252. hpsb_unregister_highlevel(&video1394_highlevel);
  1253. devfs_remove(VIDEO1394_DRIVER_NAME);
  1254. cdev_del(&video1394_cdev);
  1255. return ret;
  1256. }
  1257. PRINT_G(KERN_INFO, "Installed " VIDEO1394_DRIVER_NAME " module");
  1258. return 0;
  1259. }
  1260. module_init(video1394_init_module);
  1261. module_exit(video1394_exit_module);
  1262. MODULE_ALIAS_CHARDEV(IEEE1394_MAJOR, IEEE1394_MINOR_BLOCK_VIDEO1394 * 16);