boot.c 12 KB

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  1. /*
  2. * This file is part of wl1271
  3. *
  4. * Copyright (C) 2008-2010 Nokia Corporation
  5. *
  6. * Contact: Luciano Coelho <luciano.coelho@nokia.com>
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * version 2 as published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but
  13. * WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20. * 02110-1301 USA
  21. *
  22. */
  23. #include <linux/slab.h>
  24. #include <linux/wl12xx.h>
  25. #include <linux/export.h>
  26. #include "debug.h"
  27. #include "acx.h"
  28. #include "boot.h"
  29. #include "io.h"
  30. #include "event.h"
  31. #include "rx.h"
  32. #include "hw_ops.h"
  33. static int wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
  34. {
  35. u32 cpu_ctrl;
  36. int ret;
  37. /* 10.5.0 run the firmware (I) */
  38. ret = wlcore_read_reg(wl, REG_ECPU_CONTROL, &cpu_ctrl);
  39. if (ret < 0)
  40. goto out;
  41. /* 10.5.1 run the firmware (II) */
  42. cpu_ctrl |= flag;
  43. wlcore_write_reg(wl, REG_ECPU_CONTROL, cpu_ctrl);
  44. out:
  45. return ret;
  46. }
  47. static int wlcore_boot_parse_fw_ver(struct wl1271 *wl,
  48. struct wl1271_static_data *static_data)
  49. {
  50. int ret;
  51. strncpy(wl->chip.fw_ver_str, static_data->fw_version,
  52. sizeof(wl->chip.fw_ver_str));
  53. /* make sure the string is NULL-terminated */
  54. wl->chip.fw_ver_str[sizeof(wl->chip.fw_ver_str) - 1] = '\0';
  55. ret = sscanf(wl->chip.fw_ver_str + 4, "%u.%u.%u.%u.%u",
  56. &wl->chip.fw_ver[0], &wl->chip.fw_ver[1],
  57. &wl->chip.fw_ver[2], &wl->chip.fw_ver[3],
  58. &wl->chip.fw_ver[4]);
  59. if (ret != 5) {
  60. wl1271_warning("fw version incorrect value");
  61. memset(wl->chip.fw_ver, 0, sizeof(wl->chip.fw_ver));
  62. ret = -EINVAL;
  63. goto out;
  64. }
  65. ret = wlcore_identify_fw(wl);
  66. if (ret < 0)
  67. goto out;
  68. out:
  69. return ret;
  70. }
  71. static int wlcore_boot_static_data(struct wl1271 *wl)
  72. {
  73. struct wl1271_static_data *static_data;
  74. size_t len = sizeof(*static_data) + wl->static_data_priv_len;
  75. int ret;
  76. static_data = kmalloc(len, GFP_KERNEL);
  77. if (!static_data) {
  78. ret = -ENOMEM;
  79. goto out;
  80. }
  81. ret = wlcore_read(wl, wl->cmd_box_addr, static_data, len, false);
  82. if (ret < 0)
  83. goto out_free;
  84. ret = wlcore_boot_parse_fw_ver(wl, static_data);
  85. if (ret < 0)
  86. goto out_free;
  87. ret = wlcore_handle_static_data(wl, static_data);
  88. if (ret < 0)
  89. goto out_free;
  90. out_free:
  91. kfree(static_data);
  92. out:
  93. return ret;
  94. }
  95. static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
  96. size_t fw_data_len, u32 dest)
  97. {
  98. struct wlcore_partition_set partition;
  99. int addr, chunk_num, partition_limit;
  100. u8 *p, *chunk;
  101. int ret;
  102. /* whal_FwCtrl_LoadFwImageSm() */
  103. wl1271_debug(DEBUG_BOOT, "starting firmware upload");
  104. wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
  105. fw_data_len, CHUNK_SIZE);
  106. if ((fw_data_len % 4) != 0) {
  107. wl1271_error("firmware length not multiple of four");
  108. return -EIO;
  109. }
  110. chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
  111. if (!chunk) {
  112. wl1271_error("allocation for firmware upload chunk failed");
  113. return -ENOMEM;
  114. }
  115. memcpy(&partition, &wl->ptable[PART_DOWN], sizeof(partition));
  116. partition.mem.start = dest;
  117. wlcore_set_partition(wl, &partition);
  118. /* 10.1 set partition limit and chunk num */
  119. chunk_num = 0;
  120. partition_limit = wl->ptable[PART_DOWN].mem.size;
  121. while (chunk_num < fw_data_len / CHUNK_SIZE) {
  122. /* 10.2 update partition, if needed */
  123. addr = dest + (chunk_num + 2) * CHUNK_SIZE;
  124. if (addr > partition_limit) {
  125. addr = dest + chunk_num * CHUNK_SIZE;
  126. partition_limit = chunk_num * CHUNK_SIZE +
  127. wl->ptable[PART_DOWN].mem.size;
  128. partition.mem.start = addr;
  129. wlcore_set_partition(wl, &partition);
  130. }
  131. /* 10.3 upload the chunk */
  132. addr = dest + chunk_num * CHUNK_SIZE;
  133. p = buf + chunk_num * CHUNK_SIZE;
  134. memcpy(chunk, p, CHUNK_SIZE);
  135. wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
  136. p, addr);
  137. ret = wlcore_write(wl, addr, chunk, CHUNK_SIZE, false);
  138. if (ret < 0)
  139. goto out;
  140. chunk_num++;
  141. }
  142. /* 10.4 upload the last chunk */
  143. addr = dest + chunk_num * CHUNK_SIZE;
  144. p = buf + chunk_num * CHUNK_SIZE;
  145. memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
  146. wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
  147. fw_data_len % CHUNK_SIZE, p, addr);
  148. ret = wlcore_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);
  149. out:
  150. kfree(chunk);
  151. return ret;
  152. }
  153. int wlcore_boot_upload_firmware(struct wl1271 *wl)
  154. {
  155. u32 chunks, addr, len;
  156. int ret = 0;
  157. u8 *fw;
  158. fw = wl->fw;
  159. chunks = be32_to_cpup((__be32 *) fw);
  160. fw += sizeof(u32);
  161. wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);
  162. while (chunks--) {
  163. addr = be32_to_cpup((__be32 *) fw);
  164. fw += sizeof(u32);
  165. len = be32_to_cpup((__be32 *) fw);
  166. fw += sizeof(u32);
  167. if (len > 300000) {
  168. wl1271_info("firmware chunk too long: %u", len);
  169. return -EINVAL;
  170. }
  171. wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
  172. chunks, addr, len);
  173. ret = wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
  174. if (ret != 0)
  175. break;
  176. fw += len;
  177. }
  178. return ret;
  179. }
  180. EXPORT_SYMBOL_GPL(wlcore_boot_upload_firmware);
  181. int wlcore_boot_upload_nvs(struct wl1271 *wl)
  182. {
  183. size_t nvs_len, burst_len;
  184. int i;
  185. u32 dest_addr, val;
  186. u8 *nvs_ptr, *nvs_aligned;
  187. int ret;
  188. if (wl->nvs == NULL) {
  189. wl1271_error("NVS file is needed during boot");
  190. return -ENODEV;
  191. }
  192. if (wl->quirks & WLCORE_QUIRK_LEGACY_NVS) {
  193. struct wl1271_nvs_file *nvs =
  194. (struct wl1271_nvs_file *)wl->nvs;
  195. /*
  196. * FIXME: the LEGACY NVS image support (NVS's missing the 5GHz
  197. * band configurations) can be removed when those NVS files stop
  198. * floating around.
  199. */
  200. if (wl->nvs_len == sizeof(struct wl1271_nvs_file) ||
  201. wl->nvs_len == WL1271_INI_LEGACY_NVS_FILE_SIZE) {
  202. if (nvs->general_params.dual_mode_select)
  203. wl->enable_11a = true;
  204. }
  205. if (wl->nvs_len != sizeof(struct wl1271_nvs_file) &&
  206. (wl->nvs_len != WL1271_INI_LEGACY_NVS_FILE_SIZE ||
  207. wl->enable_11a)) {
  208. wl1271_error("nvs size is not as expected: %zu != %zu",
  209. wl->nvs_len, sizeof(struct wl1271_nvs_file));
  210. kfree(wl->nvs);
  211. wl->nvs = NULL;
  212. wl->nvs_len = 0;
  213. return -EILSEQ;
  214. }
  215. /* only the first part of the NVS needs to be uploaded */
  216. nvs_len = sizeof(nvs->nvs);
  217. nvs_ptr = (u8 *) nvs->nvs;
  218. } else {
  219. struct wl128x_nvs_file *nvs = (struct wl128x_nvs_file *)wl->nvs;
  220. if (wl->nvs_len == sizeof(struct wl128x_nvs_file)) {
  221. if (nvs->general_params.dual_mode_select)
  222. wl->enable_11a = true;
  223. } else {
  224. wl1271_error("nvs size is not as expected: %zu != %zu",
  225. wl->nvs_len,
  226. sizeof(struct wl128x_nvs_file));
  227. kfree(wl->nvs);
  228. wl->nvs = NULL;
  229. wl->nvs_len = 0;
  230. return -EILSEQ;
  231. }
  232. /* only the first part of the NVS needs to be uploaded */
  233. nvs_len = sizeof(nvs->nvs);
  234. nvs_ptr = (u8 *)nvs->nvs;
  235. }
  236. /* update current MAC address to NVS */
  237. nvs_ptr[11] = wl->addresses[0].addr[0];
  238. nvs_ptr[10] = wl->addresses[0].addr[1];
  239. nvs_ptr[6] = wl->addresses[0].addr[2];
  240. nvs_ptr[5] = wl->addresses[0].addr[3];
  241. nvs_ptr[4] = wl->addresses[0].addr[4];
  242. nvs_ptr[3] = wl->addresses[0].addr[5];
  243. /*
  244. * Layout before the actual NVS tables:
  245. * 1 byte : burst length.
  246. * 2 bytes: destination address.
  247. * n bytes: data to burst copy.
  248. *
  249. * This is ended by a 0 length, then the NVS tables.
  250. */
  251. /* FIXME: Do we need to check here whether the LSB is 1? */
  252. while (nvs_ptr[0]) {
  253. burst_len = nvs_ptr[0];
  254. dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
  255. /*
  256. * Due to our new wl1271_translate_reg_addr function,
  257. * we need to add the register partition start address
  258. * to the destination
  259. */
  260. dest_addr += wl->curr_part.reg.start;
  261. /* We move our pointer to the data */
  262. nvs_ptr += 3;
  263. for (i = 0; i < burst_len; i++) {
  264. if (nvs_ptr + 3 >= (u8 *) wl->nvs + nvs_len)
  265. goto out_badnvs;
  266. val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
  267. | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
  268. wl1271_debug(DEBUG_BOOT,
  269. "nvs burst write 0x%x: 0x%x",
  270. dest_addr, val);
  271. wl1271_write32(wl, dest_addr, val);
  272. nvs_ptr += 4;
  273. dest_addr += 4;
  274. }
  275. if (nvs_ptr >= (u8 *) wl->nvs + nvs_len)
  276. goto out_badnvs;
  277. }
  278. /*
  279. * We've reached the first zero length, the first NVS table
  280. * is located at an aligned offset which is at least 7 bytes further.
  281. * NOTE: The wl->nvs->nvs element must be first, in order to
  282. * simplify the casting, we assume it is at the beginning of
  283. * the wl->nvs structure.
  284. */
  285. nvs_ptr = (u8 *)wl->nvs +
  286. ALIGN(nvs_ptr - (u8 *)wl->nvs + 7, 4);
  287. if (nvs_ptr >= (u8 *) wl->nvs + nvs_len)
  288. goto out_badnvs;
  289. nvs_len -= nvs_ptr - (u8 *)wl->nvs;
  290. /* Now we must set the partition correctly */
  291. wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
  292. /* Copy the NVS tables to a new block to ensure alignment */
  293. nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL);
  294. if (!nvs_aligned)
  295. return -ENOMEM;
  296. /* And finally we upload the NVS tables */
  297. ret = wlcore_write_data(wl, REG_CMD_MBOX_ADDRESS, nvs_aligned, nvs_len,
  298. false);
  299. kfree(nvs_aligned);
  300. return ret;
  301. out_badnvs:
  302. wl1271_error("nvs data is malformed");
  303. return -EILSEQ;
  304. }
  305. EXPORT_SYMBOL_GPL(wlcore_boot_upload_nvs);
  306. int wlcore_boot_run_firmware(struct wl1271 *wl)
  307. {
  308. int loop, ret;
  309. u32 chip_id, intr;
  310. /* Make sure we have the boot partition */
  311. wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
  312. ret = wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
  313. if (ret < 0)
  314. return ret;
  315. ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &chip_id);
  316. if (ret < 0)
  317. return ret;
  318. wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
  319. if (chip_id != wl->chip.id) {
  320. wl1271_error("chip id doesn't match after firmware boot");
  321. return -EIO;
  322. }
  323. /* wait for init to complete */
  324. loop = 0;
  325. while (loop++ < INIT_LOOP) {
  326. udelay(INIT_LOOP_DELAY);
  327. ret = wlcore_read_reg(wl, REG_INTERRUPT_NO_CLEAR, &intr);
  328. if (ret < 0)
  329. return ret;
  330. if (intr == 0xffffffff) {
  331. wl1271_error("error reading hardware complete "
  332. "init indication");
  333. return -EIO;
  334. }
  335. /* check that ACX_INTR_INIT_COMPLETE is enabled */
  336. else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) {
  337. wlcore_write_reg(wl, REG_INTERRUPT_ACK,
  338. WL1271_ACX_INTR_INIT_COMPLETE);
  339. break;
  340. }
  341. }
  342. if (loop > INIT_LOOP) {
  343. wl1271_error("timeout waiting for the hardware to "
  344. "complete initialization");
  345. return -EIO;
  346. }
  347. /* get hardware config command mail box */
  348. ret = wlcore_read_reg(wl, REG_COMMAND_MAILBOX_PTR, &wl->cmd_box_addr);
  349. if (ret < 0)
  350. return ret;
  351. wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x", wl->cmd_box_addr);
  352. /* get hardware config event mail box */
  353. ret = wlcore_read_reg(wl, REG_EVENT_MAILBOX_PTR, &wl->mbox_ptr[0]);
  354. if (ret < 0)
  355. return ret;
  356. wl->mbox_ptr[1] = wl->mbox_ptr[0] + sizeof(struct event_mailbox);
  357. wl1271_debug(DEBUG_MAILBOX, "MBOX ptrs: 0x%x 0x%x",
  358. wl->mbox_ptr[0], wl->mbox_ptr[1]);
  359. ret = wlcore_boot_static_data(wl);
  360. if (ret < 0) {
  361. wl1271_error("error getting static data");
  362. return ret;
  363. }
  364. /*
  365. * in case of full asynchronous mode the firmware event must be
  366. * ready to receive event from the command mailbox
  367. */
  368. /* unmask required mbox events */
  369. wl->event_mask = BSS_LOSE_EVENT_ID |
  370. REGAINED_BSS_EVENT_ID |
  371. SCAN_COMPLETE_EVENT_ID |
  372. ROLE_STOP_COMPLETE_EVENT_ID |
  373. RSSI_SNR_TRIGGER_0_EVENT_ID |
  374. PSPOLL_DELIVERY_FAILURE_EVENT_ID |
  375. SOFT_GEMINI_SENSE_EVENT_ID |
  376. PERIODIC_SCAN_REPORT_EVENT_ID |
  377. PERIODIC_SCAN_COMPLETE_EVENT_ID |
  378. DUMMY_PACKET_EVENT_ID |
  379. PEER_REMOVE_COMPLETE_EVENT_ID |
  380. BA_SESSION_RX_CONSTRAINT_EVENT_ID |
  381. REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID |
  382. INACTIVE_STA_EVENT_ID |
  383. MAX_TX_RETRY_EVENT_ID |
  384. CHANNEL_SWITCH_COMPLETE_EVENT_ID;
  385. ret = wl1271_event_unmask(wl);
  386. if (ret < 0) {
  387. wl1271_error("EVENT mask setting failed");
  388. return ret;
  389. }
  390. /* set the working partition to its "running" mode offset */
  391. wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
  392. /* firmware startup completed */
  393. return 0;
  394. }
  395. EXPORT_SYMBOL_GPL(wlcore_boot_run_firmware);