mach-smdk6410.c 15 KB

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  1. /* linux/arch/arm/mach-s3c64xx/mach-smdk6410.c
  2. *
  3. * Copyright 2008 Openmoko, Inc.
  4. * Copyright 2008 Simtec Electronics
  5. * Ben Dooks <ben@simtec.co.uk>
  6. * http://armlinux.simtec.co.uk/
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/types.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/list.h>
  17. #include <linux/timer.h>
  18. #include <linux/init.h>
  19. #include <linux/serial_core.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/io.h>
  22. #include <linux/i2c.h>
  23. #include <linux/fb.h>
  24. #include <linux/gpio.h>
  25. #include <linux/delay.h>
  26. #include <linux/smsc911x.h>
  27. #include <linux/regulator/fixed.h>
  28. #ifdef CONFIG_SMDK6410_WM1190_EV1
  29. #include <linux/mfd/wm8350/core.h>
  30. #include <linux/mfd/wm8350/pmic.h>
  31. #endif
  32. #ifdef CONFIG_SMDK6410_WM1192_EV1
  33. #include <linux/mfd/wm831x/pdata.h>
  34. #endif
  35. #include <video/platform_lcd.h>
  36. #include <asm/mach/arch.h>
  37. #include <asm/mach/map.h>
  38. #include <asm/mach/irq.h>
  39. #include <mach/hardware.h>
  40. #include <mach/regs-fb.h>
  41. #include <mach/map.h>
  42. #include <asm/irq.h>
  43. #include <asm/mach-types.h>
  44. #include <plat/regs-serial.h>
  45. #include <mach/regs-modem.h>
  46. #include <mach/regs-gpio.h>
  47. #include <mach/regs-sys.h>
  48. #include <mach/regs-srom.h>
  49. #include <plat/iic.h>
  50. #include <plat/fb.h>
  51. #include <plat/gpio-cfg.h>
  52. #include <mach/s3c6410.h>
  53. #include <plat/clock.h>
  54. #include <plat/devs.h>
  55. #include <plat/cpu.h>
  56. #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
  57. #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  58. #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  59. static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
  60. [0] = {
  61. .hwport = 0,
  62. .flags = 0,
  63. .ucon = UCON,
  64. .ulcon = ULCON,
  65. .ufcon = UFCON,
  66. },
  67. [1] = {
  68. .hwport = 1,
  69. .flags = 0,
  70. .ucon = UCON,
  71. .ulcon = ULCON,
  72. .ufcon = UFCON,
  73. },
  74. [2] = {
  75. .hwport = 2,
  76. .flags = 0,
  77. .ucon = UCON,
  78. .ulcon = ULCON,
  79. .ufcon = UFCON,
  80. },
  81. [3] = {
  82. .hwport = 3,
  83. .flags = 0,
  84. .ucon = UCON,
  85. .ulcon = ULCON,
  86. .ufcon = UFCON,
  87. },
  88. };
  89. /* framebuffer and LCD setup. */
  90. /* GPF15 = LCD backlight control
  91. * GPF13 => Panel power
  92. * GPN5 = LCD nRESET signal
  93. * PWM_TOUT1 => backlight brightness
  94. */
  95. static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
  96. unsigned int power)
  97. {
  98. if (power) {
  99. gpio_direction_output(S3C64XX_GPF(13), 1);
  100. gpio_direction_output(S3C64XX_GPF(15), 1);
  101. /* fire nRESET on power up */
  102. gpio_direction_output(S3C64XX_GPN(5), 0);
  103. msleep(10);
  104. gpio_direction_output(S3C64XX_GPN(5), 1);
  105. msleep(1);
  106. } else {
  107. gpio_direction_output(S3C64XX_GPF(15), 0);
  108. gpio_direction_output(S3C64XX_GPF(13), 0);
  109. }
  110. }
  111. static struct plat_lcd_data smdk6410_lcd_power_data = {
  112. .set_power = smdk6410_lcd_power_set,
  113. };
  114. static struct platform_device smdk6410_lcd_powerdev = {
  115. .name = "platform-lcd",
  116. .dev.parent = &s3c_device_fb.dev,
  117. .dev.platform_data = &smdk6410_lcd_power_data,
  118. };
  119. static struct s3c_fb_pd_win smdk6410_fb_win0 = {
  120. /* this is to ensure we use win0 */
  121. .win_mode = {
  122. .pixclock = 41094,
  123. .left_margin = 8,
  124. .right_margin = 13,
  125. .upper_margin = 7,
  126. .lower_margin = 5,
  127. .hsync_len = 3,
  128. .vsync_len = 1,
  129. .xres = 800,
  130. .yres = 480,
  131. },
  132. .max_bpp = 32,
  133. .default_bpp = 16,
  134. };
  135. /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
  136. static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
  137. .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
  138. .win[0] = &smdk6410_fb_win0,
  139. .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
  140. .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
  141. };
  142. /*
  143. * Configuring Ethernet on SMDK6410
  144. *
  145. * Both CS8900A and LAN9115 chips share one chip select mediated by CFG6.
  146. * The constant address below corresponds to nCS1
  147. *
  148. * 1) Set CFGB2 p3 ON others off, no other CFGB selects "ethernet"
  149. * 2) CFG6 needs to be switched to "LAN9115" side
  150. */
  151. static struct resource smdk6410_smsc911x_resources[] = {
  152. [0] = {
  153. .start = S3C64XX_PA_XM0CSN1,
  154. .end = S3C64XX_PA_XM0CSN1 + SZ_64K - 1,
  155. .flags = IORESOURCE_MEM,
  156. },
  157. [1] = {
  158. .start = S3C_EINT(10),
  159. .end = S3C_EINT(10),
  160. .flags = IORESOURCE_IRQ | IRQ_TYPE_LEVEL_LOW,
  161. },
  162. };
  163. static struct smsc911x_platform_config smdk6410_smsc911x_pdata = {
  164. .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
  165. .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
  166. .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
  167. .phy_interface = PHY_INTERFACE_MODE_MII,
  168. };
  169. static struct platform_device smdk6410_smsc911x = {
  170. .name = "smsc911x",
  171. .id = -1,
  172. .num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources),
  173. .resource = &smdk6410_smsc911x_resources[0],
  174. .dev = {
  175. .platform_data = &smdk6410_smsc911x_pdata,
  176. },
  177. };
  178. #ifdef CONFIG_REGULATOR
  179. static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = {
  180. {
  181. /* WM8580 */
  182. .supply = "PVDD",
  183. .dev_name = "0-001b",
  184. },
  185. {
  186. /* WM8580 */
  187. .supply = "AVDD",
  188. .dev_name = "0-001b",
  189. },
  190. };
  191. static struct regulator_init_data smdk6410_b_pwr_5v_data = {
  192. .constraints = {
  193. .always_on = 1,
  194. },
  195. .num_consumer_supplies = ARRAY_SIZE(smdk6410_b_pwr_5v_consumers),
  196. .consumer_supplies = smdk6410_b_pwr_5v_consumers,
  197. };
  198. static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = {
  199. .supply_name = "B_PWR_5V",
  200. .microvolts = 5000000,
  201. .init_data = &smdk6410_b_pwr_5v_data,
  202. .gpio = -EINVAL,
  203. };
  204. static struct platform_device smdk6410_b_pwr_5v = {
  205. .name = "reg-fixed-voltage",
  206. .id = -1,
  207. .dev = {
  208. .platform_data = &smdk6410_b_pwr_5v_pdata,
  209. },
  210. };
  211. #endif
  212. static struct map_desc smdk6410_iodesc[] = {};
  213. static struct platform_device *smdk6410_devices[] __initdata = {
  214. #ifdef CONFIG_SMDK6410_SD_CH0
  215. &s3c_device_hsmmc0,
  216. #endif
  217. #ifdef CONFIG_SMDK6410_SD_CH1
  218. &s3c_device_hsmmc1,
  219. #endif
  220. &s3c_device_i2c0,
  221. &s3c_device_i2c1,
  222. &s3c_device_fb,
  223. &s3c_device_ohci,
  224. &s3c_device_usb_hsotg,
  225. #ifdef CONFIG_REGULATOR
  226. &smdk6410_b_pwr_5v,
  227. #endif
  228. &smdk6410_lcd_powerdev,
  229. &smdk6410_smsc911x,
  230. };
  231. #ifdef CONFIG_REGULATOR
  232. /* ARM core */
  233. static struct regulator_consumer_supply smdk6410_vddarm_consumers[] = {
  234. {
  235. .supply = "vddarm",
  236. }
  237. };
  238. /* VDDARM, BUCK1 on J5 */
  239. static struct regulator_init_data smdk6410_vddarm = {
  240. .constraints = {
  241. .name = "PVDD_ARM",
  242. .min_uV = 1000000,
  243. .max_uV = 1300000,
  244. .always_on = 1,
  245. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
  246. },
  247. .num_consumer_supplies = ARRAY_SIZE(smdk6410_vddarm_consumers),
  248. .consumer_supplies = smdk6410_vddarm_consumers,
  249. };
  250. /* VDD_INT, BUCK2 on J5 */
  251. static struct regulator_init_data smdk6410_vddint = {
  252. .constraints = {
  253. .name = "PVDD_INT",
  254. .min_uV = 1000000,
  255. .max_uV = 1200000,
  256. .always_on = 1,
  257. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
  258. },
  259. };
  260. /* VDD_HI, LDO3 on J5 */
  261. static struct regulator_init_data smdk6410_vddhi = {
  262. .constraints = {
  263. .name = "PVDD_HI",
  264. .always_on = 1,
  265. },
  266. };
  267. /* VDD_PLL, LDO2 on J5 */
  268. static struct regulator_init_data smdk6410_vddpll = {
  269. .constraints = {
  270. .name = "PVDD_PLL",
  271. .always_on = 1,
  272. },
  273. };
  274. /* VDD_UH_MMC, LDO5 on J5 */
  275. static struct regulator_init_data smdk6410_vdduh_mmc = {
  276. .constraints = {
  277. .name = "PVDD_UH/PVDD_MMC",
  278. .always_on = 1,
  279. },
  280. };
  281. /* VCCM3BT, LDO8 on J5 */
  282. static struct regulator_init_data smdk6410_vccmc3bt = {
  283. .constraints = {
  284. .name = "PVCCM3BT",
  285. .always_on = 1,
  286. },
  287. };
  288. /* VCCM2MTV, LDO11 on J5 */
  289. static struct regulator_init_data smdk6410_vccm2mtv = {
  290. .constraints = {
  291. .name = "PVCCM2MTV",
  292. .always_on = 1,
  293. },
  294. };
  295. /* VDD_LCD, LDO12 on J5 */
  296. static struct regulator_init_data smdk6410_vddlcd = {
  297. .constraints = {
  298. .name = "PVDD_LCD",
  299. .always_on = 1,
  300. },
  301. };
  302. /* VDD_OTGI, LDO9 on J5 */
  303. static struct regulator_init_data smdk6410_vddotgi = {
  304. .constraints = {
  305. .name = "PVDD_OTGI",
  306. .always_on = 1,
  307. },
  308. };
  309. /* VDD_OTG, LDO14 on J5 */
  310. static struct regulator_init_data smdk6410_vddotg = {
  311. .constraints = {
  312. .name = "PVDD_OTG",
  313. .always_on = 1,
  314. },
  315. };
  316. /* VDD_ALIVE, LDO15 on J5 */
  317. static struct regulator_init_data smdk6410_vddalive = {
  318. .constraints = {
  319. .name = "PVDD_ALIVE",
  320. .always_on = 1,
  321. },
  322. };
  323. /* VDD_AUDIO, VLDO_AUDIO on J5 */
  324. static struct regulator_init_data smdk6410_vddaudio = {
  325. .constraints = {
  326. .name = "PVDD_AUDIO",
  327. .always_on = 1,
  328. },
  329. };
  330. #endif
  331. #ifdef CONFIG_SMDK6410_WM1190_EV1
  332. /* S3C64xx internal logic & PLL */
  333. static struct regulator_init_data wm8350_dcdc1_data = {
  334. .constraints = {
  335. .name = "PVDD_INT/PVDD_PLL",
  336. .min_uV = 1200000,
  337. .max_uV = 1200000,
  338. .always_on = 1,
  339. .apply_uV = 1,
  340. },
  341. };
  342. /* Memory */
  343. static struct regulator_init_data wm8350_dcdc3_data = {
  344. .constraints = {
  345. .name = "PVDD_MEM",
  346. .min_uV = 1800000,
  347. .max_uV = 1800000,
  348. .always_on = 1,
  349. .state_mem = {
  350. .uV = 1800000,
  351. .mode = REGULATOR_MODE_NORMAL,
  352. .enabled = 1,
  353. },
  354. .initial_state = PM_SUSPEND_MEM,
  355. },
  356. };
  357. /* USB, EXT, PCM, ADC/DAC, USB, MMC */
  358. static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
  359. {
  360. /* WM8580 */
  361. .supply = "DVDD",
  362. .dev_name = "0-001b",
  363. },
  364. };
  365. static struct regulator_init_data wm8350_dcdc4_data = {
  366. .constraints = {
  367. .name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
  368. .min_uV = 3000000,
  369. .max_uV = 3000000,
  370. .always_on = 1,
  371. },
  372. .num_consumer_supplies = ARRAY_SIZE(wm8350_dcdc4_consumers),
  373. .consumer_supplies = wm8350_dcdc4_consumers,
  374. };
  375. /* OTGi/1190-EV1 HPVDD & AVDD */
  376. static struct regulator_init_data wm8350_ldo4_data = {
  377. .constraints = {
  378. .name = "PVDD_OTGI/HPVDD/AVDD",
  379. .min_uV = 1200000,
  380. .max_uV = 1200000,
  381. .apply_uV = 1,
  382. .always_on = 1,
  383. },
  384. };
  385. static struct {
  386. int regulator;
  387. struct regulator_init_data *initdata;
  388. } wm1190_regulators[] = {
  389. { WM8350_DCDC_1, &wm8350_dcdc1_data },
  390. { WM8350_DCDC_3, &wm8350_dcdc3_data },
  391. { WM8350_DCDC_4, &wm8350_dcdc4_data },
  392. { WM8350_DCDC_6, &smdk6410_vddarm },
  393. { WM8350_LDO_1, &smdk6410_vddalive },
  394. { WM8350_LDO_2, &smdk6410_vddotg },
  395. { WM8350_LDO_3, &smdk6410_vddlcd },
  396. { WM8350_LDO_4, &wm8350_ldo4_data },
  397. };
  398. static int __init smdk6410_wm8350_init(struct wm8350 *wm8350)
  399. {
  400. int i;
  401. /* Configure the IRQ line */
  402. s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);
  403. /* Instantiate the regulators */
  404. for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++)
  405. wm8350_register_regulator(wm8350,
  406. wm1190_regulators[i].regulator,
  407. wm1190_regulators[i].initdata);
  408. return 0;
  409. }
  410. static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = {
  411. .init = smdk6410_wm8350_init,
  412. .irq_high = 1,
  413. .irq_base = IRQ_BOARD_START,
  414. };
  415. #endif
  416. #ifdef CONFIG_SMDK6410_WM1192_EV1
  417. static int wm1192_pre_init(struct wm831x *wm831x)
  418. {
  419. /* Configure the IRQ line */
  420. s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);
  421. return 0;
  422. }
  423. static struct wm831x_backlight_pdata wm1192_backlight_pdata = {
  424. .isink = 1,
  425. .max_uA = 27554,
  426. };
  427. static struct regulator_init_data wm1192_dcdc3 = {
  428. .constraints = {
  429. .name = "PVDD_MEM/PVDD_GPS",
  430. .always_on = 1,
  431. },
  432. };
  433. static struct regulator_consumer_supply wm1192_ldo1_consumers[] = {
  434. { .supply = "DVDD", .dev_name = "0-001b", }, /* WM8580 */
  435. };
  436. static struct regulator_init_data wm1192_ldo1 = {
  437. .constraints = {
  438. .name = "PVDD_LCD/PVDD_EXT",
  439. .always_on = 1,
  440. },
  441. .consumer_supplies = wm1192_ldo1_consumers,
  442. .num_consumer_supplies = ARRAY_SIZE(wm1192_ldo1_consumers),
  443. };
  444. static struct wm831x_status_pdata wm1192_led7_pdata = {
  445. .name = "LED7:green:",
  446. };
  447. static struct wm831x_status_pdata wm1192_led8_pdata = {
  448. .name = "LED8:green:",
  449. };
  450. static struct wm831x_pdata smdk6410_wm1192_pdata = {
  451. .pre_init = wm1192_pre_init,
  452. .irq_base = IRQ_BOARD_START,
  453. .backlight = &wm1192_backlight_pdata,
  454. .dcdc = {
  455. &smdk6410_vddarm, /* DCDC1 */
  456. &smdk6410_vddint, /* DCDC2 */
  457. &wm1192_dcdc3,
  458. },
  459. .ldo = {
  460. &wm1192_ldo1, /* LDO1 */
  461. &smdk6410_vdduh_mmc, /* LDO2 */
  462. NULL, /* LDO3 NC */
  463. &smdk6410_vddotgi, /* LDO4 */
  464. &smdk6410_vddotg, /* LDO5 */
  465. &smdk6410_vddhi, /* LDO6 */
  466. &smdk6410_vddaudio, /* LDO7 */
  467. &smdk6410_vccm2mtv, /* LDO8 */
  468. &smdk6410_vddpll, /* LDO9 */
  469. &smdk6410_vccmc3bt, /* LDO10 */
  470. &smdk6410_vddalive, /* LDO11 */
  471. },
  472. .status = {
  473. &wm1192_led7_pdata,
  474. &wm1192_led8_pdata,
  475. },
  476. };
  477. #endif
  478. static struct i2c_board_info i2c_devs0[] __initdata = {
  479. { I2C_BOARD_INFO("24c08", 0x50), },
  480. { I2C_BOARD_INFO("wm8580", 0x1b), },
  481. #ifdef CONFIG_SMDK6410_WM1192_EV1
  482. { I2C_BOARD_INFO("wm8312", 0x34),
  483. .platform_data = &smdk6410_wm1192_pdata,
  484. .irq = S3C_EINT(12),
  485. },
  486. #endif
  487. #ifdef CONFIG_SMDK6410_WM1190_EV1
  488. { I2C_BOARD_INFO("wm8350", 0x1a),
  489. .platform_data = &smdk6410_wm8350_pdata,
  490. .irq = S3C_EINT(12),
  491. },
  492. #endif
  493. };
  494. static struct i2c_board_info i2c_devs1[] __initdata = {
  495. { I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */
  496. };
  497. static void __init smdk6410_map_io(void)
  498. {
  499. u32 tmp;
  500. s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
  501. s3c24xx_init_clocks(12000000);
  502. s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
  503. /* set the LCD type */
  504. tmp = __raw_readl(S3C64XX_SPCON);
  505. tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
  506. tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
  507. __raw_writel(tmp, S3C64XX_SPCON);
  508. /* remove the lcd bypass */
  509. tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
  510. tmp &= ~MIFPCON_LCD_BYPASS;
  511. __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
  512. }
  513. static void __init smdk6410_machine_init(void)
  514. {
  515. u32 cs1;
  516. s3c_i2c0_set_platdata(NULL);
  517. s3c_i2c1_set_platdata(NULL);
  518. s3c_fb_set_platdata(&smdk6410_lcd_pdata);
  519. /* configure nCS1 width to 16 bits */
  520. cs1 = __raw_readl(S3C64XX_SROM_BW) &
  521. ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
  522. cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
  523. (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
  524. (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
  525. S3C64XX_SROM_BW__NCS1__SHIFT;
  526. __raw_writel(cs1, S3C64XX_SROM_BW);
  527. /* set timing for nCS1 suitable for ethernet chip */
  528. __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
  529. (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
  530. (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
  531. (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
  532. (0xe << S3C64XX_SROM_BCX__TACC__SHIFT) |
  533. (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
  534. (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
  535. gpio_request(S3C64XX_GPN(5), "LCD power");
  536. gpio_request(S3C64XX_GPF(13), "LCD power");
  537. gpio_request(S3C64XX_GPF(15), "LCD power");
  538. i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
  539. i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
  540. platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
  541. }
  542. MACHINE_START(SMDK6410, "SMDK6410")
  543. /* Maintainer: Ben Dooks <ben@fluff.org> */
  544. .phys_io = S3C_PA_UART & 0xfff00000,
  545. .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
  546. .boot_params = S3C64XX_PA_SDRAM + 0x100,
  547. .init_irq = s3c6410_init_irq,
  548. .map_io = smdk6410_map_io,
  549. .init_machine = smdk6410_machine_init,
  550. .timer = &s3c24xx_timer,
  551. MACHINE_END