board-trimslice.c 4.4 KB

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  1. /*
  2. * arch/arm/mach-tegra/board-trimslice.c
  3. *
  4. * Copyright (C) 2011 CompuLab, Ltd.
  5. * Author: Mike Rapoport <mike@compulab.co.il>
  6. *
  7. * Based on board-harmony.c
  8. * Copyright (C) 2010 Google, Inc.
  9. *
  10. * This software is licensed under the terms of the GNU General Public
  11. * License version 2, as published by the Free Software Foundation, and
  12. * may be copied, distributed, and modified under those terms.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/init.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/serial_8250.h>
  24. #include <linux/io.h>
  25. #include <linux/i2c.h>
  26. #include <linux/gpio.h>
  27. #include <linux/platform_data/tegra_usb.h>
  28. #include <asm/hardware/gic.h>
  29. #include <asm/mach-types.h>
  30. #include <asm/mach/arch.h>
  31. #include <asm/setup.h>
  32. #include <mach/iomap.h>
  33. #include <mach/sdhci.h>
  34. #include "board.h"
  35. #include "clock.h"
  36. #include "devices.h"
  37. #include "gpio-names.h"
  38. #include "board-trimslice.h"
  39. static struct plat_serial8250_port debug_uart_platform_data[] = {
  40. {
  41. .membase = IO_ADDRESS(TEGRA_UARTA_BASE),
  42. .mapbase = TEGRA_UARTA_BASE,
  43. .irq = INT_UARTA,
  44. .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
  45. .type = PORT_TEGRA,
  46. .iotype = UPIO_MEM,
  47. .regshift = 2,
  48. .uartclk = 216000000,
  49. }, {
  50. .flags = 0
  51. }
  52. };
  53. static struct platform_device debug_uart = {
  54. .name = "serial8250",
  55. .id = PLAT8250_DEV_PLATFORM,
  56. .dev = {
  57. .platform_data = debug_uart_platform_data,
  58. },
  59. };
  60. static struct tegra_sdhci_platform_data sdhci_pdata1 = {
  61. .cd_gpio = -1,
  62. .wp_gpio = -1,
  63. .power_gpio = -1,
  64. };
  65. static struct tegra_sdhci_platform_data sdhci_pdata4 = {
  66. .cd_gpio = TRIMSLICE_GPIO_SD4_CD,
  67. .wp_gpio = TRIMSLICE_GPIO_SD4_WP,
  68. .power_gpio = -1,
  69. };
  70. static struct platform_device trimslice_audio_device = {
  71. .name = "tegra-snd-trimslice",
  72. .id = 0,
  73. };
  74. static struct platform_device *trimslice_devices[] __initdata = {
  75. &debug_uart,
  76. &tegra_sdhci_device1,
  77. &tegra_sdhci_device4,
  78. &tegra_i2s_device1,
  79. &tegra_das_device,
  80. &tegra_pcm_device,
  81. &trimslice_audio_device,
  82. };
  83. static struct i2c_board_info trimslice_i2c3_board_info[] = {
  84. {
  85. I2C_BOARD_INFO("tlv320aic23", 0x1a),
  86. },
  87. {
  88. I2C_BOARD_INFO("em3027", 0x56),
  89. },
  90. };
  91. static void trimslice_i2c_init(void)
  92. {
  93. platform_device_register(&tegra_i2c_device1);
  94. platform_device_register(&tegra_i2c_device2);
  95. platform_device_register(&tegra_i2c_device3);
  96. i2c_register_board_info(2, trimslice_i2c3_board_info,
  97. ARRAY_SIZE(trimslice_i2c3_board_info));
  98. }
  99. static void trimslice_usb_init(void)
  100. {
  101. struct tegra_ehci_platform_data *pdata;
  102. pdata = tegra_ehci1_device.dev.platform_data;
  103. pdata->vbus_gpio = TRIMSLICE_GPIO_USB1_MODE;
  104. tegra_ehci2_ulpi_phy_config.reset_gpio = TEGRA_GPIO_PV0;
  105. platform_device_register(&tegra_ehci3_device);
  106. platform_device_register(&tegra_ehci2_device);
  107. platform_device_register(&tegra_ehci1_device);
  108. }
  109. static void __init tegra_trimslice_fixup(struct tag *tags, char **cmdline,
  110. struct meminfo *mi)
  111. {
  112. mi->nr_banks = 2;
  113. mi->bank[0].start = PHYS_OFFSET;
  114. mi->bank[0].size = 448 * SZ_1M;
  115. mi->bank[1].start = SZ_512M;
  116. mi->bank[1].size = SZ_512M;
  117. }
  118. static __initdata struct tegra_clk_init_table trimslice_clk_init_table[] = {
  119. /* name parent rate enabled */
  120. { "uarta", "pll_p", 216000000, true },
  121. { "pll_a", "pll_p_out1", 56448000, true },
  122. { "pll_a_out0", "pll_a", 11289600, true },
  123. { "cdev1", NULL, 0, true },
  124. { "i2s1", "pll_a_out0", 11289600, false},
  125. { NULL, NULL, 0, 0},
  126. };
  127. static int __init tegra_trimslice_pci_init(void)
  128. {
  129. if (!machine_is_trimslice())
  130. return 0;
  131. return tegra_pcie_init(true, true);
  132. }
  133. subsys_initcall(tegra_trimslice_pci_init);
  134. static void __init tegra_trimslice_init(void)
  135. {
  136. tegra_clk_init_from_table(trimslice_clk_init_table);
  137. trimslice_pinmux_init();
  138. tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
  139. tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
  140. platform_add_devices(trimslice_devices, ARRAY_SIZE(trimslice_devices));
  141. trimslice_i2c_init();
  142. trimslice_usb_init();
  143. }
  144. MACHINE_START(TRIMSLICE, "trimslice")
  145. .atag_offset = 0x100,
  146. .fixup = tegra_trimslice_fixup,
  147. .map_io = tegra_map_common_io,
  148. .init_early = tegra20_init_early,
  149. .init_irq = tegra_init_irq,
  150. .handle_irq = gic_handle_irq,
  151. .timer = &tegra_timer,
  152. .init_machine = tegra_trimslice_init,
  153. .restart = tegra_assert_system_reset,
  154. MACHINE_END