ps3vram.c 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766
  1. /**
  2. * ps3vram - Use extra PS3 video ram as MTD block device.
  3. *
  4. * Copyright (c) 2007-2008 Jim Paris <jim@jtan.com>
  5. * Added support RSX DMA Vivien Chappelier <vivien.chappelier@free.fr>
  6. */
  7. #include <linux/io.h>
  8. #include <linux/init.h>
  9. #include <linux/kernel.h>
  10. #include <linux/list.h>
  11. #include <linux/module.h>
  12. #include <linux/moduleparam.h>
  13. #include <linux/slab.h>
  14. #include <linux/version.h>
  15. #include <linux/gfp.h>
  16. #include <linux/delay.h>
  17. #include <linux/mtd/mtd.h>
  18. #include <asm/lv1call.h>
  19. #include <asm/ps3.h>
  20. #define DEVICE_NAME "ps3vram"
  21. #define XDR_BUF_SIZE (2 * 1024 * 1024) /* XDR buffer (must be 1MiB aligned) */
  22. #define XDR_IOIF 0x0c000000
  23. #define FIFO_BASE XDR_IOIF
  24. #define FIFO_SIZE (64 * 1024)
  25. #define DMA_PAGE_SIZE (4 * 1024)
  26. #define CACHE_PAGE_SIZE (256 * 1024)
  27. #define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE)
  28. #define CACHE_OFFSET CACHE_PAGE_SIZE
  29. #define FIFO_OFFSET 0
  30. #define CTRL_PUT 0x10
  31. #define CTRL_GET 0x11
  32. #define CTRL_TOP 0x15
  33. #define UPLOAD_SUBCH 1
  34. #define DOWNLOAD_SUBCH 2
  35. #define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
  36. #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104
  37. #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT 0x601
  38. struct mtd_info ps3vram_mtd;
  39. #define CACHE_PAGE_PRESENT 1
  40. #define CACHE_PAGE_DIRTY 2
  41. struct ps3vram_tag {
  42. unsigned int address;
  43. unsigned int flags;
  44. };
  45. struct ps3vram_cache {
  46. unsigned int page_count;
  47. unsigned int page_size;
  48. struct ps3vram_tag *tags;
  49. };
  50. struct ps3vram_priv {
  51. u64 memory_handle;
  52. u64 context_handle;
  53. u32 *ctrl;
  54. u32 *reports;
  55. u8 *base;
  56. u8 *xdr_buf;
  57. u32 *fifo_base;
  58. u32 *fifo_ptr;
  59. struct device *dev;
  60. struct ps3vram_cache cache;
  61. /* Used to serialize cache/DMA operations */
  62. struct mutex lock;
  63. };
  64. #define DMA_NOTIFIER_HANDLE_BASE 0x66604200 /* first DMA notifier handle */
  65. #define DMA_NOTIFIER_OFFSET_BASE 0x1000 /* first DMA notifier offset */
  66. #define DMA_NOTIFIER_SIZE 0x40
  67. #define NOTIFIER 7 /* notifier used for completion report */
  68. /* A trailing '-' means to subtract off ps3fb_videomemory.size */
  69. char *size = "256M-";
  70. module_param(size, charp, 0);
  71. MODULE_PARM_DESC(size, "memory size");
  72. static u32 *ps3vram_get_notifier(u32 *reports, int notifier)
  73. {
  74. return (void *) reports +
  75. DMA_NOTIFIER_OFFSET_BASE +
  76. DMA_NOTIFIER_SIZE * notifier;
  77. }
  78. static void ps3vram_notifier_reset(struct mtd_info *mtd)
  79. {
  80. int i;
  81. struct ps3vram_priv *priv = mtd->priv;
  82. u32 *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
  83. for (i = 0; i < 4; i++)
  84. notify[i] = 0xffffffff;
  85. }
  86. static int ps3vram_notifier_wait(struct mtd_info *mtd, unsigned int timeout_ms)
  87. {
  88. struct ps3vram_priv *priv = mtd->priv;
  89. u32 *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
  90. unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
  91. do {
  92. if (!notify[3])
  93. return 0;
  94. msleep(1);
  95. } while (time_before(jiffies, timeout));
  96. return -ETIMEDOUT;
  97. }
  98. static void ps3vram_init_ring(struct mtd_info *mtd)
  99. {
  100. struct ps3vram_priv *priv = mtd->priv;
  101. priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET;
  102. priv->ctrl[CTRL_GET] = FIFO_BASE + FIFO_OFFSET;
  103. }
  104. static int ps3vram_wait_ring(struct mtd_info *mtd, unsigned int timeout_ms)
  105. {
  106. struct ps3vram_priv *priv = mtd->priv;
  107. unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
  108. do {
  109. if (priv->ctrl[CTRL_PUT] == priv->ctrl[CTRL_GET])
  110. return 0;
  111. msleep(1);
  112. } while (time_before(jiffies, timeout));
  113. dev_dbg(priv->dev, "%s:%d: FIFO timeout (%08x/%08x/%08x)\n", __func__,
  114. __LINE__, priv->ctrl[CTRL_PUT], priv->ctrl[CTRL_GET],
  115. priv->ctrl[CTRL_TOP]);
  116. return -ETIMEDOUT;
  117. }
  118. static void ps3vram_out_ring(struct ps3vram_priv *priv, u32 data)
  119. {
  120. *(priv->fifo_ptr)++ = data;
  121. }
  122. static void ps3vram_begin_ring(struct ps3vram_priv *priv, u32 chan,
  123. u32 tag, u32 size)
  124. {
  125. ps3vram_out_ring(priv, (size << 18) | (chan << 13) | tag);
  126. }
  127. static void ps3vram_rewind_ring(struct mtd_info *mtd)
  128. {
  129. struct ps3vram_priv *priv = mtd->priv;
  130. u64 status;
  131. ps3vram_out_ring(priv, 0x20000000 | (FIFO_BASE + FIFO_OFFSET));
  132. priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET;
  133. /* asking the HV for a blit will kick the fifo */
  134. status = lv1_gpu_context_attribute(priv->context_handle,
  135. L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT,
  136. 0, 0, 0, 0);
  137. if (status)
  138. dev_err(priv->dev, "%s:%d: lv1_gpu_context_attribute failed\n",
  139. __func__, __LINE__);
  140. priv->fifo_ptr = priv->fifo_base;
  141. }
  142. static void ps3vram_fire_ring(struct mtd_info *mtd)
  143. {
  144. struct ps3vram_priv *priv = mtd->priv;
  145. u64 status;
  146. mutex_lock(&ps3_gpu_mutex);
  147. priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET +
  148. (priv->fifo_ptr - priv->fifo_base) * sizeof(u32);
  149. /* asking the HV for a blit will kick the fifo */
  150. status = lv1_gpu_context_attribute(priv->context_handle,
  151. L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT,
  152. 0, 0, 0, 0);
  153. if (status)
  154. dev_err(priv->dev, "%s:%d: lv1_gpu_context_attribute failed\n",
  155. __func__, __LINE__);
  156. if ((priv->fifo_ptr - priv->fifo_base) * sizeof(u32) >
  157. FIFO_SIZE - 1024) {
  158. dev_dbg(priv->dev, "%s:%d: fifo full, rewinding\n", __func__,
  159. __LINE__);
  160. ps3vram_wait_ring(mtd, 200);
  161. ps3vram_rewind_ring(mtd);
  162. }
  163. mutex_unlock(&ps3_gpu_mutex);
  164. }
  165. static void ps3vram_bind(struct mtd_info *mtd)
  166. {
  167. struct ps3vram_priv *priv = mtd->priv;
  168. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0, 1);
  169. ps3vram_out_ring(priv, 0x31337303);
  170. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x180, 3);
  171. ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
  172. ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
  173. ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
  174. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0, 1);
  175. ps3vram_out_ring(priv, 0x3137c0de);
  176. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x180, 3);
  177. ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
  178. ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
  179. ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
  180. ps3vram_fire_ring(mtd);
  181. }
  182. static int ps3vram_upload(struct mtd_info *mtd, unsigned int src_offset,
  183. unsigned int dst_offset, int len, int count)
  184. {
  185. struct ps3vram_priv *priv = mtd->priv;
  186. ps3vram_begin_ring(priv, UPLOAD_SUBCH,
  187. NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
  188. ps3vram_out_ring(priv, XDR_IOIF + src_offset);
  189. ps3vram_out_ring(priv, dst_offset);
  190. ps3vram_out_ring(priv, len);
  191. ps3vram_out_ring(priv, len);
  192. ps3vram_out_ring(priv, len);
  193. ps3vram_out_ring(priv, count);
  194. ps3vram_out_ring(priv, (1 << 8) | 1);
  195. ps3vram_out_ring(priv, 0);
  196. ps3vram_notifier_reset(mtd);
  197. ps3vram_begin_ring(priv, UPLOAD_SUBCH,
  198. NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
  199. ps3vram_out_ring(priv, 0);
  200. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x100, 1);
  201. ps3vram_out_ring(priv, 0);
  202. ps3vram_fire_ring(mtd);
  203. if (ps3vram_notifier_wait(mtd, 200) < 0) {
  204. dev_dbg(priv->dev, "%s:%d: notifier timeout\n", __func__,
  205. __LINE__);
  206. return -1;
  207. }
  208. return 0;
  209. }
  210. static int ps3vram_download(struct mtd_info *mtd, unsigned int src_offset,
  211. unsigned int dst_offset, int len, int count)
  212. {
  213. struct ps3vram_priv *priv = mtd->priv;
  214. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
  215. NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
  216. ps3vram_out_ring(priv, src_offset);
  217. ps3vram_out_ring(priv, XDR_IOIF + dst_offset);
  218. ps3vram_out_ring(priv, len);
  219. ps3vram_out_ring(priv, len);
  220. ps3vram_out_ring(priv, len);
  221. ps3vram_out_ring(priv, count);
  222. ps3vram_out_ring(priv, (1 << 8) | 1);
  223. ps3vram_out_ring(priv, 0);
  224. ps3vram_notifier_reset(mtd);
  225. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
  226. NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
  227. ps3vram_out_ring(priv, 0);
  228. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x100, 1);
  229. ps3vram_out_ring(priv, 0);
  230. ps3vram_fire_ring(mtd);
  231. if (ps3vram_notifier_wait(mtd, 200) < 0) {
  232. dev_dbg(priv->dev, "%s:%d: notifier timeout\n", __func__,
  233. __LINE__);
  234. return -1;
  235. }
  236. return 0;
  237. }
  238. static void ps3vram_cache_evict(struct mtd_info *mtd, int entry)
  239. {
  240. struct ps3vram_priv *priv = mtd->priv;
  241. struct ps3vram_cache *cache = &priv->cache;
  242. if (cache->tags[entry].flags & CACHE_PAGE_DIRTY) {
  243. dev_dbg(priv->dev, "%s:%d: flushing %d : 0x%08x\n", __func__,
  244. __LINE__, entry, cache->tags[entry].address);
  245. if (ps3vram_upload(mtd,
  246. CACHE_OFFSET + entry * cache->page_size,
  247. cache->tags[entry].address,
  248. DMA_PAGE_SIZE,
  249. cache->page_size / DMA_PAGE_SIZE) < 0) {
  250. dev_dbg(priv->dev, "%s:%d: failed to upload from "
  251. "0x%x to 0x%x size 0x%x\n", __func__, __LINE__,
  252. entry * cache->page_size,
  253. cache->tags[entry].address, cache->page_size);
  254. }
  255. cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY;
  256. }
  257. }
  258. static void ps3vram_cache_load(struct mtd_info *mtd, int entry,
  259. unsigned int address)
  260. {
  261. struct ps3vram_priv *priv = mtd->priv;
  262. struct ps3vram_cache *cache = &priv->cache;
  263. dev_dbg(priv->dev, "%s:%d: fetching %d : 0x%08x\n", __func__, __LINE__,
  264. entry, address);
  265. if (ps3vram_download(mtd,
  266. address,
  267. CACHE_OFFSET + entry * cache->page_size,
  268. DMA_PAGE_SIZE,
  269. cache->page_size / DMA_PAGE_SIZE) < 0) {
  270. dev_err(priv->dev, "%s:%d: failed to download from "
  271. "0x%x to 0x%x size 0x%x\n", __func__, __LINE__, address,
  272. entry * cache->page_size, cache->page_size);
  273. }
  274. cache->tags[entry].address = address;
  275. cache->tags[entry].flags |= CACHE_PAGE_PRESENT;
  276. }
  277. static void ps3vram_cache_flush(struct mtd_info *mtd)
  278. {
  279. struct ps3vram_priv *priv = mtd->priv;
  280. struct ps3vram_cache *cache = &priv->cache;
  281. int i;
  282. dev_dbg(priv->dev, "%s:%d: FLUSH\n", __func__, __LINE__);
  283. for (i = 0; i < cache->page_count; i++) {
  284. ps3vram_cache_evict(mtd, i);
  285. cache->tags[i].flags = 0;
  286. }
  287. }
  288. static unsigned int ps3vram_cache_match(struct mtd_info *mtd, loff_t address)
  289. {
  290. struct ps3vram_priv *priv = mtd->priv;
  291. struct ps3vram_cache *cache = &priv->cache;
  292. unsigned int base;
  293. unsigned int offset;
  294. int i;
  295. static int counter;
  296. offset = (unsigned int) (address & (cache->page_size - 1));
  297. base = (unsigned int) (address - offset);
  298. /* fully associative check */
  299. for (i = 0; i < cache->page_count; i++) {
  300. if ((cache->tags[i].flags & CACHE_PAGE_PRESENT) &&
  301. cache->tags[i].address == base) {
  302. dev_dbg(priv->dev, "%s:%d: found entry %d : 0x%08x\n",
  303. __func__, __LINE__, i, cache->tags[i].address);
  304. return i;
  305. }
  306. }
  307. /* choose a random entry */
  308. i = (jiffies + (counter++)) % cache->page_count;
  309. dev_dbg(priv->dev, "%s:%d: using entry %d\n", __func__, __LINE__, i);
  310. ps3vram_cache_evict(mtd, i);
  311. ps3vram_cache_load(mtd, i, base);
  312. return i;
  313. }
  314. static int ps3vram_cache_init(struct mtd_info *mtd)
  315. {
  316. struct ps3vram_priv *priv = mtd->priv;
  317. priv->cache.page_count = CACHE_PAGE_COUNT;
  318. priv->cache.page_size = CACHE_PAGE_SIZE;
  319. priv->cache.tags = kzalloc(sizeof(struct ps3vram_tag) *
  320. CACHE_PAGE_COUNT, GFP_KERNEL);
  321. if (priv->cache.tags == NULL) {
  322. dev_err(priv->dev, "%s:%d: could not allocate cache tags\n",
  323. __func__, __LINE__);
  324. return -ENOMEM;
  325. }
  326. dev_info(priv->dev, "created ram cache: %d entries, %d KiB each\n",
  327. CACHE_PAGE_COUNT, CACHE_PAGE_SIZE / 1024);
  328. return 0;
  329. }
  330. static void ps3vram_cache_cleanup(struct mtd_info *mtd)
  331. {
  332. struct ps3vram_priv *priv = mtd->priv;
  333. ps3vram_cache_flush(mtd);
  334. kfree(priv->cache.tags);
  335. }
  336. static int ps3vram_erase(struct mtd_info *mtd, struct erase_info *instr)
  337. {
  338. struct ps3vram_priv *priv = mtd->priv;
  339. if (instr->addr + instr->len > mtd->size)
  340. return -EINVAL;
  341. mutex_lock(&priv->lock);
  342. ps3vram_cache_flush(mtd);
  343. /* Set bytes to 0xFF */
  344. memset(priv->base + instr->addr, 0xFF, instr->len);
  345. mutex_unlock(&priv->lock);
  346. instr->state = MTD_ERASE_DONE;
  347. mtd_erase_callback(instr);
  348. return 0;
  349. }
  350. static int ps3vram_read(struct mtd_info *mtd, loff_t from, size_t len,
  351. size_t *retlen, u_char *buf)
  352. {
  353. struct ps3vram_priv *priv = mtd->priv;
  354. unsigned int cached, count;
  355. dev_dbg(priv->dev, "%s:%d: from=0x%08x len=0x%zx\n", __func__, __LINE__,
  356. (unsigned int)from, len);
  357. if (from >= mtd->size)
  358. return -EINVAL;
  359. if (len > mtd->size - from)
  360. len = mtd->size - from;
  361. /* Copy from vram to buf */
  362. count = len;
  363. while (count) {
  364. unsigned int offset, avail;
  365. unsigned int entry;
  366. offset = (unsigned int) (from & (priv->cache.page_size - 1));
  367. avail = priv->cache.page_size - offset;
  368. mutex_lock(&priv->lock);
  369. entry = ps3vram_cache_match(mtd, from);
  370. cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
  371. dev_dbg(priv->dev, "%s:%d: from=%08x cached=%08x offset=%08x "
  372. "avail=%08x count=%08x\n", __func__, __LINE__,
  373. (unsigned int)from, cached, offset, avail, count);
  374. if (avail > count)
  375. avail = count;
  376. memcpy(buf, priv->xdr_buf + cached, avail);
  377. mutex_unlock(&priv->lock);
  378. buf += avail;
  379. count -= avail;
  380. from += avail;
  381. }
  382. *retlen = len;
  383. return 0;
  384. }
  385. static int ps3vram_write(struct mtd_info *mtd, loff_t to, size_t len,
  386. size_t *retlen, const u_char *buf)
  387. {
  388. struct ps3vram_priv *priv = mtd->priv;
  389. unsigned int cached, count;
  390. if (to >= mtd->size)
  391. return -EINVAL;
  392. if (len > mtd->size - to)
  393. len = mtd->size - to;
  394. /* Copy from buf to vram */
  395. count = len;
  396. while (count) {
  397. unsigned int offset, avail;
  398. unsigned int entry;
  399. offset = (unsigned int) (to & (priv->cache.page_size - 1));
  400. avail = priv->cache.page_size - offset;
  401. mutex_lock(&priv->lock);
  402. entry = ps3vram_cache_match(mtd, to);
  403. cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
  404. dev_dbg(priv->dev, "%s:%d: to=%08x cached=%08x offset=%08x "
  405. "avail=%08x count=%08x\n", __func__, __LINE__,
  406. (unsigned int)to, cached, offset, avail, count);
  407. if (avail > count)
  408. avail = count;
  409. memcpy(priv->xdr_buf + cached, buf, avail);
  410. priv->cache.tags[entry].flags |= CACHE_PAGE_DIRTY;
  411. mutex_unlock(&priv->lock);
  412. buf += avail;
  413. count -= avail;
  414. to += avail;
  415. }
  416. *retlen = len;
  417. return 0;
  418. }
  419. static int __devinit ps3vram_probe(struct ps3_system_bus_device *dev)
  420. {
  421. struct ps3vram_priv *priv;
  422. int status;
  423. u64 ddr_lpar;
  424. u64 ctrl_lpar;
  425. u64 info_lpar;
  426. u64 reports_lpar;
  427. u64 ddr_size;
  428. u64 reports_size;
  429. int ret = -ENOMEM;
  430. char *rest;
  431. ret = -EIO;
  432. ps3vram_mtd.priv = kzalloc(sizeof(struct ps3vram_priv), GFP_KERNEL);
  433. if (!ps3vram_mtd.priv)
  434. goto out;
  435. priv = ps3vram_mtd.priv;
  436. mutex_init(&priv->lock);
  437. priv->dev = &dev->core;
  438. /* Allocate XDR buffer (1MiB aligned) */
  439. priv->xdr_buf = (void *)__get_free_pages(GFP_KERNEL,
  440. get_order(XDR_BUF_SIZE));
  441. if (priv->xdr_buf == NULL) {
  442. dev_dbg(&dev->core, "%s:%d: could not allocate XDR buffer\n",
  443. __func__, __LINE__);
  444. ret = -ENOMEM;
  445. goto out_free_priv;
  446. }
  447. /* Put FIFO at begginning of XDR buffer */
  448. priv->fifo_base = (u32 *) (priv->xdr_buf + FIFO_OFFSET);
  449. priv->fifo_ptr = priv->fifo_base;
  450. /* XXX: Need to open GPU, in case ps3fb or snd_ps3 aren't loaded */
  451. if (ps3_open_hv_device(dev)) {
  452. dev_err(&dev->core, "%s:%d: ps3_open_hv_device failed\n",
  453. __func__, __LINE__);
  454. ret = -EAGAIN;
  455. goto out_close_gpu;
  456. }
  457. /* Request memory */
  458. status = -1;
  459. ddr_size = memparse(size, &rest);
  460. if (*rest == '-')
  461. ddr_size -= ps3fb_videomemory.size;
  462. ddr_size = ALIGN(ddr_size, 1024*1024);
  463. if (ddr_size <= 0) {
  464. dev_err(&dev->core, "%s:%d: specified size is too small\n",
  465. __func__, __LINE__);
  466. ret = -EINVAL;
  467. goto out_close_gpu;
  468. }
  469. while (ddr_size > 0) {
  470. status = lv1_gpu_memory_allocate(ddr_size, 0, 0, 0, 0,
  471. &priv->memory_handle,
  472. &ddr_lpar);
  473. if (!status)
  474. break;
  475. ddr_size -= 1024*1024;
  476. }
  477. if (status || ddr_size <= 0) {
  478. dev_err(&dev->core, "%s:%d: lv1_gpu_memory_allocate failed\n",
  479. __func__, __LINE__);
  480. ret = -ENOMEM;
  481. goto out_free_xdr_buf;
  482. }
  483. /* Request context */
  484. status = lv1_gpu_context_allocate(priv->memory_handle,
  485. 0,
  486. &priv->context_handle,
  487. &ctrl_lpar,
  488. &info_lpar,
  489. &reports_lpar,
  490. &reports_size);
  491. if (status) {
  492. dev_err(&dev->core, "%s:%d: lv1_gpu_context_allocate failed\n",
  493. __func__, __LINE__);
  494. ret = -ENOMEM;
  495. goto out_free_memory;
  496. }
  497. /* Map XDR buffer to RSX */
  498. status = lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
  499. ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)),
  500. XDR_BUF_SIZE, 0);
  501. if (status) {
  502. dev_err(&dev->core, "%s:%d: lv1_gpu_context_iomap failed\n",
  503. __func__, __LINE__);
  504. ret = -ENOMEM;
  505. goto out_free_context;
  506. }
  507. priv->base = ioremap(ddr_lpar, ddr_size);
  508. if (!priv->base) {
  509. dev_err(&dev->core, "%s:%d: ioremap failed\n", __func__,
  510. __LINE__);
  511. ret = -ENOMEM;
  512. goto out_free_context;
  513. }
  514. priv->ctrl = ioremap(ctrl_lpar, 64 * 1024);
  515. if (!priv->ctrl) {
  516. dev_err(&dev->core, "%s:%d: ioremap failed\n", __func__,
  517. __LINE__);
  518. ret = -ENOMEM;
  519. goto out_unmap_vram;
  520. }
  521. priv->reports = ioremap(reports_lpar, reports_size);
  522. if (!priv->reports) {
  523. dev_err(&dev->core, "%s:%d: ioremap failed\n", __func__,
  524. __LINE__);
  525. ret = -ENOMEM;
  526. goto out_unmap_ctrl;
  527. }
  528. mutex_lock(&ps3_gpu_mutex);
  529. ps3vram_init_ring(&ps3vram_mtd);
  530. mutex_unlock(&ps3_gpu_mutex);
  531. ps3vram_mtd.name = "ps3vram";
  532. ps3vram_mtd.size = ddr_size;
  533. ps3vram_mtd.flags = MTD_CAP_RAM;
  534. ps3vram_mtd.erase = ps3vram_erase;
  535. ps3vram_mtd.point = NULL;
  536. ps3vram_mtd.unpoint = NULL;
  537. ps3vram_mtd.read = ps3vram_read;
  538. ps3vram_mtd.write = ps3vram_write;
  539. ps3vram_mtd.owner = THIS_MODULE;
  540. ps3vram_mtd.type = MTD_RAM;
  541. ps3vram_mtd.erasesize = CACHE_PAGE_SIZE;
  542. ps3vram_mtd.writesize = 1;
  543. ps3vram_bind(&ps3vram_mtd);
  544. mutex_lock(&ps3_gpu_mutex);
  545. ret = ps3vram_wait_ring(&ps3vram_mtd, 100);
  546. mutex_unlock(&ps3_gpu_mutex);
  547. if (ret < 0) {
  548. dev_err(&dev->core, "%s:%d: failed to initialize channels\n",
  549. __func__, __LINE__);
  550. ret = -ETIMEDOUT;
  551. goto out_unmap_reports;
  552. }
  553. ps3vram_cache_init(&ps3vram_mtd);
  554. if (add_mtd_device(&ps3vram_mtd)) {
  555. dev_err(&dev->core, "%s:%d: add_mtd_device failed\n",
  556. __func__, __LINE__);
  557. ret = -EAGAIN;
  558. goto out_cache_cleanup;
  559. }
  560. dev_info(&dev->core, "reserved %u MiB of gpu memory\n",
  561. (unsigned int)(ddr_size / 1024 / 1024));
  562. return 0;
  563. out_cache_cleanup:
  564. ps3vram_cache_cleanup(&ps3vram_mtd);
  565. out_unmap_reports:
  566. iounmap(priv->reports);
  567. out_unmap_ctrl:
  568. iounmap(priv->ctrl);
  569. out_unmap_vram:
  570. iounmap(priv->base);
  571. out_free_context:
  572. lv1_gpu_context_free(priv->context_handle);
  573. out_free_memory:
  574. lv1_gpu_memory_free(priv->memory_handle);
  575. out_close_gpu:
  576. ps3_close_hv_device(dev);
  577. out_free_xdr_buf:
  578. free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
  579. out_free_priv:
  580. kfree(ps3vram_mtd.priv);
  581. ps3vram_mtd.priv = NULL;
  582. out:
  583. return ret;
  584. }
  585. static int ps3vram_shutdown(struct ps3_system_bus_device *dev)
  586. {
  587. struct ps3vram_priv *priv;
  588. priv = ps3vram_mtd.priv;
  589. del_mtd_device(&ps3vram_mtd);
  590. ps3vram_cache_cleanup(&ps3vram_mtd);
  591. iounmap(priv->reports);
  592. iounmap(priv->ctrl);
  593. iounmap(priv->base);
  594. lv1_gpu_context_free(priv->context_handle);
  595. lv1_gpu_memory_free(priv->memory_handle);
  596. ps3_close_hv_device(dev);
  597. free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
  598. kfree(priv);
  599. return 0;
  600. }
  601. static struct ps3_system_bus_driver ps3vram_driver = {
  602. .match_id = PS3_MATCH_ID_GPU,
  603. .match_sub_id = PS3_MATCH_SUB_ID_GPU_RAMDISK,
  604. .core.name = DEVICE_NAME,
  605. .core.owner = THIS_MODULE,
  606. .probe = ps3vram_probe,
  607. .remove = ps3vram_shutdown,
  608. .shutdown = ps3vram_shutdown,
  609. };
  610. static int __init ps3vram_init(void)
  611. {
  612. return ps3_system_bus_driver_register(&ps3vram_driver);
  613. }
  614. static void __exit ps3vram_exit(void)
  615. {
  616. ps3_system_bus_driver_unregister(&ps3vram_driver);
  617. }
  618. module_init(ps3vram_init);
  619. module_exit(ps3vram_exit);
  620. MODULE_LICENSE("GPL");
  621. MODULE_AUTHOR("Jim Paris <jim@jtan.com>");
  622. MODULE_DESCRIPTION("MTD driver for PS3 video RAM");
  623. MODULE_ALIAS(PS3_MODULE_ALIAS_GPU_RAMDISK);