smsc95xx.c 34 KB

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  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2007-2008 SMSC
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18. *
  19. *****************************************************************************/
  20. #include <linux/module.h>
  21. #include <linux/kmod.h>
  22. #include <linux/init.h>
  23. #include <linux/netdevice.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/mii.h>
  27. #include <linux/usb.h>
  28. #include <linux/crc32.h>
  29. #include <linux/usb/usbnet.h>
  30. #include "smsc95xx.h"
  31. #define SMSC_CHIPNAME "smsc95xx"
  32. #define SMSC_DRIVER_VERSION "1.0.4"
  33. #define HS_USB_PKT_SIZE (512)
  34. #define FS_USB_PKT_SIZE (64)
  35. #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
  36. #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
  37. #define DEFAULT_BULK_IN_DELAY (0x00002000)
  38. #define MAX_SINGLE_PACKET_SIZE (2048)
  39. #define LAN95XX_EEPROM_MAGIC (0x9500)
  40. #define EEPROM_MAC_OFFSET (0x01)
  41. #define DEFAULT_TX_CSUM_ENABLE (true)
  42. #define DEFAULT_RX_CSUM_ENABLE (true)
  43. #define SMSC95XX_INTERNAL_PHY_ID (1)
  44. #define SMSC95XX_TX_OVERHEAD (8)
  45. #define SMSC95XX_TX_OVERHEAD_CSUM (12)
  46. struct smsc95xx_priv {
  47. u32 mac_cr;
  48. spinlock_t mac_cr_lock;
  49. bool use_tx_csum;
  50. bool use_rx_csum;
  51. };
  52. struct usb_context {
  53. struct usb_ctrlrequest req;
  54. struct usbnet *dev;
  55. };
  56. static int turbo_mode = true;
  57. module_param(turbo_mode, bool, 0644);
  58. MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
  59. static int smsc95xx_read_reg(struct usbnet *dev, u32 index, u32 *data)
  60. {
  61. u32 *buf = kmalloc(4, GFP_KERNEL);
  62. int ret;
  63. BUG_ON(!dev);
  64. if (!buf)
  65. return -ENOMEM;
  66. ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0),
  67. USB_VENDOR_REQUEST_READ_REGISTER,
  68. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  69. 00, index, buf, 4, USB_CTRL_GET_TIMEOUT);
  70. if (unlikely(ret < 0))
  71. netdev_warn(dev->net, "Failed to read register index 0x%08x\n", index);
  72. le32_to_cpus(buf);
  73. *data = *buf;
  74. kfree(buf);
  75. return ret;
  76. }
  77. static int smsc95xx_write_reg(struct usbnet *dev, u32 index, u32 data)
  78. {
  79. u32 *buf = kmalloc(4, GFP_KERNEL);
  80. int ret;
  81. BUG_ON(!dev);
  82. if (!buf)
  83. return -ENOMEM;
  84. *buf = data;
  85. cpu_to_le32s(buf);
  86. ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0),
  87. USB_VENDOR_REQUEST_WRITE_REGISTER,
  88. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  89. 00, index, buf, 4, USB_CTRL_SET_TIMEOUT);
  90. if (unlikely(ret < 0))
  91. netdev_warn(dev->net, "Failed to write register index 0x%08x\n", index);
  92. kfree(buf);
  93. return ret;
  94. }
  95. /* Loop until the read is completed with timeout
  96. * called with phy_mutex held */
  97. static int smsc95xx_phy_wait_not_busy(struct usbnet *dev)
  98. {
  99. unsigned long start_time = jiffies;
  100. u32 val;
  101. do {
  102. smsc95xx_read_reg(dev, MII_ADDR, &val);
  103. if (!(val & MII_BUSY_))
  104. return 0;
  105. } while (!time_after(jiffies, start_time + HZ));
  106. return -EIO;
  107. }
  108. static int smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
  109. {
  110. struct usbnet *dev = netdev_priv(netdev);
  111. u32 val, addr;
  112. mutex_lock(&dev->phy_mutex);
  113. /* confirm MII not busy */
  114. if (smsc95xx_phy_wait_not_busy(dev)) {
  115. netdev_warn(dev->net, "MII is busy in smsc95xx_mdio_read\n");
  116. mutex_unlock(&dev->phy_mutex);
  117. return -EIO;
  118. }
  119. /* set the address, index & direction (read from PHY) */
  120. phy_id &= dev->mii.phy_id_mask;
  121. idx &= dev->mii.reg_num_mask;
  122. addr = (phy_id << 11) | (idx << 6) | MII_READ_;
  123. smsc95xx_write_reg(dev, MII_ADDR, addr);
  124. if (smsc95xx_phy_wait_not_busy(dev)) {
  125. netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
  126. mutex_unlock(&dev->phy_mutex);
  127. return -EIO;
  128. }
  129. smsc95xx_read_reg(dev, MII_DATA, &val);
  130. mutex_unlock(&dev->phy_mutex);
  131. return (u16)(val & 0xFFFF);
  132. }
  133. static void smsc95xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
  134. int regval)
  135. {
  136. struct usbnet *dev = netdev_priv(netdev);
  137. u32 val, addr;
  138. mutex_lock(&dev->phy_mutex);
  139. /* confirm MII not busy */
  140. if (smsc95xx_phy_wait_not_busy(dev)) {
  141. netdev_warn(dev->net, "MII is busy in smsc95xx_mdio_write\n");
  142. mutex_unlock(&dev->phy_mutex);
  143. return;
  144. }
  145. val = regval;
  146. smsc95xx_write_reg(dev, MII_DATA, val);
  147. /* set the address, index & direction (write to PHY) */
  148. phy_id &= dev->mii.phy_id_mask;
  149. idx &= dev->mii.reg_num_mask;
  150. addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
  151. smsc95xx_write_reg(dev, MII_ADDR, addr);
  152. if (smsc95xx_phy_wait_not_busy(dev))
  153. netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
  154. mutex_unlock(&dev->phy_mutex);
  155. }
  156. static int smsc95xx_wait_eeprom(struct usbnet *dev)
  157. {
  158. unsigned long start_time = jiffies;
  159. u32 val;
  160. do {
  161. smsc95xx_read_reg(dev, E2P_CMD, &val);
  162. if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
  163. break;
  164. udelay(40);
  165. } while (!time_after(jiffies, start_time + HZ));
  166. if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
  167. netdev_warn(dev->net, "EEPROM read operation timeout\n");
  168. return -EIO;
  169. }
  170. return 0;
  171. }
  172. static int smsc95xx_eeprom_confirm_not_busy(struct usbnet *dev)
  173. {
  174. unsigned long start_time = jiffies;
  175. u32 val;
  176. do {
  177. smsc95xx_read_reg(dev, E2P_CMD, &val);
  178. if (!(val & E2P_CMD_BUSY_))
  179. return 0;
  180. udelay(40);
  181. } while (!time_after(jiffies, start_time + HZ));
  182. netdev_warn(dev->net, "EEPROM is busy\n");
  183. return -EIO;
  184. }
  185. static int smsc95xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
  186. u8 *data)
  187. {
  188. u32 val;
  189. int i, ret;
  190. BUG_ON(!dev);
  191. BUG_ON(!data);
  192. ret = smsc95xx_eeprom_confirm_not_busy(dev);
  193. if (ret)
  194. return ret;
  195. for (i = 0; i < length; i++) {
  196. val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
  197. smsc95xx_write_reg(dev, E2P_CMD, val);
  198. ret = smsc95xx_wait_eeprom(dev);
  199. if (ret < 0)
  200. return ret;
  201. smsc95xx_read_reg(dev, E2P_DATA, &val);
  202. data[i] = val & 0xFF;
  203. offset++;
  204. }
  205. return 0;
  206. }
  207. static int smsc95xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
  208. u8 *data)
  209. {
  210. u32 val;
  211. int i, ret;
  212. BUG_ON(!dev);
  213. BUG_ON(!data);
  214. ret = smsc95xx_eeprom_confirm_not_busy(dev);
  215. if (ret)
  216. return ret;
  217. /* Issue write/erase enable command */
  218. val = E2P_CMD_BUSY_ | E2P_CMD_EWEN_;
  219. smsc95xx_write_reg(dev, E2P_CMD, val);
  220. ret = smsc95xx_wait_eeprom(dev);
  221. if (ret < 0)
  222. return ret;
  223. for (i = 0; i < length; i++) {
  224. /* Fill data register */
  225. val = data[i];
  226. smsc95xx_write_reg(dev, E2P_DATA, val);
  227. /* Send "write" command */
  228. val = E2P_CMD_BUSY_ | E2P_CMD_WRITE_ | (offset & E2P_CMD_ADDR_);
  229. smsc95xx_write_reg(dev, E2P_CMD, val);
  230. ret = smsc95xx_wait_eeprom(dev);
  231. if (ret < 0)
  232. return ret;
  233. offset++;
  234. }
  235. return 0;
  236. }
  237. static void smsc95xx_async_cmd_callback(struct urb *urb)
  238. {
  239. struct usb_context *usb_context = urb->context;
  240. struct usbnet *dev = usb_context->dev;
  241. int status = urb->status;
  242. if (status < 0)
  243. netdev_warn(dev->net, "async callback failed with %d\n", status);
  244. kfree(usb_context);
  245. usb_free_urb(urb);
  246. }
  247. static int smsc95xx_write_reg_async(struct usbnet *dev, u16 index, u32 *data)
  248. {
  249. struct usb_context *usb_context;
  250. int status;
  251. struct urb *urb;
  252. const u16 size = 4;
  253. urb = usb_alloc_urb(0, GFP_ATOMIC);
  254. if (!urb) {
  255. netdev_warn(dev->net, "Error allocating URB\n");
  256. return -ENOMEM;
  257. }
  258. usb_context = kmalloc(sizeof(struct usb_context), GFP_ATOMIC);
  259. if (usb_context == NULL) {
  260. netdev_warn(dev->net, "Error allocating control msg\n");
  261. usb_free_urb(urb);
  262. return -ENOMEM;
  263. }
  264. usb_context->req.bRequestType =
  265. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE;
  266. usb_context->req.bRequest = USB_VENDOR_REQUEST_WRITE_REGISTER;
  267. usb_context->req.wValue = 00;
  268. usb_context->req.wIndex = cpu_to_le16(index);
  269. usb_context->req.wLength = cpu_to_le16(size);
  270. usb_fill_control_urb(urb, dev->udev, usb_sndctrlpipe(dev->udev, 0),
  271. (void *)&usb_context->req, data, size,
  272. smsc95xx_async_cmd_callback,
  273. (void *)usb_context);
  274. status = usb_submit_urb(urb, GFP_ATOMIC);
  275. if (status < 0) {
  276. netdev_warn(dev->net, "Error submitting control msg, sts=%d\n",
  277. status);
  278. kfree(usb_context);
  279. usb_free_urb(urb);
  280. }
  281. return status;
  282. }
  283. /* returns hash bit number for given MAC address
  284. * example:
  285. * 01 00 5E 00 00 01 -> returns bit number 31 */
  286. static unsigned int smsc95xx_hash(char addr[ETH_ALEN])
  287. {
  288. return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
  289. }
  290. static void smsc95xx_set_multicast(struct net_device *netdev)
  291. {
  292. struct usbnet *dev = netdev_priv(netdev);
  293. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  294. u32 hash_hi = 0;
  295. u32 hash_lo = 0;
  296. unsigned long flags;
  297. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  298. if (dev->net->flags & IFF_PROMISC) {
  299. if (netif_msg_drv(dev))
  300. netdev_dbg(dev->net, "promiscuous mode enabled\n");
  301. pdata->mac_cr |= MAC_CR_PRMS_;
  302. pdata->mac_cr &= ~(MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  303. } else if (dev->net->flags & IFF_ALLMULTI) {
  304. if (netif_msg_drv(dev))
  305. netdev_dbg(dev->net, "receive all multicast enabled\n");
  306. pdata->mac_cr |= MAC_CR_MCPAS_;
  307. pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_HPFILT_);
  308. } else if (!netdev_mc_empty(dev->net)) {
  309. struct dev_mc_list *mc_list = dev->net->mc_list;
  310. int count = 0;
  311. pdata->mac_cr |= MAC_CR_HPFILT_;
  312. pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
  313. while (mc_list) {
  314. count++;
  315. if (mc_list->dmi_addrlen == ETH_ALEN) {
  316. u32 bitnum = smsc95xx_hash(mc_list->dmi_addr);
  317. u32 mask = 0x01 << (bitnum & 0x1F);
  318. if (bitnum & 0x20)
  319. hash_hi |= mask;
  320. else
  321. hash_lo |= mask;
  322. } else {
  323. netdev_warn(dev->net, "dmi_addrlen != 6\n");
  324. }
  325. mc_list = mc_list->next;
  326. }
  327. if (count != ((u32) netdev_mc_count(dev->net)))
  328. netdev_warn(dev->net, "mc_count != dev->mc_count\n");
  329. if (netif_msg_drv(dev))
  330. netdev_dbg(dev->net, "HASHH=0x%08X, HASHL=0x%08X\n",
  331. hash_hi, hash_lo);
  332. } else {
  333. if (netif_msg_drv(dev))
  334. netdev_dbg(dev->net, "receive own packets only\n");
  335. pdata->mac_cr &=
  336. ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  337. }
  338. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  339. /* Initiate async writes, as we can't wait for completion here */
  340. smsc95xx_write_reg_async(dev, HASHH, &hash_hi);
  341. smsc95xx_write_reg_async(dev, HASHL, &hash_lo);
  342. smsc95xx_write_reg_async(dev, MAC_CR, &pdata->mac_cr);
  343. }
  344. static void smsc95xx_phy_update_flowcontrol(struct usbnet *dev, u8 duplex,
  345. u16 lcladv, u16 rmtadv)
  346. {
  347. u32 flow, afc_cfg = 0;
  348. int ret = smsc95xx_read_reg(dev, AFC_CFG, &afc_cfg);
  349. if (ret < 0) {
  350. netdev_warn(dev->net, "error reading AFC_CFG\n");
  351. return;
  352. }
  353. if (duplex == DUPLEX_FULL) {
  354. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  355. if (cap & FLOW_CTRL_RX)
  356. flow = 0xFFFF0002;
  357. else
  358. flow = 0;
  359. if (cap & FLOW_CTRL_TX)
  360. afc_cfg |= 0xF;
  361. else
  362. afc_cfg &= ~0xF;
  363. if (netif_msg_link(dev))
  364. netdev_dbg(dev->net, "rx pause %s, tx pause %s\n",
  365. cap & FLOW_CTRL_RX ? "enabled" : "disabled",
  366. cap & FLOW_CTRL_TX ? "enabled" : "disabled");
  367. } else {
  368. if (netif_msg_link(dev))
  369. netdev_dbg(dev->net, "half duplex\n");
  370. flow = 0;
  371. afc_cfg |= 0xF;
  372. }
  373. smsc95xx_write_reg(dev, FLOW, flow);
  374. smsc95xx_write_reg(dev, AFC_CFG, afc_cfg);
  375. }
  376. static int smsc95xx_link_reset(struct usbnet *dev)
  377. {
  378. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  379. struct mii_if_info *mii = &dev->mii;
  380. struct ethtool_cmd ecmd;
  381. unsigned long flags;
  382. u16 lcladv, rmtadv;
  383. u32 intdata;
  384. /* clear interrupt status */
  385. smsc95xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC);
  386. intdata = 0xFFFFFFFF;
  387. smsc95xx_write_reg(dev, INT_STS, intdata);
  388. mii_check_media(mii, 1, 1);
  389. mii_ethtool_gset(&dev->mii, &ecmd);
  390. lcladv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
  391. rmtadv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
  392. if (netif_msg_link(dev))
  393. netdev_dbg(dev->net, "speed: %d duplex: %d lcladv: %04x rmtadv: %04x\n",
  394. ecmd.speed, ecmd.duplex, lcladv, rmtadv);
  395. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  396. if (ecmd.duplex != DUPLEX_FULL) {
  397. pdata->mac_cr &= ~MAC_CR_FDPX_;
  398. pdata->mac_cr |= MAC_CR_RCVOWN_;
  399. } else {
  400. pdata->mac_cr &= ~MAC_CR_RCVOWN_;
  401. pdata->mac_cr |= MAC_CR_FDPX_;
  402. }
  403. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  404. smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  405. smsc95xx_phy_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
  406. return 0;
  407. }
  408. static void smsc95xx_status(struct usbnet *dev, struct urb *urb)
  409. {
  410. u32 intdata;
  411. if (urb->actual_length != 4) {
  412. netdev_warn(dev->net, "unexpected urb length %d\n",
  413. urb->actual_length);
  414. return;
  415. }
  416. memcpy(&intdata, urb->transfer_buffer, 4);
  417. le32_to_cpus(&intdata);
  418. if (netif_msg_link(dev))
  419. netdev_dbg(dev->net, "intdata: 0x%08X\n", intdata);
  420. if (intdata & INT_ENP_PHY_INT_)
  421. usbnet_defer_kevent(dev, EVENT_LINK_RESET);
  422. else
  423. netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
  424. intdata);
  425. }
  426. /* Enable or disable Tx & Rx checksum offload engines */
  427. static int smsc95xx_set_csums(struct usbnet *dev)
  428. {
  429. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  430. u32 read_buf;
  431. int ret = smsc95xx_read_reg(dev, COE_CR, &read_buf);
  432. if (ret < 0) {
  433. netdev_warn(dev->net, "Failed to read COE_CR: %d\n", ret);
  434. return ret;
  435. }
  436. if (pdata->use_tx_csum)
  437. read_buf |= Tx_COE_EN_;
  438. else
  439. read_buf &= ~Tx_COE_EN_;
  440. if (pdata->use_rx_csum)
  441. read_buf |= Rx_COE_EN_;
  442. else
  443. read_buf &= ~Rx_COE_EN_;
  444. ret = smsc95xx_write_reg(dev, COE_CR, read_buf);
  445. if (ret < 0) {
  446. netdev_warn(dev->net, "Failed to write COE_CR: %d\n", ret);
  447. return ret;
  448. }
  449. if (netif_msg_hw(dev))
  450. netdev_dbg(dev->net, "COE_CR = 0x%08x\n", read_buf);
  451. return 0;
  452. }
  453. static int smsc95xx_ethtool_get_eeprom_len(struct net_device *net)
  454. {
  455. return MAX_EEPROM_SIZE;
  456. }
  457. static int smsc95xx_ethtool_get_eeprom(struct net_device *netdev,
  458. struct ethtool_eeprom *ee, u8 *data)
  459. {
  460. struct usbnet *dev = netdev_priv(netdev);
  461. ee->magic = LAN95XX_EEPROM_MAGIC;
  462. return smsc95xx_read_eeprom(dev, ee->offset, ee->len, data);
  463. }
  464. static int smsc95xx_ethtool_set_eeprom(struct net_device *netdev,
  465. struct ethtool_eeprom *ee, u8 *data)
  466. {
  467. struct usbnet *dev = netdev_priv(netdev);
  468. if (ee->magic != LAN95XX_EEPROM_MAGIC) {
  469. netdev_warn(dev->net, "EEPROM: magic value mismatch, magic = 0x%x\n",
  470. ee->magic);
  471. return -EINVAL;
  472. }
  473. return smsc95xx_write_eeprom(dev, ee->offset, ee->len, data);
  474. }
  475. static u32 smsc95xx_ethtool_get_rx_csum(struct net_device *netdev)
  476. {
  477. struct usbnet *dev = netdev_priv(netdev);
  478. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  479. return pdata->use_rx_csum;
  480. }
  481. static int smsc95xx_ethtool_set_rx_csum(struct net_device *netdev, u32 val)
  482. {
  483. struct usbnet *dev = netdev_priv(netdev);
  484. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  485. pdata->use_rx_csum = !!val;
  486. return smsc95xx_set_csums(dev);
  487. }
  488. static u32 smsc95xx_ethtool_get_tx_csum(struct net_device *netdev)
  489. {
  490. struct usbnet *dev = netdev_priv(netdev);
  491. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  492. return pdata->use_tx_csum;
  493. }
  494. static int smsc95xx_ethtool_set_tx_csum(struct net_device *netdev, u32 val)
  495. {
  496. struct usbnet *dev = netdev_priv(netdev);
  497. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  498. pdata->use_tx_csum = !!val;
  499. ethtool_op_set_tx_hw_csum(netdev, pdata->use_tx_csum);
  500. return smsc95xx_set_csums(dev);
  501. }
  502. static const struct ethtool_ops smsc95xx_ethtool_ops = {
  503. .get_link = usbnet_get_link,
  504. .nway_reset = usbnet_nway_reset,
  505. .get_drvinfo = usbnet_get_drvinfo,
  506. .get_msglevel = usbnet_get_msglevel,
  507. .set_msglevel = usbnet_set_msglevel,
  508. .get_settings = usbnet_get_settings,
  509. .set_settings = usbnet_set_settings,
  510. .get_eeprom_len = smsc95xx_ethtool_get_eeprom_len,
  511. .get_eeprom = smsc95xx_ethtool_get_eeprom,
  512. .set_eeprom = smsc95xx_ethtool_set_eeprom,
  513. .get_tx_csum = smsc95xx_ethtool_get_tx_csum,
  514. .set_tx_csum = smsc95xx_ethtool_set_tx_csum,
  515. .get_rx_csum = smsc95xx_ethtool_get_rx_csum,
  516. .set_rx_csum = smsc95xx_ethtool_set_rx_csum,
  517. };
  518. static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  519. {
  520. struct usbnet *dev = netdev_priv(netdev);
  521. if (!netif_running(netdev))
  522. return -EINVAL;
  523. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  524. }
  525. static void smsc95xx_init_mac_address(struct usbnet *dev)
  526. {
  527. /* try reading mac address from EEPROM */
  528. if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
  529. dev->net->dev_addr) == 0) {
  530. if (is_valid_ether_addr(dev->net->dev_addr)) {
  531. /* eeprom values are valid so use them */
  532. if (netif_msg_ifup(dev))
  533. netdev_dbg(dev->net, "MAC address read from EEPROM\n");
  534. return;
  535. }
  536. }
  537. /* no eeprom, or eeprom values are invalid. generate random MAC */
  538. random_ether_addr(dev->net->dev_addr);
  539. if (netif_msg_ifup(dev))
  540. netdev_dbg(dev->net, "MAC address set to random_ether_addr\n");
  541. }
  542. static int smsc95xx_set_mac_address(struct usbnet *dev)
  543. {
  544. u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
  545. dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
  546. u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
  547. int ret;
  548. ret = smsc95xx_write_reg(dev, ADDRL, addr_lo);
  549. if (ret < 0) {
  550. netdev_warn(dev->net, "Failed to write ADDRL: %d\n", ret);
  551. return ret;
  552. }
  553. ret = smsc95xx_write_reg(dev, ADDRH, addr_hi);
  554. if (ret < 0) {
  555. netdev_warn(dev->net, "Failed to write ADDRH: %d\n", ret);
  556. return ret;
  557. }
  558. return 0;
  559. }
  560. /* starts the TX path */
  561. static void smsc95xx_start_tx_path(struct usbnet *dev)
  562. {
  563. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  564. unsigned long flags;
  565. u32 reg_val;
  566. /* Enable Tx at MAC */
  567. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  568. pdata->mac_cr |= MAC_CR_TXEN_;
  569. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  570. smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  571. /* Enable Tx at SCSRs */
  572. reg_val = TX_CFG_ON_;
  573. smsc95xx_write_reg(dev, TX_CFG, reg_val);
  574. }
  575. /* Starts the Receive path */
  576. static void smsc95xx_start_rx_path(struct usbnet *dev)
  577. {
  578. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  579. unsigned long flags;
  580. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  581. pdata->mac_cr |= MAC_CR_RXEN_;
  582. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  583. smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  584. }
  585. static int smsc95xx_phy_initialize(struct usbnet *dev)
  586. {
  587. /* Initialize MII structure */
  588. dev->mii.dev = dev->net;
  589. dev->mii.mdio_read = smsc95xx_mdio_read;
  590. dev->mii.mdio_write = smsc95xx_mdio_write;
  591. dev->mii.phy_id_mask = 0x1f;
  592. dev->mii.reg_num_mask = 0x1f;
  593. dev->mii.phy_id = SMSC95XX_INTERNAL_PHY_ID;
  594. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  595. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  596. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
  597. ADVERTISE_PAUSE_ASYM);
  598. /* read to clear */
  599. smsc95xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
  600. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
  601. PHY_INT_MASK_DEFAULT_);
  602. mii_nway_restart(&dev->mii);
  603. if (netif_msg_ifup(dev))
  604. netdev_dbg(dev->net, "phy initialised successfully\n");
  605. return 0;
  606. }
  607. static int smsc95xx_reset(struct usbnet *dev)
  608. {
  609. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  610. struct net_device *netdev = dev->net;
  611. u32 read_buf, write_buf, burst_cap;
  612. int ret = 0, timeout;
  613. if (netif_msg_ifup(dev))
  614. netdev_dbg(dev->net, "entering smsc95xx_reset\n");
  615. write_buf = HW_CFG_LRST_;
  616. ret = smsc95xx_write_reg(dev, HW_CFG, write_buf);
  617. if (ret < 0) {
  618. netdev_warn(dev->net, "Failed to write HW_CFG_LRST_ bit in HW_CFG register, ret = %d\n",
  619. ret);
  620. return ret;
  621. }
  622. timeout = 0;
  623. do {
  624. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  625. if (ret < 0) {
  626. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  627. return ret;
  628. }
  629. msleep(10);
  630. timeout++;
  631. } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
  632. if (timeout >= 100) {
  633. netdev_warn(dev->net, "timeout waiting for completion of Lite Reset\n");
  634. return ret;
  635. }
  636. write_buf = PM_CTL_PHY_RST_;
  637. ret = smsc95xx_write_reg(dev, PM_CTRL, write_buf);
  638. if (ret < 0) {
  639. netdev_warn(dev->net, "Failed to write PM_CTRL: %d\n", ret);
  640. return ret;
  641. }
  642. timeout = 0;
  643. do {
  644. ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf);
  645. if (ret < 0) {
  646. netdev_warn(dev->net, "Failed to read PM_CTRL: %d\n", ret);
  647. return ret;
  648. }
  649. msleep(10);
  650. timeout++;
  651. } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
  652. if (timeout >= 100) {
  653. netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
  654. return ret;
  655. }
  656. smsc95xx_init_mac_address(dev);
  657. ret = smsc95xx_set_mac_address(dev);
  658. if (ret < 0)
  659. return ret;
  660. if (netif_msg_ifup(dev))
  661. netdev_dbg(dev->net, "MAC Address: %pM\n", dev->net->dev_addr);
  662. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  663. if (ret < 0) {
  664. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  665. return ret;
  666. }
  667. if (netif_msg_ifup(dev))
  668. netdev_dbg(dev->net, "Read Value from HW_CFG : 0x%08x\n", read_buf);
  669. read_buf |= HW_CFG_BIR_;
  670. ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
  671. if (ret < 0) {
  672. netdev_warn(dev->net, "Failed to write HW_CFG_BIR_ bit in HW_CFG register, ret = %d\n",
  673. ret);
  674. return ret;
  675. }
  676. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  677. if (ret < 0) {
  678. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  679. return ret;
  680. }
  681. if (netif_msg_ifup(dev))
  682. netdev_dbg(dev->net, "Read Value from HW_CFG after writing HW_CFG_BIR_: 0x%08x\n",
  683. read_buf);
  684. if (!turbo_mode) {
  685. burst_cap = 0;
  686. dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  687. } else if (dev->udev->speed == USB_SPEED_HIGH) {
  688. burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  689. dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  690. } else {
  691. burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  692. dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  693. }
  694. if (netif_msg_ifup(dev))
  695. netdev_dbg(dev->net, "rx_urb_size=%ld\n", (ulong)dev->rx_urb_size);
  696. ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);
  697. if (ret < 0) {
  698. netdev_warn(dev->net, "Failed to write BURST_CAP: %d\n", ret);
  699. return ret;
  700. }
  701. ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf);
  702. if (ret < 0) {
  703. netdev_warn(dev->net, "Failed to read BURST_CAP: %d\n", ret);
  704. return ret;
  705. }
  706. if (netif_msg_ifup(dev))
  707. netdev_dbg(dev->net, "Read Value from BURST_CAP after writing: 0x%08x\n",
  708. read_buf);
  709. read_buf = DEFAULT_BULK_IN_DELAY;
  710. ret = smsc95xx_write_reg(dev, BULK_IN_DLY, read_buf);
  711. if (ret < 0) {
  712. netdev_warn(dev->net, "ret = %d\n", ret);
  713. return ret;
  714. }
  715. ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf);
  716. if (ret < 0) {
  717. netdev_warn(dev->net, "Failed to read BULK_IN_DLY: %d\n", ret);
  718. return ret;
  719. }
  720. if (netif_msg_ifup(dev))
  721. netdev_dbg(dev->net, "Read Value from BULK_IN_DLY after writing: 0x%08x\n",
  722. read_buf);
  723. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  724. if (ret < 0) {
  725. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  726. return ret;
  727. }
  728. if (netif_msg_ifup(dev))
  729. netdev_dbg(dev->net, "Read Value from HW_CFG: 0x%08x\n", read_buf);
  730. if (turbo_mode)
  731. read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
  732. read_buf &= ~HW_CFG_RXDOFF_;
  733. /* set Rx data offset=2, Make IP header aligns on word boundary. */
  734. read_buf |= NET_IP_ALIGN << 9;
  735. ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
  736. if (ret < 0) {
  737. netdev_warn(dev->net, "Failed to write HW_CFG register, ret=%d\n",
  738. ret);
  739. return ret;
  740. }
  741. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  742. if (ret < 0) {
  743. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  744. return ret;
  745. }
  746. if (netif_msg_ifup(dev))
  747. netdev_dbg(dev->net, "Read Value from HW_CFG after writing: 0x%08x\n",
  748. read_buf);
  749. write_buf = 0xFFFFFFFF;
  750. ret = smsc95xx_write_reg(dev, INT_STS, write_buf);
  751. if (ret < 0) {
  752. netdev_warn(dev->net, "Failed to write INT_STS register, ret=%d\n",
  753. ret);
  754. return ret;
  755. }
  756. ret = smsc95xx_read_reg(dev, ID_REV, &read_buf);
  757. if (ret < 0) {
  758. netdev_warn(dev->net, "Failed to read ID_REV: %d\n", ret);
  759. return ret;
  760. }
  761. if (netif_msg_ifup(dev))
  762. netdev_dbg(dev->net, "ID_REV = 0x%08x\n", read_buf);
  763. /* Configure GPIO pins as LED outputs */
  764. write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
  765. LED_GPIO_CFG_FDX_LED;
  766. ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf);
  767. if (ret < 0) {
  768. netdev_warn(dev->net, "Failed to write LED_GPIO_CFG register, ret=%d\n",
  769. ret);
  770. return ret;
  771. }
  772. /* Init Tx */
  773. write_buf = 0;
  774. ret = smsc95xx_write_reg(dev, FLOW, write_buf);
  775. if (ret < 0) {
  776. netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret);
  777. return ret;
  778. }
  779. read_buf = AFC_CFG_DEFAULT;
  780. ret = smsc95xx_write_reg(dev, AFC_CFG, read_buf);
  781. if (ret < 0) {
  782. netdev_warn(dev->net, "Failed to write AFC_CFG: %d\n", ret);
  783. return ret;
  784. }
  785. /* Don't need mac_cr_lock during initialisation */
  786. ret = smsc95xx_read_reg(dev, MAC_CR, &pdata->mac_cr);
  787. if (ret < 0) {
  788. netdev_warn(dev->net, "Failed to read MAC_CR: %d\n", ret);
  789. return ret;
  790. }
  791. /* Init Rx */
  792. /* Set Vlan */
  793. write_buf = (u32)ETH_P_8021Q;
  794. ret = smsc95xx_write_reg(dev, VLAN1, write_buf);
  795. if (ret < 0) {
  796. netdev_warn(dev->net, "Failed to write VAN1: %d\n", ret);
  797. return ret;
  798. }
  799. /* Enable or disable checksum offload engines */
  800. ethtool_op_set_tx_hw_csum(netdev, pdata->use_tx_csum);
  801. ret = smsc95xx_set_csums(dev);
  802. if (ret < 0) {
  803. netdev_warn(dev->net, "Failed to set csum offload: %d\n", ret);
  804. return ret;
  805. }
  806. smsc95xx_set_multicast(dev->net);
  807. if (smsc95xx_phy_initialize(dev) < 0)
  808. return -EIO;
  809. ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf);
  810. if (ret < 0) {
  811. netdev_warn(dev->net, "Failed to read INT_EP_CTL: %d\n", ret);
  812. return ret;
  813. }
  814. /* enable PHY interrupts */
  815. read_buf |= INT_EP_CTL_PHY_INT_;
  816. ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf);
  817. if (ret < 0) {
  818. netdev_warn(dev->net, "Failed to write INT_EP_CTL: %d\n", ret);
  819. return ret;
  820. }
  821. smsc95xx_start_tx_path(dev);
  822. smsc95xx_start_rx_path(dev);
  823. if (netif_msg_ifup(dev))
  824. netdev_dbg(dev->net, "smsc95xx_reset, return 0\n");
  825. return 0;
  826. }
  827. static const struct net_device_ops smsc95xx_netdev_ops = {
  828. .ndo_open = usbnet_open,
  829. .ndo_stop = usbnet_stop,
  830. .ndo_start_xmit = usbnet_start_xmit,
  831. .ndo_tx_timeout = usbnet_tx_timeout,
  832. .ndo_change_mtu = usbnet_change_mtu,
  833. .ndo_set_mac_address = eth_mac_addr,
  834. .ndo_validate_addr = eth_validate_addr,
  835. .ndo_do_ioctl = smsc95xx_ioctl,
  836. .ndo_set_multicast_list = smsc95xx_set_multicast,
  837. };
  838. static int smsc95xx_bind(struct usbnet *dev, struct usb_interface *intf)
  839. {
  840. struct smsc95xx_priv *pdata = NULL;
  841. int ret;
  842. printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
  843. ret = usbnet_get_endpoints(dev, intf);
  844. if (ret < 0) {
  845. netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
  846. return ret;
  847. }
  848. dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc95xx_priv),
  849. GFP_KERNEL);
  850. pdata = (struct smsc95xx_priv *)(dev->data[0]);
  851. if (!pdata) {
  852. netdev_warn(dev->net, "Unable to allocate struct smsc95xx_priv\n");
  853. return -ENOMEM;
  854. }
  855. spin_lock_init(&pdata->mac_cr_lock);
  856. pdata->use_tx_csum = DEFAULT_TX_CSUM_ENABLE;
  857. pdata->use_rx_csum = DEFAULT_RX_CSUM_ENABLE;
  858. /* Init all registers */
  859. ret = smsc95xx_reset(dev);
  860. dev->net->netdev_ops = &smsc95xx_netdev_ops;
  861. dev->net->ethtool_ops = &smsc95xx_ethtool_ops;
  862. dev->net->flags |= IFF_MULTICAST;
  863. dev->net->hard_header_len += SMSC95XX_TX_OVERHEAD;
  864. return 0;
  865. }
  866. static void smsc95xx_unbind(struct usbnet *dev, struct usb_interface *intf)
  867. {
  868. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  869. if (pdata) {
  870. if (netif_msg_ifdown(dev))
  871. netdev_dbg(dev->net, "free pdata\n");
  872. kfree(pdata);
  873. pdata = NULL;
  874. dev->data[0] = 0;
  875. }
  876. }
  877. static void smsc95xx_rx_csum_offload(struct sk_buff *skb)
  878. {
  879. skb->csum = *(u16 *)(skb_tail_pointer(skb) - 2);
  880. skb->ip_summed = CHECKSUM_COMPLETE;
  881. skb_trim(skb, skb->len - 2);
  882. }
  883. static int smsc95xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  884. {
  885. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  886. while (skb->len > 0) {
  887. u32 header, align_count;
  888. struct sk_buff *ax_skb;
  889. unsigned char *packet;
  890. u16 size;
  891. memcpy(&header, skb->data, sizeof(header));
  892. le32_to_cpus(&header);
  893. skb_pull(skb, 4 + NET_IP_ALIGN);
  894. packet = skb->data;
  895. /* get the packet length */
  896. size = (u16)((header & RX_STS_FL_) >> 16);
  897. align_count = (4 - ((size + NET_IP_ALIGN) % 4)) % 4;
  898. if (unlikely(header & RX_STS_ES_)) {
  899. if (netif_msg_rx_err(dev))
  900. netdev_dbg(dev->net, "Error header=0x%08x\n",
  901. header);
  902. dev->net->stats.rx_errors++;
  903. dev->net->stats.rx_dropped++;
  904. if (header & RX_STS_CRC_) {
  905. dev->net->stats.rx_crc_errors++;
  906. } else {
  907. if (header & (RX_STS_TL_ | RX_STS_RF_))
  908. dev->net->stats.rx_frame_errors++;
  909. if ((header & RX_STS_LE_) &&
  910. (!(header & RX_STS_FT_)))
  911. dev->net->stats.rx_length_errors++;
  912. }
  913. } else {
  914. /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */
  915. if (unlikely(size > (ETH_FRAME_LEN + 12))) {
  916. if (netif_msg_rx_err(dev))
  917. netdev_dbg(dev->net, "size err header=0x%08x\n",
  918. header);
  919. return 0;
  920. }
  921. /* last frame in this batch */
  922. if (skb->len == size) {
  923. if (pdata->use_rx_csum)
  924. smsc95xx_rx_csum_offload(skb);
  925. skb_trim(skb, skb->len - 4); /* remove fcs */
  926. skb->truesize = size + sizeof(struct sk_buff);
  927. return 1;
  928. }
  929. ax_skb = skb_clone(skb, GFP_ATOMIC);
  930. if (unlikely(!ax_skb)) {
  931. netdev_warn(dev->net, "Error allocating skb\n");
  932. return 0;
  933. }
  934. ax_skb->len = size;
  935. ax_skb->data = packet;
  936. skb_set_tail_pointer(ax_skb, size);
  937. if (pdata->use_rx_csum)
  938. smsc95xx_rx_csum_offload(ax_skb);
  939. skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
  940. ax_skb->truesize = size + sizeof(struct sk_buff);
  941. usbnet_skb_return(dev, ax_skb);
  942. }
  943. skb_pull(skb, size);
  944. /* padding bytes before the next frame starts */
  945. if (skb->len)
  946. skb_pull(skb, align_count);
  947. }
  948. if (unlikely(skb->len < 0)) {
  949. netdev_warn(dev->net, "invalid rx length<0 %d\n", skb->len);
  950. return 0;
  951. }
  952. return 1;
  953. }
  954. static u32 smsc95xx_calc_csum_preamble(struct sk_buff *skb)
  955. {
  956. int len = skb->data - skb->head;
  957. u16 high_16 = (u16)(skb->csum_offset + skb->csum_start - len);
  958. u16 low_16 = (u16)(skb->csum_start - len);
  959. return (high_16 << 16) | low_16;
  960. }
  961. static struct sk_buff *smsc95xx_tx_fixup(struct usbnet *dev,
  962. struct sk_buff *skb, gfp_t flags)
  963. {
  964. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  965. bool csum = pdata->use_tx_csum && (skb->ip_summed == CHECKSUM_PARTIAL);
  966. int overhead = csum ? SMSC95XX_TX_OVERHEAD_CSUM : SMSC95XX_TX_OVERHEAD;
  967. u32 tx_cmd_a, tx_cmd_b;
  968. /* We do not advertise SG, so skbs should be already linearized */
  969. BUG_ON(skb_shinfo(skb)->nr_frags);
  970. if (skb_headroom(skb) < overhead) {
  971. struct sk_buff *skb2 = skb_copy_expand(skb,
  972. overhead, 0, flags);
  973. dev_kfree_skb_any(skb);
  974. skb = skb2;
  975. if (!skb)
  976. return NULL;
  977. }
  978. if (csum) {
  979. u32 csum_preamble = smsc95xx_calc_csum_preamble(skb);
  980. skb_push(skb, 4);
  981. memcpy(skb->data, &csum_preamble, 4);
  982. }
  983. skb_push(skb, 4);
  984. tx_cmd_b = (u32)(skb->len - 4);
  985. if (csum)
  986. tx_cmd_b |= TX_CMD_B_CSUM_ENABLE;
  987. cpu_to_le32s(&tx_cmd_b);
  988. memcpy(skb->data, &tx_cmd_b, 4);
  989. skb_push(skb, 4);
  990. tx_cmd_a = (u32)(skb->len - 8) | TX_CMD_A_FIRST_SEG_ |
  991. TX_CMD_A_LAST_SEG_;
  992. cpu_to_le32s(&tx_cmd_a);
  993. memcpy(skb->data, &tx_cmd_a, 4);
  994. return skb;
  995. }
  996. static const struct driver_info smsc95xx_info = {
  997. .description = "smsc95xx USB 2.0 Ethernet",
  998. .bind = smsc95xx_bind,
  999. .unbind = smsc95xx_unbind,
  1000. .link_reset = smsc95xx_link_reset,
  1001. .reset = smsc95xx_reset,
  1002. .rx_fixup = smsc95xx_rx_fixup,
  1003. .tx_fixup = smsc95xx_tx_fixup,
  1004. .status = smsc95xx_status,
  1005. .flags = FLAG_ETHER | FLAG_SEND_ZLP,
  1006. };
  1007. static const struct usb_device_id products[] = {
  1008. {
  1009. /* SMSC9500 USB Ethernet Device */
  1010. USB_DEVICE(0x0424, 0x9500),
  1011. .driver_info = (unsigned long) &smsc95xx_info,
  1012. },
  1013. {
  1014. /* SMSC9505 USB Ethernet Device */
  1015. USB_DEVICE(0x0424, 0x9505),
  1016. .driver_info = (unsigned long) &smsc95xx_info,
  1017. },
  1018. {
  1019. /* SMSC9500A USB Ethernet Device */
  1020. USB_DEVICE(0x0424, 0x9E00),
  1021. .driver_info = (unsigned long) &smsc95xx_info,
  1022. },
  1023. {
  1024. /* SMSC9505A USB Ethernet Device */
  1025. USB_DEVICE(0x0424, 0x9E01),
  1026. .driver_info = (unsigned long) &smsc95xx_info,
  1027. },
  1028. {
  1029. /* SMSC9512/9514 USB Hub & Ethernet Device */
  1030. USB_DEVICE(0x0424, 0xec00),
  1031. .driver_info = (unsigned long) &smsc95xx_info,
  1032. },
  1033. {
  1034. /* SMSC9500 USB Ethernet Device (SAL10) */
  1035. USB_DEVICE(0x0424, 0x9900),
  1036. .driver_info = (unsigned long) &smsc95xx_info,
  1037. },
  1038. {
  1039. /* SMSC9505 USB Ethernet Device (SAL10) */
  1040. USB_DEVICE(0x0424, 0x9901),
  1041. .driver_info = (unsigned long) &smsc95xx_info,
  1042. },
  1043. {
  1044. /* SMSC9500A USB Ethernet Device (SAL10) */
  1045. USB_DEVICE(0x0424, 0x9902),
  1046. .driver_info = (unsigned long) &smsc95xx_info,
  1047. },
  1048. {
  1049. /* SMSC9505A USB Ethernet Device (SAL10) */
  1050. USB_DEVICE(0x0424, 0x9903),
  1051. .driver_info = (unsigned long) &smsc95xx_info,
  1052. },
  1053. {
  1054. /* SMSC9512/9514 USB Hub & Ethernet Device (SAL10) */
  1055. USB_DEVICE(0x0424, 0x9904),
  1056. .driver_info = (unsigned long) &smsc95xx_info,
  1057. },
  1058. {
  1059. /* SMSC9500A USB Ethernet Device (HAL) */
  1060. USB_DEVICE(0x0424, 0x9905),
  1061. .driver_info = (unsigned long) &smsc95xx_info,
  1062. },
  1063. {
  1064. /* SMSC9505A USB Ethernet Device (HAL) */
  1065. USB_DEVICE(0x0424, 0x9906),
  1066. .driver_info = (unsigned long) &smsc95xx_info,
  1067. },
  1068. {
  1069. /* SMSC9500 USB Ethernet Device (Alternate ID) */
  1070. USB_DEVICE(0x0424, 0x9907),
  1071. .driver_info = (unsigned long) &smsc95xx_info,
  1072. },
  1073. {
  1074. /* SMSC9500A USB Ethernet Device (Alternate ID) */
  1075. USB_DEVICE(0x0424, 0x9908),
  1076. .driver_info = (unsigned long) &smsc95xx_info,
  1077. },
  1078. {
  1079. /* SMSC9512/9514 USB Hub & Ethernet Device (Alternate ID) */
  1080. USB_DEVICE(0x0424, 0x9909),
  1081. .driver_info = (unsigned long) &smsc95xx_info,
  1082. },
  1083. { }, /* END */
  1084. };
  1085. MODULE_DEVICE_TABLE(usb, products);
  1086. static struct usb_driver smsc95xx_driver = {
  1087. .name = "smsc95xx",
  1088. .id_table = products,
  1089. .probe = usbnet_probe,
  1090. .suspend = usbnet_suspend,
  1091. .resume = usbnet_resume,
  1092. .disconnect = usbnet_disconnect,
  1093. };
  1094. static int __init smsc95xx_init(void)
  1095. {
  1096. return usb_register(&smsc95xx_driver);
  1097. }
  1098. module_init(smsc95xx_init);
  1099. static void __exit smsc95xx_exit(void)
  1100. {
  1101. usb_deregister(&smsc95xx_driver);
  1102. }
  1103. module_exit(smsc95xx_exit);
  1104. MODULE_AUTHOR("Nancy Lin");
  1105. MODULE_AUTHOR("Steve Glendinning <steve.glendinning@smsc.com>");
  1106. MODULE_DESCRIPTION("SMSC95XX USB 2.0 Ethernet Devices");
  1107. MODULE_LICENSE("GPL");