da850.dtsi 5.6 KB

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  1. /*
  2. * Copyright 2012 DENX Software Engineering GmbH
  3. * Heiko Schocher <hs@denx.de>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2 of the License, or (at your
  8. * option) any later version.
  9. */
  10. #include "skeleton.dtsi"
  11. / {
  12. arm {
  13. #address-cells = <1>;
  14. #size-cells = <1>;
  15. ranges;
  16. intc: interrupt-controller {
  17. compatible = "ti,cp-intc";
  18. interrupt-controller;
  19. #interrupt-cells = <1>;
  20. ti,intc-size = <100>;
  21. reg = <0xfffee000 0x2000>;
  22. };
  23. };
  24. soc {
  25. compatible = "simple-bus";
  26. model = "da850";
  27. #address-cells = <1>;
  28. #size-cells = <1>;
  29. ranges = <0x0 0x01c00000 0x400000>;
  30. interrupt-parent = <&intc>;
  31. pmx_core: pinmux@1c14120 {
  32. compatible = "pinctrl-single";
  33. reg = <0x14120 0x50>;
  34. #address-cells = <1>;
  35. #size-cells = <0>;
  36. pinctrl-single,bit-per-mux;
  37. pinctrl-single,register-width = <32>;
  38. pinctrl-single,function-mask = <0xf>;
  39. status = "disabled";
  40. nand_cs3_pins: pinmux_nand_pins {
  41. pinctrl-single,bits = <
  42. /* EMA_OE, EMA_WE */
  43. 0x1c 0x00110000 0x00ff0000
  44. /* EMA_CS[4],EMA_CS[3]*/
  45. 0x1c 0x00000110 0x00000ff0
  46. /*
  47. * EMA_D[0], EMA_D[1], EMA_D[2],
  48. * EMA_D[3], EMA_D[4], EMA_D[5],
  49. * EMA_D[6], EMA_D[7]
  50. */
  51. 0x24 0x11111111 0xffffffff
  52. /* EMA_A[1], EMA_A[2] */
  53. 0x30 0x01100000 0x0ff00000
  54. >;
  55. };
  56. i2c0_pins: pinmux_i2c0_pins {
  57. pinctrl-single,bits = <
  58. /* I2C0_SDA,I2C0_SCL */
  59. 0x10 0x00002200 0x0000ff00
  60. >;
  61. };
  62. mmc0_pins: pinmux_mmc_pins {
  63. pinctrl-single,bits = <
  64. /* MMCSD0_DAT[3] MMCSD0_DAT[2]
  65. * MMCSD0_DAT[1] MMCSD0_DAT[0]
  66. * MMCSD0_CMD MMCSD0_CLK
  67. */
  68. 0x28 0x00222222 0x00ffffff
  69. >;
  70. };
  71. ehrpwm0a_pins: pinmux_ehrpwm0a_pins {
  72. pinctrl-single,bits = <
  73. /* EPWM0A */
  74. 0xc 0x00000002 0x0000000f
  75. >;
  76. };
  77. ehrpwm0b_pins: pinmux_ehrpwm0b_pins {
  78. pinctrl-single,bits = <
  79. /* EPWM0B */
  80. 0xc 0x00000020 0x000000f0
  81. >;
  82. };
  83. ehrpwm1a_pins: pinmux_ehrpwm1a_pins {
  84. pinctrl-single,bits = <
  85. /* EPWM1A */
  86. 0x14 0x00000002 0x0000000f
  87. >;
  88. };
  89. ehrpwm1b_pins: pinmux_ehrpwm1b_pins {
  90. pinctrl-single,bits = <
  91. /* EPWM1B */
  92. 0x14 0x00000020 0x000000f0
  93. >;
  94. };
  95. ecap0_pins: pinmux_ecap0_pins {
  96. pinctrl-single,bits = <
  97. /* ECAP0_APWM0 */
  98. 0x8 0x20000000 0xf0000000
  99. >;
  100. };
  101. ecap1_pins: pinmux_ecap1_pins {
  102. pinctrl-single,bits = <
  103. /* ECAP1_APWM1 */
  104. 0x4 0x40000000 0xf0000000
  105. >;
  106. };
  107. ecap2_pins: pinmux_ecap2_pins {
  108. pinctrl-single,bits = <
  109. /* ECAP2_APWM2 */
  110. 0x4 0x00000004 0x0000000f
  111. >;
  112. };
  113. spi1_pins: pinmux_spi_pins {
  114. pinctrl-single,bits = <
  115. /* SIMO, SOMI, CLK */
  116. 0x14 0x00110100 0x00ff0f00
  117. >;
  118. };
  119. spi1_cs0_pin: pinmux_spi1_cs0 {
  120. pinctrl-single,bits = <
  121. /* CS0 */
  122. 0x14 0x00000010 0x000000f0
  123. >;
  124. };
  125. mdio_pins: pinmux_mdio_pins {
  126. pinctrl-single,bits = <
  127. /* MDIO_CLK, MDIO_D */
  128. 0x10 0x00000088 0x000000ff
  129. >;
  130. };
  131. };
  132. serial0: serial@1c42000 {
  133. compatible = "ns16550a";
  134. reg = <0x42000 0x100>;
  135. clock-frequency = <150000000>;
  136. reg-shift = <2>;
  137. interrupts = <25>;
  138. status = "disabled";
  139. };
  140. serial1: serial@1d0c000 {
  141. compatible = "ns16550a";
  142. reg = <0x10c000 0x100>;
  143. clock-frequency = <150000000>;
  144. reg-shift = <2>;
  145. interrupts = <53>;
  146. status = "disabled";
  147. };
  148. serial2: serial@1d0d000 {
  149. compatible = "ns16550a";
  150. reg = <0x10d000 0x100>;
  151. clock-frequency = <150000000>;
  152. reg-shift = <2>;
  153. interrupts = <61>;
  154. status = "disabled";
  155. };
  156. rtc0: rtc@1c23000 {
  157. compatible = "ti,da830-rtc";
  158. reg = <0x23000 0x1000>;
  159. interrupts = <19
  160. 19>;
  161. status = "disabled";
  162. };
  163. i2c0: i2c@1c22000 {
  164. compatible = "ti,davinci-i2c";
  165. reg = <0x22000 0x1000>;
  166. interrupts = <15>;
  167. #address-cells = <1>;
  168. #size-cells = <0>;
  169. status = "disabled";
  170. };
  171. wdt: wdt@1c21000 {
  172. compatible = "ti,davinci-wdt";
  173. reg = <0x21000 0x1000>;
  174. status = "disabled";
  175. };
  176. mmc0: mmc@1c40000 {
  177. compatible = "ti,da830-mmc";
  178. reg = <0x40000 0x1000>;
  179. interrupts = <16>;
  180. status = "disabled";
  181. };
  182. ehrpwm0: ehrpwm@01f00000 {
  183. compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
  184. #pwm-cells = <3>;
  185. reg = <0x300000 0x2000>;
  186. status = "disabled";
  187. };
  188. ehrpwm1: ehrpwm@01f02000 {
  189. compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
  190. #pwm-cells = <3>;
  191. reg = <0x302000 0x2000>;
  192. status = "disabled";
  193. };
  194. ecap0: ecap@01f06000 {
  195. compatible = "ti,da850-ecap", "ti,am33xx-ecap";
  196. #pwm-cells = <3>;
  197. reg = <0x306000 0x80>;
  198. status = "disabled";
  199. };
  200. ecap1: ecap@01f07000 {
  201. compatible = "ti,da850-ecap", "ti,am33xx-ecap";
  202. #pwm-cells = <3>;
  203. reg = <0x307000 0x80>;
  204. status = "disabled";
  205. };
  206. ecap2: ecap@01f08000 {
  207. compatible = "ti,da850-ecap", "ti,am33xx-ecap";
  208. #pwm-cells = <3>;
  209. reg = <0x308000 0x80>;
  210. status = "disabled";
  211. };
  212. spi1: spi@1f0e000 {
  213. #address-cells = <1>;
  214. #size-cells = <0>;
  215. compatible = "ti,da830-spi";
  216. reg = <0x30e000 0x1000>;
  217. num-cs = <4>;
  218. ti,davinci-spi-intr-line = <1>;
  219. interrupts = <56>;
  220. status = "disabled";
  221. };
  222. mdio: mdio@1e24000 {
  223. compatible = "ti,davinci_mdio";
  224. #address-cells = <1>;
  225. #size-cells = <0>;
  226. reg = <0x224000 0x1000>;
  227. };
  228. };
  229. nand_cs3@62000000 {
  230. compatible = "ti,davinci-nand";
  231. reg = <0x62000000 0x807ff
  232. 0x68000000 0x8000>;
  233. ti,davinci-chipselect = <1>;
  234. ti,davinci-mask-ale = <0>;
  235. ti,davinci-mask-cle = <0>;
  236. ti,davinci-mask-chipsel = <0>;
  237. ti,davinci-ecc-mode = "hw";
  238. ti,davinci-ecc-bits = <4>;
  239. ti,davinci-nand-use-bbt;
  240. status = "disabled";
  241. };
  242. };