fimc-lite.c 41 KB

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  1. /*
  2. * Samsung EXYNOS FIMC-LITE (camera host interface) driver
  3. *
  4. * Copyright (C) 2012 Samsung Electronics Co., Ltd.
  5. * Sylwester Nawrocki <s.nawrocki@samsung.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
  12. #include <linux/bug.h>
  13. #include <linux/device.h>
  14. #include <linux/errno.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/kernel.h>
  17. #include <linux/list.h>
  18. #include <linux/module.h>
  19. #include <linux/types.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/pm_runtime.h>
  22. #include <linux/slab.h>
  23. #include <linux/videodev2.h>
  24. #include <media/v4l2-device.h>
  25. #include <media/v4l2-ioctl.h>
  26. #include <media/v4l2-mem2mem.h>
  27. #include <media/videobuf2-core.h>
  28. #include <media/videobuf2-dma-contig.h>
  29. #include "fimc-mdevice.h"
  30. #include "fimc-core.h"
  31. #include "fimc-lite-reg.h"
  32. static int debug;
  33. module_param(debug, int, 0644);
  34. static const struct fimc_fmt fimc_lite_formats[] = {
  35. {
  36. .name = "YUV 4:2:2 packed, YCbYCr",
  37. .fourcc = V4L2_PIX_FMT_YUYV,
  38. .depth = { 16 },
  39. .color = FIMC_FMT_YCBYCR422,
  40. .memplanes = 1,
  41. .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,
  42. }, {
  43. .name = "YUV 4:2:2 packed, CbYCrY",
  44. .fourcc = V4L2_PIX_FMT_UYVY,
  45. .depth = { 16 },
  46. .color = FIMC_FMT_CBYCRY422,
  47. .memplanes = 1,
  48. .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8,
  49. }, {
  50. .name = "YUV 4:2:2 packed, CrYCbY",
  51. .fourcc = V4L2_PIX_FMT_VYUY,
  52. .depth = { 16 },
  53. .color = FIMC_FMT_CRYCBY422,
  54. .memplanes = 1,
  55. .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8,
  56. }, {
  57. .name = "YUV 4:2:2 packed, YCrYCb",
  58. .fourcc = V4L2_PIX_FMT_YVYU,
  59. .depth = { 16 },
  60. .color = FIMC_FMT_YCRYCB422,
  61. .memplanes = 1,
  62. .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8,
  63. }, {
  64. .name = "RAW8 (GRBG)",
  65. .fourcc = V4L2_PIX_FMT_SGRBG8,
  66. .depth = { 8 },
  67. .color = FIMC_FMT_RAW8,
  68. .memplanes = 1,
  69. .mbus_code = V4L2_MBUS_FMT_SGRBG8_1X8,
  70. }, {
  71. .name = "RAW10 (GRBG)",
  72. .fourcc = V4L2_PIX_FMT_SGRBG10,
  73. .depth = { 10 },
  74. .color = FIMC_FMT_RAW10,
  75. .memplanes = 1,
  76. .mbus_code = V4L2_MBUS_FMT_SGRBG10_1X10,
  77. }, {
  78. .name = "RAW12 (GRBG)",
  79. .fourcc = V4L2_PIX_FMT_SGRBG12,
  80. .depth = { 12 },
  81. .color = FIMC_FMT_RAW12,
  82. .memplanes = 1,
  83. .mbus_code = V4L2_MBUS_FMT_SGRBG12_1X12,
  84. },
  85. };
  86. /**
  87. * fimc_lite_find_format - lookup fimc color format by fourcc or media bus code
  88. * @pixelformat: fourcc to match, ignored if null
  89. * @mbus_code: media bus code to match, ignored if null
  90. * @index: index to the fimc_lite_formats array, ignored if negative
  91. */
  92. static const struct fimc_fmt *fimc_lite_find_format(const u32 *pixelformat,
  93. const u32 *mbus_code, int index)
  94. {
  95. const struct fimc_fmt *fmt, *def_fmt = NULL;
  96. unsigned int i;
  97. int id = 0;
  98. if (index >= (int)ARRAY_SIZE(fimc_lite_formats))
  99. return NULL;
  100. for (i = 0; i < ARRAY_SIZE(fimc_lite_formats); ++i) {
  101. fmt = &fimc_lite_formats[i];
  102. if (pixelformat && fmt->fourcc == *pixelformat)
  103. return fmt;
  104. if (mbus_code && fmt->mbus_code == *mbus_code)
  105. return fmt;
  106. if (index == id)
  107. def_fmt = fmt;
  108. id++;
  109. }
  110. return def_fmt;
  111. }
  112. static int fimc_lite_hw_init(struct fimc_lite *fimc)
  113. {
  114. struct fimc_pipeline *pipeline = &fimc->pipeline;
  115. struct fimc_sensor_info *sensor;
  116. unsigned long flags;
  117. if (pipeline->subdevs[IDX_SENSOR] == NULL)
  118. return -ENXIO;
  119. if (fimc->fmt == NULL)
  120. return -EINVAL;
  121. sensor = v4l2_get_subdev_hostdata(pipeline->subdevs[IDX_SENSOR]);
  122. spin_lock_irqsave(&fimc->slock, flags);
  123. flite_hw_set_camera_bus(fimc, sensor->pdata);
  124. flite_hw_set_source_format(fimc, &fimc->inp_frame);
  125. flite_hw_set_window_offset(fimc, &fimc->inp_frame);
  126. flite_hw_set_output_dma(fimc, &fimc->out_frame, true);
  127. flite_hw_set_interrupt_mask(fimc);
  128. flite_hw_set_test_pattern(fimc, fimc->test_pattern->val);
  129. if (debug > 0)
  130. flite_hw_dump_regs(fimc, __func__);
  131. spin_unlock_irqrestore(&fimc->slock, flags);
  132. return 0;
  133. }
  134. /*
  135. * Reinitialize the driver so it is ready to start the streaming again.
  136. * Set fimc->state to indicate stream off and the hardware shut down state.
  137. * If not suspending (@suspend is false), return any buffers to videobuf2.
  138. * Otherwise put any owned buffers onto the pending buffers queue, so they
  139. * can be re-spun when the device is being resumed. Also perform FIMC
  140. * software reset and disable streaming on the whole pipeline if required.
  141. */
  142. static int fimc_lite_reinit(struct fimc_lite *fimc, bool suspend)
  143. {
  144. struct flite_buffer *buf;
  145. unsigned long flags;
  146. bool streaming;
  147. spin_lock_irqsave(&fimc->slock, flags);
  148. streaming = fimc->state & (1 << ST_SENSOR_STREAM);
  149. fimc->state &= ~(1 << ST_FLITE_RUN | 1 << ST_FLITE_OFF |
  150. 1 << ST_FLITE_STREAM | 1 << ST_SENSOR_STREAM);
  151. if (suspend)
  152. fimc->state |= (1 << ST_FLITE_SUSPENDED);
  153. else
  154. fimc->state &= ~(1 << ST_FLITE_PENDING |
  155. 1 << ST_FLITE_SUSPENDED);
  156. /* Release unused buffers */
  157. while (!suspend && !list_empty(&fimc->pending_buf_q)) {
  158. buf = fimc_lite_pending_queue_pop(fimc);
  159. vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
  160. }
  161. /* If suspending put unused buffers onto pending queue */
  162. while (!list_empty(&fimc->active_buf_q)) {
  163. buf = fimc_lite_active_queue_pop(fimc);
  164. if (suspend)
  165. fimc_lite_pending_queue_add(fimc, buf);
  166. else
  167. vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
  168. }
  169. spin_unlock_irqrestore(&fimc->slock, flags);
  170. flite_hw_reset(fimc);
  171. if (!streaming)
  172. return 0;
  173. return fimc_pipeline_s_stream(&fimc->pipeline, 0);
  174. }
  175. static int fimc_lite_stop_capture(struct fimc_lite *fimc, bool suspend)
  176. {
  177. unsigned long flags;
  178. if (!fimc_lite_active(fimc))
  179. return 0;
  180. spin_lock_irqsave(&fimc->slock, flags);
  181. set_bit(ST_FLITE_OFF, &fimc->state);
  182. flite_hw_capture_stop(fimc);
  183. spin_unlock_irqrestore(&fimc->slock, flags);
  184. wait_event_timeout(fimc->irq_queue,
  185. !test_bit(ST_FLITE_OFF, &fimc->state),
  186. (2*HZ/10)); /* 200 ms */
  187. return fimc_lite_reinit(fimc, suspend);
  188. }
  189. /* Must be called with fimc.slock spinlock held. */
  190. static void fimc_lite_config_update(struct fimc_lite *fimc)
  191. {
  192. flite_hw_set_window_offset(fimc, &fimc->inp_frame);
  193. flite_hw_set_dma_window(fimc, &fimc->out_frame);
  194. flite_hw_set_test_pattern(fimc, fimc->test_pattern->val);
  195. clear_bit(ST_FLITE_CONFIG, &fimc->state);
  196. }
  197. static irqreturn_t flite_irq_handler(int irq, void *priv)
  198. {
  199. struct fimc_lite *fimc = priv;
  200. struct flite_buffer *vbuf;
  201. unsigned long flags;
  202. struct timeval *tv;
  203. struct timespec ts;
  204. u32 intsrc;
  205. spin_lock_irqsave(&fimc->slock, flags);
  206. intsrc = flite_hw_get_interrupt_source(fimc);
  207. flite_hw_clear_pending_irq(fimc);
  208. if (test_and_clear_bit(ST_FLITE_OFF, &fimc->state)) {
  209. wake_up(&fimc->irq_queue);
  210. goto done;
  211. }
  212. if (intsrc & FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW) {
  213. clear_bit(ST_FLITE_RUN, &fimc->state);
  214. fimc->events.data_overflow++;
  215. }
  216. if (intsrc & FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND) {
  217. flite_hw_clear_last_capture_end(fimc);
  218. clear_bit(ST_FLITE_STREAM, &fimc->state);
  219. wake_up(&fimc->irq_queue);
  220. }
  221. if (fimc->out_path != FIMC_IO_DMA)
  222. goto done;
  223. if ((intsrc & FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART) &&
  224. test_bit(ST_FLITE_RUN, &fimc->state) &&
  225. !list_empty(&fimc->active_buf_q) &&
  226. !list_empty(&fimc->pending_buf_q)) {
  227. vbuf = fimc_lite_active_queue_pop(fimc);
  228. ktime_get_ts(&ts);
  229. tv = &vbuf->vb.v4l2_buf.timestamp;
  230. tv->tv_sec = ts.tv_sec;
  231. tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
  232. vbuf->vb.v4l2_buf.sequence = fimc->frame_count++;
  233. vb2_buffer_done(&vbuf->vb, VB2_BUF_STATE_DONE);
  234. vbuf = fimc_lite_pending_queue_pop(fimc);
  235. flite_hw_set_output_addr(fimc, vbuf->paddr);
  236. fimc_lite_active_queue_add(fimc, vbuf);
  237. }
  238. if (test_bit(ST_FLITE_CONFIG, &fimc->state))
  239. fimc_lite_config_update(fimc);
  240. if (list_empty(&fimc->pending_buf_q)) {
  241. flite_hw_capture_stop(fimc);
  242. clear_bit(ST_FLITE_STREAM, &fimc->state);
  243. }
  244. done:
  245. set_bit(ST_FLITE_RUN, &fimc->state);
  246. spin_unlock_irqrestore(&fimc->slock, flags);
  247. return IRQ_HANDLED;
  248. }
  249. static int start_streaming(struct vb2_queue *q, unsigned int count)
  250. {
  251. struct fimc_lite *fimc = q->drv_priv;
  252. int ret;
  253. fimc->frame_count = 0;
  254. ret = fimc_lite_hw_init(fimc);
  255. if (ret) {
  256. fimc_lite_reinit(fimc, false);
  257. return ret;
  258. }
  259. set_bit(ST_FLITE_PENDING, &fimc->state);
  260. if (!list_empty(&fimc->active_buf_q) &&
  261. !test_and_set_bit(ST_FLITE_STREAM, &fimc->state)) {
  262. flite_hw_capture_start(fimc);
  263. if (!test_and_set_bit(ST_SENSOR_STREAM, &fimc->state))
  264. fimc_pipeline_s_stream(&fimc->pipeline, 1);
  265. }
  266. if (debug > 0)
  267. flite_hw_dump_regs(fimc, __func__);
  268. return 0;
  269. }
  270. static int stop_streaming(struct vb2_queue *q)
  271. {
  272. struct fimc_lite *fimc = q->drv_priv;
  273. if (!fimc_lite_active(fimc))
  274. return -EINVAL;
  275. return fimc_lite_stop_capture(fimc, false);
  276. }
  277. static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *pfmt,
  278. unsigned int *num_buffers, unsigned int *num_planes,
  279. unsigned int sizes[], void *allocators[])
  280. {
  281. const struct v4l2_pix_format_mplane *pixm = NULL;
  282. struct fimc_lite *fimc = vq->drv_priv;
  283. struct flite_frame *frame = &fimc->out_frame;
  284. const struct fimc_fmt *fmt = fimc->fmt;
  285. unsigned long wh;
  286. int i;
  287. if (pfmt) {
  288. pixm = &pfmt->fmt.pix_mp;
  289. fmt = fimc_lite_find_format(&pixm->pixelformat, NULL, -1);
  290. wh = pixm->width * pixm->height;
  291. } else {
  292. wh = frame->f_width * frame->f_height;
  293. }
  294. if (fmt == NULL)
  295. return -EINVAL;
  296. *num_planes = fmt->memplanes;
  297. for (i = 0; i < fmt->memplanes; i++) {
  298. unsigned int size = (wh * fmt->depth[i]) / 8;
  299. if (pixm)
  300. sizes[i] = max(size, pixm->plane_fmt[i].sizeimage);
  301. else
  302. sizes[i] = size;
  303. allocators[i] = fimc->alloc_ctx;
  304. }
  305. return 0;
  306. }
  307. static int buffer_prepare(struct vb2_buffer *vb)
  308. {
  309. struct vb2_queue *vq = vb->vb2_queue;
  310. struct fimc_lite *fimc = vq->drv_priv;
  311. int i;
  312. if (fimc->fmt == NULL)
  313. return -EINVAL;
  314. for (i = 0; i < fimc->fmt->memplanes; i++) {
  315. unsigned long size = fimc->payload[i];
  316. if (vb2_plane_size(vb, i) < size) {
  317. v4l2_err(fimc->vfd,
  318. "User buffer too small (%ld < %ld)\n",
  319. vb2_plane_size(vb, i), size);
  320. return -EINVAL;
  321. }
  322. vb2_set_plane_payload(vb, i, size);
  323. }
  324. return 0;
  325. }
  326. static void buffer_queue(struct vb2_buffer *vb)
  327. {
  328. struct flite_buffer *buf
  329. = container_of(vb, struct flite_buffer, vb);
  330. struct fimc_lite *fimc = vb2_get_drv_priv(vb->vb2_queue);
  331. unsigned long flags;
  332. spin_lock_irqsave(&fimc->slock, flags);
  333. buf->paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
  334. if (!test_bit(ST_FLITE_SUSPENDED, &fimc->state) &&
  335. !test_bit(ST_FLITE_STREAM, &fimc->state) &&
  336. list_empty(&fimc->active_buf_q)) {
  337. flite_hw_set_output_addr(fimc, buf->paddr);
  338. fimc_lite_active_queue_add(fimc, buf);
  339. } else {
  340. fimc_lite_pending_queue_add(fimc, buf);
  341. }
  342. if (vb2_is_streaming(&fimc->vb_queue) &&
  343. !list_empty(&fimc->pending_buf_q) &&
  344. !test_and_set_bit(ST_FLITE_STREAM, &fimc->state)) {
  345. flite_hw_capture_start(fimc);
  346. spin_unlock_irqrestore(&fimc->slock, flags);
  347. if (!test_and_set_bit(ST_SENSOR_STREAM, &fimc->state))
  348. fimc_pipeline_s_stream(&fimc->pipeline, 1);
  349. return;
  350. }
  351. spin_unlock_irqrestore(&fimc->slock, flags);
  352. }
  353. static void fimc_lock(struct vb2_queue *vq)
  354. {
  355. struct fimc_lite *fimc = vb2_get_drv_priv(vq);
  356. mutex_lock(&fimc->lock);
  357. }
  358. static void fimc_unlock(struct vb2_queue *vq)
  359. {
  360. struct fimc_lite *fimc = vb2_get_drv_priv(vq);
  361. mutex_unlock(&fimc->lock);
  362. }
  363. static const struct vb2_ops fimc_lite_qops = {
  364. .queue_setup = queue_setup,
  365. .buf_prepare = buffer_prepare,
  366. .buf_queue = buffer_queue,
  367. .wait_prepare = fimc_unlock,
  368. .wait_finish = fimc_lock,
  369. .start_streaming = start_streaming,
  370. .stop_streaming = stop_streaming,
  371. };
  372. static void fimc_lite_clear_event_counters(struct fimc_lite *fimc)
  373. {
  374. unsigned long flags;
  375. spin_lock_irqsave(&fimc->slock, flags);
  376. memset(&fimc->events, 0, sizeof(fimc->events));
  377. spin_unlock_irqrestore(&fimc->slock, flags);
  378. }
  379. static int fimc_lite_open(struct file *file)
  380. {
  381. struct fimc_lite *fimc = video_drvdata(file);
  382. int ret;
  383. if (mutex_lock_interruptible(&fimc->lock))
  384. return -ERESTARTSYS;
  385. set_bit(ST_FLITE_IN_USE, &fimc->state);
  386. ret = pm_runtime_get_sync(&fimc->pdev->dev);
  387. if (ret < 0)
  388. goto done;
  389. ret = v4l2_fh_open(file);
  390. if (ret < 0)
  391. goto done;
  392. if (++fimc->ref_count == 1 && fimc->out_path == FIMC_IO_DMA) {
  393. ret = fimc_pipeline_initialize(&fimc->pipeline,
  394. &fimc->vfd->entity, true);
  395. if (ret < 0) {
  396. pm_runtime_put_sync(&fimc->pdev->dev);
  397. fimc->ref_count--;
  398. v4l2_fh_release(file);
  399. clear_bit(ST_FLITE_IN_USE, &fimc->state);
  400. }
  401. fimc_lite_clear_event_counters(fimc);
  402. }
  403. done:
  404. mutex_unlock(&fimc->lock);
  405. return ret;
  406. }
  407. static int fimc_lite_close(struct file *file)
  408. {
  409. struct fimc_lite *fimc = video_drvdata(file);
  410. int ret;
  411. if (mutex_lock_interruptible(&fimc->lock))
  412. return -ERESTARTSYS;
  413. if (--fimc->ref_count == 0 && fimc->out_path == FIMC_IO_DMA) {
  414. clear_bit(ST_FLITE_IN_USE, &fimc->state);
  415. fimc_lite_stop_capture(fimc, false);
  416. fimc_pipeline_shutdown(&fimc->pipeline);
  417. clear_bit(ST_FLITE_SUSPENDED, &fimc->state);
  418. }
  419. pm_runtime_put(&fimc->pdev->dev);
  420. if (fimc->ref_count == 0)
  421. vb2_queue_release(&fimc->vb_queue);
  422. ret = v4l2_fh_release(file);
  423. mutex_unlock(&fimc->lock);
  424. return ret;
  425. }
  426. static unsigned int fimc_lite_poll(struct file *file,
  427. struct poll_table_struct *wait)
  428. {
  429. struct fimc_lite *fimc = video_drvdata(file);
  430. int ret;
  431. if (mutex_lock_interruptible(&fimc->lock))
  432. return POLL_ERR;
  433. ret = vb2_poll(&fimc->vb_queue, file, wait);
  434. mutex_unlock(&fimc->lock);
  435. return ret;
  436. }
  437. static int fimc_lite_mmap(struct file *file, struct vm_area_struct *vma)
  438. {
  439. struct fimc_lite *fimc = video_drvdata(file);
  440. int ret;
  441. if (mutex_lock_interruptible(&fimc->lock))
  442. return -ERESTARTSYS;
  443. ret = vb2_mmap(&fimc->vb_queue, vma);
  444. mutex_unlock(&fimc->lock);
  445. return ret;
  446. }
  447. static const struct v4l2_file_operations fimc_lite_fops = {
  448. .owner = THIS_MODULE,
  449. .open = fimc_lite_open,
  450. .release = fimc_lite_close,
  451. .poll = fimc_lite_poll,
  452. .unlocked_ioctl = video_ioctl2,
  453. .mmap = fimc_lite_mmap,
  454. };
  455. /*
  456. * Format and crop negotiation helpers
  457. */
  458. static const struct fimc_fmt *fimc_lite_try_format(struct fimc_lite *fimc,
  459. u32 *width, u32 *height,
  460. u32 *code, u32 *fourcc, int pad)
  461. {
  462. struct flite_variant *variant = fimc->variant;
  463. const struct fimc_fmt *fmt;
  464. fmt = fimc_lite_find_format(fourcc, code, 0);
  465. if (WARN_ON(!fmt))
  466. return NULL;
  467. if (code)
  468. *code = fmt->mbus_code;
  469. if (fourcc)
  470. *fourcc = fmt->fourcc;
  471. if (pad == FLITE_SD_PAD_SINK) {
  472. v4l_bound_align_image(width, 8, variant->max_width,
  473. ffs(variant->out_width_align) - 1,
  474. height, 0, variant->max_height, 0, 0);
  475. } else {
  476. v4l_bound_align_image(width, 8, fimc->inp_frame.rect.width,
  477. ffs(variant->out_width_align) - 1,
  478. height, 0, fimc->inp_frame.rect.height,
  479. 0, 0);
  480. }
  481. v4l2_dbg(1, debug, &fimc->subdev, "code: 0x%x, %dx%d\n",
  482. code ? *code : 0, *width, *height);
  483. return fmt;
  484. }
  485. static void fimc_lite_try_crop(struct fimc_lite *fimc, struct v4l2_rect *r)
  486. {
  487. struct flite_frame *frame = &fimc->inp_frame;
  488. v4l_bound_align_image(&r->width, 0, frame->f_width, 0,
  489. &r->height, 0, frame->f_height, 0, 0);
  490. /* Adjust left/top if cropping rectangle got out of bounds */
  491. r->left = clamp_t(u32, r->left, 0, frame->f_width - r->width);
  492. r->left = round_down(r->left, fimc->variant->win_hor_offs_align);
  493. r->top = clamp_t(u32, r->top, 0, frame->f_height - r->height);
  494. v4l2_dbg(1, debug, &fimc->subdev, "(%d,%d)/%dx%d, sink fmt: %dx%d",
  495. r->left, r->top, r->width, r->height,
  496. frame->f_width, frame->f_height);
  497. }
  498. static void fimc_lite_try_compose(struct fimc_lite *fimc, struct v4l2_rect *r)
  499. {
  500. struct flite_frame *frame = &fimc->out_frame;
  501. struct v4l2_rect *crop_rect = &fimc->inp_frame.rect;
  502. /* Scaling is not supported so we enforce compose rectangle size
  503. same as size of the sink crop rectangle. */
  504. r->width = crop_rect->width;
  505. r->height = crop_rect->height;
  506. /* Adjust left/top if the composing rectangle got out of bounds */
  507. r->left = clamp_t(u32, r->left, 0, frame->f_width - r->width);
  508. r->left = round_down(r->left, fimc->variant->out_hor_offs_align);
  509. r->top = clamp_t(u32, r->top, 0, fimc->out_frame.f_height - r->height);
  510. v4l2_dbg(1, debug, &fimc->subdev, "(%d,%d)/%dx%d, source fmt: %dx%d",
  511. r->left, r->top, r->width, r->height,
  512. frame->f_width, frame->f_height);
  513. }
  514. /*
  515. * Video node ioctl operations
  516. */
  517. static int fimc_vidioc_querycap_capture(struct file *file, void *priv,
  518. struct v4l2_capability *cap)
  519. {
  520. strlcpy(cap->driver, FIMC_LITE_DRV_NAME, sizeof(cap->driver));
  521. cap->bus_info[0] = 0;
  522. cap->card[0] = 0;
  523. cap->capabilities = V4L2_CAP_STREAMING;
  524. return 0;
  525. }
  526. static int fimc_lite_enum_fmt_mplane(struct file *file, void *priv,
  527. struct v4l2_fmtdesc *f)
  528. {
  529. const struct fimc_fmt *fmt;
  530. if (f->index >= ARRAY_SIZE(fimc_lite_formats))
  531. return -EINVAL;
  532. fmt = &fimc_lite_formats[f->index];
  533. strlcpy(f->description, fmt->name, sizeof(f->description));
  534. f->pixelformat = fmt->fourcc;
  535. return 0;
  536. }
  537. static int fimc_lite_g_fmt_mplane(struct file *file, void *fh,
  538. struct v4l2_format *f)
  539. {
  540. struct fimc_lite *fimc = video_drvdata(file);
  541. struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
  542. struct v4l2_plane_pix_format *plane_fmt = &pixm->plane_fmt[0];
  543. struct flite_frame *frame = &fimc->out_frame;
  544. const struct fimc_fmt *fmt = fimc->fmt;
  545. plane_fmt->bytesperline = (frame->f_width * fmt->depth[0]) / 8;
  546. plane_fmt->sizeimage = plane_fmt->bytesperline * frame->f_height;
  547. pixm->num_planes = fmt->memplanes;
  548. pixm->pixelformat = fmt->fourcc;
  549. pixm->width = frame->f_width;
  550. pixm->height = frame->f_height;
  551. pixm->field = V4L2_FIELD_NONE;
  552. pixm->colorspace = V4L2_COLORSPACE_JPEG;
  553. return 0;
  554. }
  555. static int fimc_lite_try_fmt(struct fimc_lite *fimc,
  556. struct v4l2_pix_format_mplane *pixm,
  557. const struct fimc_fmt **ffmt)
  558. {
  559. struct flite_variant *variant = fimc->variant;
  560. u32 bpl = pixm->plane_fmt[0].bytesperline;
  561. const struct fimc_fmt *fmt;
  562. fmt = fimc_lite_find_format(&pixm->pixelformat, NULL, 0);
  563. if (WARN_ON(fmt == NULL))
  564. return -EINVAL;
  565. if (ffmt)
  566. *ffmt = fmt;
  567. v4l_bound_align_image(&pixm->width, 8, variant->max_width,
  568. ffs(variant->out_width_align) - 1,
  569. &pixm->height, 0, variant->max_height, 0, 0);
  570. if ((bpl == 0 || ((bpl * 8) / fmt->depth[0]) < pixm->width))
  571. pixm->plane_fmt[0].bytesperline = (pixm->width *
  572. fmt->depth[0]) / 8;
  573. if (pixm->plane_fmt[0].sizeimage == 0)
  574. pixm->plane_fmt[0].sizeimage = (pixm->width * pixm->height *
  575. fmt->depth[0]) / 8;
  576. pixm->num_planes = fmt->memplanes;
  577. pixm->pixelformat = fmt->fourcc;
  578. pixm->colorspace = V4L2_COLORSPACE_JPEG;
  579. pixm->field = V4L2_FIELD_NONE;
  580. return 0;
  581. }
  582. static int fimc_lite_try_fmt_mplane(struct file *file, void *fh,
  583. struct v4l2_format *f)
  584. {
  585. struct fimc_lite *fimc = video_drvdata(file);
  586. return fimc_lite_try_fmt(fimc, &f->fmt.pix_mp, NULL);
  587. }
  588. static int fimc_lite_s_fmt_mplane(struct file *file, void *priv,
  589. struct v4l2_format *f)
  590. {
  591. struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
  592. struct fimc_lite *fimc = video_drvdata(file);
  593. struct flite_frame *frame = &fimc->out_frame;
  594. const struct fimc_fmt *fmt = NULL;
  595. int ret;
  596. if (vb2_is_busy(&fimc->vb_queue))
  597. return -EBUSY;
  598. ret = fimc_lite_try_fmt(fimc, &f->fmt.pix_mp, &fmt);
  599. if (ret < 0)
  600. return ret;
  601. fimc->fmt = fmt;
  602. fimc->payload[0] = max((pixm->width * pixm->height * fmt->depth[0]) / 8,
  603. pixm->plane_fmt[0].sizeimage);
  604. frame->f_width = pixm->width;
  605. frame->f_height = pixm->height;
  606. return 0;
  607. }
  608. static int fimc_pipeline_validate(struct fimc_lite *fimc)
  609. {
  610. struct v4l2_subdev *sd = &fimc->subdev;
  611. struct v4l2_subdev_format sink_fmt, src_fmt;
  612. struct media_pad *pad;
  613. int ret;
  614. while (1) {
  615. /* Retrieve format at the sink pad */
  616. pad = &sd->entity.pads[0];
  617. if (!(pad->flags & MEDIA_PAD_FL_SINK))
  618. break;
  619. /* Don't call FIMC subdev operation to avoid nested locking */
  620. if (sd == &fimc->subdev) {
  621. struct flite_frame *ff = &fimc->out_frame;
  622. sink_fmt.format.width = ff->f_width;
  623. sink_fmt.format.height = ff->f_height;
  624. sink_fmt.format.code = fimc->fmt->mbus_code;
  625. } else {
  626. sink_fmt.pad = pad->index;
  627. sink_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
  628. ret = v4l2_subdev_call(sd, pad, get_fmt, NULL,
  629. &sink_fmt);
  630. if (ret < 0 && ret != -ENOIOCTLCMD)
  631. return -EPIPE;
  632. }
  633. /* Retrieve format at the source pad */
  634. pad = media_entity_remote_source(pad);
  635. if (pad == NULL ||
  636. media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
  637. break;
  638. sd = media_entity_to_v4l2_subdev(pad->entity);
  639. src_fmt.pad = pad->index;
  640. src_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
  641. ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &src_fmt);
  642. if (ret < 0 && ret != -ENOIOCTLCMD)
  643. return -EPIPE;
  644. if (src_fmt.format.width != sink_fmt.format.width ||
  645. src_fmt.format.height != sink_fmt.format.height ||
  646. src_fmt.format.code != sink_fmt.format.code)
  647. return -EPIPE;
  648. }
  649. return 0;
  650. }
  651. static int fimc_lite_streamon(struct file *file, void *priv,
  652. enum v4l2_buf_type type)
  653. {
  654. struct fimc_lite *fimc = video_drvdata(file);
  655. struct v4l2_subdev *sensor = fimc->pipeline.subdevs[IDX_SENSOR];
  656. struct fimc_pipeline *p = &fimc->pipeline;
  657. int ret;
  658. if (fimc_lite_active(fimc))
  659. return -EBUSY;
  660. ret = media_entity_pipeline_start(&sensor->entity, p->m_pipeline);
  661. if (ret < 0)
  662. return ret;
  663. ret = fimc_pipeline_validate(fimc);
  664. if (ret) {
  665. media_entity_pipeline_stop(&sensor->entity);
  666. return ret;
  667. }
  668. return vb2_streamon(&fimc->vb_queue, type);
  669. }
  670. static int fimc_lite_streamoff(struct file *file, void *priv,
  671. enum v4l2_buf_type type)
  672. {
  673. struct fimc_lite *fimc = video_drvdata(file);
  674. struct v4l2_subdev *sd = fimc->pipeline.subdevs[IDX_SENSOR];
  675. int ret;
  676. ret = vb2_streamoff(&fimc->vb_queue, type);
  677. if (ret == 0)
  678. media_entity_pipeline_stop(&sd->entity);
  679. return ret;
  680. }
  681. static int fimc_lite_reqbufs(struct file *file, void *priv,
  682. struct v4l2_requestbuffers *reqbufs)
  683. {
  684. struct fimc_lite *fimc = video_drvdata(file);
  685. int ret;
  686. reqbufs->count = max_t(u32, FLITE_REQ_BUFS_MIN, reqbufs->count);
  687. ret = vb2_reqbufs(&fimc->vb_queue, reqbufs);
  688. if (!ret < 0)
  689. fimc->reqbufs_count = reqbufs->count;
  690. return ret;
  691. }
  692. static int fimc_lite_querybuf(struct file *file, void *priv,
  693. struct v4l2_buffer *buf)
  694. {
  695. struct fimc_lite *fimc = video_drvdata(file);
  696. return vb2_querybuf(&fimc->vb_queue, buf);
  697. }
  698. static int fimc_lite_qbuf(struct file *file, void *priv,
  699. struct v4l2_buffer *buf)
  700. {
  701. struct fimc_lite *fimc = video_drvdata(file);
  702. return vb2_qbuf(&fimc->vb_queue, buf);
  703. }
  704. static int fimc_lite_dqbuf(struct file *file, void *priv,
  705. struct v4l2_buffer *buf)
  706. {
  707. struct fimc_lite *fimc = video_drvdata(file);
  708. return vb2_dqbuf(&fimc->vb_queue, buf, file->f_flags & O_NONBLOCK);
  709. }
  710. static int fimc_lite_create_bufs(struct file *file, void *priv,
  711. struct v4l2_create_buffers *create)
  712. {
  713. struct fimc_lite *fimc = video_drvdata(file);
  714. return vb2_create_bufs(&fimc->vb_queue, create);
  715. }
  716. static int fimc_lite_prepare_buf(struct file *file, void *priv,
  717. struct v4l2_buffer *b)
  718. {
  719. struct fimc_lite *fimc = video_drvdata(file);
  720. return vb2_prepare_buf(&fimc->vb_queue, b);
  721. }
  722. /* Return 1 if rectangle a is enclosed in rectangle b, or 0 otherwise. */
  723. static int enclosed_rectangle(struct v4l2_rect *a, struct v4l2_rect *b)
  724. {
  725. if (a->left < b->left || a->top < b->top)
  726. return 0;
  727. if (a->left + a->width > b->left + b->width)
  728. return 0;
  729. if (a->top + a->height > b->top + b->height)
  730. return 0;
  731. return 1;
  732. }
  733. static int fimc_lite_g_selection(struct file *file, void *fh,
  734. struct v4l2_selection *sel)
  735. {
  736. struct fimc_lite *fimc = video_drvdata(file);
  737. struct flite_frame *f = &fimc->out_frame;
  738. if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
  739. return -EINVAL;
  740. switch (sel->target) {
  741. case V4L2_SEL_TGT_COMPOSE_BOUNDS:
  742. case V4L2_SEL_TGT_COMPOSE_DEFAULT:
  743. sel->r.left = 0;
  744. sel->r.top = 0;
  745. sel->r.width = f->f_width;
  746. sel->r.height = f->f_height;
  747. return 0;
  748. case V4L2_SEL_TGT_COMPOSE_ACTIVE:
  749. sel->r = f->rect;
  750. return 0;
  751. }
  752. return -EINVAL;
  753. }
  754. static int fimc_lite_s_selection(struct file *file, void *fh,
  755. struct v4l2_selection *sel)
  756. {
  757. struct fimc_lite *fimc = video_drvdata(file);
  758. struct flite_frame *f = &fimc->out_frame;
  759. struct v4l2_rect rect = sel->r;
  760. unsigned long flags;
  761. if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE ||
  762. sel->target != V4L2_SEL_TGT_COMPOSE_ACTIVE)
  763. return -EINVAL;
  764. fimc_lite_try_compose(fimc, &rect);
  765. if ((sel->flags & V4L2_SEL_FLAG_LE) &&
  766. !enclosed_rectangle(&rect, &sel->r))
  767. return -ERANGE;
  768. if ((sel->flags & V4L2_SEL_FLAG_GE) &&
  769. !enclosed_rectangle(&sel->r, &rect))
  770. return -ERANGE;
  771. sel->r = rect;
  772. spin_lock_irqsave(&fimc->slock, flags);
  773. f->rect = rect;
  774. set_bit(ST_FLITE_CONFIG, &fimc->state);
  775. spin_unlock_irqrestore(&fimc->slock, flags);
  776. return 0;
  777. }
  778. static const struct v4l2_ioctl_ops fimc_lite_ioctl_ops = {
  779. .vidioc_querycap = fimc_vidioc_querycap_capture,
  780. .vidioc_enum_fmt_vid_cap_mplane = fimc_lite_enum_fmt_mplane,
  781. .vidioc_try_fmt_vid_cap_mplane = fimc_lite_try_fmt_mplane,
  782. .vidioc_s_fmt_vid_cap_mplane = fimc_lite_s_fmt_mplane,
  783. .vidioc_g_fmt_vid_cap_mplane = fimc_lite_g_fmt_mplane,
  784. .vidioc_g_selection = fimc_lite_g_selection,
  785. .vidioc_s_selection = fimc_lite_s_selection,
  786. .vidioc_reqbufs = fimc_lite_reqbufs,
  787. .vidioc_querybuf = fimc_lite_querybuf,
  788. .vidioc_prepare_buf = fimc_lite_prepare_buf,
  789. .vidioc_create_bufs = fimc_lite_create_bufs,
  790. .vidioc_qbuf = fimc_lite_qbuf,
  791. .vidioc_dqbuf = fimc_lite_dqbuf,
  792. .vidioc_streamon = fimc_lite_streamon,
  793. .vidioc_streamoff = fimc_lite_streamoff,
  794. };
  795. /* Capture subdev media entity operations */
  796. static int fimc_lite_link_setup(struct media_entity *entity,
  797. const struct media_pad *local,
  798. const struct media_pad *remote, u32 flags)
  799. {
  800. struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
  801. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  802. unsigned int remote_ent_type = media_entity_type(remote->entity);
  803. if (WARN_ON(fimc == NULL))
  804. return 0;
  805. v4l2_dbg(1, debug, sd, "%s: %s --> %s, flags: 0x%x. source_id: 0x%x",
  806. __func__, local->entity->name, remote->entity->name,
  807. flags, fimc->source_subdev_grp_id);
  808. switch (local->index) {
  809. case FIMC_SD_PAD_SINK:
  810. if (remote_ent_type != MEDIA_ENT_T_V4L2_SUBDEV)
  811. return -EINVAL;
  812. if (flags & MEDIA_LNK_FL_ENABLED) {
  813. if (fimc->source_subdev_grp_id != 0)
  814. return -EBUSY;
  815. fimc->source_subdev_grp_id = sd->grp_id;
  816. return 0;
  817. }
  818. fimc->source_subdev_grp_id = 0;
  819. break;
  820. case FIMC_SD_PAD_SOURCE:
  821. if (!(flags & MEDIA_LNK_FL_ENABLED)) {
  822. fimc->out_path = FIMC_IO_NONE;
  823. return 0;
  824. }
  825. if (remote_ent_type == MEDIA_ENT_T_V4L2_SUBDEV)
  826. fimc->out_path = FIMC_IO_ISP;
  827. else
  828. fimc->out_path = FIMC_IO_DMA;
  829. break;
  830. default:
  831. v4l2_err(sd, "Invalid pad index\n");
  832. return -EINVAL;
  833. }
  834. return 0;
  835. }
  836. static const struct media_entity_operations fimc_lite_subdev_media_ops = {
  837. .link_setup = fimc_lite_link_setup,
  838. };
  839. static int fimc_lite_subdev_enum_mbus_code(struct v4l2_subdev *sd,
  840. struct v4l2_subdev_fh *fh,
  841. struct v4l2_subdev_mbus_code_enum *code)
  842. {
  843. const struct fimc_fmt *fmt;
  844. fmt = fimc_lite_find_format(NULL, NULL, code->index);
  845. if (!fmt)
  846. return -EINVAL;
  847. code->code = fmt->mbus_code;
  848. return 0;
  849. }
  850. static int fimc_lite_subdev_get_fmt(struct v4l2_subdev *sd,
  851. struct v4l2_subdev_fh *fh,
  852. struct v4l2_subdev_format *fmt)
  853. {
  854. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  855. struct v4l2_mbus_framefmt *mf = &fmt->format;
  856. struct flite_frame *f = &fimc->out_frame;
  857. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  858. mf = v4l2_subdev_get_try_format(fh, fmt->pad);
  859. fmt->format = *mf;
  860. return 0;
  861. }
  862. mf->colorspace = V4L2_COLORSPACE_JPEG;
  863. mutex_lock(&fimc->lock);
  864. mf->code = fimc->fmt->mbus_code;
  865. if (fmt->pad == FLITE_SD_PAD_SINK) {
  866. /* full camera input frame size */
  867. mf->width = f->f_width;
  868. mf->height = f->f_height;
  869. } else {
  870. /* crop size */
  871. mf->width = f->rect.width;
  872. mf->height = f->rect.height;
  873. }
  874. mutex_unlock(&fimc->lock);
  875. return 0;
  876. }
  877. static int fimc_lite_subdev_set_fmt(struct v4l2_subdev *sd,
  878. struct v4l2_subdev_fh *fh,
  879. struct v4l2_subdev_format *fmt)
  880. {
  881. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  882. struct v4l2_mbus_framefmt *mf = &fmt->format;
  883. struct flite_frame *sink = &fimc->inp_frame;
  884. const struct fimc_fmt *ffmt;
  885. v4l2_dbg(1, debug, sd, "pad%d: code: 0x%x, %dx%d",
  886. fmt->pad, mf->code, mf->width, mf->height);
  887. mf->colorspace = V4L2_COLORSPACE_JPEG;
  888. mutex_lock(&fimc->lock);
  889. if ((fimc->out_path == FIMC_IO_ISP && sd->entity.stream_count > 0) ||
  890. (fimc->out_path == FIMC_IO_DMA && vb2_is_busy(&fimc->vb_queue))) {
  891. mutex_unlock(&fimc->lock);
  892. return -EBUSY;
  893. }
  894. ffmt = fimc_lite_try_format(fimc, &mf->width, &mf->height,
  895. &mf->code, NULL, fmt->pad);
  896. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  897. mf = v4l2_subdev_get_try_format(fh, fmt->pad);
  898. *mf = fmt->format;
  899. mutex_unlock(&fimc->lock);
  900. return 0;
  901. }
  902. if (fmt->pad == FLITE_SD_PAD_SINK) {
  903. sink->f_width = mf->width;
  904. sink->f_height = mf->height;
  905. fimc->fmt = ffmt;
  906. /* Set sink crop rectangle */
  907. sink->rect.width = mf->width;
  908. sink->rect.height = mf->height;
  909. sink->rect.left = 0;
  910. sink->rect.top = 0;
  911. /* Reset source crop rectangle */
  912. fimc->out_frame.rect = sink->rect;
  913. } else {
  914. /* Allow changing format only on sink pad */
  915. mf->code = fimc->fmt->mbus_code;
  916. mf->width = sink->rect.width;
  917. mf->height = sink->rect.height;
  918. }
  919. mutex_unlock(&fimc->lock);
  920. return 0;
  921. }
  922. static int fimc_lite_subdev_get_selection(struct v4l2_subdev *sd,
  923. struct v4l2_subdev_fh *fh,
  924. struct v4l2_subdev_selection *sel)
  925. {
  926. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  927. struct flite_frame *f = &fimc->inp_frame;
  928. if ((sel->target != V4L2_SUBDEV_SEL_TGT_CROP_ACTUAL &&
  929. sel->target != V4L2_SUBDEV_SEL_TGT_CROP_BOUNDS) ||
  930. sel->pad != FLITE_SD_PAD_SINK)
  931. return -EINVAL;
  932. if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
  933. sel->r = *v4l2_subdev_get_try_crop(fh, sel->pad);
  934. return 0;
  935. }
  936. mutex_lock(&fimc->lock);
  937. if (sel->target == V4L2_SUBDEV_SEL_TGT_CROP_ACTUAL) {
  938. sel->r = f->rect;
  939. } else {
  940. sel->r.left = 0;
  941. sel->r.top = 0;
  942. sel->r.width = f->f_width;
  943. sel->r.height = f->f_height;
  944. }
  945. mutex_unlock(&fimc->lock);
  946. v4l2_dbg(1, debug, sd, "%s: (%d,%d) %dx%d, f_w: %d, f_h: %d",
  947. __func__, f->rect.left, f->rect.top, f->rect.width,
  948. f->rect.height, f->f_width, f->f_height);
  949. return 0;
  950. }
  951. static int fimc_lite_subdev_set_selection(struct v4l2_subdev *sd,
  952. struct v4l2_subdev_fh *fh,
  953. struct v4l2_subdev_selection *sel)
  954. {
  955. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  956. struct flite_frame *f = &fimc->inp_frame;
  957. int ret = 0;
  958. if (sel->target != V4L2_SUBDEV_SEL_TGT_CROP_ACTUAL ||
  959. sel->pad != FLITE_SD_PAD_SINK)
  960. return -EINVAL;
  961. mutex_lock(&fimc->lock);
  962. fimc_lite_try_crop(fimc, &sel->r);
  963. if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
  964. *v4l2_subdev_get_try_crop(fh, sel->pad) = sel->r;
  965. } else {
  966. unsigned long flags;
  967. spin_lock_irqsave(&fimc->slock, flags);
  968. f->rect = sel->r;
  969. /* Same crop rectangle on the source pad */
  970. fimc->out_frame.rect = sel->r;
  971. set_bit(ST_FLITE_CONFIG, &fimc->state);
  972. spin_unlock_irqrestore(&fimc->slock, flags);
  973. }
  974. mutex_unlock(&fimc->lock);
  975. v4l2_dbg(1, debug, sd, "%s: (%d,%d) %dx%d, f_w: %d, f_h: %d",
  976. __func__, f->rect.left, f->rect.top, f->rect.width,
  977. f->rect.height, f->f_width, f->f_height);
  978. return ret;
  979. }
  980. static int fimc_lite_subdev_s_stream(struct v4l2_subdev *sd, int on)
  981. {
  982. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  983. if (fimc->out_path == FIMC_IO_DMA)
  984. return -ENOIOCTLCMD;
  985. /* TODO: */
  986. return 0;
  987. }
  988. static int fimc_lite_subdev_s_power(struct v4l2_subdev *sd, int on)
  989. {
  990. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  991. if (fimc->out_path == FIMC_IO_DMA)
  992. return -ENOIOCTLCMD;
  993. /* TODO: */
  994. return 0;
  995. }
  996. static int fimc_lite_log_status(struct v4l2_subdev *sd)
  997. {
  998. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  999. flite_hw_dump_regs(fimc, __func__);
  1000. return 0;
  1001. }
  1002. static int fimc_lite_subdev_registered(struct v4l2_subdev *sd)
  1003. {
  1004. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1005. struct vb2_queue *q = &fimc->vb_queue;
  1006. struct video_device *vfd;
  1007. int ret;
  1008. fimc->fmt = &fimc_lite_formats[0];
  1009. fimc->out_path = FIMC_IO_DMA;
  1010. vfd = video_device_alloc();
  1011. if (!vfd) {
  1012. v4l2_err(sd->v4l2_dev, "Failed to allocate video device\n");
  1013. return -ENOMEM;
  1014. }
  1015. snprintf(vfd->name, sizeof(vfd->name), "fimc-lite.%d.capture",
  1016. fimc->index);
  1017. vfd->fops = &fimc_lite_fops;
  1018. vfd->ioctl_ops = &fimc_lite_ioctl_ops;
  1019. vfd->v4l2_dev = sd->v4l2_dev;
  1020. vfd->minor = -1;
  1021. vfd->release = video_device_release;
  1022. vfd->lock = &fimc->lock;
  1023. fimc->vfd = vfd;
  1024. fimc->ref_count = 0;
  1025. fimc->reqbufs_count = 0;
  1026. INIT_LIST_HEAD(&fimc->pending_buf_q);
  1027. INIT_LIST_HEAD(&fimc->active_buf_q);
  1028. memset(q, 0, sizeof(*q));
  1029. q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
  1030. q->io_modes = VB2_MMAP | VB2_USERPTR;
  1031. q->ops = &fimc_lite_qops;
  1032. q->mem_ops = &vb2_dma_contig_memops;
  1033. q->buf_struct_size = sizeof(struct flite_buffer);
  1034. q->drv_priv = fimc;
  1035. vb2_queue_init(q);
  1036. fimc->vd_pad.flags = MEDIA_PAD_FL_SINK;
  1037. ret = media_entity_init(&vfd->entity, 1, &fimc->vd_pad, 0);
  1038. if (ret)
  1039. goto err;
  1040. video_set_drvdata(vfd, fimc);
  1041. ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
  1042. if (ret)
  1043. goto err_vd;
  1044. v4l2_info(sd->v4l2_dev, "Registered %s as /dev/%s\n",
  1045. vfd->name, video_device_node_name(vfd));
  1046. return 0;
  1047. err_vd:
  1048. media_entity_cleanup(&vfd->entity);
  1049. err:
  1050. video_device_release(vfd);
  1051. return ret;
  1052. }
  1053. static void fimc_lite_subdev_unregistered(struct v4l2_subdev *sd)
  1054. {
  1055. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1056. if (fimc == NULL)
  1057. return;
  1058. if (fimc->vfd) {
  1059. video_unregister_device(fimc->vfd);
  1060. media_entity_cleanup(&fimc->vfd->entity);
  1061. fimc->vfd = NULL;
  1062. }
  1063. }
  1064. static const struct v4l2_subdev_internal_ops fimc_lite_subdev_internal_ops = {
  1065. .registered = fimc_lite_subdev_registered,
  1066. .unregistered = fimc_lite_subdev_unregistered,
  1067. };
  1068. static const struct v4l2_subdev_pad_ops fimc_lite_subdev_pad_ops = {
  1069. .enum_mbus_code = fimc_lite_subdev_enum_mbus_code,
  1070. .get_selection = fimc_lite_subdev_get_selection,
  1071. .set_selection = fimc_lite_subdev_set_selection,
  1072. .get_fmt = fimc_lite_subdev_get_fmt,
  1073. .set_fmt = fimc_lite_subdev_set_fmt,
  1074. };
  1075. static const struct v4l2_subdev_video_ops fimc_lite_subdev_video_ops = {
  1076. .s_stream = fimc_lite_subdev_s_stream,
  1077. };
  1078. static const struct v4l2_subdev_core_ops fimc_lite_core_ops = {
  1079. .s_power = fimc_lite_subdev_s_power,
  1080. .log_status = fimc_lite_log_status,
  1081. };
  1082. static struct v4l2_subdev_ops fimc_lite_subdev_ops = {
  1083. .core = &fimc_lite_core_ops,
  1084. .video = &fimc_lite_subdev_video_ops,
  1085. .pad = &fimc_lite_subdev_pad_ops,
  1086. };
  1087. static int fimc_lite_s_ctrl(struct v4l2_ctrl *ctrl)
  1088. {
  1089. struct fimc_lite *fimc = container_of(ctrl->handler, struct fimc_lite,
  1090. ctrl_handler);
  1091. set_bit(ST_FLITE_CONFIG, &fimc->state);
  1092. return 0;
  1093. }
  1094. static const struct v4l2_ctrl_ops fimc_lite_ctrl_ops = {
  1095. .s_ctrl = fimc_lite_s_ctrl,
  1096. };
  1097. static const struct v4l2_ctrl_config fimc_lite_ctrl = {
  1098. .ops = &fimc_lite_ctrl_ops,
  1099. .id = V4L2_CTRL_CLASS_USER | 0x1001,
  1100. .type = V4L2_CTRL_TYPE_BOOLEAN,
  1101. .name = "Test Pattern 640x480",
  1102. };
  1103. static int fimc_lite_create_capture_subdev(struct fimc_lite *fimc)
  1104. {
  1105. struct v4l2_ctrl_handler *handler = &fimc->ctrl_handler;
  1106. struct v4l2_subdev *sd = &fimc->subdev;
  1107. int ret;
  1108. v4l2_subdev_init(sd, &fimc_lite_subdev_ops);
  1109. sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
  1110. snprintf(sd->name, sizeof(sd->name), "FIMC-LITE.%d", fimc->index);
  1111. fimc->subdev_pads[FIMC_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
  1112. fimc->subdev_pads[FIMC_SD_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
  1113. ret = media_entity_init(&sd->entity, FIMC_SD_PADS_NUM,
  1114. fimc->subdev_pads, 0);
  1115. if (ret)
  1116. return ret;
  1117. v4l2_ctrl_handler_init(handler, 1);
  1118. fimc->test_pattern = v4l2_ctrl_new_custom(handler, &fimc_lite_ctrl,
  1119. NULL);
  1120. if (handler->error) {
  1121. media_entity_cleanup(&sd->entity);
  1122. return handler->error;
  1123. }
  1124. sd->ctrl_handler = handler;
  1125. sd->internal_ops = &fimc_lite_subdev_internal_ops;
  1126. sd->entity.ops = &fimc_lite_subdev_media_ops;
  1127. v4l2_set_subdevdata(sd, fimc);
  1128. return 0;
  1129. }
  1130. static void fimc_lite_unregister_capture_subdev(struct fimc_lite *fimc)
  1131. {
  1132. struct v4l2_subdev *sd = &fimc->subdev;
  1133. v4l2_device_unregister_subdev(sd);
  1134. media_entity_cleanup(&sd->entity);
  1135. v4l2_ctrl_handler_free(&fimc->ctrl_handler);
  1136. v4l2_set_subdevdata(sd, NULL);
  1137. }
  1138. static void fimc_lite_clk_put(struct fimc_lite *fimc)
  1139. {
  1140. if (IS_ERR_OR_NULL(fimc->clock))
  1141. return;
  1142. clk_unprepare(fimc->clock);
  1143. clk_put(fimc->clock);
  1144. fimc->clock = NULL;
  1145. }
  1146. static int fimc_lite_clk_get(struct fimc_lite *fimc)
  1147. {
  1148. int ret;
  1149. fimc->clock = clk_get(&fimc->pdev->dev, FLITE_CLK_NAME);
  1150. if (IS_ERR(fimc->clock))
  1151. return PTR_ERR(fimc->clock);
  1152. ret = clk_prepare(fimc->clock);
  1153. if (ret < 0) {
  1154. clk_put(fimc->clock);
  1155. fimc->clock = NULL;
  1156. }
  1157. return ret;
  1158. }
  1159. static int __devinit fimc_lite_probe(struct platform_device *pdev)
  1160. {
  1161. struct flite_drvdata *drv_data = fimc_lite_get_drvdata(pdev);
  1162. struct fimc_lite *fimc;
  1163. struct resource *res;
  1164. int ret;
  1165. fimc = devm_kzalloc(&pdev->dev, sizeof(*fimc), GFP_KERNEL);
  1166. if (!fimc)
  1167. return -ENOMEM;
  1168. fimc->index = pdev->id;
  1169. fimc->variant = drv_data->variant[fimc->index];
  1170. fimc->pdev = pdev;
  1171. init_waitqueue_head(&fimc->irq_queue);
  1172. spin_lock_init(&fimc->slock);
  1173. mutex_init(&fimc->lock);
  1174. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1175. fimc->regs = devm_request_and_ioremap(&pdev->dev, res);
  1176. if (fimc->regs == NULL) {
  1177. dev_err(&pdev->dev, "Failed to obtain io memory\n");
  1178. return -ENOENT;
  1179. }
  1180. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1181. if (res == NULL) {
  1182. dev_err(&pdev->dev, "Failed to get IRQ resource\n");
  1183. return -ENXIO;
  1184. }
  1185. ret = fimc_lite_clk_get(fimc);
  1186. if (ret)
  1187. return ret;
  1188. ret = devm_request_irq(&pdev->dev, res->start, flite_irq_handler,
  1189. 0, dev_name(&pdev->dev), fimc);
  1190. if (ret) {
  1191. dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
  1192. goto err_clk;
  1193. }
  1194. /* The video node will be created within the subdev's registered() op */
  1195. ret = fimc_lite_create_capture_subdev(fimc);
  1196. if (ret)
  1197. goto err_clk;
  1198. platform_set_drvdata(pdev, fimc);
  1199. pm_runtime_enable(&pdev->dev);
  1200. ret = pm_runtime_get_sync(&pdev->dev);
  1201. if (ret < 0)
  1202. goto err_sd;
  1203. fimc->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
  1204. if (IS_ERR(fimc->alloc_ctx)) {
  1205. ret = PTR_ERR(fimc->alloc_ctx);
  1206. goto err_pm;
  1207. }
  1208. pm_runtime_put(&pdev->dev);
  1209. dev_dbg(&pdev->dev, "FIMC-LITE.%d registered successfully\n",
  1210. fimc->index);
  1211. return 0;
  1212. err_pm:
  1213. pm_runtime_put(&pdev->dev);
  1214. err_sd:
  1215. fimc_lite_unregister_capture_subdev(fimc);
  1216. err_clk:
  1217. fimc_lite_clk_put(fimc);
  1218. return ret;
  1219. }
  1220. static int fimc_lite_runtime_resume(struct device *dev)
  1221. {
  1222. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1223. clk_enable(fimc->clock);
  1224. return 0;
  1225. }
  1226. static int fimc_lite_runtime_suspend(struct device *dev)
  1227. {
  1228. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1229. clk_disable(fimc->clock);
  1230. return 0;
  1231. }
  1232. #ifdef CONFIG_PM_SLEEP
  1233. static int fimc_lite_resume(struct device *dev)
  1234. {
  1235. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1236. struct flite_buffer *buf;
  1237. unsigned long flags;
  1238. int i;
  1239. spin_lock_irqsave(&fimc->slock, flags);
  1240. if (!test_and_clear_bit(ST_LPM, &fimc->state) ||
  1241. !test_bit(ST_FLITE_IN_USE, &fimc->state)) {
  1242. spin_unlock_irqrestore(&fimc->slock, flags);
  1243. return 0;
  1244. }
  1245. flite_hw_reset(fimc);
  1246. spin_unlock_irqrestore(&fimc->slock, flags);
  1247. if (!test_and_clear_bit(ST_FLITE_SUSPENDED, &fimc->state))
  1248. return 0;
  1249. INIT_LIST_HEAD(&fimc->active_buf_q);
  1250. fimc_pipeline_initialize(&fimc->pipeline, &fimc->vfd->entity, false);
  1251. fimc_lite_hw_init(fimc);
  1252. clear_bit(ST_FLITE_SUSPENDED, &fimc->state);
  1253. for (i = 0; i < fimc->reqbufs_count; i++) {
  1254. if (list_empty(&fimc->pending_buf_q))
  1255. break;
  1256. buf = fimc_lite_pending_queue_pop(fimc);
  1257. buffer_queue(&buf->vb);
  1258. }
  1259. return 0;
  1260. }
  1261. static int fimc_lite_suspend(struct device *dev)
  1262. {
  1263. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1264. bool suspend = test_bit(ST_FLITE_IN_USE, &fimc->state);
  1265. int ret;
  1266. if (test_and_set_bit(ST_LPM, &fimc->state))
  1267. return 0;
  1268. ret = fimc_lite_stop_capture(fimc, suspend);
  1269. if (ret < 0 || !fimc_lite_active(fimc))
  1270. return ret;
  1271. return fimc_pipeline_shutdown(&fimc->pipeline);
  1272. }
  1273. #endif /* CONFIG_PM_SLEEP */
  1274. static int __devexit fimc_lite_remove(struct platform_device *pdev)
  1275. {
  1276. struct fimc_lite *fimc = platform_get_drvdata(pdev);
  1277. struct device *dev = &pdev->dev;
  1278. pm_runtime_disable(dev);
  1279. pm_runtime_set_suspended(dev);
  1280. fimc_lite_unregister_capture_subdev(fimc);
  1281. vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
  1282. fimc_lite_clk_put(fimc);
  1283. dev_info(dev, "Driver unloaded\n");
  1284. return 0;
  1285. }
  1286. static struct flite_variant fimc_lite0_variant_exynos4 = {
  1287. .max_width = 8192,
  1288. .max_height = 8192,
  1289. .out_width_align = 8,
  1290. .win_hor_offs_align = 2,
  1291. .out_hor_offs_align = 8,
  1292. };
  1293. /* EXYNOS4212, EXYNOS4412 */
  1294. static struct flite_drvdata fimc_lite_drvdata_exynos4 = {
  1295. .variant = {
  1296. [0] = &fimc_lite0_variant_exynos4,
  1297. [1] = &fimc_lite0_variant_exynos4,
  1298. },
  1299. };
  1300. static struct platform_device_id fimc_lite_driver_ids[] = {
  1301. {
  1302. .name = "exynos-fimc-lite",
  1303. .driver_data = (unsigned long)&fimc_lite_drvdata_exynos4,
  1304. },
  1305. { /* sentinel */ },
  1306. };
  1307. MODULE_DEVICE_TABLE(platform, fimc_lite_driver_ids);
  1308. static const struct dev_pm_ops fimc_lite_pm_ops = {
  1309. SET_SYSTEM_SLEEP_PM_OPS(fimc_lite_suspend, fimc_lite_resume)
  1310. SET_RUNTIME_PM_OPS(fimc_lite_runtime_suspend, fimc_lite_runtime_resume,
  1311. NULL)
  1312. };
  1313. static struct platform_driver fimc_lite_driver = {
  1314. .probe = fimc_lite_probe,
  1315. .remove = __devexit_p(fimc_lite_remove),
  1316. .id_table = fimc_lite_driver_ids,
  1317. .driver = {
  1318. .name = FIMC_LITE_DRV_NAME,
  1319. .owner = THIS_MODULE,
  1320. .pm = &fimc_lite_pm_ops,
  1321. }
  1322. };
  1323. module_platform_driver(fimc_lite_driver);
  1324. MODULE_LICENSE("GPL");
  1325. MODULE_ALIAS("platform:" FIMC_LITE_DRV_NAME);