cx23885-dvb.c 36 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/module.h>
  22. #include <linux/init.h>
  23. #include <linux/device.h>
  24. #include <linux/fs.h>
  25. #include <linux/kthread.h>
  26. #include <linux/file.h>
  27. #include <linux/suspend.h>
  28. #include "cx23885.h"
  29. #include <media/v4l2-common.h>
  30. #include "dvb_ca_en50221.h"
  31. #include "s5h1409.h"
  32. #include "s5h1411.h"
  33. #include "mt2131.h"
  34. #include "tda8290.h"
  35. #include "tda18271.h"
  36. #include "lgdt330x.h"
  37. #include "xc4000.h"
  38. #include "xc5000.h"
  39. #include "max2165.h"
  40. #include "tda10048.h"
  41. #include "tuner-xc2028.h"
  42. #include "tuner-simple.h"
  43. #include "dib7000p.h"
  44. #include "dibx000_common.h"
  45. #include "zl10353.h"
  46. #include "stv0900.h"
  47. #include "stv0900_reg.h"
  48. #include "stv6110.h"
  49. #include "lnbh24.h"
  50. #include "cx24116.h"
  51. #include "cimax2.h"
  52. #include "lgs8gxx.h"
  53. #include "netup-eeprom.h"
  54. #include "netup-init.h"
  55. #include "lgdt3305.h"
  56. #include "atbm8830.h"
  57. #include "ds3000.h"
  58. #include "cx23885-f300.h"
  59. #include "altera-ci.h"
  60. #include "stv0367.h"
  61. #include "drxk.h"
  62. #include "mt2063.h"
  63. static unsigned int debug;
  64. #define dprintk(level, fmt, arg...)\
  65. do { if (debug >= level)\
  66. printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
  67. } while (0)
  68. /* ------------------------------------------------------------------ */
  69. static unsigned int alt_tuner;
  70. module_param(alt_tuner, int, 0644);
  71. MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
  72. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  73. /* ------------------------------------------------------------------ */
  74. static int dvb_buf_setup(struct videobuf_queue *q,
  75. unsigned int *count, unsigned int *size)
  76. {
  77. struct cx23885_tsport *port = q->priv_data;
  78. port->ts_packet_size = 188 * 4;
  79. port->ts_packet_count = 32;
  80. *size = port->ts_packet_size * port->ts_packet_count;
  81. *count = 32;
  82. return 0;
  83. }
  84. static int dvb_buf_prepare(struct videobuf_queue *q,
  85. struct videobuf_buffer *vb, enum v4l2_field field)
  86. {
  87. struct cx23885_tsport *port = q->priv_data;
  88. return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
  89. }
  90. static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
  91. {
  92. struct cx23885_tsport *port = q->priv_data;
  93. cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
  94. }
  95. static void dvb_buf_release(struct videobuf_queue *q,
  96. struct videobuf_buffer *vb)
  97. {
  98. cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
  99. }
  100. static int cx23885_dvb_set_frontend(struct dvb_frontend *fe);
  101. static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open)
  102. {
  103. struct videobuf_dvb_frontends *f;
  104. struct videobuf_dvb_frontend *fe;
  105. f = &port->frontends;
  106. if (f->gate <= 1) /* undefined or fe0 */
  107. fe = videobuf_dvb_get_frontend(f, 1);
  108. else
  109. fe = videobuf_dvb_get_frontend(f, f->gate);
  110. if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
  111. fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
  112. /*
  113. * FIXME: Improve this path to avoid calling the
  114. * cx23885_dvb_set_frontend() every time it passes here.
  115. */
  116. cx23885_dvb_set_frontend(fe->dvb.frontend);
  117. }
  118. static struct videobuf_queue_ops dvb_qops = {
  119. .buf_setup = dvb_buf_setup,
  120. .buf_prepare = dvb_buf_prepare,
  121. .buf_queue = dvb_buf_queue,
  122. .buf_release = dvb_buf_release,
  123. };
  124. static struct s5h1409_config hauppauge_generic_config = {
  125. .demod_address = 0x32 >> 1,
  126. .output_mode = S5H1409_SERIAL_OUTPUT,
  127. .gpio = S5H1409_GPIO_ON,
  128. .qam_if = 44000,
  129. .inversion = S5H1409_INVERSION_OFF,
  130. .status_mode = S5H1409_DEMODLOCKING,
  131. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  132. };
  133. static struct tda10048_config hauppauge_hvr1200_config = {
  134. .demod_address = 0x10 >> 1,
  135. .output_mode = TDA10048_SERIAL_OUTPUT,
  136. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  137. .inversion = TDA10048_INVERSION_ON,
  138. .dtv6_if_freq_khz = TDA10048_IF_3300,
  139. .dtv7_if_freq_khz = TDA10048_IF_3800,
  140. .dtv8_if_freq_khz = TDA10048_IF_4300,
  141. .clk_freq_khz = TDA10048_CLK_16000,
  142. };
  143. static struct tda10048_config hauppauge_hvr1210_config = {
  144. .demod_address = 0x10 >> 1,
  145. .output_mode = TDA10048_SERIAL_OUTPUT,
  146. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  147. .inversion = TDA10048_INVERSION_ON,
  148. .dtv6_if_freq_khz = TDA10048_IF_3300,
  149. .dtv7_if_freq_khz = TDA10048_IF_3500,
  150. .dtv8_if_freq_khz = TDA10048_IF_4000,
  151. .clk_freq_khz = TDA10048_CLK_16000,
  152. };
  153. static struct s5h1409_config hauppauge_ezqam_config = {
  154. .demod_address = 0x32 >> 1,
  155. .output_mode = S5H1409_SERIAL_OUTPUT,
  156. .gpio = S5H1409_GPIO_OFF,
  157. .qam_if = 4000,
  158. .inversion = S5H1409_INVERSION_ON,
  159. .status_mode = S5H1409_DEMODLOCKING,
  160. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  161. };
  162. static struct s5h1409_config hauppauge_hvr1800lp_config = {
  163. .demod_address = 0x32 >> 1,
  164. .output_mode = S5H1409_SERIAL_OUTPUT,
  165. .gpio = S5H1409_GPIO_OFF,
  166. .qam_if = 44000,
  167. .inversion = S5H1409_INVERSION_OFF,
  168. .status_mode = S5H1409_DEMODLOCKING,
  169. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  170. };
  171. static struct s5h1409_config hauppauge_hvr1500_config = {
  172. .demod_address = 0x32 >> 1,
  173. .output_mode = S5H1409_SERIAL_OUTPUT,
  174. .gpio = S5H1409_GPIO_OFF,
  175. .inversion = S5H1409_INVERSION_OFF,
  176. .status_mode = S5H1409_DEMODLOCKING,
  177. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  178. };
  179. static struct mt2131_config hauppauge_generic_tunerconfig = {
  180. 0x61
  181. };
  182. static struct lgdt330x_config fusionhdtv_5_express = {
  183. .demod_address = 0x0e,
  184. .demod_chip = LGDT3303,
  185. .serial_mpeg = 0x40,
  186. };
  187. static struct s5h1409_config hauppauge_hvr1500q_config = {
  188. .demod_address = 0x32 >> 1,
  189. .output_mode = S5H1409_SERIAL_OUTPUT,
  190. .gpio = S5H1409_GPIO_ON,
  191. .qam_if = 44000,
  192. .inversion = S5H1409_INVERSION_OFF,
  193. .status_mode = S5H1409_DEMODLOCKING,
  194. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  195. };
  196. static struct s5h1409_config dvico_s5h1409_config = {
  197. .demod_address = 0x32 >> 1,
  198. .output_mode = S5H1409_SERIAL_OUTPUT,
  199. .gpio = S5H1409_GPIO_ON,
  200. .qam_if = 44000,
  201. .inversion = S5H1409_INVERSION_OFF,
  202. .status_mode = S5H1409_DEMODLOCKING,
  203. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  204. };
  205. static struct s5h1411_config dvico_s5h1411_config = {
  206. .output_mode = S5H1411_SERIAL_OUTPUT,
  207. .gpio = S5H1411_GPIO_ON,
  208. .qam_if = S5H1411_IF_44000,
  209. .vsb_if = S5H1411_IF_44000,
  210. .inversion = S5H1411_INVERSION_OFF,
  211. .status_mode = S5H1411_DEMODLOCKING,
  212. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  213. };
  214. static struct s5h1411_config hcw_s5h1411_config = {
  215. .output_mode = S5H1411_SERIAL_OUTPUT,
  216. .gpio = S5H1411_GPIO_OFF,
  217. .vsb_if = S5H1411_IF_44000,
  218. .qam_if = S5H1411_IF_4000,
  219. .inversion = S5H1411_INVERSION_ON,
  220. .status_mode = S5H1411_DEMODLOCKING,
  221. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  222. };
  223. static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
  224. .i2c_address = 0x61,
  225. .if_khz = 5380,
  226. };
  227. static struct xc5000_config dvico_xc5000_tunerconfig = {
  228. .i2c_address = 0x64,
  229. .if_khz = 5380,
  230. };
  231. static struct tda829x_config tda829x_no_probe = {
  232. .probe_tuner = TDA829X_DONT_PROBE,
  233. };
  234. static struct tda18271_std_map hauppauge_tda18271_std_map = {
  235. .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
  236. .if_lvl = 6, .rfagc_top = 0x37 },
  237. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
  238. .if_lvl = 6, .rfagc_top = 0x37 },
  239. };
  240. static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
  241. .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
  242. .if_lvl = 1, .rfagc_top = 0x37, },
  243. .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
  244. .if_lvl = 1, .rfagc_top = 0x37, },
  245. .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
  246. .if_lvl = 1, .rfagc_top = 0x37, },
  247. };
  248. static struct tda18271_config hauppauge_tda18271_config = {
  249. .std_map = &hauppauge_tda18271_std_map,
  250. .gate = TDA18271_GATE_ANALOG,
  251. .output_opt = TDA18271_OUTPUT_LT_OFF,
  252. };
  253. static struct tda18271_config hauppauge_hvr1200_tuner_config = {
  254. .std_map = &hauppauge_hvr1200_tda18271_std_map,
  255. .gate = TDA18271_GATE_ANALOG,
  256. .output_opt = TDA18271_OUTPUT_LT_OFF,
  257. };
  258. static struct tda18271_config hauppauge_hvr1210_tuner_config = {
  259. .gate = TDA18271_GATE_DIGITAL,
  260. .output_opt = TDA18271_OUTPUT_LT_OFF,
  261. };
  262. static struct tda18271_std_map hauppauge_hvr127x_std_map = {
  263. .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
  264. .if_lvl = 1, .rfagc_top = 0x58 },
  265. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
  266. .if_lvl = 1, .rfagc_top = 0x58 },
  267. };
  268. static struct tda18271_config hauppauge_hvr127x_config = {
  269. .std_map = &hauppauge_hvr127x_std_map,
  270. .output_opt = TDA18271_OUTPUT_LT_OFF,
  271. };
  272. static struct lgdt3305_config hauppauge_lgdt3305_config = {
  273. .i2c_addr = 0x0e,
  274. .mpeg_mode = LGDT3305_MPEG_SERIAL,
  275. .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
  276. .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
  277. .deny_i2c_rptr = 1,
  278. .spectral_inversion = 1,
  279. .qam_if_khz = 4000,
  280. .vsb_if_khz = 3250,
  281. };
  282. static struct dibx000_agc_config xc3028_agc_config = {
  283. BAND_VHF | BAND_UHF, /* band_caps */
  284. /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
  285. * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
  286. * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
  287. * P_agc_nb_est=2, P_agc_write=0
  288. */
  289. (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
  290. (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
  291. 712, /* inv_gain */
  292. 21, /* time_stabiliz */
  293. 0, /* alpha_level */
  294. 118, /* thlock */
  295. 0, /* wbd_inv */
  296. 2867, /* wbd_ref */
  297. 0, /* wbd_sel */
  298. 2, /* wbd_alpha */
  299. 0, /* agc1_max */
  300. 0, /* agc1_min */
  301. 39718, /* agc2_max */
  302. 9930, /* agc2_min */
  303. 0, /* agc1_pt1 */
  304. 0, /* agc1_pt2 */
  305. 0, /* agc1_pt3 */
  306. 0, /* agc1_slope1 */
  307. 0, /* agc1_slope2 */
  308. 0, /* agc2_pt1 */
  309. 128, /* agc2_pt2 */
  310. 29, /* agc2_slope1 */
  311. 29, /* agc2_slope2 */
  312. 17, /* alpha_mant */
  313. 27, /* alpha_exp */
  314. 23, /* beta_mant */
  315. 51, /* beta_exp */
  316. 1, /* perform_agc_softsplit */
  317. };
  318. /* PLL Configuration for COFDM BW_MHz = 8.000000
  319. * With external clock = 30.000000 */
  320. static struct dibx000_bandwidth_config xc3028_bw_config = {
  321. 60000, /* internal */
  322. 30000, /* sampling */
  323. 1, /* pll_cfg: prediv */
  324. 8, /* pll_cfg: ratio */
  325. 3, /* pll_cfg: range */
  326. 1, /* pll_cfg: reset */
  327. 0, /* pll_cfg: bypass */
  328. 0, /* misc: refdiv */
  329. 0, /* misc: bypclk_div */
  330. 1, /* misc: IO_CLK_en_core */
  331. 1, /* misc: ADClkSrc */
  332. 0, /* misc: modulo */
  333. (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
  334. (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
  335. 20452225, /* timf */
  336. 30000000 /* xtal_hz */
  337. };
  338. static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
  339. .output_mpeg2_in_188_bytes = 1,
  340. .hostbus_diversity = 1,
  341. .tuner_is_baseband = 0,
  342. .update_lna = NULL,
  343. .agc_config_count = 1,
  344. .agc = &xc3028_agc_config,
  345. .bw = &xc3028_bw_config,
  346. .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
  347. .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
  348. .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
  349. .pwm_freq_div = 0,
  350. .agc_control = NULL,
  351. .spur_protect = 0,
  352. .output_mode = OUTMODE_MPEG2_SERIAL,
  353. };
  354. static struct zl10353_config dvico_fusionhdtv_xc3028 = {
  355. .demod_address = 0x0f,
  356. .if2 = 45600,
  357. .no_tuner = 1,
  358. .disable_i2c_gate_ctrl = 1,
  359. };
  360. static struct stv0900_reg stv0900_ts_regs[] = {
  361. { R0900_TSGENERAL, 0x00 },
  362. { R0900_P1_TSSPEED, 0x40 },
  363. { R0900_P2_TSSPEED, 0x40 },
  364. { R0900_P1_TSCFGM, 0xc0 },
  365. { R0900_P2_TSCFGM, 0xc0 },
  366. { R0900_P1_TSCFGH, 0xe0 },
  367. { R0900_P2_TSCFGH, 0xe0 },
  368. { R0900_P1_TSCFGL, 0x20 },
  369. { R0900_P2_TSCFGL, 0x20 },
  370. { 0xffff, 0xff }, /* terminate */
  371. };
  372. static struct stv0900_config netup_stv0900_config = {
  373. .demod_address = 0x68,
  374. .demod_mode = 1, /* dual */
  375. .xtal = 8000000,
  376. .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
  377. .diseqc_mode = 2,/* 2/3 PWM */
  378. .ts_config_regs = stv0900_ts_regs,
  379. .tun1_maddress = 0,/* 0x60 */
  380. .tun2_maddress = 3,/* 0x63 */
  381. .tun1_adc = 1,/* 1 Vpp */
  382. .tun2_adc = 1,/* 1 Vpp */
  383. };
  384. static struct stv6110_config netup_stv6110_tunerconfig_a = {
  385. .i2c_address = 0x60,
  386. .mclk = 16000000,
  387. .clk_div = 1,
  388. .gain = 8, /* +16 dB - maximum gain */
  389. };
  390. static struct stv6110_config netup_stv6110_tunerconfig_b = {
  391. .i2c_address = 0x63,
  392. .mclk = 16000000,
  393. .clk_div = 1,
  394. .gain = 8, /* +16 dB - maximum gain */
  395. };
  396. static struct cx24116_config tbs_cx24116_config = {
  397. .demod_address = 0x55,
  398. };
  399. static struct ds3000_config tevii_ds3000_config = {
  400. .demod_address = 0x68,
  401. };
  402. static struct cx24116_config dvbworld_cx24116_config = {
  403. .demod_address = 0x05,
  404. };
  405. static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
  406. .prod = LGS8GXX_PROD_LGS8GL5,
  407. .demod_address = 0x19,
  408. .serial_ts = 0,
  409. .ts_clk_pol = 1,
  410. .ts_clk_gated = 1,
  411. .if_clk_freq = 30400, /* 30.4 MHz */
  412. .if_freq = 5380, /* 5.38 MHz */
  413. .if_neg_center = 1,
  414. .ext_adc = 0,
  415. .adc_signed = 0,
  416. .if_neg_edge = 0,
  417. };
  418. static struct xc5000_config mygica_x8506_xc5000_config = {
  419. .i2c_address = 0x61,
  420. .if_khz = 5380,
  421. };
  422. static int cx23885_dvb_set_frontend(struct dvb_frontend *fe)
  423. {
  424. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  425. struct cx23885_tsport *port = fe->dvb->priv;
  426. struct cx23885_dev *dev = port->dev;
  427. switch (dev->board) {
  428. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  429. switch (p->modulation) {
  430. case VSB_8:
  431. cx23885_gpio_clear(dev, GPIO_5);
  432. break;
  433. case QAM_64:
  434. case QAM_256:
  435. default:
  436. cx23885_gpio_set(dev, GPIO_5);
  437. break;
  438. }
  439. break;
  440. case CX23885_BOARD_MYGICA_X8506:
  441. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  442. /* Select Digital TV */
  443. cx23885_gpio_set(dev, GPIO_0);
  444. break;
  445. }
  446. return 0;
  447. }
  448. static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
  449. .prod = LGS8GXX_PROD_LGS8G75,
  450. .demod_address = 0x19,
  451. .serial_ts = 0,
  452. .ts_clk_pol = 1,
  453. .ts_clk_gated = 1,
  454. .if_clk_freq = 30400, /* 30.4 MHz */
  455. .if_freq = 6500, /* 6.50 MHz */
  456. .if_neg_center = 1,
  457. .ext_adc = 0,
  458. .adc_signed = 1,
  459. .adc_vpp = 2, /* 1.6 Vpp */
  460. .if_neg_edge = 1,
  461. };
  462. static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
  463. .i2c_address = 0x61,
  464. .if_khz = 6500,
  465. };
  466. static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
  467. .prod = ATBM8830_PROD_8830,
  468. .demod_address = 0x44,
  469. .serial_ts = 0,
  470. .ts_sampling_edge = 1,
  471. .ts_clk_gated = 0,
  472. .osc_clk_freq = 30400, /* in kHz */
  473. .if_freq = 0, /* zero IF */
  474. .zif_swap_iq = 1,
  475. .agc_min = 0x2E,
  476. .agc_max = 0xFF,
  477. .agc_hold_loop = 0,
  478. };
  479. static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
  480. .i2c_address = 0x60,
  481. .osc_clk = 20
  482. };
  483. static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
  484. .prod = ATBM8830_PROD_8830,
  485. .demod_address = 0x44,
  486. .serial_ts = 1,
  487. .ts_sampling_edge = 1,
  488. .ts_clk_gated = 0,
  489. .osc_clk_freq = 30400, /* in kHz */
  490. .if_freq = 0, /* zero IF */
  491. .zif_swap_iq = 1,
  492. .agc_min = 0x2E,
  493. .agc_max = 0xFF,
  494. .agc_hold_loop = 0,
  495. };
  496. static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
  497. .i2c_address = 0x60,
  498. .osc_clk = 20
  499. };
  500. static struct stv0367_config netup_stv0367_config[] = {
  501. {
  502. .demod_address = 0x1c,
  503. .xtal = 27000000,
  504. .if_khz = 4500,
  505. .if_iq_mode = 0,
  506. .ts_mode = 1,
  507. .clk_pol = 0,
  508. }, {
  509. .demod_address = 0x1d,
  510. .xtal = 27000000,
  511. .if_khz = 4500,
  512. .if_iq_mode = 0,
  513. .ts_mode = 1,
  514. .clk_pol = 0,
  515. },
  516. };
  517. static struct xc5000_config netup_xc5000_config[] = {
  518. {
  519. .i2c_address = 0x61,
  520. .if_khz = 4500,
  521. }, {
  522. .i2c_address = 0x64,
  523. .if_khz = 4500,
  524. },
  525. };
  526. static struct drxk_config terratec_drxk_config[] = {
  527. {
  528. .adr = 0x29,
  529. .no_i2c_bridge = 1,
  530. }, {
  531. .adr = 0x2a,
  532. .no_i2c_bridge = 1,
  533. },
  534. };
  535. static struct mt2063_config terratec_mt2063_config[] = {
  536. {
  537. .tuner_address = 0x60,
  538. }, {
  539. .tuner_address = 0x67,
  540. },
  541. };
  542. int netup_altera_fpga_rw(void *device, int flag, int data, int read)
  543. {
  544. struct cx23885_dev *dev = (struct cx23885_dev *)device;
  545. unsigned long timeout = jiffies + msecs_to_jiffies(1);
  546. uint32_t mem = 0;
  547. mem = cx_read(MC417_RWD);
  548. if (read)
  549. cx_set(MC417_OEN, ALT_DATA);
  550. else {
  551. cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */
  552. mem &= ~ALT_DATA;
  553. mem |= (data & ALT_DATA);
  554. }
  555. if (flag)
  556. mem |= ALT_AD_RG;
  557. else
  558. mem &= ~ALT_AD_RG;
  559. mem &= ~ALT_CS;
  560. if (read)
  561. mem = (mem & ~ALT_RD) | ALT_WR;
  562. else
  563. mem = (mem & ~ALT_WR) | ALT_RD;
  564. cx_write(MC417_RWD, mem); /* start RW cycle */
  565. for (;;) {
  566. mem = cx_read(MC417_RWD);
  567. if ((mem & ALT_RDY) == 0)
  568. break;
  569. if (time_after(jiffies, timeout))
  570. break;
  571. udelay(1);
  572. }
  573. cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS);
  574. if (read)
  575. return mem & ALT_DATA;
  576. return 0;
  577. };
  578. static int dvb_register(struct cx23885_tsport *port)
  579. {
  580. struct cx23885_dev *dev = port->dev;
  581. struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
  582. struct videobuf_dvb_frontend *fe0, *fe1 = NULL;
  583. int mfe_shared = 0; /* bus not shared by default */
  584. int ret;
  585. /* Get the first frontend */
  586. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  587. if (!fe0)
  588. return -EINVAL;
  589. /* init struct videobuf_dvb */
  590. fe0->dvb.name = dev->name;
  591. /* multi-frontend gate control is undefined or defaults to fe0 */
  592. port->frontends.gate = 0;
  593. /* Sets the gate control callback to be used by i2c command calls */
  594. port->gate_ctrl = cx23885_dvb_gate_ctrl;
  595. /* init frontend */
  596. switch (dev->board) {
  597. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  598. i2c_bus = &dev->i2c_bus[0];
  599. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  600. &hauppauge_generic_config,
  601. &i2c_bus->i2c_adap);
  602. if (fe0->dvb.frontend != NULL) {
  603. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  604. &i2c_bus->i2c_adap,
  605. &hauppauge_generic_tunerconfig, 0);
  606. }
  607. break;
  608. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  609. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  610. i2c_bus = &dev->i2c_bus[0];
  611. fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
  612. &hauppauge_lgdt3305_config,
  613. &i2c_bus->i2c_adap);
  614. if (fe0->dvb.frontend != NULL) {
  615. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  616. 0x60, &dev->i2c_bus[1].i2c_adap,
  617. &hauppauge_hvr127x_config);
  618. }
  619. break;
  620. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  621. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  622. i2c_bus = &dev->i2c_bus[0];
  623. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  624. &hcw_s5h1411_config,
  625. &i2c_bus->i2c_adap);
  626. if (fe0->dvb.frontend != NULL) {
  627. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  628. 0x60, &dev->i2c_bus[1].i2c_adap,
  629. &hauppauge_tda18271_config);
  630. }
  631. tda18271_attach(&dev->ts1.analog_fe,
  632. 0x60, &dev->i2c_bus[1].i2c_adap,
  633. &hauppauge_tda18271_config);
  634. break;
  635. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  636. i2c_bus = &dev->i2c_bus[0];
  637. switch (alt_tuner) {
  638. case 1:
  639. fe0->dvb.frontend =
  640. dvb_attach(s5h1409_attach,
  641. &hauppauge_ezqam_config,
  642. &i2c_bus->i2c_adap);
  643. if (fe0->dvb.frontend != NULL) {
  644. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  645. &dev->i2c_bus[1].i2c_adap, 0x42,
  646. &tda829x_no_probe);
  647. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  648. 0x60, &dev->i2c_bus[1].i2c_adap,
  649. &hauppauge_tda18271_config);
  650. }
  651. break;
  652. case 0:
  653. default:
  654. fe0->dvb.frontend =
  655. dvb_attach(s5h1409_attach,
  656. &hauppauge_generic_config,
  657. &i2c_bus->i2c_adap);
  658. if (fe0->dvb.frontend != NULL)
  659. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  660. &i2c_bus->i2c_adap,
  661. &hauppauge_generic_tunerconfig, 0);
  662. break;
  663. }
  664. break;
  665. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  666. i2c_bus = &dev->i2c_bus[0];
  667. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  668. &hauppauge_hvr1800lp_config,
  669. &i2c_bus->i2c_adap);
  670. if (fe0->dvb.frontend != NULL) {
  671. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  672. &i2c_bus->i2c_adap,
  673. &hauppauge_generic_tunerconfig, 0);
  674. }
  675. break;
  676. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  677. i2c_bus = &dev->i2c_bus[0];
  678. fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
  679. &fusionhdtv_5_express,
  680. &i2c_bus->i2c_adap);
  681. if (fe0->dvb.frontend != NULL) {
  682. dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  683. &i2c_bus->i2c_adap, 0x61,
  684. TUNER_LG_TDVS_H06XF);
  685. }
  686. break;
  687. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  688. i2c_bus = &dev->i2c_bus[1];
  689. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  690. &hauppauge_hvr1500q_config,
  691. &dev->i2c_bus[0].i2c_adap);
  692. if (fe0->dvb.frontend != NULL)
  693. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  694. &i2c_bus->i2c_adap,
  695. &hauppauge_hvr1500q_tunerconfig);
  696. break;
  697. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  698. i2c_bus = &dev->i2c_bus[1];
  699. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  700. &hauppauge_hvr1500_config,
  701. &dev->i2c_bus[0].i2c_adap);
  702. if (fe0->dvb.frontend != NULL) {
  703. struct dvb_frontend *fe;
  704. struct xc2028_config cfg = {
  705. .i2c_adap = &i2c_bus->i2c_adap,
  706. .i2c_addr = 0x61,
  707. };
  708. static struct xc2028_ctrl ctl = {
  709. .fname = XC2028_DEFAULT_FIRMWARE,
  710. .max_len = 64,
  711. .demod = XC3028_FE_OREN538,
  712. };
  713. fe = dvb_attach(xc2028_attach,
  714. fe0->dvb.frontend, &cfg);
  715. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  716. fe->ops.tuner_ops.set_config(fe, &ctl);
  717. }
  718. break;
  719. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  720. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  721. i2c_bus = &dev->i2c_bus[0];
  722. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  723. &hauppauge_hvr1200_config,
  724. &i2c_bus->i2c_adap);
  725. if (fe0->dvb.frontend != NULL) {
  726. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  727. &dev->i2c_bus[1].i2c_adap, 0x42,
  728. &tda829x_no_probe);
  729. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  730. 0x60, &dev->i2c_bus[1].i2c_adap,
  731. &hauppauge_hvr1200_tuner_config);
  732. }
  733. break;
  734. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  735. i2c_bus = &dev->i2c_bus[0];
  736. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  737. &hauppauge_hvr1210_config,
  738. &i2c_bus->i2c_adap);
  739. if (fe0->dvb.frontend != NULL) {
  740. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  741. 0x60, &dev->i2c_bus[1].i2c_adap,
  742. &hauppauge_hvr1210_tuner_config);
  743. }
  744. break;
  745. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  746. i2c_bus = &dev->i2c_bus[0];
  747. fe0->dvb.frontend = dvb_attach(dib7000p_attach,
  748. &i2c_bus->i2c_adap,
  749. 0x12, &hauppauge_hvr1400_dib7000_config);
  750. if (fe0->dvb.frontend != NULL) {
  751. struct dvb_frontend *fe;
  752. struct xc2028_config cfg = {
  753. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  754. .i2c_addr = 0x64,
  755. };
  756. static struct xc2028_ctrl ctl = {
  757. .fname = XC3028L_DEFAULT_FIRMWARE,
  758. .max_len = 64,
  759. .demod = XC3028_FE_DIBCOM52,
  760. /* This is true for all demods with
  761. v36 firmware? */
  762. .type = XC2028_D2633,
  763. };
  764. fe = dvb_attach(xc2028_attach,
  765. fe0->dvb.frontend, &cfg);
  766. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  767. fe->ops.tuner_ops.set_config(fe, &ctl);
  768. }
  769. break;
  770. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  771. i2c_bus = &dev->i2c_bus[port->nr - 1];
  772. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  773. &dvico_s5h1409_config,
  774. &i2c_bus->i2c_adap);
  775. if (fe0->dvb.frontend == NULL)
  776. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  777. &dvico_s5h1411_config,
  778. &i2c_bus->i2c_adap);
  779. if (fe0->dvb.frontend != NULL)
  780. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  781. &i2c_bus->i2c_adap,
  782. &dvico_xc5000_tunerconfig);
  783. break;
  784. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
  785. i2c_bus = &dev->i2c_bus[port->nr - 1];
  786. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  787. &dvico_fusionhdtv_xc3028,
  788. &i2c_bus->i2c_adap);
  789. if (fe0->dvb.frontend != NULL) {
  790. struct dvb_frontend *fe;
  791. struct xc2028_config cfg = {
  792. .i2c_adap = &i2c_bus->i2c_adap,
  793. .i2c_addr = 0x61,
  794. };
  795. static struct xc2028_ctrl ctl = {
  796. .fname = XC2028_DEFAULT_FIRMWARE,
  797. .max_len = 64,
  798. .demod = XC3028_FE_ZARLINK456,
  799. };
  800. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  801. &cfg);
  802. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  803. fe->ops.tuner_ops.set_config(fe, &ctl);
  804. }
  805. break;
  806. }
  807. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  808. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  809. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  810. i2c_bus = &dev->i2c_bus[0];
  811. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  812. &dvico_fusionhdtv_xc3028,
  813. &i2c_bus->i2c_adap);
  814. if (fe0->dvb.frontend != NULL) {
  815. struct dvb_frontend *fe;
  816. struct xc2028_config cfg = {
  817. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  818. .i2c_addr = 0x61,
  819. };
  820. static struct xc2028_ctrl ctl = {
  821. .fname = XC2028_DEFAULT_FIRMWARE,
  822. .max_len = 64,
  823. .demod = XC3028_FE_ZARLINK456,
  824. };
  825. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  826. &cfg);
  827. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  828. fe->ops.tuner_ops.set_config(fe, &ctl);
  829. }
  830. break;
  831. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  832. i2c_bus = &dev->i2c_bus[0];
  833. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  834. &dvico_fusionhdtv_xc3028,
  835. &i2c_bus->i2c_adap);
  836. if (fe0->dvb.frontend != NULL) {
  837. struct dvb_frontend *fe;
  838. struct xc4000_config cfg = {
  839. .i2c_address = 0x61,
  840. .default_pm = 0,
  841. .dvb_amplitude = 134,
  842. .set_smoothedcvbs = 1,
  843. .if_khz = 4560
  844. };
  845. fe = dvb_attach(xc4000_attach, fe0->dvb.frontend,
  846. &dev->i2c_bus[1].i2c_adap, &cfg);
  847. if (!fe) {
  848. printk(KERN_ERR "%s/2: xc4000 attach failed\n",
  849. dev->name);
  850. goto frontend_detach;
  851. }
  852. }
  853. break;
  854. case CX23885_BOARD_TBS_6920:
  855. i2c_bus = &dev->i2c_bus[1];
  856. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  857. &tbs_cx24116_config,
  858. &i2c_bus->i2c_adap);
  859. if (fe0->dvb.frontend != NULL)
  860. fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
  861. break;
  862. case CX23885_BOARD_TEVII_S470:
  863. i2c_bus = &dev->i2c_bus[1];
  864. fe0->dvb.frontend = dvb_attach(ds3000_attach,
  865. &tevii_ds3000_config,
  866. &i2c_bus->i2c_adap);
  867. if (fe0->dvb.frontend != NULL)
  868. fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
  869. break;
  870. case CX23885_BOARD_DVBWORLD_2005:
  871. i2c_bus = &dev->i2c_bus[1];
  872. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  873. &dvbworld_cx24116_config,
  874. &i2c_bus->i2c_adap);
  875. break;
  876. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  877. i2c_bus = &dev->i2c_bus[0];
  878. switch (port->nr) {
  879. /* port B */
  880. case 1:
  881. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  882. &netup_stv0900_config,
  883. &i2c_bus->i2c_adap, 0);
  884. if (fe0->dvb.frontend != NULL) {
  885. if (dvb_attach(stv6110_attach,
  886. fe0->dvb.frontend,
  887. &netup_stv6110_tunerconfig_a,
  888. &i2c_bus->i2c_adap)) {
  889. if (!dvb_attach(lnbh24_attach,
  890. fe0->dvb.frontend,
  891. &i2c_bus->i2c_adap,
  892. LNBH24_PCL | LNBH24_TTX,
  893. LNBH24_TEN, 0x09))
  894. printk(KERN_ERR
  895. "No LNBH24 found!\n");
  896. }
  897. }
  898. break;
  899. /* port C */
  900. case 2:
  901. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  902. &netup_stv0900_config,
  903. &i2c_bus->i2c_adap, 1);
  904. if (fe0->dvb.frontend != NULL) {
  905. if (dvb_attach(stv6110_attach,
  906. fe0->dvb.frontend,
  907. &netup_stv6110_tunerconfig_b,
  908. &i2c_bus->i2c_adap)) {
  909. if (!dvb_attach(lnbh24_attach,
  910. fe0->dvb.frontend,
  911. &i2c_bus->i2c_adap,
  912. LNBH24_PCL | LNBH24_TTX,
  913. LNBH24_TEN, 0x0a))
  914. printk(KERN_ERR
  915. "No LNBH24 found!\n");
  916. }
  917. }
  918. break;
  919. }
  920. break;
  921. case CX23885_BOARD_MYGICA_X8506:
  922. i2c_bus = &dev->i2c_bus[0];
  923. i2c_bus2 = &dev->i2c_bus[1];
  924. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  925. &mygica_x8506_lgs8gl5_config,
  926. &i2c_bus->i2c_adap);
  927. if (fe0->dvb.frontend != NULL) {
  928. dvb_attach(xc5000_attach,
  929. fe0->dvb.frontend,
  930. &i2c_bus2->i2c_adap,
  931. &mygica_x8506_xc5000_config);
  932. }
  933. break;
  934. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  935. i2c_bus = &dev->i2c_bus[0];
  936. i2c_bus2 = &dev->i2c_bus[1];
  937. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  938. &magicpro_prohdtve2_lgs8g75_config,
  939. &i2c_bus->i2c_adap);
  940. if (fe0->dvb.frontend != NULL) {
  941. dvb_attach(xc5000_attach,
  942. fe0->dvb.frontend,
  943. &i2c_bus2->i2c_adap,
  944. &magicpro_prohdtve2_xc5000_config);
  945. }
  946. break;
  947. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  948. i2c_bus = &dev->i2c_bus[0];
  949. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  950. &hcw_s5h1411_config,
  951. &i2c_bus->i2c_adap);
  952. if (fe0->dvb.frontend != NULL)
  953. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  954. 0x60, &dev->i2c_bus[0].i2c_adap,
  955. &hauppauge_tda18271_config);
  956. tda18271_attach(&dev->ts1.analog_fe,
  957. 0x60, &dev->i2c_bus[1].i2c_adap,
  958. &hauppauge_tda18271_config);
  959. break;
  960. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  961. i2c_bus = &dev->i2c_bus[0];
  962. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  963. &hcw_s5h1411_config,
  964. &i2c_bus->i2c_adap);
  965. if (fe0->dvb.frontend != NULL)
  966. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  967. 0x60, &dev->i2c_bus[0].i2c_adap,
  968. &hauppauge_tda18271_config);
  969. break;
  970. case CX23885_BOARD_MYGICA_X8558PRO:
  971. switch (port->nr) {
  972. /* port B */
  973. case 1:
  974. i2c_bus = &dev->i2c_bus[0];
  975. fe0->dvb.frontend = dvb_attach(atbm8830_attach,
  976. &mygica_x8558pro_atbm8830_cfg1,
  977. &i2c_bus->i2c_adap);
  978. if (fe0->dvb.frontend != NULL) {
  979. dvb_attach(max2165_attach,
  980. fe0->dvb.frontend,
  981. &i2c_bus->i2c_adap,
  982. &mygic_x8558pro_max2165_cfg1);
  983. }
  984. break;
  985. /* port C */
  986. case 2:
  987. i2c_bus = &dev->i2c_bus[1];
  988. fe0->dvb.frontend = dvb_attach(atbm8830_attach,
  989. &mygica_x8558pro_atbm8830_cfg2,
  990. &i2c_bus->i2c_adap);
  991. if (fe0->dvb.frontend != NULL) {
  992. dvb_attach(max2165_attach,
  993. fe0->dvb.frontend,
  994. &i2c_bus->i2c_adap,
  995. &mygic_x8558pro_max2165_cfg2);
  996. }
  997. break;
  998. }
  999. break;
  1000. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1001. i2c_bus = &dev->i2c_bus[0];
  1002. mfe_shared = 1;/* MFE */
  1003. port->frontends.gate = 0;/* not clear for me yet */
  1004. /* ports B, C */
  1005. /* MFE frontend 1 DVB-T */
  1006. fe0->dvb.frontend = dvb_attach(stv0367ter_attach,
  1007. &netup_stv0367_config[port->nr - 1],
  1008. &i2c_bus->i2c_adap);
  1009. if (fe0->dvb.frontend != NULL) {
  1010. if (NULL == dvb_attach(xc5000_attach,
  1011. fe0->dvb.frontend,
  1012. &i2c_bus->i2c_adap,
  1013. &netup_xc5000_config[port->nr - 1]))
  1014. goto frontend_detach;
  1015. /* load xc5000 firmware */
  1016. fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend);
  1017. }
  1018. /* MFE frontend 2 */
  1019. fe1 = videobuf_dvb_get_frontend(&port->frontends, 2);
  1020. if (fe1 == NULL)
  1021. goto frontend_detach;
  1022. /* DVB-C init */
  1023. fe1->dvb.frontend = dvb_attach(stv0367cab_attach,
  1024. &netup_stv0367_config[port->nr - 1],
  1025. &i2c_bus->i2c_adap);
  1026. if (fe1->dvb.frontend != NULL) {
  1027. fe1->dvb.frontend->id = 1;
  1028. if (NULL == dvb_attach(xc5000_attach,
  1029. fe1->dvb.frontend,
  1030. &i2c_bus->i2c_adap,
  1031. &netup_xc5000_config[port->nr - 1]))
  1032. goto frontend_detach;
  1033. }
  1034. break;
  1035. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  1036. i2c_bus = &dev->i2c_bus[0];
  1037. i2c_bus2 = &dev->i2c_bus[1];
  1038. switch (port->nr) {
  1039. /* port b */
  1040. case 1:
  1041. fe0->dvb.frontend = dvb_attach(drxk_attach,
  1042. &terratec_drxk_config[0],
  1043. &i2c_bus->i2c_adap);
  1044. if (fe0->dvb.frontend != NULL) {
  1045. if (!dvb_attach(mt2063_attach,
  1046. fe0->dvb.frontend,
  1047. &terratec_mt2063_config[0],
  1048. &i2c_bus2->i2c_adap))
  1049. goto frontend_detach;
  1050. }
  1051. break;
  1052. /* port c */
  1053. case 2:
  1054. fe0->dvb.frontend = dvb_attach(drxk_attach,
  1055. &terratec_drxk_config[1],
  1056. &i2c_bus->i2c_adap);
  1057. if (fe0->dvb.frontend != NULL) {
  1058. if (!dvb_attach(mt2063_attach,
  1059. fe0->dvb.frontend,
  1060. &terratec_mt2063_config[1],
  1061. &i2c_bus2->i2c_adap))
  1062. goto frontend_detach;
  1063. }
  1064. break;
  1065. }
  1066. break;
  1067. case CX23885_BOARD_TEVII_S471:
  1068. i2c_bus = &dev->i2c_bus[1];
  1069. fe0->dvb.frontend = dvb_attach(ds3000_attach,
  1070. &tevii_ds3000_config,
  1071. &i2c_bus->i2c_adap);
  1072. break;
  1073. default:
  1074. printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
  1075. " isn't supported yet\n",
  1076. dev->name);
  1077. break;
  1078. }
  1079. if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
  1080. printk(KERN_ERR "%s: frontend initialization failed\n",
  1081. dev->name);
  1082. goto frontend_detach;
  1083. }
  1084. /* define general-purpose callback pointer */
  1085. fe0->dvb.frontend->callback = cx23885_tuner_callback;
  1086. if (fe1)
  1087. fe1->dvb.frontend->callback = cx23885_tuner_callback;
  1088. #if 0
  1089. /* Ensure all frontends negotiate bus access */
  1090. fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
  1091. if (fe1)
  1092. fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
  1093. #endif
  1094. /* Put the analog decoder in standby to keep it quiet */
  1095. call_all(dev, core, s_power, 0);
  1096. if (fe0->dvb.frontend->ops.analog_ops.standby)
  1097. fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
  1098. /* register everything */
  1099. ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
  1100. &dev->pci->dev, adapter_nr, mfe_shared,
  1101. NULL);
  1102. if (ret)
  1103. goto frontend_detach;
  1104. /* init CI & MAC */
  1105. switch (dev->board) {
  1106. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
  1107. static struct netup_card_info cinfo;
  1108. netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
  1109. memcpy(port->frontends.adapter.proposed_mac,
  1110. cinfo.port[port->nr - 1].mac, 6);
  1111. printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n",
  1112. port->nr, port->frontends.adapter.proposed_mac);
  1113. netup_ci_init(port);
  1114. break;
  1115. }
  1116. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
  1117. struct altera_ci_config netup_ci_cfg = {
  1118. .dev = dev,/* magic number to identify*/
  1119. .adapter = &port->frontends.adapter,/* for CI */
  1120. .demux = &fe0->dvb.demux,/* for hw pid filter */
  1121. .fpga_rw = netup_altera_fpga_rw,
  1122. };
  1123. altera_ci_init(&netup_ci_cfg, port->nr);
  1124. break;
  1125. }
  1126. case CX23885_BOARD_TEVII_S470: {
  1127. u8 eeprom[256]; /* 24C02 i2c eeprom */
  1128. if (port->nr != 1)
  1129. break;
  1130. /* Read entire EEPROM */
  1131. dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
  1132. tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom));
  1133. printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0);
  1134. memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6);
  1135. break;
  1136. }
  1137. }
  1138. return ret;
  1139. frontend_detach:
  1140. port->gate_ctrl = NULL;
  1141. videobuf_dvb_dealloc_frontends(&port->frontends);
  1142. return -EINVAL;
  1143. }
  1144. int cx23885_dvb_register(struct cx23885_tsport *port)
  1145. {
  1146. struct videobuf_dvb_frontend *fe0;
  1147. struct cx23885_dev *dev = port->dev;
  1148. int err, i;
  1149. /* Here we need to allocate the correct number of frontends,
  1150. * as reflected in the cards struct. The reality is that currently
  1151. * no cx23885 boards support this - yet. But, if we don't modify this
  1152. * code then the second frontend would never be allocated (later)
  1153. * and fail with error before the attach in dvb_register().
  1154. * Without these changes we risk an OOPS later. The changes here
  1155. * are for safety, and should provide a good foundation for the
  1156. * future addition of any multi-frontend cx23885 based boards.
  1157. */
  1158. printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
  1159. port->num_frontends);
  1160. for (i = 1; i <= port->num_frontends; i++) {
  1161. if (videobuf_dvb_alloc_frontend(
  1162. &port->frontends, i) == NULL) {
  1163. printk(KERN_ERR "%s() failed to alloc\n", __func__);
  1164. return -ENOMEM;
  1165. }
  1166. fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
  1167. if (!fe0)
  1168. err = -EINVAL;
  1169. dprintk(1, "%s\n", __func__);
  1170. dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
  1171. dev->board,
  1172. dev->name,
  1173. dev->pci_bus,
  1174. dev->pci_slot);
  1175. err = -ENODEV;
  1176. /* dvb stuff */
  1177. /* We have to init the queue for each frontend on a port. */
  1178. printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
  1179. videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
  1180. &dev->pci->dev, &port->slock,
  1181. V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
  1182. sizeof(struct cx23885_buffer), port, NULL);
  1183. }
  1184. err = dvb_register(port);
  1185. if (err != 0)
  1186. printk(KERN_ERR "%s() dvb_register failed err = %d\n",
  1187. __func__, err);
  1188. return err;
  1189. }
  1190. int cx23885_dvb_unregister(struct cx23885_tsport *port)
  1191. {
  1192. struct videobuf_dvb_frontend *fe0;
  1193. /* FIXME: in an error condition where the we have
  1194. * an expected number of frontends (attach problem)
  1195. * then this might not clean up correctly, if 1
  1196. * is invalid.
  1197. * This comment only applies to future boards IF they
  1198. * implement MFE support.
  1199. */
  1200. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  1201. if (fe0 && fe0->dvb.frontend)
  1202. videobuf_dvb_unregister_bus(&port->frontends);
  1203. switch (port->dev->board) {
  1204. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1205. netup_ci_exit(port);
  1206. break;
  1207. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1208. altera_ci_release(port->dev, port->nr);
  1209. break;
  1210. }
  1211. port->gate_ctrl = NULL;
  1212. return 0;
  1213. }