asix_devices.c 26 KB

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  1. /*
  2. * ASIX AX8817X based USB 2.0 Ethernet Devices
  3. * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
  4. * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
  5. * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
  6. * Copyright (c) 2002-2003 TiVo Inc.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include "asix.h"
  23. #define PHY_MODE_MARVELL 0x0000
  24. #define MII_MARVELL_LED_CTRL 0x0018
  25. #define MII_MARVELL_STATUS 0x001b
  26. #define MII_MARVELL_CTRL 0x0014
  27. #define MARVELL_LED_MANUAL 0x0019
  28. #define MARVELL_STATUS_HWCFG 0x0004
  29. #define MARVELL_CTRL_TXDELAY 0x0002
  30. #define MARVELL_CTRL_RXDELAY 0x0080
  31. #define PHY_MODE_RTL8211CL 0x000C
  32. struct ax88172_int_data {
  33. __le16 res1;
  34. u8 link;
  35. __le16 res2;
  36. u8 status;
  37. __le16 res3;
  38. } __packed;
  39. static void asix_status(struct usbnet *dev, struct urb *urb)
  40. {
  41. struct ax88172_int_data *event;
  42. int link;
  43. if (urb->actual_length < 8)
  44. return;
  45. event = urb->transfer_buffer;
  46. link = event->link & 0x01;
  47. if (netif_carrier_ok(dev->net) != link) {
  48. if (link) {
  49. netif_carrier_on(dev->net);
  50. usbnet_defer_kevent (dev, EVENT_LINK_RESET );
  51. } else
  52. netif_carrier_off(dev->net);
  53. netdev_dbg(dev->net, "Link Status is: %d\n", link);
  54. }
  55. }
  56. /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
  57. static u32 asix_get_phyid(struct usbnet *dev)
  58. {
  59. int phy_reg;
  60. u32 phy_id;
  61. int i;
  62. /* Poll for the rare case the FW or phy isn't ready yet. */
  63. for (i = 0; i < 100; i++) {
  64. phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
  65. if (phy_reg != 0 && phy_reg != 0xFFFF)
  66. break;
  67. mdelay(1);
  68. }
  69. if (phy_reg <= 0 || phy_reg == 0xFFFF)
  70. return 0;
  71. phy_id = (phy_reg & 0xffff) << 16;
  72. phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
  73. if (phy_reg < 0)
  74. return 0;
  75. phy_id |= (phy_reg & 0xffff);
  76. return phy_id;
  77. }
  78. static u32 asix_get_link(struct net_device *net)
  79. {
  80. struct usbnet *dev = netdev_priv(net);
  81. return mii_link_ok(&dev->mii);
  82. }
  83. static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd)
  84. {
  85. struct usbnet *dev = netdev_priv(net);
  86. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  87. }
  88. /* We need to override some ethtool_ops so we require our
  89. own structure so we don't interfere with other usbnet
  90. devices that may be connected at the same time. */
  91. static const struct ethtool_ops ax88172_ethtool_ops = {
  92. .get_drvinfo = asix_get_drvinfo,
  93. .get_link = asix_get_link,
  94. .get_msglevel = usbnet_get_msglevel,
  95. .set_msglevel = usbnet_set_msglevel,
  96. .get_wol = asix_get_wol,
  97. .set_wol = asix_set_wol,
  98. .get_eeprom_len = asix_get_eeprom_len,
  99. .get_eeprom = asix_get_eeprom,
  100. .get_settings = usbnet_get_settings,
  101. .set_settings = usbnet_set_settings,
  102. .nway_reset = usbnet_nway_reset,
  103. };
  104. static void ax88172_set_multicast(struct net_device *net)
  105. {
  106. struct usbnet *dev = netdev_priv(net);
  107. struct asix_data *data = (struct asix_data *)&dev->data;
  108. u8 rx_ctl = 0x8c;
  109. if (net->flags & IFF_PROMISC) {
  110. rx_ctl |= 0x01;
  111. } else if (net->flags & IFF_ALLMULTI ||
  112. netdev_mc_count(net) > AX_MAX_MCAST) {
  113. rx_ctl |= 0x02;
  114. } else if (netdev_mc_empty(net)) {
  115. /* just broadcast and directed */
  116. } else {
  117. /* We use the 20 byte dev->data
  118. * for our 8 byte filter buffer
  119. * to avoid allocating memory that
  120. * is tricky to free later */
  121. struct netdev_hw_addr *ha;
  122. u32 crc_bits;
  123. memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
  124. /* Build the multicast hash filter. */
  125. netdev_for_each_mc_addr(ha, net) {
  126. crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
  127. data->multi_filter[crc_bits >> 3] |=
  128. 1 << (crc_bits & 7);
  129. }
  130. asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
  131. AX_MCAST_FILTER_SIZE, data->multi_filter);
  132. rx_ctl |= 0x10;
  133. }
  134. asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
  135. }
  136. static int ax88172_link_reset(struct usbnet *dev)
  137. {
  138. u8 mode;
  139. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  140. mii_check_media(&dev->mii, 1, 1);
  141. mii_ethtool_gset(&dev->mii, &ecmd);
  142. mode = AX88172_MEDIUM_DEFAULT;
  143. if (ecmd.duplex != DUPLEX_FULL)
  144. mode |= ~AX88172_MEDIUM_FD;
  145. netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
  146. ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
  147. asix_write_medium_mode(dev, mode);
  148. return 0;
  149. }
  150. static const struct net_device_ops ax88172_netdev_ops = {
  151. .ndo_open = usbnet_open,
  152. .ndo_stop = usbnet_stop,
  153. .ndo_start_xmit = usbnet_start_xmit,
  154. .ndo_tx_timeout = usbnet_tx_timeout,
  155. .ndo_change_mtu = usbnet_change_mtu,
  156. .ndo_set_mac_address = eth_mac_addr,
  157. .ndo_validate_addr = eth_validate_addr,
  158. .ndo_do_ioctl = asix_ioctl,
  159. .ndo_set_rx_mode = ax88172_set_multicast,
  160. };
  161. static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf)
  162. {
  163. int ret = 0;
  164. u8 buf[ETH_ALEN];
  165. int i;
  166. unsigned long gpio_bits = dev->driver_info->data;
  167. struct asix_data *data = (struct asix_data *)&dev->data;
  168. data->eeprom_len = AX88172_EEPROM_LEN;
  169. usbnet_get_endpoints(dev,intf);
  170. /* Toggle the GPIOs in a manufacturer/model specific way */
  171. for (i = 2; i >= 0; i--) {
  172. ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
  173. (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL);
  174. if (ret < 0)
  175. goto out;
  176. msleep(5);
  177. }
  178. ret = asix_write_rx_ctl(dev, 0x80);
  179. if (ret < 0)
  180. goto out;
  181. /* Get the MAC address */
  182. ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
  183. if (ret < 0) {
  184. dbg("read AX_CMD_READ_NODE_ID failed: %d", ret);
  185. goto out;
  186. }
  187. memcpy(dev->net->dev_addr, buf, ETH_ALEN);
  188. /* Initialize MII structure */
  189. dev->mii.dev = dev->net;
  190. dev->mii.mdio_read = asix_mdio_read;
  191. dev->mii.mdio_write = asix_mdio_write;
  192. dev->mii.phy_id_mask = 0x3f;
  193. dev->mii.reg_num_mask = 0x1f;
  194. dev->mii.phy_id = asix_get_phy_addr(dev);
  195. dev->net->netdev_ops = &ax88172_netdev_ops;
  196. dev->net->ethtool_ops = &ax88172_ethtool_ops;
  197. dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
  198. dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
  199. asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  200. asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  201. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
  202. mii_nway_restart(&dev->mii);
  203. return 0;
  204. out:
  205. return ret;
  206. }
  207. static const struct ethtool_ops ax88772_ethtool_ops = {
  208. .get_drvinfo = asix_get_drvinfo,
  209. .get_link = asix_get_link,
  210. .get_msglevel = usbnet_get_msglevel,
  211. .set_msglevel = usbnet_set_msglevel,
  212. .get_wol = asix_get_wol,
  213. .set_wol = asix_set_wol,
  214. .get_eeprom_len = asix_get_eeprom_len,
  215. .get_eeprom = asix_get_eeprom,
  216. .get_settings = usbnet_get_settings,
  217. .set_settings = usbnet_set_settings,
  218. .nway_reset = usbnet_nway_reset,
  219. };
  220. static int ax88772_link_reset(struct usbnet *dev)
  221. {
  222. u16 mode;
  223. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  224. mii_check_media(&dev->mii, 1, 1);
  225. mii_ethtool_gset(&dev->mii, &ecmd);
  226. mode = AX88772_MEDIUM_DEFAULT;
  227. if (ethtool_cmd_speed(&ecmd) != SPEED_100)
  228. mode &= ~AX_MEDIUM_PS;
  229. if (ecmd.duplex != DUPLEX_FULL)
  230. mode &= ~AX_MEDIUM_FD;
  231. netdev_dbg(dev->net, "ax88772_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
  232. ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
  233. asix_write_medium_mode(dev, mode);
  234. return 0;
  235. }
  236. static int ax88772_reset(struct usbnet *dev)
  237. {
  238. struct asix_data *data = (struct asix_data *)&dev->data;
  239. int ret, embd_phy;
  240. u16 rx_ctl;
  241. ret = asix_write_gpio(dev,
  242. AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5);
  243. if (ret < 0)
  244. goto out;
  245. embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0);
  246. ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL);
  247. if (ret < 0) {
  248. dbg("Select PHY #1 failed: %d", ret);
  249. goto out;
  250. }
  251. ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL);
  252. if (ret < 0)
  253. goto out;
  254. msleep(150);
  255. ret = asix_sw_reset(dev, AX_SWRESET_CLEAR);
  256. if (ret < 0)
  257. goto out;
  258. msleep(150);
  259. if (embd_phy) {
  260. ret = asix_sw_reset(dev, AX_SWRESET_IPRL);
  261. if (ret < 0)
  262. goto out;
  263. } else {
  264. ret = asix_sw_reset(dev, AX_SWRESET_PRTE);
  265. if (ret < 0)
  266. goto out;
  267. }
  268. msleep(150);
  269. rx_ctl = asix_read_rx_ctl(dev);
  270. dbg("RX_CTL is 0x%04x after software reset", rx_ctl);
  271. ret = asix_write_rx_ctl(dev, 0x0000);
  272. if (ret < 0)
  273. goto out;
  274. rx_ctl = asix_read_rx_ctl(dev);
  275. dbg("RX_CTL is 0x%04x setting to 0x0000", rx_ctl);
  276. ret = asix_sw_reset(dev, AX_SWRESET_PRL);
  277. if (ret < 0)
  278. goto out;
  279. msleep(150);
  280. ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL);
  281. if (ret < 0)
  282. goto out;
  283. msleep(150);
  284. asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  285. asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  286. ADVERTISE_ALL | ADVERTISE_CSMA);
  287. mii_nway_restart(&dev->mii);
  288. ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT);
  289. if (ret < 0)
  290. goto out;
  291. ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
  292. AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
  293. AX88772_IPG2_DEFAULT, 0, NULL);
  294. if (ret < 0) {
  295. dbg("Write IPG,IPG1,IPG2 failed: %d", ret);
  296. goto out;
  297. }
  298. /* Rewrite MAC address */
  299. memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
  300. ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
  301. data->mac_addr);
  302. if (ret < 0)
  303. goto out;
  304. /* Set RX_CTL to default values with 2k buffer, and enable cactus */
  305. ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL);
  306. if (ret < 0)
  307. goto out;
  308. rx_ctl = asix_read_rx_ctl(dev);
  309. dbg("RX_CTL is 0x%04x after all initializations", rx_ctl);
  310. rx_ctl = asix_read_medium_status(dev);
  311. dbg("Medium Status is 0x%04x after all initializations", rx_ctl);
  312. return 0;
  313. out:
  314. return ret;
  315. }
  316. static const struct net_device_ops ax88772_netdev_ops = {
  317. .ndo_open = usbnet_open,
  318. .ndo_stop = usbnet_stop,
  319. .ndo_start_xmit = usbnet_start_xmit,
  320. .ndo_tx_timeout = usbnet_tx_timeout,
  321. .ndo_change_mtu = usbnet_change_mtu,
  322. .ndo_set_mac_address = asix_set_mac_address,
  323. .ndo_validate_addr = eth_validate_addr,
  324. .ndo_do_ioctl = asix_ioctl,
  325. .ndo_set_rx_mode = asix_set_multicast,
  326. };
  327. static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)
  328. {
  329. int ret, embd_phy;
  330. struct asix_data *data = (struct asix_data *)&dev->data;
  331. u8 buf[ETH_ALEN];
  332. u32 phyid;
  333. data->eeprom_len = AX88772_EEPROM_LEN;
  334. usbnet_get_endpoints(dev,intf);
  335. /* Get the MAC address */
  336. ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
  337. if (ret < 0) {
  338. dbg("Failed to read MAC address: %d", ret);
  339. return ret;
  340. }
  341. memcpy(dev->net->dev_addr, buf, ETH_ALEN);
  342. /* Initialize MII structure */
  343. dev->mii.dev = dev->net;
  344. dev->mii.mdio_read = asix_mdio_read;
  345. dev->mii.mdio_write = asix_mdio_write;
  346. dev->mii.phy_id_mask = 0x1f;
  347. dev->mii.reg_num_mask = 0x1f;
  348. dev->mii.phy_id = asix_get_phy_addr(dev);
  349. dev->net->netdev_ops = &ax88772_netdev_ops;
  350. dev->net->ethtool_ops = &ax88772_ethtool_ops;
  351. dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
  352. dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
  353. embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
  354. /* Reset the PHY to normal operation mode */
  355. ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL);
  356. if (ret < 0) {
  357. dbg("Select PHY #1 failed: %d", ret);
  358. return ret;
  359. }
  360. ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL);
  361. if (ret < 0)
  362. return ret;
  363. msleep(150);
  364. ret = asix_sw_reset(dev, AX_SWRESET_CLEAR);
  365. if (ret < 0)
  366. return ret;
  367. msleep(150);
  368. ret = asix_sw_reset(dev, embd_phy ? AX_SWRESET_IPRL : AX_SWRESET_PRTE);
  369. /* Read PHYID register *AFTER* the PHY was reset properly */
  370. phyid = asix_get_phyid(dev);
  371. dbg("PHYID=0x%08x", phyid);
  372. /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
  373. if (dev->driver_info->flags & FLAG_FRAMING_AX) {
  374. /* hard_mtu is still the default - the device does not support
  375. jumbo eth frames */
  376. dev->rx_urb_size = 2048;
  377. }
  378. return 0;
  379. }
  380. static const struct ethtool_ops ax88178_ethtool_ops = {
  381. .get_drvinfo = asix_get_drvinfo,
  382. .get_link = asix_get_link,
  383. .get_msglevel = usbnet_get_msglevel,
  384. .set_msglevel = usbnet_set_msglevel,
  385. .get_wol = asix_get_wol,
  386. .set_wol = asix_set_wol,
  387. .get_eeprom_len = asix_get_eeprom_len,
  388. .get_eeprom = asix_get_eeprom,
  389. .get_settings = usbnet_get_settings,
  390. .set_settings = usbnet_set_settings,
  391. .nway_reset = usbnet_nway_reset,
  392. };
  393. static int marvell_phy_init(struct usbnet *dev)
  394. {
  395. struct asix_data *data = (struct asix_data *)&dev->data;
  396. u16 reg;
  397. netdev_dbg(dev->net, "marvell_phy_init()\n");
  398. reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
  399. netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg);
  400. asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
  401. MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY);
  402. if (data->ledmode) {
  403. reg = asix_mdio_read(dev->net, dev->mii.phy_id,
  404. MII_MARVELL_LED_CTRL);
  405. netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg);
  406. reg &= 0xf8ff;
  407. reg |= (1 + 0x0100);
  408. asix_mdio_write(dev->net, dev->mii.phy_id,
  409. MII_MARVELL_LED_CTRL, reg);
  410. reg = asix_mdio_read(dev->net, dev->mii.phy_id,
  411. MII_MARVELL_LED_CTRL);
  412. netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg);
  413. reg &= 0xfc0f;
  414. }
  415. return 0;
  416. }
  417. static int rtl8211cl_phy_init(struct usbnet *dev)
  418. {
  419. struct asix_data *data = (struct asix_data *)&dev->data;
  420. netdev_dbg(dev->net, "rtl8211cl_phy_init()\n");
  421. asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);
  422. asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);
  423. asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,
  424. asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);
  425. asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
  426. if (data->ledmode == 12) {
  427. asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);
  428. asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);
  429. asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
  430. }
  431. return 0;
  432. }
  433. static int marvell_led_status(struct usbnet *dev, u16 speed)
  434. {
  435. u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
  436. netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg);
  437. /* Clear out the center LED bits - 0x03F0 */
  438. reg &= 0xfc0f;
  439. switch (speed) {
  440. case SPEED_1000:
  441. reg |= 0x03e0;
  442. break;
  443. case SPEED_100:
  444. reg |= 0x03b0;
  445. break;
  446. default:
  447. reg |= 0x02f0;
  448. }
  449. netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg);
  450. asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
  451. return 0;
  452. }
  453. static int ax88178_reset(struct usbnet *dev)
  454. {
  455. struct asix_data *data = (struct asix_data *)&dev->data;
  456. int ret;
  457. __le16 eeprom;
  458. u8 status;
  459. int gpio0 = 0;
  460. u32 phyid;
  461. asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status);
  462. dbg("GPIO Status: 0x%04x", status);
  463. asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL);
  464. asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom);
  465. asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL);
  466. dbg("EEPROM index 0x17 is 0x%04x", eeprom);
  467. if (eeprom == cpu_to_le16(0xffff)) {
  468. data->phymode = PHY_MODE_MARVELL;
  469. data->ledmode = 0;
  470. gpio0 = 1;
  471. } else {
  472. data->phymode = le16_to_cpu(eeprom) & 0x7F;
  473. data->ledmode = le16_to_cpu(eeprom) >> 8;
  474. gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1;
  475. }
  476. dbg("GPIO0: %d, PhyMode: %d", gpio0, data->phymode);
  477. /* Power up external GigaPHY through AX88178 GPIO pin */
  478. asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | AX_GPIO_GPO1EN, 40);
  479. if ((le16_to_cpu(eeprom) >> 8) != 1) {
  480. asix_write_gpio(dev, 0x003c, 30);
  481. asix_write_gpio(dev, 0x001c, 300);
  482. asix_write_gpio(dev, 0x003c, 30);
  483. } else {
  484. dbg("gpio phymode == 1 path");
  485. asix_write_gpio(dev, AX_GPIO_GPO1EN, 30);
  486. asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30);
  487. }
  488. /* Read PHYID register *AFTER* powering up PHY */
  489. phyid = asix_get_phyid(dev);
  490. dbg("PHYID=0x%08x", phyid);
  491. /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */
  492. asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL);
  493. asix_sw_reset(dev, 0);
  494. msleep(150);
  495. asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD);
  496. msleep(150);
  497. asix_write_rx_ctl(dev, 0);
  498. if (data->phymode == PHY_MODE_MARVELL) {
  499. marvell_phy_init(dev);
  500. msleep(60);
  501. } else if (data->phymode == PHY_MODE_RTL8211CL)
  502. rtl8211cl_phy_init(dev);
  503. asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR,
  504. BMCR_RESET | BMCR_ANENABLE);
  505. asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  506. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
  507. asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
  508. ADVERTISE_1000FULL);
  509. mii_nway_restart(&dev->mii);
  510. ret = asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT);
  511. if (ret < 0)
  512. return ret;
  513. /* Rewrite MAC address */
  514. memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
  515. ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
  516. data->mac_addr);
  517. if (ret < 0)
  518. return ret;
  519. ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL);
  520. if (ret < 0)
  521. return ret;
  522. return 0;
  523. }
  524. static int ax88178_link_reset(struct usbnet *dev)
  525. {
  526. u16 mode;
  527. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  528. struct asix_data *data = (struct asix_data *)&dev->data;
  529. u32 speed;
  530. netdev_dbg(dev->net, "ax88178_link_reset()\n");
  531. mii_check_media(&dev->mii, 1, 1);
  532. mii_ethtool_gset(&dev->mii, &ecmd);
  533. mode = AX88178_MEDIUM_DEFAULT;
  534. speed = ethtool_cmd_speed(&ecmd);
  535. if (speed == SPEED_1000)
  536. mode |= AX_MEDIUM_GM;
  537. else if (speed == SPEED_100)
  538. mode |= AX_MEDIUM_PS;
  539. else
  540. mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM);
  541. mode |= AX_MEDIUM_ENCK;
  542. if (ecmd.duplex == DUPLEX_FULL)
  543. mode |= AX_MEDIUM_FD;
  544. else
  545. mode &= ~AX_MEDIUM_FD;
  546. netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
  547. speed, ecmd.duplex, mode);
  548. asix_write_medium_mode(dev, mode);
  549. if (data->phymode == PHY_MODE_MARVELL && data->ledmode)
  550. marvell_led_status(dev, speed);
  551. return 0;
  552. }
  553. static void ax88178_set_mfb(struct usbnet *dev)
  554. {
  555. u16 mfb = AX_RX_CTL_MFB_16384;
  556. u16 rxctl;
  557. u16 medium;
  558. int old_rx_urb_size = dev->rx_urb_size;
  559. if (dev->hard_mtu < 2048) {
  560. dev->rx_urb_size = 2048;
  561. mfb = AX_RX_CTL_MFB_2048;
  562. } else if (dev->hard_mtu < 4096) {
  563. dev->rx_urb_size = 4096;
  564. mfb = AX_RX_CTL_MFB_4096;
  565. } else if (dev->hard_mtu < 8192) {
  566. dev->rx_urb_size = 8192;
  567. mfb = AX_RX_CTL_MFB_8192;
  568. } else if (dev->hard_mtu < 16384) {
  569. dev->rx_urb_size = 16384;
  570. mfb = AX_RX_CTL_MFB_16384;
  571. }
  572. rxctl = asix_read_rx_ctl(dev);
  573. asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb);
  574. medium = asix_read_medium_status(dev);
  575. if (dev->net->mtu > 1500)
  576. medium |= AX_MEDIUM_JFE;
  577. else
  578. medium &= ~AX_MEDIUM_JFE;
  579. asix_write_medium_mode(dev, medium);
  580. if (dev->rx_urb_size > old_rx_urb_size)
  581. usbnet_unlink_rx_urbs(dev);
  582. }
  583. static int ax88178_change_mtu(struct net_device *net, int new_mtu)
  584. {
  585. struct usbnet *dev = netdev_priv(net);
  586. int ll_mtu = new_mtu + net->hard_header_len + 4;
  587. netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu);
  588. if (new_mtu <= 0 || ll_mtu > 16384)
  589. return -EINVAL;
  590. if ((ll_mtu % dev->maxpacket) == 0)
  591. return -EDOM;
  592. net->mtu = new_mtu;
  593. dev->hard_mtu = net->mtu + net->hard_header_len;
  594. ax88178_set_mfb(dev);
  595. return 0;
  596. }
  597. static const struct net_device_ops ax88178_netdev_ops = {
  598. .ndo_open = usbnet_open,
  599. .ndo_stop = usbnet_stop,
  600. .ndo_start_xmit = usbnet_start_xmit,
  601. .ndo_tx_timeout = usbnet_tx_timeout,
  602. .ndo_set_mac_address = asix_set_mac_address,
  603. .ndo_validate_addr = eth_validate_addr,
  604. .ndo_set_rx_mode = asix_set_multicast,
  605. .ndo_do_ioctl = asix_ioctl,
  606. .ndo_change_mtu = ax88178_change_mtu,
  607. };
  608. static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf)
  609. {
  610. int ret;
  611. u8 buf[ETH_ALEN];
  612. struct asix_data *data = (struct asix_data *)&dev->data;
  613. data->eeprom_len = AX88772_EEPROM_LEN;
  614. usbnet_get_endpoints(dev,intf);
  615. /* Get the MAC address */
  616. ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
  617. if (ret < 0) {
  618. dbg("Failed to read MAC address: %d", ret);
  619. return ret;
  620. }
  621. memcpy(dev->net->dev_addr, buf, ETH_ALEN);
  622. /* Initialize MII structure */
  623. dev->mii.dev = dev->net;
  624. dev->mii.mdio_read = asix_mdio_read;
  625. dev->mii.mdio_write = asix_mdio_write;
  626. dev->mii.phy_id_mask = 0x1f;
  627. dev->mii.reg_num_mask = 0xff;
  628. dev->mii.supports_gmii = 1;
  629. dev->mii.phy_id = asix_get_phy_addr(dev);
  630. dev->net->netdev_ops = &ax88178_netdev_ops;
  631. dev->net->ethtool_ops = &ax88178_ethtool_ops;
  632. /* Blink LEDS so users know driver saw dongle */
  633. asix_sw_reset(dev, 0);
  634. msleep(150);
  635. asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD);
  636. msleep(150);
  637. /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
  638. if (dev->driver_info->flags & FLAG_FRAMING_AX) {
  639. /* hard_mtu is still the default - the device does not support
  640. jumbo eth frames */
  641. dev->rx_urb_size = 2048;
  642. }
  643. return 0;
  644. }
  645. static const struct driver_info ax8817x_info = {
  646. .description = "ASIX AX8817x USB 2.0 Ethernet",
  647. .bind = ax88172_bind,
  648. .status = asix_status,
  649. .link_reset = ax88172_link_reset,
  650. .reset = ax88172_link_reset,
  651. .flags = FLAG_ETHER | FLAG_LINK_INTR,
  652. .data = 0x00130103,
  653. };
  654. static const struct driver_info dlink_dub_e100_info = {
  655. .description = "DLink DUB-E100 USB Ethernet",
  656. .bind = ax88172_bind,
  657. .status = asix_status,
  658. .link_reset = ax88172_link_reset,
  659. .reset = ax88172_link_reset,
  660. .flags = FLAG_ETHER | FLAG_LINK_INTR,
  661. .data = 0x009f9d9f,
  662. };
  663. static const struct driver_info netgear_fa120_info = {
  664. .description = "Netgear FA-120 USB Ethernet",
  665. .bind = ax88172_bind,
  666. .status = asix_status,
  667. .link_reset = ax88172_link_reset,
  668. .reset = ax88172_link_reset,
  669. .flags = FLAG_ETHER | FLAG_LINK_INTR,
  670. .data = 0x00130103,
  671. };
  672. static const struct driver_info hawking_uf200_info = {
  673. .description = "Hawking UF200 USB Ethernet",
  674. .bind = ax88172_bind,
  675. .status = asix_status,
  676. .link_reset = ax88172_link_reset,
  677. .reset = ax88172_link_reset,
  678. .flags = FLAG_ETHER | FLAG_LINK_INTR,
  679. .data = 0x001f1d1f,
  680. };
  681. static const struct driver_info ax88772_info = {
  682. .description = "ASIX AX88772 USB 2.0 Ethernet",
  683. .bind = ax88772_bind,
  684. .status = asix_status,
  685. .link_reset = ax88772_link_reset,
  686. .reset = ax88772_reset,
  687. .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET,
  688. .rx_fixup = asix_rx_fixup,
  689. .tx_fixup = asix_tx_fixup,
  690. };
  691. static const struct driver_info ax88178_info = {
  692. .description = "ASIX AX88178 USB 2.0 Ethernet",
  693. .bind = ax88178_bind,
  694. .status = asix_status,
  695. .link_reset = ax88178_link_reset,
  696. .reset = ax88178_reset,
  697. .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR,
  698. .rx_fixup = asix_rx_fixup,
  699. .tx_fixup = asix_tx_fixup,
  700. };
  701. static const struct usb_device_id products [] = {
  702. {
  703. // Linksys USB200M
  704. USB_DEVICE (0x077b, 0x2226),
  705. .driver_info = (unsigned long) &ax8817x_info,
  706. }, {
  707. // Netgear FA120
  708. USB_DEVICE (0x0846, 0x1040),
  709. .driver_info = (unsigned long) &netgear_fa120_info,
  710. }, {
  711. // DLink DUB-E100
  712. USB_DEVICE (0x2001, 0x1a00),
  713. .driver_info = (unsigned long) &dlink_dub_e100_info,
  714. }, {
  715. // Intellinet, ST Lab USB Ethernet
  716. USB_DEVICE (0x0b95, 0x1720),
  717. .driver_info = (unsigned long) &ax8817x_info,
  718. }, {
  719. // Hawking UF200, TrendNet TU2-ET100
  720. USB_DEVICE (0x07b8, 0x420a),
  721. .driver_info = (unsigned long) &hawking_uf200_info,
  722. }, {
  723. // Billionton Systems, USB2AR
  724. USB_DEVICE (0x08dd, 0x90ff),
  725. .driver_info = (unsigned long) &ax8817x_info,
  726. }, {
  727. // ATEN UC210T
  728. USB_DEVICE (0x0557, 0x2009),
  729. .driver_info = (unsigned long) &ax8817x_info,
  730. }, {
  731. // Buffalo LUA-U2-KTX
  732. USB_DEVICE (0x0411, 0x003d),
  733. .driver_info = (unsigned long) &ax8817x_info,
  734. }, {
  735. // Buffalo LUA-U2-GT 10/100/1000
  736. USB_DEVICE (0x0411, 0x006e),
  737. .driver_info = (unsigned long) &ax88178_info,
  738. }, {
  739. // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
  740. USB_DEVICE (0x6189, 0x182d),
  741. .driver_info = (unsigned long) &ax8817x_info,
  742. }, {
  743. // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter"
  744. USB_DEVICE (0x0df6, 0x0056),
  745. .driver_info = (unsigned long) &ax88178_info,
  746. }, {
  747. // corega FEther USB2-TX
  748. USB_DEVICE (0x07aa, 0x0017),
  749. .driver_info = (unsigned long) &ax8817x_info,
  750. }, {
  751. // Surecom EP-1427X-2
  752. USB_DEVICE (0x1189, 0x0893),
  753. .driver_info = (unsigned long) &ax8817x_info,
  754. }, {
  755. // goodway corp usb gwusb2e
  756. USB_DEVICE (0x1631, 0x6200),
  757. .driver_info = (unsigned long) &ax8817x_info,
  758. }, {
  759. // JVC MP-PRX1 Port Replicator
  760. USB_DEVICE (0x04f1, 0x3008),
  761. .driver_info = (unsigned long) &ax8817x_info,
  762. }, {
  763. // ASIX AX88772B 10/100
  764. USB_DEVICE (0x0b95, 0x772b),
  765. .driver_info = (unsigned long) &ax88772_info,
  766. }, {
  767. // ASIX AX88772 10/100
  768. USB_DEVICE (0x0b95, 0x7720),
  769. .driver_info = (unsigned long) &ax88772_info,
  770. }, {
  771. // ASIX AX88178 10/100/1000
  772. USB_DEVICE (0x0b95, 0x1780),
  773. .driver_info = (unsigned long) &ax88178_info,
  774. }, {
  775. // Logitec LAN-GTJ/U2A
  776. USB_DEVICE (0x0789, 0x0160),
  777. .driver_info = (unsigned long) &ax88178_info,
  778. }, {
  779. // Linksys USB200M Rev 2
  780. USB_DEVICE (0x13b1, 0x0018),
  781. .driver_info = (unsigned long) &ax88772_info,
  782. }, {
  783. // 0Q0 cable ethernet
  784. USB_DEVICE (0x1557, 0x7720),
  785. .driver_info = (unsigned long) &ax88772_info,
  786. }, {
  787. // DLink DUB-E100 H/W Ver B1
  788. USB_DEVICE (0x07d1, 0x3c05),
  789. .driver_info = (unsigned long) &ax88772_info,
  790. }, {
  791. // DLink DUB-E100 H/W Ver B1 Alternate
  792. USB_DEVICE (0x2001, 0x3c05),
  793. .driver_info = (unsigned long) &ax88772_info,
  794. }, {
  795. // Linksys USB1000
  796. USB_DEVICE (0x1737, 0x0039),
  797. .driver_info = (unsigned long) &ax88178_info,
  798. }, {
  799. // IO-DATA ETG-US2
  800. USB_DEVICE (0x04bb, 0x0930),
  801. .driver_info = (unsigned long) &ax88178_info,
  802. }, {
  803. // Belkin F5D5055
  804. USB_DEVICE(0x050d, 0x5055),
  805. .driver_info = (unsigned long) &ax88178_info,
  806. }, {
  807. // Apple USB Ethernet Adapter
  808. USB_DEVICE(0x05ac, 0x1402),
  809. .driver_info = (unsigned long) &ax88772_info,
  810. }, {
  811. // Cables-to-Go USB Ethernet Adapter
  812. USB_DEVICE(0x0b95, 0x772a),
  813. .driver_info = (unsigned long) &ax88772_info,
  814. }, {
  815. // ABOCOM for pci
  816. USB_DEVICE(0x14ea, 0xab11),
  817. .driver_info = (unsigned long) &ax88178_info,
  818. }, {
  819. // ASIX 88772a
  820. USB_DEVICE(0x0db0, 0xa877),
  821. .driver_info = (unsigned long) &ax88772_info,
  822. }, {
  823. // Asus USB Ethernet Adapter
  824. USB_DEVICE (0x0b95, 0x7e2b),
  825. .driver_info = (unsigned long) &ax88772_info,
  826. },
  827. { }, // END
  828. };
  829. MODULE_DEVICE_TABLE(usb, products);
  830. static struct usb_driver asix_driver = {
  831. .name = DRIVER_NAME,
  832. .id_table = products,
  833. .probe = usbnet_probe,
  834. .suspend = usbnet_suspend,
  835. .resume = usbnet_resume,
  836. .disconnect = usbnet_disconnect,
  837. .supports_autosuspend = 1,
  838. .disable_hub_initiated_lpm = 1,
  839. };
  840. module_usb_driver(asix_driver);
  841. MODULE_AUTHOR("David Hollis");
  842. MODULE_VERSION(DRIVER_VERSION);
  843. MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices");
  844. MODULE_LICENSE("GPL");