i915_irq.c 90 KB

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  1. /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
  2. */
  3. /*
  4. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  5. * All Rights Reserved.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the
  9. * "Software"), to deal in the Software without restriction, including
  10. * without limitation the rights to use, copy, modify, merge, publish,
  11. * distribute, sub license, and/or sell copies of the Software, and to
  12. * permit persons to whom the Software is furnished to do so, subject to
  13. * the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the
  16. * next paragraph) shall be included in all copies or substantial portions
  17. * of the Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26. *
  27. */
  28. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  29. #include <linux/sysrq.h>
  30. #include <linux/slab.h>
  31. #include <drm/drmP.h>
  32. #include <drm/i915_drm.h>
  33. #include "i915_drv.h"
  34. #include "i915_trace.h"
  35. #include "intel_drv.h"
  36. static const u32 hpd_ibx[] = {
  37. [HPD_CRT] = SDE_CRT_HOTPLUG,
  38. [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  39. [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  40. [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  41. [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  42. };
  43. static const u32 hpd_cpt[] = {
  44. [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  45. [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  46. [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  47. [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  48. [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  49. };
  50. static const u32 hpd_mask_i915[] = {
  51. [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  52. [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  53. [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  54. [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  55. [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  56. [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  57. };
  58. static const u32 hpd_status_gen4[] = {
  59. [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  60. [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  61. [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  62. [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  63. [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  64. [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  65. };
  66. static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
  67. [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  68. [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  69. [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  70. [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  71. [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  72. [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  73. };
  74. /* For display hotplug interrupt */
  75. static void
  76. ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  77. {
  78. assert_spin_locked(&dev_priv->irq_lock);
  79. if ((dev_priv->irq_mask & mask) != 0) {
  80. dev_priv->irq_mask &= ~mask;
  81. I915_WRITE(DEIMR, dev_priv->irq_mask);
  82. POSTING_READ(DEIMR);
  83. }
  84. }
  85. static void
  86. ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  87. {
  88. assert_spin_locked(&dev_priv->irq_lock);
  89. if ((dev_priv->irq_mask & mask) != mask) {
  90. dev_priv->irq_mask |= mask;
  91. I915_WRITE(DEIMR, dev_priv->irq_mask);
  92. POSTING_READ(DEIMR);
  93. }
  94. }
  95. /**
  96. * ilk_update_gt_irq - update GTIMR
  97. * @dev_priv: driver private
  98. * @interrupt_mask: mask of interrupt bits to update
  99. * @enabled_irq_mask: mask of interrupt bits to enable
  100. */
  101. static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
  102. uint32_t interrupt_mask,
  103. uint32_t enabled_irq_mask)
  104. {
  105. assert_spin_locked(&dev_priv->irq_lock);
  106. dev_priv->gt_irq_mask &= ~interrupt_mask;
  107. dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
  108. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  109. POSTING_READ(GTIMR);
  110. }
  111. void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
  112. {
  113. ilk_update_gt_irq(dev_priv, mask, mask);
  114. }
  115. void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
  116. {
  117. ilk_update_gt_irq(dev_priv, mask, 0);
  118. }
  119. /**
  120. * snb_update_pm_irq - update GEN6_PMIMR
  121. * @dev_priv: driver private
  122. * @interrupt_mask: mask of interrupt bits to update
  123. * @enabled_irq_mask: mask of interrupt bits to enable
  124. */
  125. static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
  126. uint32_t interrupt_mask,
  127. uint32_t enabled_irq_mask)
  128. {
  129. uint32_t new_val;
  130. assert_spin_locked(&dev_priv->irq_lock);
  131. new_val = dev_priv->pm_irq_mask;
  132. new_val &= ~interrupt_mask;
  133. new_val |= (~enabled_irq_mask & interrupt_mask);
  134. if (new_val != dev_priv->pm_irq_mask) {
  135. dev_priv->pm_irq_mask = new_val;
  136. I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
  137. POSTING_READ(GEN6_PMIMR);
  138. }
  139. }
  140. void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
  141. {
  142. snb_update_pm_irq(dev_priv, mask, mask);
  143. }
  144. void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
  145. {
  146. snb_update_pm_irq(dev_priv, mask, 0);
  147. }
  148. static void snb_set_pm_irq(struct drm_i915_private *dev_priv, uint32_t val)
  149. {
  150. snb_update_pm_irq(dev_priv, 0xffffffff, ~val);
  151. }
  152. static bool ivb_can_enable_err_int(struct drm_device *dev)
  153. {
  154. struct drm_i915_private *dev_priv = dev->dev_private;
  155. struct intel_crtc *crtc;
  156. enum pipe pipe;
  157. assert_spin_locked(&dev_priv->irq_lock);
  158. for_each_pipe(pipe) {
  159. crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  160. if (crtc->cpu_fifo_underrun_disabled)
  161. return false;
  162. }
  163. return true;
  164. }
  165. static bool cpt_can_enable_serr_int(struct drm_device *dev)
  166. {
  167. struct drm_i915_private *dev_priv = dev->dev_private;
  168. enum pipe pipe;
  169. struct intel_crtc *crtc;
  170. assert_spin_locked(&dev_priv->irq_lock);
  171. for_each_pipe(pipe) {
  172. crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  173. if (crtc->pch_fifo_underrun_disabled)
  174. return false;
  175. }
  176. return true;
  177. }
  178. static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
  179. enum pipe pipe, bool enable)
  180. {
  181. struct drm_i915_private *dev_priv = dev->dev_private;
  182. uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
  183. DE_PIPEB_FIFO_UNDERRUN;
  184. if (enable)
  185. ironlake_enable_display_irq(dev_priv, bit);
  186. else
  187. ironlake_disable_display_irq(dev_priv, bit);
  188. }
  189. static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
  190. enum pipe pipe, bool enable)
  191. {
  192. struct drm_i915_private *dev_priv = dev->dev_private;
  193. if (enable) {
  194. I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
  195. if (!ivb_can_enable_err_int(dev))
  196. return;
  197. ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
  198. } else {
  199. bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
  200. /* Change the state _after_ we've read out the current one. */
  201. ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
  202. if (!was_enabled &&
  203. (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
  204. DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
  205. pipe_name(pipe));
  206. }
  207. }
  208. }
  209. /**
  210. * ibx_display_interrupt_update - update SDEIMR
  211. * @dev_priv: driver private
  212. * @interrupt_mask: mask of interrupt bits to update
  213. * @enabled_irq_mask: mask of interrupt bits to enable
  214. */
  215. static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
  216. uint32_t interrupt_mask,
  217. uint32_t enabled_irq_mask)
  218. {
  219. uint32_t sdeimr = I915_READ(SDEIMR);
  220. sdeimr &= ~interrupt_mask;
  221. sdeimr |= (~enabled_irq_mask & interrupt_mask);
  222. assert_spin_locked(&dev_priv->irq_lock);
  223. I915_WRITE(SDEIMR, sdeimr);
  224. POSTING_READ(SDEIMR);
  225. }
  226. #define ibx_enable_display_interrupt(dev_priv, bits) \
  227. ibx_display_interrupt_update((dev_priv), (bits), (bits))
  228. #define ibx_disable_display_interrupt(dev_priv, bits) \
  229. ibx_display_interrupt_update((dev_priv), (bits), 0)
  230. static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
  231. enum transcoder pch_transcoder,
  232. bool enable)
  233. {
  234. struct drm_i915_private *dev_priv = dev->dev_private;
  235. uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
  236. SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
  237. if (enable)
  238. ibx_enable_display_interrupt(dev_priv, bit);
  239. else
  240. ibx_disable_display_interrupt(dev_priv, bit);
  241. }
  242. static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
  243. enum transcoder pch_transcoder,
  244. bool enable)
  245. {
  246. struct drm_i915_private *dev_priv = dev->dev_private;
  247. if (enable) {
  248. I915_WRITE(SERR_INT,
  249. SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
  250. if (!cpt_can_enable_serr_int(dev))
  251. return;
  252. ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
  253. } else {
  254. uint32_t tmp = I915_READ(SERR_INT);
  255. bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
  256. /* Change the state _after_ we've read out the current one. */
  257. ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
  258. if (!was_enabled &&
  259. (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
  260. DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
  261. transcoder_name(pch_transcoder));
  262. }
  263. }
  264. }
  265. /**
  266. * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
  267. * @dev: drm device
  268. * @pipe: pipe
  269. * @enable: true if we want to report FIFO underrun errors, false otherwise
  270. *
  271. * This function makes us disable or enable CPU fifo underruns for a specific
  272. * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
  273. * reporting for one pipe may also disable all the other CPU error interruts for
  274. * the other pipes, due to the fact that there's just one interrupt mask/enable
  275. * bit for all the pipes.
  276. *
  277. * Returns the previous state of underrun reporting.
  278. */
  279. bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
  280. enum pipe pipe, bool enable)
  281. {
  282. struct drm_i915_private *dev_priv = dev->dev_private;
  283. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  284. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  285. unsigned long flags;
  286. bool ret;
  287. spin_lock_irqsave(&dev_priv->irq_lock, flags);
  288. ret = !intel_crtc->cpu_fifo_underrun_disabled;
  289. if (enable == ret)
  290. goto done;
  291. intel_crtc->cpu_fifo_underrun_disabled = !enable;
  292. if (IS_GEN5(dev) || IS_GEN6(dev))
  293. ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
  294. else if (IS_GEN7(dev))
  295. ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
  296. done:
  297. spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
  298. return ret;
  299. }
  300. /**
  301. * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
  302. * @dev: drm device
  303. * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
  304. * @enable: true if we want to report FIFO underrun errors, false otherwise
  305. *
  306. * This function makes us disable or enable PCH fifo underruns for a specific
  307. * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
  308. * underrun reporting for one transcoder may also disable all the other PCH
  309. * error interruts for the other transcoders, due to the fact that there's just
  310. * one interrupt mask/enable bit for all the transcoders.
  311. *
  312. * Returns the previous state of underrun reporting.
  313. */
  314. bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
  315. enum transcoder pch_transcoder,
  316. bool enable)
  317. {
  318. struct drm_i915_private *dev_priv = dev->dev_private;
  319. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
  320. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  321. unsigned long flags;
  322. bool ret;
  323. /*
  324. * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
  325. * has only one pch transcoder A that all pipes can use. To avoid racy
  326. * pch transcoder -> pipe lookups from interrupt code simply store the
  327. * underrun statistics in crtc A. Since we never expose this anywhere
  328. * nor use it outside of the fifo underrun code here using the "wrong"
  329. * crtc on LPT won't cause issues.
  330. */
  331. spin_lock_irqsave(&dev_priv->irq_lock, flags);
  332. ret = !intel_crtc->pch_fifo_underrun_disabled;
  333. if (enable == ret)
  334. goto done;
  335. intel_crtc->pch_fifo_underrun_disabled = !enable;
  336. if (HAS_PCH_IBX(dev))
  337. ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
  338. else
  339. cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
  340. done:
  341. spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
  342. return ret;
  343. }
  344. void
  345. i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  346. {
  347. u32 reg = PIPESTAT(pipe);
  348. u32 pipestat = I915_READ(reg) & 0x7fff0000;
  349. assert_spin_locked(&dev_priv->irq_lock);
  350. if ((pipestat & mask) == mask)
  351. return;
  352. /* Enable the interrupt, clear any pending status */
  353. pipestat |= mask | (mask >> 16);
  354. I915_WRITE(reg, pipestat);
  355. POSTING_READ(reg);
  356. }
  357. void
  358. i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  359. {
  360. u32 reg = PIPESTAT(pipe);
  361. u32 pipestat = I915_READ(reg) & 0x7fff0000;
  362. assert_spin_locked(&dev_priv->irq_lock);
  363. if ((pipestat & mask) == 0)
  364. return;
  365. pipestat &= ~mask;
  366. I915_WRITE(reg, pipestat);
  367. POSTING_READ(reg);
  368. }
  369. /**
  370. * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
  371. */
  372. static void i915_enable_asle_pipestat(struct drm_device *dev)
  373. {
  374. drm_i915_private_t *dev_priv = dev->dev_private;
  375. unsigned long irqflags;
  376. if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
  377. return;
  378. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  379. i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
  380. if (INTEL_INFO(dev)->gen >= 4)
  381. i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
  382. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  383. }
  384. /**
  385. * i915_pipe_enabled - check if a pipe is enabled
  386. * @dev: DRM device
  387. * @pipe: pipe to check
  388. *
  389. * Reading certain registers when the pipe is disabled can hang the chip.
  390. * Use this routine to make sure the PLL is running and the pipe is active
  391. * before reading such registers if unsure.
  392. */
  393. static int
  394. i915_pipe_enabled(struct drm_device *dev, int pipe)
  395. {
  396. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  397. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  398. /* Locking is horribly broken here, but whatever. */
  399. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  400. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  401. return intel_crtc->active;
  402. } else {
  403. return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
  404. }
  405. }
  406. /* Called from drm generic code, passed a 'crtc', which
  407. * we use as a pipe index
  408. */
  409. static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
  410. {
  411. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  412. unsigned long high_frame;
  413. unsigned long low_frame;
  414. u32 high1, high2, low;
  415. if (!i915_pipe_enabled(dev, pipe)) {
  416. DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
  417. "pipe %c\n", pipe_name(pipe));
  418. return 0;
  419. }
  420. high_frame = PIPEFRAME(pipe);
  421. low_frame = PIPEFRAMEPIXEL(pipe);
  422. /*
  423. * High & low register fields aren't synchronized, so make sure
  424. * we get a low value that's stable across two reads of the high
  425. * register.
  426. */
  427. do {
  428. high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
  429. low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
  430. high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
  431. } while (high1 != high2);
  432. high1 >>= PIPE_FRAME_HIGH_SHIFT;
  433. low >>= PIPE_FRAME_LOW_SHIFT;
  434. return (high1 << 8) | low;
  435. }
  436. static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
  437. {
  438. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  439. int reg = PIPE_FRMCOUNT_GM45(pipe);
  440. if (!i915_pipe_enabled(dev, pipe)) {
  441. DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
  442. "pipe %c\n", pipe_name(pipe));
  443. return 0;
  444. }
  445. return I915_READ(reg);
  446. }
  447. static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
  448. int *vpos, int *hpos)
  449. {
  450. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  451. u32 vbl = 0, position = 0;
  452. int vbl_start, vbl_end, htotal, vtotal;
  453. bool in_vbl = true;
  454. int ret = 0;
  455. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  456. pipe);
  457. if (!i915_pipe_enabled(dev, pipe)) {
  458. DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
  459. "pipe %c\n", pipe_name(pipe));
  460. return 0;
  461. }
  462. /* Get vtotal. */
  463. vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
  464. if (INTEL_INFO(dev)->gen >= 4) {
  465. /* No obvious pixelcount register. Only query vertical
  466. * scanout position from Display scan line register.
  467. */
  468. position = I915_READ(PIPEDSL(pipe));
  469. /* Decode into vertical scanout position. Don't have
  470. * horizontal scanout position.
  471. */
  472. *vpos = position & 0x1fff;
  473. *hpos = 0;
  474. } else {
  475. /* Have access to pixelcount since start of frame.
  476. * We can split this into vertical and horizontal
  477. * scanout position.
  478. */
  479. position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
  480. htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
  481. *vpos = position / htotal;
  482. *hpos = position - (*vpos * htotal);
  483. }
  484. /* Query vblank area. */
  485. vbl = I915_READ(VBLANK(cpu_transcoder));
  486. /* Test position against vblank region. */
  487. vbl_start = vbl & 0x1fff;
  488. vbl_end = (vbl >> 16) & 0x1fff;
  489. if ((*vpos < vbl_start) || (*vpos > vbl_end))
  490. in_vbl = false;
  491. /* Inside "upper part" of vblank area? Apply corrective offset: */
  492. if (in_vbl && (*vpos >= vbl_start))
  493. *vpos = *vpos - vtotal;
  494. /* Readouts valid? */
  495. if (vbl > 0)
  496. ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
  497. /* In vblank? */
  498. if (in_vbl)
  499. ret |= DRM_SCANOUTPOS_INVBL;
  500. return ret;
  501. }
  502. static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
  503. int *max_error,
  504. struct timeval *vblank_time,
  505. unsigned flags)
  506. {
  507. struct drm_crtc *crtc;
  508. if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
  509. DRM_ERROR("Invalid crtc %d\n", pipe);
  510. return -EINVAL;
  511. }
  512. /* Get drm_crtc to timestamp: */
  513. crtc = intel_get_crtc_for_pipe(dev, pipe);
  514. if (crtc == NULL) {
  515. DRM_ERROR("Invalid crtc %d\n", pipe);
  516. return -EINVAL;
  517. }
  518. if (!crtc->enabled) {
  519. DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
  520. return -EBUSY;
  521. }
  522. /* Helper routine in DRM core does all the work: */
  523. return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
  524. vblank_time, flags,
  525. crtc);
  526. }
  527. static int intel_hpd_irq_event(struct drm_device *dev, struct drm_connector *connector)
  528. {
  529. enum drm_connector_status old_status;
  530. WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
  531. old_status = connector->status;
  532. connector->status = connector->funcs->detect(connector, false);
  533. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
  534. connector->base.id,
  535. drm_get_connector_name(connector),
  536. old_status, connector->status);
  537. return (old_status != connector->status);
  538. }
  539. /*
  540. * Handle hotplug events outside the interrupt handler proper.
  541. */
  542. #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
  543. static void i915_hotplug_work_func(struct work_struct *work)
  544. {
  545. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  546. hotplug_work);
  547. struct drm_device *dev = dev_priv->dev;
  548. struct drm_mode_config *mode_config = &dev->mode_config;
  549. struct intel_connector *intel_connector;
  550. struct intel_encoder *intel_encoder;
  551. struct drm_connector *connector;
  552. unsigned long irqflags;
  553. bool hpd_disabled = false;
  554. bool changed = false;
  555. u32 hpd_event_bits;
  556. /* HPD irq before everything is fully set up. */
  557. if (!dev_priv->enable_hotplug_processing)
  558. return;
  559. mutex_lock(&mode_config->mutex);
  560. DRM_DEBUG_KMS("running encoder hotplug functions\n");
  561. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  562. hpd_event_bits = dev_priv->hpd_event_bits;
  563. dev_priv->hpd_event_bits = 0;
  564. list_for_each_entry(connector, &mode_config->connector_list, head) {
  565. intel_connector = to_intel_connector(connector);
  566. intel_encoder = intel_connector->encoder;
  567. if (intel_encoder->hpd_pin > HPD_NONE &&
  568. dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
  569. connector->polled == DRM_CONNECTOR_POLL_HPD) {
  570. DRM_INFO("HPD interrupt storm detected on connector %s: "
  571. "switching from hotplug detection to polling\n",
  572. drm_get_connector_name(connector));
  573. dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
  574. connector->polled = DRM_CONNECTOR_POLL_CONNECT
  575. | DRM_CONNECTOR_POLL_DISCONNECT;
  576. hpd_disabled = true;
  577. }
  578. if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
  579. DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
  580. drm_get_connector_name(connector), intel_encoder->hpd_pin);
  581. }
  582. }
  583. /* if there were no outputs to poll, poll was disabled,
  584. * therefore make sure it's enabled when disabling HPD on
  585. * some connectors */
  586. if (hpd_disabled) {
  587. drm_kms_helper_poll_enable(dev);
  588. mod_timer(&dev_priv->hotplug_reenable_timer,
  589. jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
  590. }
  591. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  592. list_for_each_entry(connector, &mode_config->connector_list, head) {
  593. intel_connector = to_intel_connector(connector);
  594. intel_encoder = intel_connector->encoder;
  595. if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
  596. if (intel_encoder->hot_plug)
  597. intel_encoder->hot_plug(intel_encoder);
  598. if (intel_hpd_irq_event(dev, connector))
  599. changed = true;
  600. }
  601. }
  602. mutex_unlock(&mode_config->mutex);
  603. if (changed)
  604. drm_kms_helper_hotplug_event(dev);
  605. }
  606. static void ironlake_rps_change_irq_handler(struct drm_device *dev)
  607. {
  608. drm_i915_private_t *dev_priv = dev->dev_private;
  609. u32 busy_up, busy_down, max_avg, min_avg;
  610. u8 new_delay;
  611. spin_lock(&mchdev_lock);
  612. I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
  613. new_delay = dev_priv->ips.cur_delay;
  614. I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
  615. busy_up = I915_READ(RCPREVBSYTUPAVG);
  616. busy_down = I915_READ(RCPREVBSYTDNAVG);
  617. max_avg = I915_READ(RCBMAXAVG);
  618. min_avg = I915_READ(RCBMINAVG);
  619. /* Handle RCS change request from hw */
  620. if (busy_up > max_avg) {
  621. if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
  622. new_delay = dev_priv->ips.cur_delay - 1;
  623. if (new_delay < dev_priv->ips.max_delay)
  624. new_delay = dev_priv->ips.max_delay;
  625. } else if (busy_down < min_avg) {
  626. if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
  627. new_delay = dev_priv->ips.cur_delay + 1;
  628. if (new_delay > dev_priv->ips.min_delay)
  629. new_delay = dev_priv->ips.min_delay;
  630. }
  631. if (ironlake_set_drps(dev, new_delay))
  632. dev_priv->ips.cur_delay = new_delay;
  633. spin_unlock(&mchdev_lock);
  634. return;
  635. }
  636. static void notify_ring(struct drm_device *dev,
  637. struct intel_ring_buffer *ring)
  638. {
  639. if (ring->obj == NULL)
  640. return;
  641. trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
  642. wake_up_all(&ring->irq_queue);
  643. i915_queue_hangcheck(dev);
  644. }
  645. static void gen6_pm_rps_work(struct work_struct *work)
  646. {
  647. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  648. rps.work);
  649. u32 pm_iir;
  650. u8 new_delay;
  651. spin_lock_irq(&dev_priv->irq_lock);
  652. pm_iir = dev_priv->rps.pm_iir;
  653. dev_priv->rps.pm_iir = 0;
  654. /* Make sure not to corrupt PMIMR state used by ringbuffer code */
  655. snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
  656. spin_unlock_irq(&dev_priv->irq_lock);
  657. /* Make sure we didn't queue anything we're not going to process. */
  658. WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);
  659. if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
  660. return;
  661. mutex_lock(&dev_priv->rps.hw_lock);
  662. if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
  663. new_delay = dev_priv->rps.cur_delay + 1;
  664. /*
  665. * For better performance, jump directly
  666. * to RPe if we're below it.
  667. */
  668. if (IS_VALLEYVIEW(dev_priv->dev) &&
  669. dev_priv->rps.cur_delay < dev_priv->rps.rpe_delay)
  670. new_delay = dev_priv->rps.rpe_delay;
  671. } else
  672. new_delay = dev_priv->rps.cur_delay - 1;
  673. /* sysfs frequency interfaces may have snuck in while servicing the
  674. * interrupt
  675. */
  676. if (new_delay >= dev_priv->rps.min_delay &&
  677. new_delay <= dev_priv->rps.max_delay) {
  678. if (IS_VALLEYVIEW(dev_priv->dev))
  679. valleyview_set_rps(dev_priv->dev, new_delay);
  680. else
  681. gen6_set_rps(dev_priv->dev, new_delay);
  682. }
  683. if (IS_VALLEYVIEW(dev_priv->dev)) {
  684. /*
  685. * On VLV, when we enter RC6 we may not be at the minimum
  686. * voltage level, so arm a timer to check. It should only
  687. * fire when there's activity or once after we've entered
  688. * RC6, and then won't be re-armed until the next RPS interrupt.
  689. */
  690. mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work,
  691. msecs_to_jiffies(100));
  692. }
  693. mutex_unlock(&dev_priv->rps.hw_lock);
  694. }
  695. /**
  696. * ivybridge_parity_work - Workqueue called when a parity error interrupt
  697. * occurred.
  698. * @work: workqueue struct
  699. *
  700. * Doesn't actually do anything except notify userspace. As a consequence of
  701. * this event, userspace should try to remap the bad rows since statistically
  702. * it is likely the same row is more likely to go bad again.
  703. */
  704. static void ivybridge_parity_work(struct work_struct *work)
  705. {
  706. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  707. l3_parity.error_work);
  708. u32 error_status, row, bank, subbank;
  709. char *parity_event[5];
  710. uint32_t misccpctl;
  711. unsigned long flags;
  712. /* We must turn off DOP level clock gating to access the L3 registers.
  713. * In order to prevent a get/put style interface, acquire struct mutex
  714. * any time we access those registers.
  715. */
  716. mutex_lock(&dev_priv->dev->struct_mutex);
  717. misccpctl = I915_READ(GEN7_MISCCPCTL);
  718. I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
  719. POSTING_READ(GEN7_MISCCPCTL);
  720. error_status = I915_READ(GEN7_L3CDERRST1);
  721. row = GEN7_PARITY_ERROR_ROW(error_status);
  722. bank = GEN7_PARITY_ERROR_BANK(error_status);
  723. subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
  724. I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
  725. GEN7_L3CDERRST1_ENABLE);
  726. POSTING_READ(GEN7_L3CDERRST1);
  727. I915_WRITE(GEN7_MISCCPCTL, misccpctl);
  728. spin_lock_irqsave(&dev_priv->irq_lock, flags);
  729. ilk_enable_gt_irq(dev_priv, GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
  730. spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
  731. mutex_unlock(&dev_priv->dev->struct_mutex);
  732. parity_event[0] = I915_L3_PARITY_UEVENT "=1";
  733. parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
  734. parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
  735. parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
  736. parity_event[4] = NULL;
  737. kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
  738. KOBJ_CHANGE, parity_event);
  739. DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
  740. row, bank, subbank);
  741. kfree(parity_event[3]);
  742. kfree(parity_event[2]);
  743. kfree(parity_event[1]);
  744. }
  745. static void ivybridge_parity_error_irq_handler(struct drm_device *dev)
  746. {
  747. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  748. if (!HAS_L3_GPU_CACHE(dev))
  749. return;
  750. spin_lock(&dev_priv->irq_lock);
  751. ilk_disable_gt_irq(dev_priv, GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
  752. spin_unlock(&dev_priv->irq_lock);
  753. queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
  754. }
  755. static void ilk_gt_irq_handler(struct drm_device *dev,
  756. struct drm_i915_private *dev_priv,
  757. u32 gt_iir)
  758. {
  759. if (gt_iir &
  760. (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
  761. notify_ring(dev, &dev_priv->ring[RCS]);
  762. if (gt_iir & ILK_BSD_USER_INTERRUPT)
  763. notify_ring(dev, &dev_priv->ring[VCS]);
  764. }
  765. static void snb_gt_irq_handler(struct drm_device *dev,
  766. struct drm_i915_private *dev_priv,
  767. u32 gt_iir)
  768. {
  769. if (gt_iir &
  770. (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
  771. notify_ring(dev, &dev_priv->ring[RCS]);
  772. if (gt_iir & GT_BSD_USER_INTERRUPT)
  773. notify_ring(dev, &dev_priv->ring[VCS]);
  774. if (gt_iir & GT_BLT_USER_INTERRUPT)
  775. notify_ring(dev, &dev_priv->ring[BCS]);
  776. if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
  777. GT_BSD_CS_ERROR_INTERRUPT |
  778. GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
  779. DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
  780. i915_handle_error(dev, false);
  781. }
  782. if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
  783. ivybridge_parity_error_irq_handler(dev);
  784. }
  785. /* Legacy way of handling PM interrupts */
  786. static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv,
  787. u32 pm_iir)
  788. {
  789. /*
  790. * IIR bits should never already be set because IMR should
  791. * prevent an interrupt from being shown in IIR. The warning
  792. * displays a case where we've unsafely cleared
  793. * dev_priv->rps.pm_iir. Although missing an interrupt of the same
  794. * type is not a problem, it displays a problem in the logic.
  795. *
  796. * The mask bit in IMR is cleared by dev_priv->rps.work.
  797. */
  798. spin_lock(&dev_priv->irq_lock);
  799. dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
  800. snb_set_pm_irq(dev_priv, dev_priv->rps.pm_iir);
  801. spin_unlock(&dev_priv->irq_lock);
  802. queue_work(dev_priv->wq, &dev_priv->rps.work);
  803. }
  804. #define HPD_STORM_DETECT_PERIOD 1000
  805. #define HPD_STORM_THRESHOLD 5
  806. static inline void intel_hpd_irq_handler(struct drm_device *dev,
  807. u32 hotplug_trigger,
  808. const u32 *hpd)
  809. {
  810. drm_i915_private_t *dev_priv = dev->dev_private;
  811. int i;
  812. bool storm_detected = false;
  813. if (!hotplug_trigger)
  814. return;
  815. spin_lock(&dev_priv->irq_lock);
  816. for (i = 1; i < HPD_NUM_PINS; i++) {
  817. WARN(((hpd[i] & hotplug_trigger) &&
  818. dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED),
  819. "Received HPD interrupt although disabled\n");
  820. if (!(hpd[i] & hotplug_trigger) ||
  821. dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
  822. continue;
  823. dev_priv->hpd_event_bits |= (1 << i);
  824. if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
  825. dev_priv->hpd_stats[i].hpd_last_jiffies
  826. + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
  827. dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
  828. dev_priv->hpd_stats[i].hpd_cnt = 0;
  829. DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
  830. } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
  831. dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
  832. dev_priv->hpd_event_bits &= ~(1 << i);
  833. DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
  834. storm_detected = true;
  835. } else {
  836. dev_priv->hpd_stats[i].hpd_cnt++;
  837. DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
  838. dev_priv->hpd_stats[i].hpd_cnt);
  839. }
  840. }
  841. if (storm_detected)
  842. dev_priv->display.hpd_irq_setup(dev);
  843. spin_unlock(&dev_priv->irq_lock);
  844. queue_work(dev_priv->wq,
  845. &dev_priv->hotplug_work);
  846. }
  847. static void gmbus_irq_handler(struct drm_device *dev)
  848. {
  849. struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
  850. wake_up_all(&dev_priv->gmbus_wait_queue);
  851. }
  852. static void dp_aux_irq_handler(struct drm_device *dev)
  853. {
  854. struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
  855. wake_up_all(&dev_priv->gmbus_wait_queue);
  856. }
  857. /* Unlike gen6_rps_irq_handler() from which this function is originally derived,
  858. * we must be able to deal with other PM interrupts. This is complicated because
  859. * of the way in which we use the masks to defer the RPS work (which for
  860. * posterity is necessary because of forcewake).
  861. */
  862. static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv,
  863. u32 pm_iir)
  864. {
  865. if (pm_iir & GEN6_PM_RPS_EVENTS) {
  866. spin_lock(&dev_priv->irq_lock);
  867. dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
  868. snb_set_pm_irq(dev_priv, dev_priv->rps.pm_iir);
  869. /* never want to mask useful interrupts. */
  870. WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
  871. spin_unlock(&dev_priv->irq_lock);
  872. queue_work(dev_priv->wq, &dev_priv->rps.work);
  873. }
  874. if (pm_iir & PM_VEBOX_USER_INTERRUPT)
  875. notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
  876. if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
  877. DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
  878. i915_handle_error(dev_priv->dev, false);
  879. }
  880. }
  881. static irqreturn_t valleyview_irq_handler(int irq, void *arg)
  882. {
  883. struct drm_device *dev = (struct drm_device *) arg;
  884. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  885. u32 iir, gt_iir, pm_iir;
  886. irqreturn_t ret = IRQ_NONE;
  887. unsigned long irqflags;
  888. int pipe;
  889. u32 pipe_stats[I915_MAX_PIPES];
  890. atomic_inc(&dev_priv->irq_received);
  891. while (true) {
  892. iir = I915_READ(VLV_IIR);
  893. gt_iir = I915_READ(GTIIR);
  894. pm_iir = I915_READ(GEN6_PMIIR);
  895. if (gt_iir == 0 && pm_iir == 0 && iir == 0)
  896. goto out;
  897. ret = IRQ_HANDLED;
  898. snb_gt_irq_handler(dev, dev_priv, gt_iir);
  899. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  900. for_each_pipe(pipe) {
  901. int reg = PIPESTAT(pipe);
  902. pipe_stats[pipe] = I915_READ(reg);
  903. /*
  904. * Clear the PIPE*STAT regs before the IIR
  905. */
  906. if (pipe_stats[pipe] & 0x8000ffff) {
  907. if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  908. DRM_DEBUG_DRIVER("pipe %c underrun\n",
  909. pipe_name(pipe));
  910. I915_WRITE(reg, pipe_stats[pipe]);
  911. }
  912. }
  913. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  914. for_each_pipe(pipe) {
  915. if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
  916. drm_handle_vblank(dev, pipe);
  917. if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
  918. intel_prepare_page_flip(dev, pipe);
  919. intel_finish_page_flip(dev, pipe);
  920. }
  921. }
  922. /* Consume port. Then clear IIR or we'll miss events */
  923. if (iir & I915_DISPLAY_PORT_INTERRUPT) {
  924. u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
  925. u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
  926. DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
  927. hotplug_status);
  928. intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
  929. I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
  930. I915_READ(PORT_HOTPLUG_STAT);
  931. }
  932. if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
  933. gmbus_irq_handler(dev);
  934. if (pm_iir)
  935. gen6_rps_irq_handler(dev_priv, pm_iir);
  936. I915_WRITE(GTIIR, gt_iir);
  937. I915_WRITE(GEN6_PMIIR, pm_iir);
  938. I915_WRITE(VLV_IIR, iir);
  939. }
  940. out:
  941. return ret;
  942. }
  943. static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
  944. {
  945. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  946. int pipe;
  947. u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
  948. intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
  949. if (pch_iir & SDE_AUDIO_POWER_MASK) {
  950. int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
  951. SDE_AUDIO_POWER_SHIFT);
  952. DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
  953. port_name(port));
  954. }
  955. if (pch_iir & SDE_AUX_MASK)
  956. dp_aux_irq_handler(dev);
  957. if (pch_iir & SDE_GMBUS)
  958. gmbus_irq_handler(dev);
  959. if (pch_iir & SDE_AUDIO_HDCP_MASK)
  960. DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
  961. if (pch_iir & SDE_AUDIO_TRANS_MASK)
  962. DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
  963. if (pch_iir & SDE_POISON)
  964. DRM_ERROR("PCH poison interrupt\n");
  965. if (pch_iir & SDE_FDI_MASK)
  966. for_each_pipe(pipe)
  967. DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
  968. pipe_name(pipe),
  969. I915_READ(FDI_RX_IIR(pipe)));
  970. if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
  971. DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
  972. if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
  973. DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
  974. if (pch_iir & SDE_TRANSA_FIFO_UNDER)
  975. if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
  976. false))
  977. DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
  978. if (pch_iir & SDE_TRANSB_FIFO_UNDER)
  979. if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
  980. false))
  981. DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
  982. }
  983. static void ivb_err_int_handler(struct drm_device *dev)
  984. {
  985. struct drm_i915_private *dev_priv = dev->dev_private;
  986. u32 err_int = I915_READ(GEN7_ERR_INT);
  987. if (err_int & ERR_INT_POISON)
  988. DRM_ERROR("Poison interrupt\n");
  989. if (err_int & ERR_INT_FIFO_UNDERRUN_A)
  990. if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
  991. DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
  992. if (err_int & ERR_INT_FIFO_UNDERRUN_B)
  993. if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
  994. DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
  995. if (err_int & ERR_INT_FIFO_UNDERRUN_C)
  996. if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
  997. DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
  998. I915_WRITE(GEN7_ERR_INT, err_int);
  999. }
  1000. static void cpt_serr_int_handler(struct drm_device *dev)
  1001. {
  1002. struct drm_i915_private *dev_priv = dev->dev_private;
  1003. u32 serr_int = I915_READ(SERR_INT);
  1004. if (serr_int & SERR_INT_POISON)
  1005. DRM_ERROR("PCH poison interrupt\n");
  1006. if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
  1007. if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
  1008. false))
  1009. DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
  1010. if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
  1011. if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
  1012. false))
  1013. DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
  1014. if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
  1015. if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
  1016. false))
  1017. DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
  1018. I915_WRITE(SERR_INT, serr_int);
  1019. }
  1020. static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
  1021. {
  1022. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1023. int pipe;
  1024. u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
  1025. intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
  1026. if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
  1027. int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
  1028. SDE_AUDIO_POWER_SHIFT_CPT);
  1029. DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
  1030. port_name(port));
  1031. }
  1032. if (pch_iir & SDE_AUX_MASK_CPT)
  1033. dp_aux_irq_handler(dev);
  1034. if (pch_iir & SDE_GMBUS_CPT)
  1035. gmbus_irq_handler(dev);
  1036. if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
  1037. DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
  1038. if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
  1039. DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
  1040. if (pch_iir & SDE_FDI_MASK_CPT)
  1041. for_each_pipe(pipe)
  1042. DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
  1043. pipe_name(pipe),
  1044. I915_READ(FDI_RX_IIR(pipe)));
  1045. if (pch_iir & SDE_ERROR_CPT)
  1046. cpt_serr_int_handler(dev);
  1047. }
  1048. static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
  1049. {
  1050. struct drm_i915_private *dev_priv = dev->dev_private;
  1051. if (de_iir & DE_AUX_CHANNEL_A)
  1052. dp_aux_irq_handler(dev);
  1053. if (de_iir & DE_GSE)
  1054. intel_opregion_asle_intr(dev);
  1055. if (de_iir & DE_PIPEA_VBLANK)
  1056. drm_handle_vblank(dev, 0);
  1057. if (de_iir & DE_PIPEB_VBLANK)
  1058. drm_handle_vblank(dev, 1);
  1059. if (de_iir & DE_POISON)
  1060. DRM_ERROR("Poison interrupt\n");
  1061. if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
  1062. if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
  1063. DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
  1064. if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
  1065. if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
  1066. DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
  1067. if (de_iir & DE_PLANEA_FLIP_DONE) {
  1068. intel_prepare_page_flip(dev, 0);
  1069. intel_finish_page_flip_plane(dev, 0);
  1070. }
  1071. if (de_iir & DE_PLANEB_FLIP_DONE) {
  1072. intel_prepare_page_flip(dev, 1);
  1073. intel_finish_page_flip_plane(dev, 1);
  1074. }
  1075. /* check event from PCH */
  1076. if (de_iir & DE_PCH_EVENT) {
  1077. u32 pch_iir = I915_READ(SDEIIR);
  1078. if (HAS_PCH_CPT(dev))
  1079. cpt_irq_handler(dev, pch_iir);
  1080. else
  1081. ibx_irq_handler(dev, pch_iir);
  1082. /* should clear PCH hotplug event before clear CPU irq */
  1083. I915_WRITE(SDEIIR, pch_iir);
  1084. }
  1085. if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
  1086. ironlake_rps_change_irq_handler(dev);
  1087. }
  1088. static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
  1089. {
  1090. struct drm_i915_private *dev_priv = dev->dev_private;
  1091. int i;
  1092. if (de_iir & DE_ERR_INT_IVB)
  1093. ivb_err_int_handler(dev);
  1094. if (de_iir & DE_AUX_CHANNEL_A_IVB)
  1095. dp_aux_irq_handler(dev);
  1096. if (de_iir & DE_GSE_IVB)
  1097. intel_opregion_asle_intr(dev);
  1098. for (i = 0; i < 3; i++) {
  1099. if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
  1100. drm_handle_vblank(dev, i);
  1101. if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
  1102. intel_prepare_page_flip(dev, i);
  1103. intel_finish_page_flip_plane(dev, i);
  1104. }
  1105. }
  1106. /* check event from PCH */
  1107. if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
  1108. u32 pch_iir = I915_READ(SDEIIR);
  1109. cpt_irq_handler(dev, pch_iir);
  1110. /* clear PCH hotplug event before clear CPU irq */
  1111. I915_WRITE(SDEIIR, pch_iir);
  1112. }
  1113. }
  1114. static irqreturn_t ironlake_irq_handler(int irq, void *arg)
  1115. {
  1116. struct drm_device *dev = (struct drm_device *) arg;
  1117. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1118. u32 de_iir, gt_iir, de_ier, sde_ier = 0;
  1119. irqreturn_t ret = IRQ_NONE;
  1120. bool err_int_reenable = false;
  1121. atomic_inc(&dev_priv->irq_received);
  1122. /* We get interrupts on unclaimed registers, so check for this before we
  1123. * do any I915_{READ,WRITE}. */
  1124. intel_uncore_check_errors(dev);
  1125. /* disable master interrupt before clearing iir */
  1126. de_ier = I915_READ(DEIER);
  1127. I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
  1128. POSTING_READ(DEIER);
  1129. /* Disable south interrupts. We'll only write to SDEIIR once, so further
  1130. * interrupts will will be stored on its back queue, and then we'll be
  1131. * able to process them after we restore SDEIER (as soon as we restore
  1132. * it, we'll get an interrupt if SDEIIR still has something to process
  1133. * due to its back queue). */
  1134. if (!HAS_PCH_NOP(dev)) {
  1135. sde_ier = I915_READ(SDEIER);
  1136. I915_WRITE(SDEIER, 0);
  1137. POSTING_READ(SDEIER);
  1138. }
  1139. /* On Haswell, also mask ERR_INT because we don't want to risk
  1140. * generating "unclaimed register" interrupts from inside the interrupt
  1141. * handler. */
  1142. if (IS_HASWELL(dev)) {
  1143. spin_lock(&dev_priv->irq_lock);
  1144. err_int_reenable = ~dev_priv->irq_mask & DE_ERR_INT_IVB;
  1145. if (err_int_reenable)
  1146. ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
  1147. spin_unlock(&dev_priv->irq_lock);
  1148. }
  1149. gt_iir = I915_READ(GTIIR);
  1150. if (gt_iir) {
  1151. if (INTEL_INFO(dev)->gen >= 6)
  1152. snb_gt_irq_handler(dev, dev_priv, gt_iir);
  1153. else
  1154. ilk_gt_irq_handler(dev, dev_priv, gt_iir);
  1155. I915_WRITE(GTIIR, gt_iir);
  1156. ret = IRQ_HANDLED;
  1157. }
  1158. de_iir = I915_READ(DEIIR);
  1159. if (de_iir) {
  1160. if (INTEL_INFO(dev)->gen >= 7)
  1161. ivb_display_irq_handler(dev, de_iir);
  1162. else
  1163. ilk_display_irq_handler(dev, de_iir);
  1164. I915_WRITE(DEIIR, de_iir);
  1165. ret = IRQ_HANDLED;
  1166. }
  1167. if (INTEL_INFO(dev)->gen >= 6) {
  1168. u32 pm_iir = I915_READ(GEN6_PMIIR);
  1169. if (pm_iir) {
  1170. if (IS_HASWELL(dev))
  1171. hsw_pm_irq_handler(dev_priv, pm_iir);
  1172. else
  1173. gen6_rps_irq_handler(dev_priv, pm_iir);
  1174. I915_WRITE(GEN6_PMIIR, pm_iir);
  1175. ret = IRQ_HANDLED;
  1176. }
  1177. }
  1178. if (err_int_reenable) {
  1179. spin_lock(&dev_priv->irq_lock);
  1180. if (ivb_can_enable_err_int(dev))
  1181. ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
  1182. spin_unlock(&dev_priv->irq_lock);
  1183. }
  1184. I915_WRITE(DEIER, de_ier);
  1185. POSTING_READ(DEIER);
  1186. if (!HAS_PCH_NOP(dev)) {
  1187. I915_WRITE(SDEIER, sde_ier);
  1188. POSTING_READ(SDEIER);
  1189. }
  1190. return ret;
  1191. }
  1192. /**
  1193. * i915_error_work_func - do process context error handling work
  1194. * @work: work struct
  1195. *
  1196. * Fire an error uevent so userspace can see that a hang or error
  1197. * was detected.
  1198. */
  1199. static void i915_error_work_func(struct work_struct *work)
  1200. {
  1201. struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
  1202. work);
  1203. drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
  1204. gpu_error);
  1205. struct drm_device *dev = dev_priv->dev;
  1206. struct intel_ring_buffer *ring;
  1207. char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
  1208. char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
  1209. char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
  1210. int i, ret;
  1211. kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
  1212. /*
  1213. * Note that there's only one work item which does gpu resets, so we
  1214. * need not worry about concurrent gpu resets potentially incrementing
  1215. * error->reset_counter twice. We only need to take care of another
  1216. * racing irq/hangcheck declaring the gpu dead for a second time. A
  1217. * quick check for that is good enough: schedule_work ensures the
  1218. * correct ordering between hang detection and this work item, and since
  1219. * the reset in-progress bit is only ever set by code outside of this
  1220. * work we don't need to worry about any other races.
  1221. */
  1222. if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
  1223. DRM_DEBUG_DRIVER("resetting chip\n");
  1224. kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
  1225. reset_event);
  1226. ret = i915_reset(dev);
  1227. if (ret == 0) {
  1228. /*
  1229. * After all the gem state is reset, increment the reset
  1230. * counter and wake up everyone waiting for the reset to
  1231. * complete.
  1232. *
  1233. * Since unlock operations are a one-sided barrier only,
  1234. * we need to insert a barrier here to order any seqno
  1235. * updates before
  1236. * the counter increment.
  1237. */
  1238. smp_mb__before_atomic_inc();
  1239. atomic_inc(&dev_priv->gpu_error.reset_counter);
  1240. kobject_uevent_env(&dev->primary->kdev.kobj,
  1241. KOBJ_CHANGE, reset_done_event);
  1242. } else {
  1243. atomic_set(&error->reset_counter, I915_WEDGED);
  1244. }
  1245. for_each_ring(ring, dev_priv, i)
  1246. wake_up_all(&ring->irq_queue);
  1247. intel_display_handle_reset(dev);
  1248. wake_up_all(&dev_priv->gpu_error.reset_queue);
  1249. }
  1250. }
  1251. static void i915_report_and_clear_eir(struct drm_device *dev)
  1252. {
  1253. struct drm_i915_private *dev_priv = dev->dev_private;
  1254. uint32_t instdone[I915_NUM_INSTDONE_REG];
  1255. u32 eir = I915_READ(EIR);
  1256. int pipe, i;
  1257. if (!eir)
  1258. return;
  1259. pr_err("render error detected, EIR: 0x%08x\n", eir);
  1260. i915_get_extra_instdone(dev, instdone);
  1261. if (IS_G4X(dev)) {
  1262. if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
  1263. u32 ipeir = I915_READ(IPEIR_I965);
  1264. pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
  1265. pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
  1266. for (i = 0; i < ARRAY_SIZE(instdone); i++)
  1267. pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
  1268. pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
  1269. pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
  1270. I915_WRITE(IPEIR_I965, ipeir);
  1271. POSTING_READ(IPEIR_I965);
  1272. }
  1273. if (eir & GM45_ERROR_PAGE_TABLE) {
  1274. u32 pgtbl_err = I915_READ(PGTBL_ER);
  1275. pr_err("page table error\n");
  1276. pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
  1277. I915_WRITE(PGTBL_ER, pgtbl_err);
  1278. POSTING_READ(PGTBL_ER);
  1279. }
  1280. }
  1281. if (!IS_GEN2(dev)) {
  1282. if (eir & I915_ERROR_PAGE_TABLE) {
  1283. u32 pgtbl_err = I915_READ(PGTBL_ER);
  1284. pr_err("page table error\n");
  1285. pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
  1286. I915_WRITE(PGTBL_ER, pgtbl_err);
  1287. POSTING_READ(PGTBL_ER);
  1288. }
  1289. }
  1290. if (eir & I915_ERROR_MEMORY_REFRESH) {
  1291. pr_err("memory refresh error:\n");
  1292. for_each_pipe(pipe)
  1293. pr_err("pipe %c stat: 0x%08x\n",
  1294. pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
  1295. /* pipestat has already been acked */
  1296. }
  1297. if (eir & I915_ERROR_INSTRUCTION) {
  1298. pr_err("instruction error\n");
  1299. pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
  1300. for (i = 0; i < ARRAY_SIZE(instdone); i++)
  1301. pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
  1302. if (INTEL_INFO(dev)->gen < 4) {
  1303. u32 ipeir = I915_READ(IPEIR);
  1304. pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
  1305. pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
  1306. pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
  1307. I915_WRITE(IPEIR, ipeir);
  1308. POSTING_READ(IPEIR);
  1309. } else {
  1310. u32 ipeir = I915_READ(IPEIR_I965);
  1311. pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
  1312. pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
  1313. pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
  1314. pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
  1315. I915_WRITE(IPEIR_I965, ipeir);
  1316. POSTING_READ(IPEIR_I965);
  1317. }
  1318. }
  1319. I915_WRITE(EIR, eir);
  1320. POSTING_READ(EIR);
  1321. eir = I915_READ(EIR);
  1322. if (eir) {
  1323. /*
  1324. * some errors might have become stuck,
  1325. * mask them.
  1326. */
  1327. DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
  1328. I915_WRITE(EMR, I915_READ(EMR) | eir);
  1329. I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  1330. }
  1331. }
  1332. /**
  1333. * i915_handle_error - handle an error interrupt
  1334. * @dev: drm device
  1335. *
  1336. * Do some basic checking of regsiter state at error interrupt time and
  1337. * dump it to the syslog. Also call i915_capture_error_state() to make
  1338. * sure we get a record and make it available in debugfs. Fire a uevent
  1339. * so userspace knows something bad happened (should trigger collection
  1340. * of a ring dump etc.).
  1341. */
  1342. void i915_handle_error(struct drm_device *dev, bool wedged)
  1343. {
  1344. struct drm_i915_private *dev_priv = dev->dev_private;
  1345. struct intel_ring_buffer *ring;
  1346. int i;
  1347. i915_capture_error_state(dev);
  1348. i915_report_and_clear_eir(dev);
  1349. if (wedged) {
  1350. atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
  1351. &dev_priv->gpu_error.reset_counter);
  1352. /*
  1353. * Wakeup waiting processes so that the reset work item
  1354. * doesn't deadlock trying to grab various locks.
  1355. */
  1356. for_each_ring(ring, dev_priv, i)
  1357. wake_up_all(&ring->irq_queue);
  1358. }
  1359. queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
  1360. }
  1361. static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
  1362. {
  1363. drm_i915_private_t *dev_priv = dev->dev_private;
  1364. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  1365. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1366. struct drm_i915_gem_object *obj;
  1367. struct intel_unpin_work *work;
  1368. unsigned long flags;
  1369. bool stall_detected;
  1370. /* Ignore early vblank irqs */
  1371. if (intel_crtc == NULL)
  1372. return;
  1373. spin_lock_irqsave(&dev->event_lock, flags);
  1374. work = intel_crtc->unpin_work;
  1375. if (work == NULL ||
  1376. atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
  1377. !work->enable_stall_check) {
  1378. /* Either the pending flip IRQ arrived, or we're too early. Don't check */
  1379. spin_unlock_irqrestore(&dev->event_lock, flags);
  1380. return;
  1381. }
  1382. /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
  1383. obj = work->pending_flip_obj;
  1384. if (INTEL_INFO(dev)->gen >= 4) {
  1385. int dspsurf = DSPSURF(intel_crtc->plane);
  1386. stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
  1387. i915_gem_obj_ggtt_offset(obj);
  1388. } else {
  1389. int dspaddr = DSPADDR(intel_crtc->plane);
  1390. stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
  1391. crtc->y * crtc->fb->pitches[0] +
  1392. crtc->x * crtc->fb->bits_per_pixel/8);
  1393. }
  1394. spin_unlock_irqrestore(&dev->event_lock, flags);
  1395. if (stall_detected) {
  1396. DRM_DEBUG_DRIVER("Pageflip stall detected\n");
  1397. intel_prepare_page_flip(dev, intel_crtc->plane);
  1398. }
  1399. }
  1400. /* Called from drm generic code, passed 'crtc' which
  1401. * we use as a pipe index
  1402. */
  1403. static int i915_enable_vblank(struct drm_device *dev, int pipe)
  1404. {
  1405. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1406. unsigned long irqflags;
  1407. if (!i915_pipe_enabled(dev, pipe))
  1408. return -EINVAL;
  1409. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1410. if (INTEL_INFO(dev)->gen >= 4)
  1411. i915_enable_pipestat(dev_priv, pipe,
  1412. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1413. else
  1414. i915_enable_pipestat(dev_priv, pipe,
  1415. PIPE_VBLANK_INTERRUPT_ENABLE);
  1416. /* maintain vblank delivery even in deep C-states */
  1417. if (dev_priv->info->gen == 3)
  1418. I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
  1419. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1420. return 0;
  1421. }
  1422. static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
  1423. {
  1424. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1425. unsigned long irqflags;
  1426. uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
  1427. DE_PIPE_VBLANK_ILK(pipe);
  1428. if (!i915_pipe_enabled(dev, pipe))
  1429. return -EINVAL;
  1430. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1431. ironlake_enable_display_irq(dev_priv, bit);
  1432. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1433. return 0;
  1434. }
  1435. static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
  1436. {
  1437. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1438. unsigned long irqflags;
  1439. u32 imr;
  1440. if (!i915_pipe_enabled(dev, pipe))
  1441. return -EINVAL;
  1442. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1443. imr = I915_READ(VLV_IMR);
  1444. if (pipe == 0)
  1445. imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
  1446. else
  1447. imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  1448. I915_WRITE(VLV_IMR, imr);
  1449. i915_enable_pipestat(dev_priv, pipe,
  1450. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1451. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1452. return 0;
  1453. }
  1454. /* Called from drm generic code, passed 'crtc' which
  1455. * we use as a pipe index
  1456. */
  1457. static void i915_disable_vblank(struct drm_device *dev, int pipe)
  1458. {
  1459. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1460. unsigned long irqflags;
  1461. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1462. if (dev_priv->info->gen == 3)
  1463. I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
  1464. i915_disable_pipestat(dev_priv, pipe,
  1465. PIPE_VBLANK_INTERRUPT_ENABLE |
  1466. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1467. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1468. }
  1469. static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
  1470. {
  1471. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1472. unsigned long irqflags;
  1473. uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
  1474. DE_PIPE_VBLANK_ILK(pipe);
  1475. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1476. ironlake_disable_display_irq(dev_priv, bit);
  1477. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1478. }
  1479. static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
  1480. {
  1481. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1482. unsigned long irqflags;
  1483. u32 imr;
  1484. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1485. i915_disable_pipestat(dev_priv, pipe,
  1486. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1487. imr = I915_READ(VLV_IMR);
  1488. if (pipe == 0)
  1489. imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
  1490. else
  1491. imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  1492. I915_WRITE(VLV_IMR, imr);
  1493. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1494. }
  1495. static u32
  1496. ring_last_seqno(struct intel_ring_buffer *ring)
  1497. {
  1498. return list_entry(ring->request_list.prev,
  1499. struct drm_i915_gem_request, list)->seqno;
  1500. }
  1501. static bool
  1502. ring_idle(struct intel_ring_buffer *ring, u32 seqno)
  1503. {
  1504. return (list_empty(&ring->request_list) ||
  1505. i915_seqno_passed(seqno, ring_last_seqno(ring)));
  1506. }
  1507. static struct intel_ring_buffer *
  1508. semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
  1509. {
  1510. struct drm_i915_private *dev_priv = ring->dev->dev_private;
  1511. u32 cmd, ipehr, acthd, acthd_min;
  1512. ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
  1513. if ((ipehr & ~(0x3 << 16)) !=
  1514. (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
  1515. return NULL;
  1516. /* ACTHD is likely pointing to the dword after the actual command,
  1517. * so scan backwards until we find the MBOX.
  1518. */
  1519. acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
  1520. acthd_min = max((int)acthd - 3 * 4, 0);
  1521. do {
  1522. cmd = ioread32(ring->virtual_start + acthd);
  1523. if (cmd == ipehr)
  1524. break;
  1525. acthd -= 4;
  1526. if (acthd < acthd_min)
  1527. return NULL;
  1528. } while (1);
  1529. *seqno = ioread32(ring->virtual_start+acthd+4)+1;
  1530. return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
  1531. }
  1532. static int semaphore_passed(struct intel_ring_buffer *ring)
  1533. {
  1534. struct drm_i915_private *dev_priv = ring->dev->dev_private;
  1535. struct intel_ring_buffer *signaller;
  1536. u32 seqno, ctl;
  1537. ring->hangcheck.deadlock = true;
  1538. signaller = semaphore_waits_for(ring, &seqno);
  1539. if (signaller == NULL || signaller->hangcheck.deadlock)
  1540. return -1;
  1541. /* cursory check for an unkickable deadlock */
  1542. ctl = I915_READ_CTL(signaller);
  1543. if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
  1544. return -1;
  1545. return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
  1546. }
  1547. static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
  1548. {
  1549. struct intel_ring_buffer *ring;
  1550. int i;
  1551. for_each_ring(ring, dev_priv, i)
  1552. ring->hangcheck.deadlock = false;
  1553. }
  1554. static enum intel_ring_hangcheck_action
  1555. ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
  1556. {
  1557. struct drm_device *dev = ring->dev;
  1558. struct drm_i915_private *dev_priv = dev->dev_private;
  1559. u32 tmp;
  1560. if (ring->hangcheck.acthd != acthd)
  1561. return HANGCHECK_ACTIVE;
  1562. if (IS_GEN2(dev))
  1563. return HANGCHECK_HUNG;
  1564. /* Is the chip hanging on a WAIT_FOR_EVENT?
  1565. * If so we can simply poke the RB_WAIT bit
  1566. * and break the hang. This should work on
  1567. * all but the second generation chipsets.
  1568. */
  1569. tmp = I915_READ_CTL(ring);
  1570. if (tmp & RING_WAIT) {
  1571. DRM_ERROR("Kicking stuck wait on %s\n",
  1572. ring->name);
  1573. I915_WRITE_CTL(ring, tmp);
  1574. return HANGCHECK_KICK;
  1575. }
  1576. if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
  1577. switch (semaphore_passed(ring)) {
  1578. default:
  1579. return HANGCHECK_HUNG;
  1580. case 1:
  1581. DRM_ERROR("Kicking stuck semaphore on %s\n",
  1582. ring->name);
  1583. I915_WRITE_CTL(ring, tmp);
  1584. return HANGCHECK_KICK;
  1585. case 0:
  1586. return HANGCHECK_WAIT;
  1587. }
  1588. }
  1589. return HANGCHECK_HUNG;
  1590. }
  1591. /**
  1592. * This is called when the chip hasn't reported back with completed
  1593. * batchbuffers in a long time. We keep track per ring seqno progress and
  1594. * if there are no progress, hangcheck score for that ring is increased.
  1595. * Further, acthd is inspected to see if the ring is stuck. On stuck case
  1596. * we kick the ring. If we see no progress on three subsequent calls
  1597. * we assume chip is wedged and try to fix it by resetting the chip.
  1598. */
  1599. static void i915_hangcheck_elapsed(unsigned long data)
  1600. {
  1601. struct drm_device *dev = (struct drm_device *)data;
  1602. drm_i915_private_t *dev_priv = dev->dev_private;
  1603. struct intel_ring_buffer *ring;
  1604. int i;
  1605. int busy_count = 0, rings_hung = 0;
  1606. bool stuck[I915_NUM_RINGS] = { 0 };
  1607. #define BUSY 1
  1608. #define KICK 5
  1609. #define HUNG 20
  1610. #define FIRE 30
  1611. if (!i915_enable_hangcheck)
  1612. return;
  1613. for_each_ring(ring, dev_priv, i) {
  1614. u32 seqno, acthd;
  1615. bool busy = true;
  1616. semaphore_clear_deadlocks(dev_priv);
  1617. seqno = ring->get_seqno(ring, false);
  1618. acthd = intel_ring_get_active_head(ring);
  1619. if (ring->hangcheck.seqno == seqno) {
  1620. if (ring_idle(ring, seqno)) {
  1621. if (waitqueue_active(&ring->irq_queue)) {
  1622. /* Issue a wake-up to catch stuck h/w. */
  1623. DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
  1624. ring->name);
  1625. wake_up_all(&ring->irq_queue);
  1626. ring->hangcheck.score += HUNG;
  1627. } else
  1628. busy = false;
  1629. } else {
  1630. /* We always increment the hangcheck score
  1631. * if the ring is busy and still processing
  1632. * the same request, so that no single request
  1633. * can run indefinitely (such as a chain of
  1634. * batches). The only time we do not increment
  1635. * the hangcheck score on this ring, if this
  1636. * ring is in a legitimate wait for another
  1637. * ring. In that case the waiting ring is a
  1638. * victim and we want to be sure we catch the
  1639. * right culprit. Then every time we do kick
  1640. * the ring, add a small increment to the
  1641. * score so that we can catch a batch that is
  1642. * being repeatedly kicked and so responsible
  1643. * for stalling the machine.
  1644. */
  1645. ring->hangcheck.action = ring_stuck(ring,
  1646. acthd);
  1647. switch (ring->hangcheck.action) {
  1648. case HANGCHECK_WAIT:
  1649. break;
  1650. case HANGCHECK_ACTIVE:
  1651. ring->hangcheck.score += BUSY;
  1652. break;
  1653. case HANGCHECK_KICK:
  1654. ring->hangcheck.score += KICK;
  1655. break;
  1656. case HANGCHECK_HUNG:
  1657. ring->hangcheck.score += HUNG;
  1658. stuck[i] = true;
  1659. break;
  1660. }
  1661. }
  1662. } else {
  1663. /* Gradually reduce the count so that we catch DoS
  1664. * attempts across multiple batches.
  1665. */
  1666. if (ring->hangcheck.score > 0)
  1667. ring->hangcheck.score--;
  1668. }
  1669. ring->hangcheck.seqno = seqno;
  1670. ring->hangcheck.acthd = acthd;
  1671. busy_count += busy;
  1672. }
  1673. for_each_ring(ring, dev_priv, i) {
  1674. if (ring->hangcheck.score > FIRE) {
  1675. DRM_ERROR("%s on %s\n",
  1676. stuck[i] ? "stuck" : "no progress",
  1677. ring->name);
  1678. rings_hung++;
  1679. }
  1680. }
  1681. if (rings_hung)
  1682. return i915_handle_error(dev, true);
  1683. if (busy_count)
  1684. /* Reset timer case chip hangs without another request
  1685. * being added */
  1686. i915_queue_hangcheck(dev);
  1687. }
  1688. void i915_queue_hangcheck(struct drm_device *dev)
  1689. {
  1690. struct drm_i915_private *dev_priv = dev->dev_private;
  1691. if (!i915_enable_hangcheck)
  1692. return;
  1693. mod_timer(&dev_priv->gpu_error.hangcheck_timer,
  1694. round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
  1695. }
  1696. static void ibx_irq_preinstall(struct drm_device *dev)
  1697. {
  1698. struct drm_i915_private *dev_priv = dev->dev_private;
  1699. if (HAS_PCH_NOP(dev))
  1700. return;
  1701. /* south display irq */
  1702. I915_WRITE(SDEIMR, 0xffffffff);
  1703. /*
  1704. * SDEIER is also touched by the interrupt handler to work around missed
  1705. * PCH interrupts. Hence we can't update it after the interrupt handler
  1706. * is enabled - instead we unconditionally enable all PCH interrupt
  1707. * sources here, but then only unmask them as needed with SDEIMR.
  1708. */
  1709. I915_WRITE(SDEIER, 0xffffffff);
  1710. POSTING_READ(SDEIER);
  1711. }
  1712. static void gen5_gt_irq_preinstall(struct drm_device *dev)
  1713. {
  1714. struct drm_i915_private *dev_priv = dev->dev_private;
  1715. /* and GT */
  1716. I915_WRITE(GTIMR, 0xffffffff);
  1717. I915_WRITE(GTIER, 0x0);
  1718. POSTING_READ(GTIER);
  1719. if (INTEL_INFO(dev)->gen >= 6) {
  1720. /* and PM */
  1721. I915_WRITE(GEN6_PMIMR, 0xffffffff);
  1722. I915_WRITE(GEN6_PMIER, 0x0);
  1723. POSTING_READ(GEN6_PMIER);
  1724. }
  1725. }
  1726. /* drm_dma.h hooks
  1727. */
  1728. static void ironlake_irq_preinstall(struct drm_device *dev)
  1729. {
  1730. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1731. atomic_set(&dev_priv->irq_received, 0);
  1732. I915_WRITE(HWSTAM, 0xeffe);
  1733. I915_WRITE(DEIMR, 0xffffffff);
  1734. I915_WRITE(DEIER, 0x0);
  1735. POSTING_READ(DEIER);
  1736. gen5_gt_irq_preinstall(dev);
  1737. ibx_irq_preinstall(dev);
  1738. }
  1739. static void valleyview_irq_preinstall(struct drm_device *dev)
  1740. {
  1741. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1742. int pipe;
  1743. atomic_set(&dev_priv->irq_received, 0);
  1744. /* VLV magic */
  1745. I915_WRITE(VLV_IMR, 0);
  1746. I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
  1747. I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
  1748. I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
  1749. /* and GT */
  1750. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1751. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1752. gen5_gt_irq_preinstall(dev);
  1753. I915_WRITE(DPINVGTT, 0xff);
  1754. I915_WRITE(PORT_HOTPLUG_EN, 0);
  1755. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  1756. for_each_pipe(pipe)
  1757. I915_WRITE(PIPESTAT(pipe), 0xffff);
  1758. I915_WRITE(VLV_IIR, 0xffffffff);
  1759. I915_WRITE(VLV_IMR, 0xffffffff);
  1760. I915_WRITE(VLV_IER, 0x0);
  1761. POSTING_READ(VLV_IER);
  1762. }
  1763. static void ibx_hpd_irq_setup(struct drm_device *dev)
  1764. {
  1765. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1766. struct drm_mode_config *mode_config = &dev->mode_config;
  1767. struct intel_encoder *intel_encoder;
  1768. u32 hotplug_irqs, hotplug, enabled_irqs = 0;
  1769. if (HAS_PCH_IBX(dev)) {
  1770. hotplug_irqs = SDE_HOTPLUG_MASK;
  1771. list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
  1772. if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
  1773. enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
  1774. } else {
  1775. hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
  1776. list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
  1777. if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
  1778. enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
  1779. }
  1780. ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
  1781. /*
  1782. * Enable digital hotplug on the PCH, and configure the DP short pulse
  1783. * duration to 2ms (which is the minimum in the Display Port spec)
  1784. *
  1785. * This register is the same on all known PCH chips.
  1786. */
  1787. hotplug = I915_READ(PCH_PORT_HOTPLUG);
  1788. hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
  1789. hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
  1790. hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
  1791. hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
  1792. I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
  1793. }
  1794. static void ibx_irq_postinstall(struct drm_device *dev)
  1795. {
  1796. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1797. u32 mask;
  1798. if (HAS_PCH_NOP(dev))
  1799. return;
  1800. if (HAS_PCH_IBX(dev)) {
  1801. mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
  1802. SDE_TRANSA_FIFO_UNDER | SDE_POISON;
  1803. } else {
  1804. mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
  1805. I915_WRITE(SERR_INT, I915_READ(SERR_INT));
  1806. }
  1807. I915_WRITE(SDEIIR, I915_READ(SDEIIR));
  1808. I915_WRITE(SDEIMR, ~mask);
  1809. }
  1810. static void gen5_gt_irq_postinstall(struct drm_device *dev)
  1811. {
  1812. struct drm_i915_private *dev_priv = dev->dev_private;
  1813. u32 pm_irqs, gt_irqs;
  1814. pm_irqs = gt_irqs = 0;
  1815. dev_priv->gt_irq_mask = ~0;
  1816. if (HAS_L3_GPU_CACHE(dev)) {
  1817. /* L3 parity interrupt is always unmasked. */
  1818. dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
  1819. gt_irqs |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
  1820. }
  1821. gt_irqs |= GT_RENDER_USER_INTERRUPT;
  1822. if (IS_GEN5(dev)) {
  1823. gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
  1824. ILK_BSD_USER_INTERRUPT;
  1825. } else {
  1826. gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
  1827. }
  1828. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1829. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  1830. I915_WRITE(GTIER, gt_irqs);
  1831. POSTING_READ(GTIER);
  1832. if (INTEL_INFO(dev)->gen >= 6) {
  1833. pm_irqs |= GEN6_PM_RPS_EVENTS;
  1834. if (HAS_VEBOX(dev))
  1835. pm_irqs |= PM_VEBOX_USER_INTERRUPT;
  1836. dev_priv->pm_irq_mask = 0xffffffff;
  1837. I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
  1838. I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
  1839. I915_WRITE(GEN6_PMIER, pm_irqs);
  1840. POSTING_READ(GEN6_PMIER);
  1841. }
  1842. }
  1843. static int ironlake_irq_postinstall(struct drm_device *dev)
  1844. {
  1845. unsigned long irqflags;
  1846. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1847. u32 display_mask, extra_mask;
  1848. if (INTEL_INFO(dev)->gen >= 7) {
  1849. display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
  1850. DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
  1851. DE_PLANEB_FLIP_DONE_IVB |
  1852. DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
  1853. DE_ERR_INT_IVB);
  1854. extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
  1855. DE_PIPEA_VBLANK_IVB);
  1856. I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
  1857. } else {
  1858. display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
  1859. DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
  1860. DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
  1861. DE_PIPEA_FIFO_UNDERRUN | DE_POISON);
  1862. extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
  1863. }
  1864. dev_priv->irq_mask = ~display_mask;
  1865. /* should always can generate irq */
  1866. I915_WRITE(DEIIR, I915_READ(DEIIR));
  1867. I915_WRITE(DEIMR, dev_priv->irq_mask);
  1868. I915_WRITE(DEIER, display_mask | extra_mask);
  1869. POSTING_READ(DEIER);
  1870. gen5_gt_irq_postinstall(dev);
  1871. ibx_irq_postinstall(dev);
  1872. if (IS_IRONLAKE_M(dev)) {
  1873. /* Enable PCU event interrupts
  1874. *
  1875. * spinlocking not required here for correctness since interrupt
  1876. * setup is guaranteed to run in single-threaded context. But we
  1877. * need it to make the assert_spin_locked happy. */
  1878. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1879. ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
  1880. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1881. }
  1882. return 0;
  1883. }
  1884. static int valleyview_irq_postinstall(struct drm_device *dev)
  1885. {
  1886. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1887. u32 enable_mask;
  1888. u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
  1889. unsigned long irqflags;
  1890. enable_mask = I915_DISPLAY_PORT_INTERRUPT;
  1891. enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  1892. I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
  1893. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  1894. I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  1895. /*
  1896. *Leave vblank interrupts masked initially. enable/disable will
  1897. * toggle them based on usage.
  1898. */
  1899. dev_priv->irq_mask = (~enable_mask) |
  1900. I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
  1901. I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  1902. I915_WRITE(PORT_HOTPLUG_EN, 0);
  1903. POSTING_READ(PORT_HOTPLUG_EN);
  1904. I915_WRITE(VLV_IMR, dev_priv->irq_mask);
  1905. I915_WRITE(VLV_IER, enable_mask);
  1906. I915_WRITE(VLV_IIR, 0xffffffff);
  1907. I915_WRITE(PIPESTAT(0), 0xffff);
  1908. I915_WRITE(PIPESTAT(1), 0xffff);
  1909. POSTING_READ(VLV_IER);
  1910. /* Interrupt setup is already guaranteed to be single-threaded, this is
  1911. * just to make the assert_spin_locked check happy. */
  1912. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1913. i915_enable_pipestat(dev_priv, 0, pipestat_enable);
  1914. i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
  1915. i915_enable_pipestat(dev_priv, 1, pipestat_enable);
  1916. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1917. I915_WRITE(VLV_IIR, 0xffffffff);
  1918. I915_WRITE(VLV_IIR, 0xffffffff);
  1919. gen5_gt_irq_postinstall(dev);
  1920. /* ack & enable invalid PTE error interrupts */
  1921. #if 0 /* FIXME: add support to irq handler for checking these bits */
  1922. I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
  1923. I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
  1924. #endif
  1925. I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
  1926. return 0;
  1927. }
  1928. static void valleyview_irq_uninstall(struct drm_device *dev)
  1929. {
  1930. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1931. int pipe;
  1932. if (!dev_priv)
  1933. return;
  1934. del_timer_sync(&dev_priv->hotplug_reenable_timer);
  1935. for_each_pipe(pipe)
  1936. I915_WRITE(PIPESTAT(pipe), 0xffff);
  1937. I915_WRITE(HWSTAM, 0xffffffff);
  1938. I915_WRITE(PORT_HOTPLUG_EN, 0);
  1939. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  1940. for_each_pipe(pipe)
  1941. I915_WRITE(PIPESTAT(pipe), 0xffff);
  1942. I915_WRITE(VLV_IIR, 0xffffffff);
  1943. I915_WRITE(VLV_IMR, 0xffffffff);
  1944. I915_WRITE(VLV_IER, 0x0);
  1945. POSTING_READ(VLV_IER);
  1946. }
  1947. static void ironlake_irq_uninstall(struct drm_device *dev)
  1948. {
  1949. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1950. if (!dev_priv)
  1951. return;
  1952. del_timer_sync(&dev_priv->hotplug_reenable_timer);
  1953. I915_WRITE(HWSTAM, 0xffffffff);
  1954. I915_WRITE(DEIMR, 0xffffffff);
  1955. I915_WRITE(DEIER, 0x0);
  1956. I915_WRITE(DEIIR, I915_READ(DEIIR));
  1957. if (IS_GEN7(dev))
  1958. I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
  1959. I915_WRITE(GTIMR, 0xffffffff);
  1960. I915_WRITE(GTIER, 0x0);
  1961. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1962. if (HAS_PCH_NOP(dev))
  1963. return;
  1964. I915_WRITE(SDEIMR, 0xffffffff);
  1965. I915_WRITE(SDEIER, 0x0);
  1966. I915_WRITE(SDEIIR, I915_READ(SDEIIR));
  1967. if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
  1968. I915_WRITE(SERR_INT, I915_READ(SERR_INT));
  1969. }
  1970. static void i8xx_irq_preinstall(struct drm_device * dev)
  1971. {
  1972. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1973. int pipe;
  1974. atomic_set(&dev_priv->irq_received, 0);
  1975. for_each_pipe(pipe)
  1976. I915_WRITE(PIPESTAT(pipe), 0);
  1977. I915_WRITE16(IMR, 0xffff);
  1978. I915_WRITE16(IER, 0x0);
  1979. POSTING_READ16(IER);
  1980. }
  1981. static int i8xx_irq_postinstall(struct drm_device *dev)
  1982. {
  1983. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1984. I915_WRITE16(EMR,
  1985. ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
  1986. /* Unmask the interrupts that we always want on. */
  1987. dev_priv->irq_mask =
  1988. ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  1989. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  1990. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  1991. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
  1992. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  1993. I915_WRITE16(IMR, dev_priv->irq_mask);
  1994. I915_WRITE16(IER,
  1995. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  1996. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  1997. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
  1998. I915_USER_INTERRUPT);
  1999. POSTING_READ16(IER);
  2000. return 0;
  2001. }
  2002. /*
  2003. * Returns true when a page flip has completed.
  2004. */
  2005. static bool i8xx_handle_vblank(struct drm_device *dev,
  2006. int pipe, u16 iir)
  2007. {
  2008. drm_i915_private_t *dev_priv = dev->dev_private;
  2009. u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
  2010. if (!drm_handle_vblank(dev, pipe))
  2011. return false;
  2012. if ((iir & flip_pending) == 0)
  2013. return false;
  2014. intel_prepare_page_flip(dev, pipe);
  2015. /* We detect FlipDone by looking for the change in PendingFlip from '1'
  2016. * to '0' on the following vblank, i.e. IIR has the Pendingflip
  2017. * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
  2018. * the flip is completed (no longer pending). Since this doesn't raise
  2019. * an interrupt per se, we watch for the change at vblank.
  2020. */
  2021. if (I915_READ16(ISR) & flip_pending)
  2022. return false;
  2023. intel_finish_page_flip(dev, pipe);
  2024. return true;
  2025. }
  2026. static irqreturn_t i8xx_irq_handler(int irq, void *arg)
  2027. {
  2028. struct drm_device *dev = (struct drm_device *) arg;
  2029. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2030. u16 iir, new_iir;
  2031. u32 pipe_stats[2];
  2032. unsigned long irqflags;
  2033. int pipe;
  2034. u16 flip_mask =
  2035. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2036. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
  2037. atomic_inc(&dev_priv->irq_received);
  2038. iir = I915_READ16(IIR);
  2039. if (iir == 0)
  2040. return IRQ_NONE;
  2041. while (iir & ~flip_mask) {
  2042. /* Can't rely on pipestat interrupt bit in iir as it might
  2043. * have been cleared after the pipestat interrupt was received.
  2044. * It doesn't set the bit in iir again, but it still produces
  2045. * interrupts (for non-MSI).
  2046. */
  2047. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2048. if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  2049. i915_handle_error(dev, false);
  2050. for_each_pipe(pipe) {
  2051. int reg = PIPESTAT(pipe);
  2052. pipe_stats[pipe] = I915_READ(reg);
  2053. /*
  2054. * Clear the PIPE*STAT regs before the IIR
  2055. */
  2056. if (pipe_stats[pipe] & 0x8000ffff) {
  2057. if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  2058. DRM_DEBUG_DRIVER("pipe %c underrun\n",
  2059. pipe_name(pipe));
  2060. I915_WRITE(reg, pipe_stats[pipe]);
  2061. }
  2062. }
  2063. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2064. I915_WRITE16(IIR, iir & ~flip_mask);
  2065. new_iir = I915_READ16(IIR); /* Flush posted writes */
  2066. i915_update_dri1_breadcrumb(dev);
  2067. if (iir & I915_USER_INTERRUPT)
  2068. notify_ring(dev, &dev_priv->ring[RCS]);
  2069. if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
  2070. i8xx_handle_vblank(dev, 0, iir))
  2071. flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
  2072. if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
  2073. i8xx_handle_vblank(dev, 1, iir))
  2074. flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
  2075. iir = new_iir;
  2076. }
  2077. return IRQ_HANDLED;
  2078. }
  2079. static void i8xx_irq_uninstall(struct drm_device * dev)
  2080. {
  2081. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2082. int pipe;
  2083. for_each_pipe(pipe) {
  2084. /* Clear enable bits; then clear status bits */
  2085. I915_WRITE(PIPESTAT(pipe), 0);
  2086. I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
  2087. }
  2088. I915_WRITE16(IMR, 0xffff);
  2089. I915_WRITE16(IER, 0x0);
  2090. I915_WRITE16(IIR, I915_READ16(IIR));
  2091. }
  2092. static void i915_irq_preinstall(struct drm_device * dev)
  2093. {
  2094. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2095. int pipe;
  2096. atomic_set(&dev_priv->irq_received, 0);
  2097. if (I915_HAS_HOTPLUG(dev)) {
  2098. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2099. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2100. }
  2101. I915_WRITE16(HWSTAM, 0xeffe);
  2102. for_each_pipe(pipe)
  2103. I915_WRITE(PIPESTAT(pipe), 0);
  2104. I915_WRITE(IMR, 0xffffffff);
  2105. I915_WRITE(IER, 0x0);
  2106. POSTING_READ(IER);
  2107. }
  2108. static int i915_irq_postinstall(struct drm_device *dev)
  2109. {
  2110. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2111. u32 enable_mask;
  2112. I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
  2113. /* Unmask the interrupts that we always want on. */
  2114. dev_priv->irq_mask =
  2115. ~(I915_ASLE_INTERRUPT |
  2116. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  2117. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  2118. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2119. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
  2120. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  2121. enable_mask =
  2122. I915_ASLE_INTERRUPT |
  2123. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  2124. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  2125. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
  2126. I915_USER_INTERRUPT;
  2127. if (I915_HAS_HOTPLUG(dev)) {
  2128. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2129. POSTING_READ(PORT_HOTPLUG_EN);
  2130. /* Enable in IER... */
  2131. enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
  2132. /* and unmask in IMR */
  2133. dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
  2134. }
  2135. I915_WRITE(IMR, dev_priv->irq_mask);
  2136. I915_WRITE(IER, enable_mask);
  2137. POSTING_READ(IER);
  2138. i915_enable_asle_pipestat(dev);
  2139. return 0;
  2140. }
  2141. /*
  2142. * Returns true when a page flip has completed.
  2143. */
  2144. static bool i915_handle_vblank(struct drm_device *dev,
  2145. int plane, int pipe, u32 iir)
  2146. {
  2147. drm_i915_private_t *dev_priv = dev->dev_private;
  2148. u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
  2149. if (!drm_handle_vblank(dev, pipe))
  2150. return false;
  2151. if ((iir & flip_pending) == 0)
  2152. return false;
  2153. intel_prepare_page_flip(dev, plane);
  2154. /* We detect FlipDone by looking for the change in PendingFlip from '1'
  2155. * to '0' on the following vblank, i.e. IIR has the Pendingflip
  2156. * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
  2157. * the flip is completed (no longer pending). Since this doesn't raise
  2158. * an interrupt per se, we watch for the change at vblank.
  2159. */
  2160. if (I915_READ(ISR) & flip_pending)
  2161. return false;
  2162. intel_finish_page_flip(dev, pipe);
  2163. return true;
  2164. }
  2165. static irqreturn_t i915_irq_handler(int irq, void *arg)
  2166. {
  2167. struct drm_device *dev = (struct drm_device *) arg;
  2168. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2169. u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
  2170. unsigned long irqflags;
  2171. u32 flip_mask =
  2172. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2173. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
  2174. int pipe, ret = IRQ_NONE;
  2175. atomic_inc(&dev_priv->irq_received);
  2176. iir = I915_READ(IIR);
  2177. do {
  2178. bool irq_received = (iir & ~flip_mask) != 0;
  2179. bool blc_event = false;
  2180. /* Can't rely on pipestat interrupt bit in iir as it might
  2181. * have been cleared after the pipestat interrupt was received.
  2182. * It doesn't set the bit in iir again, but it still produces
  2183. * interrupts (for non-MSI).
  2184. */
  2185. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2186. if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  2187. i915_handle_error(dev, false);
  2188. for_each_pipe(pipe) {
  2189. int reg = PIPESTAT(pipe);
  2190. pipe_stats[pipe] = I915_READ(reg);
  2191. /* Clear the PIPE*STAT regs before the IIR */
  2192. if (pipe_stats[pipe] & 0x8000ffff) {
  2193. if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  2194. DRM_DEBUG_DRIVER("pipe %c underrun\n",
  2195. pipe_name(pipe));
  2196. I915_WRITE(reg, pipe_stats[pipe]);
  2197. irq_received = true;
  2198. }
  2199. }
  2200. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2201. if (!irq_received)
  2202. break;
  2203. /* Consume port. Then clear IIR or we'll miss events */
  2204. if ((I915_HAS_HOTPLUG(dev)) &&
  2205. (iir & I915_DISPLAY_PORT_INTERRUPT)) {
  2206. u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
  2207. u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
  2208. DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
  2209. hotplug_status);
  2210. intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
  2211. I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
  2212. POSTING_READ(PORT_HOTPLUG_STAT);
  2213. }
  2214. I915_WRITE(IIR, iir & ~flip_mask);
  2215. new_iir = I915_READ(IIR); /* Flush posted writes */
  2216. if (iir & I915_USER_INTERRUPT)
  2217. notify_ring(dev, &dev_priv->ring[RCS]);
  2218. for_each_pipe(pipe) {
  2219. int plane = pipe;
  2220. if (IS_MOBILE(dev))
  2221. plane = !plane;
  2222. if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
  2223. i915_handle_vblank(dev, plane, pipe, iir))
  2224. flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
  2225. if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
  2226. blc_event = true;
  2227. }
  2228. if (blc_event || (iir & I915_ASLE_INTERRUPT))
  2229. intel_opregion_asle_intr(dev);
  2230. /* With MSI, interrupts are only generated when iir
  2231. * transitions from zero to nonzero. If another bit got
  2232. * set while we were handling the existing iir bits, then
  2233. * we would never get another interrupt.
  2234. *
  2235. * This is fine on non-MSI as well, as if we hit this path
  2236. * we avoid exiting the interrupt handler only to generate
  2237. * another one.
  2238. *
  2239. * Note that for MSI this could cause a stray interrupt report
  2240. * if an interrupt landed in the time between writing IIR and
  2241. * the posting read. This should be rare enough to never
  2242. * trigger the 99% of 100,000 interrupts test for disabling
  2243. * stray interrupts.
  2244. */
  2245. ret = IRQ_HANDLED;
  2246. iir = new_iir;
  2247. } while (iir & ~flip_mask);
  2248. i915_update_dri1_breadcrumb(dev);
  2249. return ret;
  2250. }
  2251. static void i915_irq_uninstall(struct drm_device * dev)
  2252. {
  2253. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2254. int pipe;
  2255. del_timer_sync(&dev_priv->hotplug_reenable_timer);
  2256. if (I915_HAS_HOTPLUG(dev)) {
  2257. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2258. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2259. }
  2260. I915_WRITE16(HWSTAM, 0xffff);
  2261. for_each_pipe(pipe) {
  2262. /* Clear enable bits; then clear status bits */
  2263. I915_WRITE(PIPESTAT(pipe), 0);
  2264. I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
  2265. }
  2266. I915_WRITE(IMR, 0xffffffff);
  2267. I915_WRITE(IER, 0x0);
  2268. I915_WRITE(IIR, I915_READ(IIR));
  2269. }
  2270. static void i965_irq_preinstall(struct drm_device * dev)
  2271. {
  2272. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2273. int pipe;
  2274. atomic_set(&dev_priv->irq_received, 0);
  2275. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2276. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2277. I915_WRITE(HWSTAM, 0xeffe);
  2278. for_each_pipe(pipe)
  2279. I915_WRITE(PIPESTAT(pipe), 0);
  2280. I915_WRITE(IMR, 0xffffffff);
  2281. I915_WRITE(IER, 0x0);
  2282. POSTING_READ(IER);
  2283. }
  2284. static int i965_irq_postinstall(struct drm_device *dev)
  2285. {
  2286. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2287. u32 enable_mask;
  2288. u32 error_mask;
  2289. unsigned long irqflags;
  2290. /* Unmask the interrupts that we always want on. */
  2291. dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
  2292. I915_DISPLAY_PORT_INTERRUPT |
  2293. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  2294. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  2295. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2296. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
  2297. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  2298. enable_mask = ~dev_priv->irq_mask;
  2299. enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2300. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
  2301. enable_mask |= I915_USER_INTERRUPT;
  2302. if (IS_G4X(dev))
  2303. enable_mask |= I915_BSD_USER_INTERRUPT;
  2304. /* Interrupt setup is already guaranteed to be single-threaded, this is
  2305. * just to make the assert_spin_locked check happy. */
  2306. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2307. i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
  2308. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2309. /*
  2310. * Enable some error detection, note the instruction error mask
  2311. * bit is reserved, so we leave it masked.
  2312. */
  2313. if (IS_G4X(dev)) {
  2314. error_mask = ~(GM45_ERROR_PAGE_TABLE |
  2315. GM45_ERROR_MEM_PRIV |
  2316. GM45_ERROR_CP_PRIV |
  2317. I915_ERROR_MEMORY_REFRESH);
  2318. } else {
  2319. error_mask = ~(I915_ERROR_PAGE_TABLE |
  2320. I915_ERROR_MEMORY_REFRESH);
  2321. }
  2322. I915_WRITE(EMR, error_mask);
  2323. I915_WRITE(IMR, dev_priv->irq_mask);
  2324. I915_WRITE(IER, enable_mask);
  2325. POSTING_READ(IER);
  2326. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2327. POSTING_READ(PORT_HOTPLUG_EN);
  2328. i915_enable_asle_pipestat(dev);
  2329. return 0;
  2330. }
  2331. static void i915_hpd_irq_setup(struct drm_device *dev)
  2332. {
  2333. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2334. struct drm_mode_config *mode_config = &dev->mode_config;
  2335. struct intel_encoder *intel_encoder;
  2336. u32 hotplug_en;
  2337. assert_spin_locked(&dev_priv->irq_lock);
  2338. if (I915_HAS_HOTPLUG(dev)) {
  2339. hotplug_en = I915_READ(PORT_HOTPLUG_EN);
  2340. hotplug_en &= ~HOTPLUG_INT_EN_MASK;
  2341. /* Note HDMI and DP share hotplug bits */
  2342. /* enable bits are the same for all generations */
  2343. list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
  2344. if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
  2345. hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
  2346. /* Programming the CRT detection parameters tends
  2347. to generate a spurious hotplug event about three
  2348. seconds later. So just do it once.
  2349. */
  2350. if (IS_G4X(dev))
  2351. hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
  2352. hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
  2353. hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
  2354. /* Ignore TV since it's buggy */
  2355. I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  2356. }
  2357. }
  2358. static irqreturn_t i965_irq_handler(int irq, void *arg)
  2359. {
  2360. struct drm_device *dev = (struct drm_device *) arg;
  2361. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2362. u32 iir, new_iir;
  2363. u32 pipe_stats[I915_MAX_PIPES];
  2364. unsigned long irqflags;
  2365. int irq_received;
  2366. int ret = IRQ_NONE, pipe;
  2367. u32 flip_mask =
  2368. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2369. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
  2370. atomic_inc(&dev_priv->irq_received);
  2371. iir = I915_READ(IIR);
  2372. for (;;) {
  2373. bool blc_event = false;
  2374. irq_received = (iir & ~flip_mask) != 0;
  2375. /* Can't rely on pipestat interrupt bit in iir as it might
  2376. * have been cleared after the pipestat interrupt was received.
  2377. * It doesn't set the bit in iir again, but it still produces
  2378. * interrupts (for non-MSI).
  2379. */
  2380. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2381. if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  2382. i915_handle_error(dev, false);
  2383. for_each_pipe(pipe) {
  2384. int reg = PIPESTAT(pipe);
  2385. pipe_stats[pipe] = I915_READ(reg);
  2386. /*
  2387. * Clear the PIPE*STAT regs before the IIR
  2388. */
  2389. if (pipe_stats[pipe] & 0x8000ffff) {
  2390. if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  2391. DRM_DEBUG_DRIVER("pipe %c underrun\n",
  2392. pipe_name(pipe));
  2393. I915_WRITE(reg, pipe_stats[pipe]);
  2394. irq_received = 1;
  2395. }
  2396. }
  2397. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2398. if (!irq_received)
  2399. break;
  2400. ret = IRQ_HANDLED;
  2401. /* Consume port. Then clear IIR or we'll miss events */
  2402. if (iir & I915_DISPLAY_PORT_INTERRUPT) {
  2403. u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
  2404. u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
  2405. HOTPLUG_INT_STATUS_G4X :
  2406. HOTPLUG_INT_STATUS_I915);
  2407. DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
  2408. hotplug_status);
  2409. intel_hpd_irq_handler(dev, hotplug_trigger,
  2410. IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);
  2411. I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
  2412. I915_READ(PORT_HOTPLUG_STAT);
  2413. }
  2414. I915_WRITE(IIR, iir & ~flip_mask);
  2415. new_iir = I915_READ(IIR); /* Flush posted writes */
  2416. if (iir & I915_USER_INTERRUPT)
  2417. notify_ring(dev, &dev_priv->ring[RCS]);
  2418. if (iir & I915_BSD_USER_INTERRUPT)
  2419. notify_ring(dev, &dev_priv->ring[VCS]);
  2420. for_each_pipe(pipe) {
  2421. if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
  2422. i915_handle_vblank(dev, pipe, pipe, iir))
  2423. flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
  2424. if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
  2425. blc_event = true;
  2426. }
  2427. if (blc_event || (iir & I915_ASLE_INTERRUPT))
  2428. intel_opregion_asle_intr(dev);
  2429. if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
  2430. gmbus_irq_handler(dev);
  2431. /* With MSI, interrupts are only generated when iir
  2432. * transitions from zero to nonzero. If another bit got
  2433. * set while we were handling the existing iir bits, then
  2434. * we would never get another interrupt.
  2435. *
  2436. * This is fine on non-MSI as well, as if we hit this path
  2437. * we avoid exiting the interrupt handler only to generate
  2438. * another one.
  2439. *
  2440. * Note that for MSI this could cause a stray interrupt report
  2441. * if an interrupt landed in the time between writing IIR and
  2442. * the posting read. This should be rare enough to never
  2443. * trigger the 99% of 100,000 interrupts test for disabling
  2444. * stray interrupts.
  2445. */
  2446. iir = new_iir;
  2447. }
  2448. i915_update_dri1_breadcrumb(dev);
  2449. return ret;
  2450. }
  2451. static void i965_irq_uninstall(struct drm_device * dev)
  2452. {
  2453. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2454. int pipe;
  2455. if (!dev_priv)
  2456. return;
  2457. del_timer_sync(&dev_priv->hotplug_reenable_timer);
  2458. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2459. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2460. I915_WRITE(HWSTAM, 0xffffffff);
  2461. for_each_pipe(pipe)
  2462. I915_WRITE(PIPESTAT(pipe), 0);
  2463. I915_WRITE(IMR, 0xffffffff);
  2464. I915_WRITE(IER, 0x0);
  2465. for_each_pipe(pipe)
  2466. I915_WRITE(PIPESTAT(pipe),
  2467. I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
  2468. I915_WRITE(IIR, I915_READ(IIR));
  2469. }
  2470. static void i915_reenable_hotplug_timer_func(unsigned long data)
  2471. {
  2472. drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
  2473. struct drm_device *dev = dev_priv->dev;
  2474. struct drm_mode_config *mode_config = &dev->mode_config;
  2475. unsigned long irqflags;
  2476. int i;
  2477. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2478. for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
  2479. struct drm_connector *connector;
  2480. if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
  2481. continue;
  2482. dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
  2483. list_for_each_entry(connector, &mode_config->connector_list, head) {
  2484. struct intel_connector *intel_connector = to_intel_connector(connector);
  2485. if (intel_connector->encoder->hpd_pin == i) {
  2486. if (connector->polled != intel_connector->polled)
  2487. DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
  2488. drm_get_connector_name(connector));
  2489. connector->polled = intel_connector->polled;
  2490. if (!connector->polled)
  2491. connector->polled = DRM_CONNECTOR_POLL_HPD;
  2492. }
  2493. }
  2494. }
  2495. if (dev_priv->display.hpd_irq_setup)
  2496. dev_priv->display.hpd_irq_setup(dev);
  2497. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2498. }
  2499. void intel_irq_init(struct drm_device *dev)
  2500. {
  2501. struct drm_i915_private *dev_priv = dev->dev_private;
  2502. INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
  2503. INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
  2504. INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
  2505. INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
  2506. setup_timer(&dev_priv->gpu_error.hangcheck_timer,
  2507. i915_hangcheck_elapsed,
  2508. (unsigned long) dev);
  2509. setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
  2510. (unsigned long) dev_priv);
  2511. pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
  2512. dev->driver->get_vblank_counter = i915_get_vblank_counter;
  2513. dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
  2514. if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
  2515. dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
  2516. dev->driver->get_vblank_counter = gm45_get_vblank_counter;
  2517. }
  2518. if (drm_core_check_feature(dev, DRIVER_MODESET))
  2519. dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
  2520. else
  2521. dev->driver->get_vblank_timestamp = NULL;
  2522. dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
  2523. if (IS_VALLEYVIEW(dev)) {
  2524. dev->driver->irq_handler = valleyview_irq_handler;
  2525. dev->driver->irq_preinstall = valleyview_irq_preinstall;
  2526. dev->driver->irq_postinstall = valleyview_irq_postinstall;
  2527. dev->driver->irq_uninstall = valleyview_irq_uninstall;
  2528. dev->driver->enable_vblank = valleyview_enable_vblank;
  2529. dev->driver->disable_vblank = valleyview_disable_vblank;
  2530. dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
  2531. } else if (HAS_PCH_SPLIT(dev)) {
  2532. dev->driver->irq_handler = ironlake_irq_handler;
  2533. dev->driver->irq_preinstall = ironlake_irq_preinstall;
  2534. dev->driver->irq_postinstall = ironlake_irq_postinstall;
  2535. dev->driver->irq_uninstall = ironlake_irq_uninstall;
  2536. dev->driver->enable_vblank = ironlake_enable_vblank;
  2537. dev->driver->disable_vblank = ironlake_disable_vblank;
  2538. dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
  2539. } else {
  2540. if (INTEL_INFO(dev)->gen == 2) {
  2541. dev->driver->irq_preinstall = i8xx_irq_preinstall;
  2542. dev->driver->irq_postinstall = i8xx_irq_postinstall;
  2543. dev->driver->irq_handler = i8xx_irq_handler;
  2544. dev->driver->irq_uninstall = i8xx_irq_uninstall;
  2545. } else if (INTEL_INFO(dev)->gen == 3) {
  2546. dev->driver->irq_preinstall = i915_irq_preinstall;
  2547. dev->driver->irq_postinstall = i915_irq_postinstall;
  2548. dev->driver->irq_uninstall = i915_irq_uninstall;
  2549. dev->driver->irq_handler = i915_irq_handler;
  2550. dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
  2551. } else {
  2552. dev->driver->irq_preinstall = i965_irq_preinstall;
  2553. dev->driver->irq_postinstall = i965_irq_postinstall;
  2554. dev->driver->irq_uninstall = i965_irq_uninstall;
  2555. dev->driver->irq_handler = i965_irq_handler;
  2556. dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
  2557. }
  2558. dev->driver->enable_vblank = i915_enable_vblank;
  2559. dev->driver->disable_vblank = i915_disable_vblank;
  2560. }
  2561. }
  2562. void intel_hpd_init(struct drm_device *dev)
  2563. {
  2564. struct drm_i915_private *dev_priv = dev->dev_private;
  2565. struct drm_mode_config *mode_config = &dev->mode_config;
  2566. struct drm_connector *connector;
  2567. unsigned long irqflags;
  2568. int i;
  2569. for (i = 1; i < HPD_NUM_PINS; i++) {
  2570. dev_priv->hpd_stats[i].hpd_cnt = 0;
  2571. dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
  2572. }
  2573. list_for_each_entry(connector, &mode_config->connector_list, head) {
  2574. struct intel_connector *intel_connector = to_intel_connector(connector);
  2575. connector->polled = intel_connector->polled;
  2576. if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
  2577. connector->polled = DRM_CONNECTOR_POLL_HPD;
  2578. }
  2579. /* Interrupt setup is already guaranteed to be single-threaded, this is
  2580. * just to make the assert_spin_locked checks happy. */
  2581. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2582. if (dev_priv->display.hpd_irq_setup)
  2583. dev_priv->display.hpd_irq_setup(dev);
  2584. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2585. }