be_main.c 127 KB

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  1. /**
  2. * Copyright (C) 2005 - 2011 Emulex
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License version 2
  7. * as published by the Free Software Foundation. The full GNU General
  8. * Public License is included in this distribution in the file called COPYING.
  9. *
  10. * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
  11. *
  12. * Contact Information:
  13. * linux-drivers@emulex.com
  14. *
  15. * Emulex
  16. * 3333 Susan Street
  17. * Costa Mesa, CA 92626
  18. */
  19. #include <linux/reboot.h>
  20. #include <linux/delay.h>
  21. #include <linux/slab.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/blkdev.h>
  24. #include <linux/pci.h>
  25. #include <linux/string.h>
  26. #include <linux/kernel.h>
  27. #include <linux/semaphore.h>
  28. #include <linux/iscsi_boot_sysfs.h>
  29. #include <linux/module.h>
  30. #include <scsi/libiscsi.h>
  31. #include <scsi/scsi_transport_iscsi.h>
  32. #include <scsi/scsi_transport.h>
  33. #include <scsi/scsi_cmnd.h>
  34. #include <scsi/scsi_device.h>
  35. #include <scsi/scsi_host.h>
  36. #include <scsi/scsi.h>
  37. #include "be_main.h"
  38. #include "be_iscsi.h"
  39. #include "be_mgmt.h"
  40. static unsigned int be_iopoll_budget = 10;
  41. static unsigned int be_max_phys_size = 64;
  42. static unsigned int enable_msix = 1;
  43. static unsigned int gcrashmode = 0;
  44. static unsigned int num_hba = 0;
  45. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  46. MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR);
  47. MODULE_VERSION(BUILD_STR);
  48. MODULE_AUTHOR("Emulex Corporation");
  49. MODULE_LICENSE("GPL");
  50. module_param(be_iopoll_budget, int, 0);
  51. module_param(enable_msix, int, 0);
  52. module_param(be_max_phys_size, uint, S_IRUGO);
  53. MODULE_PARM_DESC(be_max_phys_size, "Maximum Size (In Kilobytes) of physically"
  54. "contiguous memory that can be allocated."
  55. "Range is 16 - 128");
  56. static int beiscsi_slave_configure(struct scsi_device *sdev)
  57. {
  58. blk_queue_max_segment_size(sdev->request_queue, 65536);
  59. return 0;
  60. }
  61. static int beiscsi_eh_abort(struct scsi_cmnd *sc)
  62. {
  63. struct iscsi_cls_session *cls_session;
  64. struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr;
  65. struct beiscsi_io_task *aborted_io_task;
  66. struct iscsi_conn *conn;
  67. struct beiscsi_conn *beiscsi_conn;
  68. struct beiscsi_hba *phba;
  69. struct iscsi_session *session;
  70. struct invalidate_command_table *inv_tbl;
  71. struct be_dma_mem nonemb_cmd;
  72. unsigned int cid, tag, num_invalidate;
  73. cls_session = starget_to_session(scsi_target(sc->device));
  74. session = cls_session->dd_data;
  75. spin_lock_bh(&session->lock);
  76. if (!aborted_task || !aborted_task->sc) {
  77. /* we raced */
  78. spin_unlock_bh(&session->lock);
  79. return SUCCESS;
  80. }
  81. aborted_io_task = aborted_task->dd_data;
  82. if (!aborted_io_task->scsi_cmnd) {
  83. /* raced or invalid command */
  84. spin_unlock_bh(&session->lock);
  85. return SUCCESS;
  86. }
  87. spin_unlock_bh(&session->lock);
  88. conn = aborted_task->conn;
  89. beiscsi_conn = conn->dd_data;
  90. phba = beiscsi_conn->phba;
  91. /* invalidate iocb */
  92. cid = beiscsi_conn->beiscsi_conn_cid;
  93. inv_tbl = phba->inv_tbl;
  94. memset(inv_tbl, 0x0, sizeof(*inv_tbl));
  95. inv_tbl->cid = cid;
  96. inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index;
  97. num_invalidate = 1;
  98. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  99. sizeof(struct invalidate_commands_params_in),
  100. &nonemb_cmd.dma);
  101. if (nonemb_cmd.va == NULL) {
  102. SE_DEBUG(DBG_LVL_1,
  103. "Failed to allocate memory for"
  104. "mgmt_invalidate_icds\n");
  105. return FAILED;
  106. }
  107. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  108. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  109. cid, &nonemb_cmd);
  110. if (!tag) {
  111. shost_printk(KERN_WARNING, phba->shost,
  112. "mgmt_invalidate_icds could not be"
  113. " submitted\n");
  114. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  115. nonemb_cmd.va, nonemb_cmd.dma);
  116. return FAILED;
  117. } else {
  118. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  119. phba->ctrl.mcc_numtag[tag]);
  120. free_mcc_tag(&phba->ctrl, tag);
  121. }
  122. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  123. nonemb_cmd.va, nonemb_cmd.dma);
  124. return iscsi_eh_abort(sc);
  125. }
  126. static int beiscsi_eh_device_reset(struct scsi_cmnd *sc)
  127. {
  128. struct iscsi_task *abrt_task;
  129. struct beiscsi_io_task *abrt_io_task;
  130. struct iscsi_conn *conn;
  131. struct beiscsi_conn *beiscsi_conn;
  132. struct beiscsi_hba *phba;
  133. struct iscsi_session *session;
  134. struct iscsi_cls_session *cls_session;
  135. struct invalidate_command_table *inv_tbl;
  136. struct be_dma_mem nonemb_cmd;
  137. unsigned int cid, tag, i, num_invalidate;
  138. /* invalidate iocbs */
  139. cls_session = starget_to_session(scsi_target(sc->device));
  140. session = cls_session->dd_data;
  141. spin_lock_bh(&session->lock);
  142. if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) {
  143. spin_unlock_bh(&session->lock);
  144. return FAILED;
  145. }
  146. conn = session->leadconn;
  147. beiscsi_conn = conn->dd_data;
  148. phba = beiscsi_conn->phba;
  149. cid = beiscsi_conn->beiscsi_conn_cid;
  150. inv_tbl = phba->inv_tbl;
  151. memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN);
  152. num_invalidate = 0;
  153. for (i = 0; i < conn->session->cmds_max; i++) {
  154. abrt_task = conn->session->cmds[i];
  155. abrt_io_task = abrt_task->dd_data;
  156. if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE)
  157. continue;
  158. if (abrt_task->sc->device->lun != abrt_task->sc->device->lun)
  159. continue;
  160. inv_tbl->cid = cid;
  161. inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index;
  162. num_invalidate++;
  163. inv_tbl++;
  164. }
  165. spin_unlock_bh(&session->lock);
  166. inv_tbl = phba->inv_tbl;
  167. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  168. sizeof(struct invalidate_commands_params_in),
  169. &nonemb_cmd.dma);
  170. if (nonemb_cmd.va == NULL) {
  171. SE_DEBUG(DBG_LVL_1,
  172. "Failed to allocate memory for"
  173. "mgmt_invalidate_icds\n");
  174. return FAILED;
  175. }
  176. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  177. memset(nonemb_cmd.va, 0, nonemb_cmd.size);
  178. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  179. cid, &nonemb_cmd);
  180. if (!tag) {
  181. shost_printk(KERN_WARNING, phba->shost,
  182. "mgmt_invalidate_icds could not be"
  183. " submitted\n");
  184. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  185. nonemb_cmd.va, nonemb_cmd.dma);
  186. return FAILED;
  187. } else {
  188. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  189. phba->ctrl.mcc_numtag[tag]);
  190. free_mcc_tag(&phba->ctrl, tag);
  191. }
  192. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  193. nonemb_cmd.va, nonemb_cmd.dma);
  194. return iscsi_eh_device_reset(sc);
  195. }
  196. static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf)
  197. {
  198. struct beiscsi_hba *phba = data;
  199. struct mgmt_session_info *boot_sess = &phba->boot_sess;
  200. struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0];
  201. char *str = buf;
  202. int rc;
  203. switch (type) {
  204. case ISCSI_BOOT_TGT_NAME:
  205. rc = sprintf(buf, "%.*s\n",
  206. (int)strlen(boot_sess->target_name),
  207. (char *)&boot_sess->target_name);
  208. break;
  209. case ISCSI_BOOT_TGT_IP_ADDR:
  210. if (boot_conn->dest_ipaddr.ip_type == 0x1)
  211. rc = sprintf(buf, "%pI4\n",
  212. (char *)&boot_conn->dest_ipaddr.ip_address);
  213. else
  214. rc = sprintf(str, "%pI6\n",
  215. (char *)&boot_conn->dest_ipaddr.ip_address);
  216. break;
  217. case ISCSI_BOOT_TGT_PORT:
  218. rc = sprintf(str, "%d\n", boot_conn->dest_port);
  219. break;
  220. case ISCSI_BOOT_TGT_CHAP_NAME:
  221. rc = sprintf(str, "%.*s\n",
  222. boot_conn->negotiated_login_options.auth_data.chap.
  223. target_chap_name_length,
  224. (char *)&boot_conn->negotiated_login_options.
  225. auth_data.chap.target_chap_name);
  226. break;
  227. case ISCSI_BOOT_TGT_CHAP_SECRET:
  228. rc = sprintf(str, "%.*s\n",
  229. boot_conn->negotiated_login_options.auth_data.chap.
  230. target_secret_length,
  231. (char *)&boot_conn->negotiated_login_options.
  232. auth_data.chap.target_secret);
  233. break;
  234. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  235. rc = sprintf(str, "%.*s\n",
  236. boot_conn->negotiated_login_options.auth_data.chap.
  237. intr_chap_name_length,
  238. (char *)&boot_conn->negotiated_login_options.
  239. auth_data.chap.intr_chap_name);
  240. break;
  241. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  242. rc = sprintf(str, "%.*s\n",
  243. boot_conn->negotiated_login_options.auth_data.chap.
  244. intr_secret_length,
  245. (char *)&boot_conn->negotiated_login_options.
  246. auth_data.chap.intr_secret);
  247. break;
  248. case ISCSI_BOOT_TGT_FLAGS:
  249. rc = sprintf(str, "2\n");
  250. break;
  251. case ISCSI_BOOT_TGT_NIC_ASSOC:
  252. rc = sprintf(str, "0\n");
  253. break;
  254. default:
  255. rc = -ENOSYS;
  256. break;
  257. }
  258. return rc;
  259. }
  260. static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf)
  261. {
  262. struct beiscsi_hba *phba = data;
  263. char *str = buf;
  264. int rc;
  265. switch (type) {
  266. case ISCSI_BOOT_INI_INITIATOR_NAME:
  267. rc = sprintf(str, "%s\n", phba->boot_sess.initiator_iscsiname);
  268. break;
  269. default:
  270. rc = -ENOSYS;
  271. break;
  272. }
  273. return rc;
  274. }
  275. static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf)
  276. {
  277. struct beiscsi_hba *phba = data;
  278. char *str = buf;
  279. int rc;
  280. switch (type) {
  281. case ISCSI_BOOT_ETH_FLAGS:
  282. rc = sprintf(str, "2\n");
  283. break;
  284. case ISCSI_BOOT_ETH_INDEX:
  285. rc = sprintf(str, "0\n");
  286. break;
  287. case ISCSI_BOOT_ETH_MAC:
  288. rc = beiscsi_get_macaddr(buf, phba);
  289. if (rc < 0) {
  290. SE_DEBUG(DBG_LVL_1, "beiscsi_get_macaddr Failed\n");
  291. return rc;
  292. }
  293. break;
  294. default:
  295. rc = -ENOSYS;
  296. break;
  297. }
  298. return rc;
  299. }
  300. static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type)
  301. {
  302. umode_t rc;
  303. switch (type) {
  304. case ISCSI_BOOT_TGT_NAME:
  305. case ISCSI_BOOT_TGT_IP_ADDR:
  306. case ISCSI_BOOT_TGT_PORT:
  307. case ISCSI_BOOT_TGT_CHAP_NAME:
  308. case ISCSI_BOOT_TGT_CHAP_SECRET:
  309. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  310. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  311. case ISCSI_BOOT_TGT_NIC_ASSOC:
  312. case ISCSI_BOOT_TGT_FLAGS:
  313. rc = S_IRUGO;
  314. break;
  315. default:
  316. rc = 0;
  317. break;
  318. }
  319. return rc;
  320. }
  321. static umode_t beiscsi_ini_get_attr_visibility(void *data, int type)
  322. {
  323. umode_t rc;
  324. switch (type) {
  325. case ISCSI_BOOT_INI_INITIATOR_NAME:
  326. rc = S_IRUGO;
  327. break;
  328. default:
  329. rc = 0;
  330. break;
  331. }
  332. return rc;
  333. }
  334. static umode_t beiscsi_eth_get_attr_visibility(void *data, int type)
  335. {
  336. umode_t rc;
  337. switch (type) {
  338. case ISCSI_BOOT_ETH_FLAGS:
  339. case ISCSI_BOOT_ETH_MAC:
  340. case ISCSI_BOOT_ETH_INDEX:
  341. rc = S_IRUGO;
  342. break;
  343. default:
  344. rc = 0;
  345. break;
  346. }
  347. return rc;
  348. }
  349. /*------------------- PCI Driver operations and data ----------------- */
  350. static DEFINE_PCI_DEVICE_TABLE(beiscsi_pci_id_table) = {
  351. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
  352. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
  353. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
  354. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
  355. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) },
  356. { 0 }
  357. };
  358. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  359. static struct scsi_host_template beiscsi_sht = {
  360. .module = THIS_MODULE,
  361. .name = "Emulex 10Gbe open-iscsi Initiator Driver",
  362. .proc_name = DRV_NAME,
  363. .queuecommand = iscsi_queuecommand,
  364. .change_queue_depth = iscsi_change_queue_depth,
  365. .slave_configure = beiscsi_slave_configure,
  366. .target_alloc = iscsi_target_alloc,
  367. .eh_abort_handler = beiscsi_eh_abort,
  368. .eh_device_reset_handler = beiscsi_eh_device_reset,
  369. .eh_target_reset_handler = iscsi_eh_session_reset,
  370. .sg_tablesize = BEISCSI_SGLIST_ELEMENTS,
  371. .can_queue = BE2_IO_DEPTH,
  372. .this_id = -1,
  373. .max_sectors = BEISCSI_MAX_SECTORS,
  374. .cmd_per_lun = BEISCSI_CMD_PER_LUN,
  375. .use_clustering = ENABLE_CLUSTERING,
  376. };
  377. static struct scsi_transport_template *beiscsi_scsi_transport;
  378. static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev)
  379. {
  380. struct beiscsi_hba *phba;
  381. struct Scsi_Host *shost;
  382. shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0);
  383. if (!shost) {
  384. dev_err(&pcidev->dev, "beiscsi_hba_alloc -"
  385. "iscsi_host_alloc failed\n");
  386. return NULL;
  387. }
  388. shost->dma_boundary = pcidev->dma_mask;
  389. shost->max_id = BE2_MAX_SESSIONS;
  390. shost->max_channel = 0;
  391. shost->max_cmd_len = BEISCSI_MAX_CMD_LEN;
  392. shost->max_lun = BEISCSI_NUM_MAX_LUN;
  393. shost->transportt = beiscsi_scsi_transport;
  394. phba = iscsi_host_priv(shost);
  395. memset(phba, 0, sizeof(*phba));
  396. phba->shost = shost;
  397. phba->pcidev = pci_dev_get(pcidev);
  398. pci_set_drvdata(pcidev, phba);
  399. if (iscsi_host_add(shost, &phba->pcidev->dev))
  400. goto free_devices;
  401. return phba;
  402. free_devices:
  403. pci_dev_put(phba->pcidev);
  404. iscsi_host_free(phba->shost);
  405. return NULL;
  406. }
  407. static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba)
  408. {
  409. if (phba->csr_va) {
  410. iounmap(phba->csr_va);
  411. phba->csr_va = NULL;
  412. }
  413. if (phba->db_va) {
  414. iounmap(phba->db_va);
  415. phba->db_va = NULL;
  416. }
  417. if (phba->pci_va) {
  418. iounmap(phba->pci_va);
  419. phba->pci_va = NULL;
  420. }
  421. }
  422. static int beiscsi_map_pci_bars(struct beiscsi_hba *phba,
  423. struct pci_dev *pcidev)
  424. {
  425. u8 __iomem *addr;
  426. int pcicfg_reg;
  427. addr = ioremap_nocache(pci_resource_start(pcidev, 2),
  428. pci_resource_len(pcidev, 2));
  429. if (addr == NULL)
  430. return -ENOMEM;
  431. phba->ctrl.csr = addr;
  432. phba->csr_va = addr;
  433. phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2);
  434. addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024);
  435. if (addr == NULL)
  436. goto pci_map_err;
  437. phba->ctrl.db = addr;
  438. phba->db_va = addr;
  439. phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4);
  440. if (phba->generation == BE_GEN2)
  441. pcicfg_reg = 1;
  442. else
  443. pcicfg_reg = 0;
  444. addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg),
  445. pci_resource_len(pcidev, pcicfg_reg));
  446. if (addr == NULL)
  447. goto pci_map_err;
  448. phba->ctrl.pcicfg = addr;
  449. phba->pci_va = addr;
  450. phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg);
  451. return 0;
  452. pci_map_err:
  453. beiscsi_unmap_pci_function(phba);
  454. return -ENOMEM;
  455. }
  456. static int beiscsi_enable_pci(struct pci_dev *pcidev)
  457. {
  458. int ret;
  459. ret = pci_enable_device(pcidev);
  460. if (ret) {
  461. dev_err(&pcidev->dev, "beiscsi_enable_pci - enable device "
  462. "failed. Returning -ENODEV\n");
  463. return ret;
  464. }
  465. pci_set_master(pcidev);
  466. if (pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64))) {
  467. ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
  468. if (ret) {
  469. dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
  470. pci_disable_device(pcidev);
  471. return ret;
  472. }
  473. }
  474. return 0;
  475. }
  476. static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev)
  477. {
  478. struct be_ctrl_info *ctrl = &phba->ctrl;
  479. struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced;
  480. struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem;
  481. int status = 0;
  482. ctrl->pdev = pdev;
  483. status = beiscsi_map_pci_bars(phba, pdev);
  484. if (status)
  485. return status;
  486. mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
  487. mbox_mem_alloc->va = pci_alloc_consistent(pdev,
  488. mbox_mem_alloc->size,
  489. &mbox_mem_alloc->dma);
  490. if (!mbox_mem_alloc->va) {
  491. beiscsi_unmap_pci_function(phba);
  492. return -ENOMEM;
  493. }
  494. mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
  495. mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
  496. mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
  497. memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
  498. spin_lock_init(&ctrl->mbox_lock);
  499. spin_lock_init(&phba->ctrl.mcc_lock);
  500. spin_lock_init(&phba->ctrl.mcc_cq_lock);
  501. return status;
  502. }
  503. static void beiscsi_get_params(struct beiscsi_hba *phba)
  504. {
  505. phba->params.ios_per_ctrl = (phba->fw_config.iscsi_icd_count
  506. - (phba->fw_config.iscsi_cid_count
  507. + BE2_TMFS
  508. + BE2_NOPOUT_REQ));
  509. phba->params.cxns_per_ctrl = phba->fw_config.iscsi_cid_count;
  510. phba->params.asyncpdus_per_ctrl = phba->fw_config.iscsi_cid_count * 2;
  511. phba->params.icds_per_ctrl = phba->fw_config.iscsi_icd_count;
  512. phba->params.num_sge_per_io = BE2_SGE;
  513. phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ;
  514. phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ;
  515. phba->params.eq_timer = 64;
  516. phba->params.num_eq_entries =
  517. (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
  518. + BE2_TMFS) / 512) + 1) * 512;
  519. phba->params.num_eq_entries = (phba->params.num_eq_entries < 1024)
  520. ? 1024 : phba->params.num_eq_entries;
  521. SE_DEBUG(DBG_LVL_8, "phba->params.num_eq_entries=%d\n",
  522. phba->params.num_eq_entries);
  523. phba->params.num_cq_entries =
  524. (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
  525. + BE2_TMFS) / 512) + 1) * 512;
  526. phba->params.wrbs_per_cxn = 256;
  527. }
  528. static void hwi_ring_eq_db(struct beiscsi_hba *phba,
  529. unsigned int id, unsigned int clr_interrupt,
  530. unsigned int num_processed,
  531. unsigned char rearm, unsigned char event)
  532. {
  533. u32 val = 0;
  534. val |= id & DB_EQ_RING_ID_MASK;
  535. if (rearm)
  536. val |= 1 << DB_EQ_REARM_SHIFT;
  537. if (clr_interrupt)
  538. val |= 1 << DB_EQ_CLR_SHIFT;
  539. if (event)
  540. val |= 1 << DB_EQ_EVNT_SHIFT;
  541. val |= num_processed << DB_EQ_NUM_POPPED_SHIFT;
  542. iowrite32(val, phba->db_va + DB_EQ_OFFSET);
  543. }
  544. /**
  545. * be_isr_mcc - The isr routine of the driver.
  546. * @irq: Not used
  547. * @dev_id: Pointer to host adapter structure
  548. */
  549. static irqreturn_t be_isr_mcc(int irq, void *dev_id)
  550. {
  551. struct beiscsi_hba *phba;
  552. struct be_eq_entry *eqe = NULL;
  553. struct be_queue_info *eq;
  554. struct be_queue_info *mcc;
  555. unsigned int num_eq_processed;
  556. struct be_eq_obj *pbe_eq;
  557. unsigned long flags;
  558. pbe_eq = dev_id;
  559. eq = &pbe_eq->q;
  560. phba = pbe_eq->phba;
  561. mcc = &phba->ctrl.mcc_obj.cq;
  562. eqe = queue_tail_node(eq);
  563. if (!eqe)
  564. SE_DEBUG(DBG_LVL_1, "eqe is NULL\n");
  565. num_eq_processed = 0;
  566. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  567. & EQE_VALID_MASK) {
  568. if (((eqe->dw[offsetof(struct amap_eq_entry,
  569. resource_id) / 32] &
  570. EQE_RESID_MASK) >> 16) == mcc->id) {
  571. spin_lock_irqsave(&phba->isr_lock, flags);
  572. phba->todo_mcc_cq = 1;
  573. spin_unlock_irqrestore(&phba->isr_lock, flags);
  574. }
  575. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  576. queue_tail_inc(eq);
  577. eqe = queue_tail_node(eq);
  578. num_eq_processed++;
  579. }
  580. if (phba->todo_mcc_cq)
  581. queue_work(phba->wq, &phba->work_cqs);
  582. if (num_eq_processed)
  583. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
  584. return IRQ_HANDLED;
  585. }
  586. /**
  587. * be_isr_msix - The isr routine of the driver.
  588. * @irq: Not used
  589. * @dev_id: Pointer to host adapter structure
  590. */
  591. static irqreturn_t be_isr_msix(int irq, void *dev_id)
  592. {
  593. struct beiscsi_hba *phba;
  594. struct be_eq_entry *eqe = NULL;
  595. struct be_queue_info *eq;
  596. struct be_queue_info *cq;
  597. unsigned int num_eq_processed;
  598. struct be_eq_obj *pbe_eq;
  599. unsigned long flags;
  600. pbe_eq = dev_id;
  601. eq = &pbe_eq->q;
  602. cq = pbe_eq->cq;
  603. eqe = queue_tail_node(eq);
  604. if (!eqe)
  605. SE_DEBUG(DBG_LVL_1, "eqe is NULL\n");
  606. phba = pbe_eq->phba;
  607. num_eq_processed = 0;
  608. if (blk_iopoll_enabled) {
  609. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  610. & EQE_VALID_MASK) {
  611. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  612. blk_iopoll_sched(&pbe_eq->iopoll);
  613. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  614. queue_tail_inc(eq);
  615. eqe = queue_tail_node(eq);
  616. num_eq_processed++;
  617. }
  618. if (num_eq_processed)
  619. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1);
  620. return IRQ_HANDLED;
  621. } else {
  622. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  623. & EQE_VALID_MASK) {
  624. spin_lock_irqsave(&phba->isr_lock, flags);
  625. phba->todo_cq = 1;
  626. spin_unlock_irqrestore(&phba->isr_lock, flags);
  627. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  628. queue_tail_inc(eq);
  629. eqe = queue_tail_node(eq);
  630. num_eq_processed++;
  631. }
  632. if (phba->todo_cq)
  633. queue_work(phba->wq, &phba->work_cqs);
  634. if (num_eq_processed)
  635. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
  636. return IRQ_HANDLED;
  637. }
  638. }
  639. /**
  640. * be_isr - The isr routine of the driver.
  641. * @irq: Not used
  642. * @dev_id: Pointer to host adapter structure
  643. */
  644. static irqreturn_t be_isr(int irq, void *dev_id)
  645. {
  646. struct beiscsi_hba *phba;
  647. struct hwi_controller *phwi_ctrlr;
  648. struct hwi_context_memory *phwi_context;
  649. struct be_eq_entry *eqe = NULL;
  650. struct be_queue_info *eq;
  651. struct be_queue_info *cq;
  652. struct be_queue_info *mcc;
  653. unsigned long flags, index;
  654. unsigned int num_mcceq_processed, num_ioeq_processed;
  655. struct be_ctrl_info *ctrl;
  656. struct be_eq_obj *pbe_eq;
  657. int isr;
  658. phba = dev_id;
  659. ctrl = &phba->ctrl;
  660. isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET +
  661. (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE));
  662. if (!isr)
  663. return IRQ_NONE;
  664. phwi_ctrlr = phba->phwi_ctrlr;
  665. phwi_context = phwi_ctrlr->phwi_ctxt;
  666. pbe_eq = &phwi_context->be_eq[0];
  667. eq = &phwi_context->be_eq[0].q;
  668. mcc = &phba->ctrl.mcc_obj.cq;
  669. index = 0;
  670. eqe = queue_tail_node(eq);
  671. if (!eqe)
  672. SE_DEBUG(DBG_LVL_1, "eqe is NULL\n");
  673. num_ioeq_processed = 0;
  674. num_mcceq_processed = 0;
  675. if (blk_iopoll_enabled) {
  676. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  677. & EQE_VALID_MASK) {
  678. if (((eqe->dw[offsetof(struct amap_eq_entry,
  679. resource_id) / 32] &
  680. EQE_RESID_MASK) >> 16) == mcc->id) {
  681. spin_lock_irqsave(&phba->isr_lock, flags);
  682. phba->todo_mcc_cq = 1;
  683. spin_unlock_irqrestore(&phba->isr_lock, flags);
  684. num_mcceq_processed++;
  685. } else {
  686. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  687. blk_iopoll_sched(&pbe_eq->iopoll);
  688. num_ioeq_processed++;
  689. }
  690. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  691. queue_tail_inc(eq);
  692. eqe = queue_tail_node(eq);
  693. }
  694. if (num_ioeq_processed || num_mcceq_processed) {
  695. if (phba->todo_mcc_cq)
  696. queue_work(phba->wq, &phba->work_cqs);
  697. if ((num_mcceq_processed) && (!num_ioeq_processed))
  698. hwi_ring_eq_db(phba, eq->id, 0,
  699. (num_ioeq_processed +
  700. num_mcceq_processed) , 1, 1);
  701. else
  702. hwi_ring_eq_db(phba, eq->id, 0,
  703. (num_ioeq_processed +
  704. num_mcceq_processed), 0, 1);
  705. return IRQ_HANDLED;
  706. } else
  707. return IRQ_NONE;
  708. } else {
  709. cq = &phwi_context->be_cq[0];
  710. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  711. & EQE_VALID_MASK) {
  712. if (((eqe->dw[offsetof(struct amap_eq_entry,
  713. resource_id) / 32] &
  714. EQE_RESID_MASK) >> 16) != cq->id) {
  715. spin_lock_irqsave(&phba->isr_lock, flags);
  716. phba->todo_mcc_cq = 1;
  717. spin_unlock_irqrestore(&phba->isr_lock, flags);
  718. } else {
  719. spin_lock_irqsave(&phba->isr_lock, flags);
  720. phba->todo_cq = 1;
  721. spin_unlock_irqrestore(&phba->isr_lock, flags);
  722. }
  723. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  724. queue_tail_inc(eq);
  725. eqe = queue_tail_node(eq);
  726. num_ioeq_processed++;
  727. }
  728. if (phba->todo_cq || phba->todo_mcc_cq)
  729. queue_work(phba->wq, &phba->work_cqs);
  730. if (num_ioeq_processed) {
  731. hwi_ring_eq_db(phba, eq->id, 0,
  732. num_ioeq_processed, 1, 1);
  733. return IRQ_HANDLED;
  734. } else
  735. return IRQ_NONE;
  736. }
  737. }
  738. static int beiscsi_init_irqs(struct beiscsi_hba *phba)
  739. {
  740. struct pci_dev *pcidev = phba->pcidev;
  741. struct hwi_controller *phwi_ctrlr;
  742. struct hwi_context_memory *phwi_context;
  743. int ret, msix_vec, i, j;
  744. phwi_ctrlr = phba->phwi_ctrlr;
  745. phwi_context = phwi_ctrlr->phwi_ctxt;
  746. if (phba->msix_enabled) {
  747. for (i = 0; i < phba->num_cpus; i++) {
  748. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME,
  749. GFP_KERNEL);
  750. if (!phba->msi_name[i]) {
  751. ret = -ENOMEM;
  752. goto free_msix_irqs;
  753. }
  754. sprintf(phba->msi_name[i], "beiscsi_%02x_%02x",
  755. phba->shost->host_no, i);
  756. msix_vec = phba->msix_entries[i].vector;
  757. ret = request_irq(msix_vec, be_isr_msix, 0,
  758. phba->msi_name[i],
  759. &phwi_context->be_eq[i]);
  760. if (ret) {
  761. shost_printk(KERN_ERR, phba->shost,
  762. "beiscsi_init_irqs-Failed to"
  763. "register msix for i = %d\n", i);
  764. kfree(phba->msi_name[i]);
  765. goto free_msix_irqs;
  766. }
  767. }
  768. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL);
  769. if (!phba->msi_name[i]) {
  770. ret = -ENOMEM;
  771. goto free_msix_irqs;
  772. }
  773. sprintf(phba->msi_name[i], "beiscsi_mcc_%02x",
  774. phba->shost->host_no);
  775. msix_vec = phba->msix_entries[i].vector;
  776. ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i],
  777. &phwi_context->be_eq[i]);
  778. if (ret) {
  779. shost_printk(KERN_ERR, phba->shost, "beiscsi_init_irqs-"
  780. "Failed to register beiscsi_msix_mcc\n");
  781. kfree(phba->msi_name[i]);
  782. goto free_msix_irqs;
  783. }
  784. } else {
  785. ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED,
  786. "beiscsi", phba);
  787. if (ret) {
  788. shost_printk(KERN_ERR, phba->shost, "beiscsi_init_irqs-"
  789. "Failed to register irq\\n");
  790. return ret;
  791. }
  792. }
  793. return 0;
  794. free_msix_irqs:
  795. for (j = i - 1; j >= 0; j--) {
  796. kfree(phba->msi_name[j]);
  797. msix_vec = phba->msix_entries[j].vector;
  798. free_irq(msix_vec, &phwi_context->be_eq[j]);
  799. }
  800. return ret;
  801. }
  802. static void hwi_ring_cq_db(struct beiscsi_hba *phba,
  803. unsigned int id, unsigned int num_processed,
  804. unsigned char rearm, unsigned char event)
  805. {
  806. u32 val = 0;
  807. val |= id & DB_CQ_RING_ID_MASK;
  808. if (rearm)
  809. val |= 1 << DB_CQ_REARM_SHIFT;
  810. val |= num_processed << DB_CQ_NUM_POPPED_SHIFT;
  811. iowrite32(val, phba->db_va + DB_CQ_OFFSET);
  812. }
  813. static unsigned int
  814. beiscsi_process_async_pdu(struct beiscsi_conn *beiscsi_conn,
  815. struct beiscsi_hba *phba,
  816. unsigned short cid,
  817. struct pdu_base *ppdu,
  818. unsigned long pdu_len,
  819. void *pbuffer, unsigned long buf_len)
  820. {
  821. struct iscsi_conn *conn = beiscsi_conn->conn;
  822. struct iscsi_session *session = conn->session;
  823. struct iscsi_task *task;
  824. struct beiscsi_io_task *io_task;
  825. struct iscsi_hdr *login_hdr;
  826. switch (ppdu->dw[offsetof(struct amap_pdu_base, opcode) / 32] &
  827. PDUBASE_OPCODE_MASK) {
  828. case ISCSI_OP_NOOP_IN:
  829. pbuffer = NULL;
  830. buf_len = 0;
  831. break;
  832. case ISCSI_OP_ASYNC_EVENT:
  833. break;
  834. case ISCSI_OP_REJECT:
  835. WARN_ON(!pbuffer);
  836. WARN_ON(!(buf_len == 48));
  837. SE_DEBUG(DBG_LVL_1, "In ISCSI_OP_REJECT\n");
  838. break;
  839. case ISCSI_OP_LOGIN_RSP:
  840. case ISCSI_OP_TEXT_RSP:
  841. task = conn->login_task;
  842. io_task = task->dd_data;
  843. login_hdr = (struct iscsi_hdr *)ppdu;
  844. login_hdr->itt = io_task->libiscsi_itt;
  845. break;
  846. default:
  847. shost_printk(KERN_WARNING, phba->shost,
  848. "Unrecognized opcode 0x%x in async msg\n",
  849. (ppdu->
  850. dw[offsetof(struct amap_pdu_base, opcode) / 32]
  851. & PDUBASE_OPCODE_MASK));
  852. return 1;
  853. }
  854. spin_lock_bh(&session->lock);
  855. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)ppdu, pbuffer, buf_len);
  856. spin_unlock_bh(&session->lock);
  857. return 0;
  858. }
  859. static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba)
  860. {
  861. struct sgl_handle *psgl_handle;
  862. if (phba->io_sgl_hndl_avbl) {
  863. SE_DEBUG(DBG_LVL_8,
  864. "In alloc_io_sgl_handle,io_sgl_alloc_index=%d\n",
  865. phba->io_sgl_alloc_index);
  866. psgl_handle = phba->io_sgl_hndl_base[phba->
  867. io_sgl_alloc_index];
  868. phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL;
  869. phba->io_sgl_hndl_avbl--;
  870. if (phba->io_sgl_alloc_index == (phba->params.
  871. ios_per_ctrl - 1))
  872. phba->io_sgl_alloc_index = 0;
  873. else
  874. phba->io_sgl_alloc_index++;
  875. } else
  876. psgl_handle = NULL;
  877. return psgl_handle;
  878. }
  879. static void
  880. free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  881. {
  882. SE_DEBUG(DBG_LVL_8, "In free_,io_sgl_free_index=%d\n",
  883. phba->io_sgl_free_index);
  884. if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) {
  885. /*
  886. * this can happen if clean_task is called on a task that
  887. * failed in xmit_task or alloc_pdu.
  888. */
  889. SE_DEBUG(DBG_LVL_8,
  890. "Double Free in IO SGL io_sgl_free_index=%d,"
  891. "value there=%p\n", phba->io_sgl_free_index,
  892. phba->io_sgl_hndl_base[phba->io_sgl_free_index]);
  893. return;
  894. }
  895. phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle;
  896. phba->io_sgl_hndl_avbl++;
  897. if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1))
  898. phba->io_sgl_free_index = 0;
  899. else
  900. phba->io_sgl_free_index++;
  901. }
  902. /**
  903. * alloc_wrb_handle - To allocate a wrb handle
  904. * @phba: The hba pointer
  905. * @cid: The cid to use for allocation
  906. *
  907. * This happens under session_lock until submission to chip
  908. */
  909. struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid)
  910. {
  911. struct hwi_wrb_context *pwrb_context;
  912. struct hwi_controller *phwi_ctrlr;
  913. struct wrb_handle *pwrb_handle, *pwrb_handle_tmp;
  914. phwi_ctrlr = phba->phwi_ctrlr;
  915. pwrb_context = &phwi_ctrlr->wrb_context[cid];
  916. if (pwrb_context->wrb_handles_available >= 2) {
  917. pwrb_handle = pwrb_context->pwrb_handle_base[
  918. pwrb_context->alloc_index];
  919. pwrb_context->wrb_handles_available--;
  920. if (pwrb_context->alloc_index ==
  921. (phba->params.wrbs_per_cxn - 1))
  922. pwrb_context->alloc_index = 0;
  923. else
  924. pwrb_context->alloc_index++;
  925. pwrb_handle_tmp = pwrb_context->pwrb_handle_base[
  926. pwrb_context->alloc_index];
  927. pwrb_handle->nxt_wrb_index = pwrb_handle_tmp->wrb_index;
  928. } else
  929. pwrb_handle = NULL;
  930. return pwrb_handle;
  931. }
  932. /**
  933. * free_wrb_handle - To free the wrb handle back to pool
  934. * @phba: The hba pointer
  935. * @pwrb_context: The context to free from
  936. * @pwrb_handle: The wrb_handle to free
  937. *
  938. * This happens under session_lock until submission to chip
  939. */
  940. static void
  941. free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context,
  942. struct wrb_handle *pwrb_handle)
  943. {
  944. pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle;
  945. pwrb_context->wrb_handles_available++;
  946. if (pwrb_context->free_index == (phba->params.wrbs_per_cxn - 1))
  947. pwrb_context->free_index = 0;
  948. else
  949. pwrb_context->free_index++;
  950. SE_DEBUG(DBG_LVL_8,
  951. "FREE WRB: pwrb_handle=%p free_index=0x%x"
  952. "wrb_handles_available=%d\n",
  953. pwrb_handle, pwrb_context->free_index,
  954. pwrb_context->wrb_handles_available);
  955. }
  956. static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba)
  957. {
  958. struct sgl_handle *psgl_handle;
  959. if (phba->eh_sgl_hndl_avbl) {
  960. psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index];
  961. phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL;
  962. SE_DEBUG(DBG_LVL_8, "mgmt_sgl_alloc_index=%d=0x%x\n",
  963. phba->eh_sgl_alloc_index, phba->eh_sgl_alloc_index);
  964. phba->eh_sgl_hndl_avbl--;
  965. if (phba->eh_sgl_alloc_index ==
  966. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl -
  967. 1))
  968. phba->eh_sgl_alloc_index = 0;
  969. else
  970. phba->eh_sgl_alloc_index++;
  971. } else
  972. psgl_handle = NULL;
  973. return psgl_handle;
  974. }
  975. void
  976. free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  977. {
  978. SE_DEBUG(DBG_LVL_8, "In free_mgmt_sgl_handle,eh_sgl_free_index=%d\n",
  979. phba->eh_sgl_free_index);
  980. if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) {
  981. /*
  982. * this can happen if clean_task is called on a task that
  983. * failed in xmit_task or alloc_pdu.
  984. */
  985. SE_DEBUG(DBG_LVL_8,
  986. "Double Free in eh SGL ,eh_sgl_free_index=%d\n",
  987. phba->eh_sgl_free_index);
  988. return;
  989. }
  990. phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle;
  991. phba->eh_sgl_hndl_avbl++;
  992. if (phba->eh_sgl_free_index ==
  993. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1))
  994. phba->eh_sgl_free_index = 0;
  995. else
  996. phba->eh_sgl_free_index++;
  997. }
  998. static void
  999. be_complete_io(struct beiscsi_conn *beiscsi_conn,
  1000. struct iscsi_task *task, struct sol_cqe *psol)
  1001. {
  1002. struct beiscsi_io_task *io_task = task->dd_data;
  1003. struct be_status_bhs *sts_bhs =
  1004. (struct be_status_bhs *)io_task->cmd_bhs;
  1005. struct iscsi_conn *conn = beiscsi_conn->conn;
  1006. unsigned char *sense;
  1007. u32 resid = 0, exp_cmdsn, max_cmdsn;
  1008. u8 rsp, status, flags;
  1009. exp_cmdsn = (psol->
  1010. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1011. & SOL_EXP_CMD_SN_MASK);
  1012. max_cmdsn = ((psol->
  1013. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1014. & SOL_EXP_CMD_SN_MASK) +
  1015. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1016. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1017. rsp = ((psol->dw[offsetof(struct amap_sol_cqe, i_resp) / 32]
  1018. & SOL_RESP_MASK) >> 16);
  1019. status = ((psol->dw[offsetof(struct amap_sol_cqe, i_sts) / 32]
  1020. & SOL_STS_MASK) >> 8);
  1021. flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1022. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1023. if (!task->sc) {
  1024. if (io_task->scsi_cmnd)
  1025. scsi_dma_unmap(io_task->scsi_cmnd);
  1026. return;
  1027. }
  1028. task->sc->result = (DID_OK << 16) | status;
  1029. if (rsp != ISCSI_STATUS_CMD_COMPLETED) {
  1030. task->sc->result = DID_ERROR << 16;
  1031. goto unmap;
  1032. }
  1033. /* bidi not initially supported */
  1034. if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) {
  1035. resid = (psol->dw[offsetof(struct amap_sol_cqe, i_res_cnt) /
  1036. 32] & SOL_RES_CNT_MASK);
  1037. if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW))
  1038. task->sc->result = DID_ERROR << 16;
  1039. if (flags & ISCSI_FLAG_CMD_UNDERFLOW) {
  1040. scsi_set_resid(task->sc, resid);
  1041. if (!status && (scsi_bufflen(task->sc) - resid <
  1042. task->sc->underflow))
  1043. task->sc->result = DID_ERROR << 16;
  1044. }
  1045. }
  1046. if (status == SAM_STAT_CHECK_CONDITION) {
  1047. u16 sense_len;
  1048. unsigned short *slen = (unsigned short *)sts_bhs->sense_info;
  1049. sense = sts_bhs->sense_info + sizeof(unsigned short);
  1050. sense_len = be16_to_cpu(*slen);
  1051. memcpy(task->sc->sense_buffer, sense,
  1052. min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE));
  1053. }
  1054. if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ) {
  1055. if (psol->dw[offsetof(struct amap_sol_cqe, i_res_cnt) / 32]
  1056. & SOL_RES_CNT_MASK)
  1057. conn->rxdata_octets += (psol->
  1058. dw[offsetof(struct amap_sol_cqe, i_res_cnt) / 32]
  1059. & SOL_RES_CNT_MASK);
  1060. }
  1061. unmap:
  1062. scsi_dma_unmap(io_task->scsi_cmnd);
  1063. iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn);
  1064. }
  1065. static void
  1066. be_complete_logout(struct beiscsi_conn *beiscsi_conn,
  1067. struct iscsi_task *task, struct sol_cqe *psol)
  1068. {
  1069. struct iscsi_logout_rsp *hdr;
  1070. struct beiscsi_io_task *io_task = task->dd_data;
  1071. struct iscsi_conn *conn = beiscsi_conn->conn;
  1072. hdr = (struct iscsi_logout_rsp *)task->hdr;
  1073. hdr->opcode = ISCSI_OP_LOGOUT_RSP;
  1074. hdr->t2wait = 5;
  1075. hdr->t2retain = 0;
  1076. hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1077. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1078. hdr->response = (psol->dw[offsetof(struct amap_sol_cqe, i_resp) /
  1079. 32] & SOL_RESP_MASK);
  1080. hdr->exp_cmdsn = cpu_to_be32(psol->
  1081. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1082. & SOL_EXP_CMD_SN_MASK);
  1083. hdr->max_cmdsn = be32_to_cpu((psol->
  1084. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1085. & SOL_EXP_CMD_SN_MASK) +
  1086. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1087. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1088. hdr->dlength[0] = 0;
  1089. hdr->dlength[1] = 0;
  1090. hdr->dlength[2] = 0;
  1091. hdr->hlength = 0;
  1092. hdr->itt = io_task->libiscsi_itt;
  1093. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1094. }
  1095. static void
  1096. be_complete_tmf(struct beiscsi_conn *beiscsi_conn,
  1097. struct iscsi_task *task, struct sol_cqe *psol)
  1098. {
  1099. struct iscsi_tm_rsp *hdr;
  1100. struct iscsi_conn *conn = beiscsi_conn->conn;
  1101. struct beiscsi_io_task *io_task = task->dd_data;
  1102. hdr = (struct iscsi_tm_rsp *)task->hdr;
  1103. hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP;
  1104. hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1105. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1106. hdr->response = (psol->dw[offsetof(struct amap_sol_cqe, i_resp) /
  1107. 32] & SOL_RESP_MASK);
  1108. hdr->exp_cmdsn = cpu_to_be32(psol->dw[offsetof(struct amap_sol_cqe,
  1109. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK);
  1110. hdr->max_cmdsn = be32_to_cpu((psol->dw[offsetof(struct amap_sol_cqe,
  1111. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK) +
  1112. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1113. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1114. hdr->itt = io_task->libiscsi_itt;
  1115. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1116. }
  1117. static void
  1118. hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
  1119. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1120. {
  1121. struct hwi_wrb_context *pwrb_context;
  1122. struct wrb_handle *pwrb_handle = NULL;
  1123. struct hwi_controller *phwi_ctrlr;
  1124. struct iscsi_task *task;
  1125. struct beiscsi_io_task *io_task;
  1126. struct iscsi_conn *conn = beiscsi_conn->conn;
  1127. struct iscsi_session *session = conn->session;
  1128. phwi_ctrlr = phba->phwi_ctrlr;
  1129. pwrb_context = &phwi_ctrlr->wrb_context[((psol->
  1130. dw[offsetof(struct amap_sol_cqe, cid) / 32] &
  1131. SOL_CID_MASK) >> 6) -
  1132. phba->fw_config.iscsi_cid_start];
  1133. pwrb_handle = pwrb_context->pwrb_handle_basestd[((psol->
  1134. dw[offsetof(struct amap_sol_cqe, wrb_index) /
  1135. 32] & SOL_WRB_INDEX_MASK) >> 16)];
  1136. task = pwrb_handle->pio_handle;
  1137. io_task = task->dd_data;
  1138. spin_lock_bh(&phba->mgmt_sgl_lock);
  1139. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  1140. spin_unlock_bh(&phba->mgmt_sgl_lock);
  1141. spin_lock_bh(&session->lock);
  1142. free_wrb_handle(phba, pwrb_context, pwrb_handle);
  1143. spin_unlock_bh(&session->lock);
  1144. }
  1145. static void
  1146. be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn,
  1147. struct iscsi_task *task, struct sol_cqe *psol)
  1148. {
  1149. struct iscsi_nopin *hdr;
  1150. struct iscsi_conn *conn = beiscsi_conn->conn;
  1151. struct beiscsi_io_task *io_task = task->dd_data;
  1152. hdr = (struct iscsi_nopin *)task->hdr;
  1153. hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1154. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1155. hdr->exp_cmdsn = cpu_to_be32(psol->dw[offsetof(struct amap_sol_cqe,
  1156. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK);
  1157. hdr->max_cmdsn = be32_to_cpu((psol->dw[offsetof(struct amap_sol_cqe,
  1158. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK) +
  1159. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1160. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1161. hdr->opcode = ISCSI_OP_NOOP_IN;
  1162. hdr->itt = io_task->libiscsi_itt;
  1163. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1164. }
  1165. static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn,
  1166. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1167. {
  1168. struct hwi_wrb_context *pwrb_context;
  1169. struct wrb_handle *pwrb_handle;
  1170. struct iscsi_wrb *pwrb = NULL;
  1171. struct hwi_controller *phwi_ctrlr;
  1172. struct iscsi_task *task;
  1173. unsigned int type;
  1174. struct iscsi_conn *conn = beiscsi_conn->conn;
  1175. struct iscsi_session *session = conn->session;
  1176. phwi_ctrlr = phba->phwi_ctrlr;
  1177. pwrb_context = &phwi_ctrlr->wrb_context[((psol->dw[offsetof
  1178. (struct amap_sol_cqe, cid) / 32]
  1179. & SOL_CID_MASK) >> 6) -
  1180. phba->fw_config.iscsi_cid_start];
  1181. pwrb_handle = pwrb_context->pwrb_handle_basestd[((psol->
  1182. dw[offsetof(struct amap_sol_cqe, wrb_index) /
  1183. 32] & SOL_WRB_INDEX_MASK) >> 16)];
  1184. task = pwrb_handle->pio_handle;
  1185. pwrb = pwrb_handle->pwrb;
  1186. type = (pwrb->dw[offsetof(struct amap_iscsi_wrb, type) / 32] &
  1187. WRB_TYPE_MASK) >> 28;
  1188. spin_lock_bh(&session->lock);
  1189. switch (type) {
  1190. case HWH_TYPE_IO:
  1191. case HWH_TYPE_IO_RD:
  1192. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) ==
  1193. ISCSI_OP_NOOP_OUT)
  1194. be_complete_nopin_resp(beiscsi_conn, task, psol);
  1195. else
  1196. be_complete_io(beiscsi_conn, task, psol);
  1197. break;
  1198. case HWH_TYPE_LOGOUT:
  1199. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT)
  1200. be_complete_logout(beiscsi_conn, task, psol);
  1201. else
  1202. be_complete_tmf(beiscsi_conn, task, psol);
  1203. break;
  1204. case HWH_TYPE_LOGIN:
  1205. SE_DEBUG(DBG_LVL_1,
  1206. "\t\t No HWH_TYPE_LOGIN Expected in hwi_complete_cmd"
  1207. "- Solicited path\n");
  1208. break;
  1209. case HWH_TYPE_NOP:
  1210. be_complete_nopin_resp(beiscsi_conn, task, psol);
  1211. break;
  1212. default:
  1213. shost_printk(KERN_WARNING, phba->shost,
  1214. "In hwi_complete_cmd, unknown type = %d"
  1215. "wrb_index 0x%x CID 0x%x\n", type,
  1216. ((psol->dw[offsetof(struct amap_iscsi_wrb,
  1217. type) / 32] & SOL_WRB_INDEX_MASK) >> 16),
  1218. ((psol->dw[offsetof(struct amap_sol_cqe,
  1219. cid) / 32] & SOL_CID_MASK) >> 6));
  1220. break;
  1221. }
  1222. spin_unlock_bh(&session->lock);
  1223. }
  1224. static struct list_head *hwi_get_async_busy_list(struct hwi_async_pdu_context
  1225. *pasync_ctx, unsigned int is_header,
  1226. unsigned int host_write_ptr)
  1227. {
  1228. if (is_header)
  1229. return &pasync_ctx->async_entry[host_write_ptr].
  1230. header_busy_list;
  1231. else
  1232. return &pasync_ctx->async_entry[host_write_ptr].data_busy_list;
  1233. }
  1234. static struct async_pdu_handle *
  1235. hwi_get_async_handle(struct beiscsi_hba *phba,
  1236. struct beiscsi_conn *beiscsi_conn,
  1237. struct hwi_async_pdu_context *pasync_ctx,
  1238. struct i_t_dpdu_cqe *pdpdu_cqe, unsigned int *pcq_index)
  1239. {
  1240. struct be_bus_address phys_addr;
  1241. struct list_head *pbusy_list;
  1242. struct async_pdu_handle *pasync_handle = NULL;
  1243. unsigned char is_header = 0;
  1244. phys_addr.u.a32.address_lo =
  1245. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, db_addr_lo) / 32] -
  1246. ((pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, dpl) / 32]
  1247. & PDUCQE_DPL_MASK) >> 16);
  1248. phys_addr.u.a32.address_hi =
  1249. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, db_addr_hi) / 32];
  1250. phys_addr.u.a64.address =
  1251. *((unsigned long long *)(&phys_addr.u.a64.address));
  1252. switch (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, code) / 32]
  1253. & PDUCQE_CODE_MASK) {
  1254. case UNSOL_HDR_NOTIFY:
  1255. is_header = 1;
  1256. pbusy_list = hwi_get_async_busy_list(pasync_ctx, 1,
  1257. (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1258. index) / 32] & PDUCQE_INDEX_MASK));
  1259. break;
  1260. case UNSOL_DATA_NOTIFY:
  1261. pbusy_list = hwi_get_async_busy_list(pasync_ctx, 0, (pdpdu_cqe->
  1262. dw[offsetof(struct amap_i_t_dpdu_cqe,
  1263. index) / 32] & PDUCQE_INDEX_MASK));
  1264. break;
  1265. default:
  1266. pbusy_list = NULL;
  1267. shost_printk(KERN_WARNING, phba->shost,
  1268. "Unexpected code=%d\n",
  1269. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1270. code) / 32] & PDUCQE_CODE_MASK);
  1271. return NULL;
  1272. }
  1273. WARN_ON(list_empty(pbusy_list));
  1274. list_for_each_entry(pasync_handle, pbusy_list, link) {
  1275. if (pasync_handle->pa.u.a64.address == phys_addr.u.a64.address)
  1276. break;
  1277. }
  1278. WARN_ON(!pasync_handle);
  1279. pasync_handle->cri = (unsigned short)beiscsi_conn->beiscsi_conn_cid -
  1280. phba->fw_config.iscsi_cid_start;
  1281. pasync_handle->is_header = is_header;
  1282. pasync_handle->buffer_len = ((pdpdu_cqe->
  1283. dw[offsetof(struct amap_i_t_dpdu_cqe, dpl) / 32]
  1284. & PDUCQE_DPL_MASK) >> 16);
  1285. *pcq_index = (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1286. index) / 32] & PDUCQE_INDEX_MASK);
  1287. return pasync_handle;
  1288. }
  1289. static unsigned int
  1290. hwi_update_async_writables(struct hwi_async_pdu_context *pasync_ctx,
  1291. unsigned int is_header, unsigned int cq_index)
  1292. {
  1293. struct list_head *pbusy_list;
  1294. struct async_pdu_handle *pasync_handle;
  1295. unsigned int num_entries, writables = 0;
  1296. unsigned int *pep_read_ptr, *pwritables;
  1297. num_entries = pasync_ctx->num_entries;
  1298. if (is_header) {
  1299. pep_read_ptr = &pasync_ctx->async_header.ep_read_ptr;
  1300. pwritables = &pasync_ctx->async_header.writables;
  1301. } else {
  1302. pep_read_ptr = &pasync_ctx->async_data.ep_read_ptr;
  1303. pwritables = &pasync_ctx->async_data.writables;
  1304. }
  1305. while ((*pep_read_ptr) != cq_index) {
  1306. (*pep_read_ptr)++;
  1307. *pep_read_ptr = (*pep_read_ptr) % num_entries;
  1308. pbusy_list = hwi_get_async_busy_list(pasync_ctx, is_header,
  1309. *pep_read_ptr);
  1310. if (writables == 0)
  1311. WARN_ON(list_empty(pbusy_list));
  1312. if (!list_empty(pbusy_list)) {
  1313. pasync_handle = list_entry(pbusy_list->next,
  1314. struct async_pdu_handle,
  1315. link);
  1316. WARN_ON(!pasync_handle);
  1317. pasync_handle->consumed = 1;
  1318. }
  1319. writables++;
  1320. }
  1321. if (!writables) {
  1322. SE_DEBUG(DBG_LVL_1,
  1323. "Duplicate notification received - index 0x%x!!\n",
  1324. cq_index);
  1325. WARN_ON(1);
  1326. }
  1327. *pwritables = *pwritables + writables;
  1328. return 0;
  1329. }
  1330. static void hwi_free_async_msg(struct beiscsi_hba *phba,
  1331. unsigned int cri)
  1332. {
  1333. struct hwi_controller *phwi_ctrlr;
  1334. struct hwi_async_pdu_context *pasync_ctx;
  1335. struct async_pdu_handle *pasync_handle, *tmp_handle;
  1336. struct list_head *plist;
  1337. phwi_ctrlr = phba->phwi_ctrlr;
  1338. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1339. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1340. list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) {
  1341. list_del(&pasync_handle->link);
  1342. if (pasync_handle->is_header) {
  1343. list_add_tail(&pasync_handle->link,
  1344. &pasync_ctx->async_header.free_list);
  1345. pasync_ctx->async_header.free_entries++;
  1346. } else {
  1347. list_add_tail(&pasync_handle->link,
  1348. &pasync_ctx->async_data.free_list);
  1349. pasync_ctx->async_data.free_entries++;
  1350. }
  1351. }
  1352. INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wait_queue.list);
  1353. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 0;
  1354. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1355. }
  1356. static struct phys_addr *
  1357. hwi_get_ring_address(struct hwi_async_pdu_context *pasync_ctx,
  1358. unsigned int is_header, unsigned int host_write_ptr)
  1359. {
  1360. struct phys_addr *pasync_sge = NULL;
  1361. if (is_header)
  1362. pasync_sge = pasync_ctx->async_header.ring_base;
  1363. else
  1364. pasync_sge = pasync_ctx->async_data.ring_base;
  1365. return pasync_sge + host_write_ptr;
  1366. }
  1367. static void hwi_post_async_buffers(struct beiscsi_hba *phba,
  1368. unsigned int is_header)
  1369. {
  1370. struct hwi_controller *phwi_ctrlr;
  1371. struct hwi_async_pdu_context *pasync_ctx;
  1372. struct async_pdu_handle *pasync_handle;
  1373. struct list_head *pfree_link, *pbusy_list;
  1374. struct phys_addr *pasync_sge;
  1375. unsigned int ring_id, num_entries;
  1376. unsigned int host_write_num;
  1377. unsigned int writables;
  1378. unsigned int i = 0;
  1379. u32 doorbell = 0;
  1380. phwi_ctrlr = phba->phwi_ctrlr;
  1381. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1382. num_entries = pasync_ctx->num_entries;
  1383. if (is_header) {
  1384. writables = min(pasync_ctx->async_header.writables,
  1385. pasync_ctx->async_header.free_entries);
  1386. pfree_link = pasync_ctx->async_header.free_list.next;
  1387. host_write_num = pasync_ctx->async_header.host_write_ptr;
  1388. ring_id = phwi_ctrlr->default_pdu_hdr.id;
  1389. } else {
  1390. writables = min(pasync_ctx->async_data.writables,
  1391. pasync_ctx->async_data.free_entries);
  1392. pfree_link = pasync_ctx->async_data.free_list.next;
  1393. host_write_num = pasync_ctx->async_data.host_write_ptr;
  1394. ring_id = phwi_ctrlr->default_pdu_data.id;
  1395. }
  1396. writables = (writables / 8) * 8;
  1397. if (writables) {
  1398. for (i = 0; i < writables; i++) {
  1399. pbusy_list =
  1400. hwi_get_async_busy_list(pasync_ctx, is_header,
  1401. host_write_num);
  1402. pasync_handle =
  1403. list_entry(pfree_link, struct async_pdu_handle,
  1404. link);
  1405. WARN_ON(!pasync_handle);
  1406. pasync_handle->consumed = 0;
  1407. pfree_link = pfree_link->next;
  1408. pasync_sge = hwi_get_ring_address(pasync_ctx,
  1409. is_header, host_write_num);
  1410. pasync_sge->hi = pasync_handle->pa.u.a32.address_lo;
  1411. pasync_sge->lo = pasync_handle->pa.u.a32.address_hi;
  1412. list_move(&pasync_handle->link, pbusy_list);
  1413. host_write_num++;
  1414. host_write_num = host_write_num % num_entries;
  1415. }
  1416. if (is_header) {
  1417. pasync_ctx->async_header.host_write_ptr =
  1418. host_write_num;
  1419. pasync_ctx->async_header.free_entries -= writables;
  1420. pasync_ctx->async_header.writables -= writables;
  1421. pasync_ctx->async_header.busy_entries += writables;
  1422. } else {
  1423. pasync_ctx->async_data.host_write_ptr = host_write_num;
  1424. pasync_ctx->async_data.free_entries -= writables;
  1425. pasync_ctx->async_data.writables -= writables;
  1426. pasync_ctx->async_data.busy_entries += writables;
  1427. }
  1428. doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK;
  1429. doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT;
  1430. doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT;
  1431. doorbell |= (writables & DB_DEF_PDU_CQPROC_MASK)
  1432. << DB_DEF_PDU_CQPROC_SHIFT;
  1433. iowrite32(doorbell, phba->db_va + DB_RXULP0_OFFSET);
  1434. }
  1435. }
  1436. static void hwi_flush_default_pdu_buffer(struct beiscsi_hba *phba,
  1437. struct beiscsi_conn *beiscsi_conn,
  1438. struct i_t_dpdu_cqe *pdpdu_cqe)
  1439. {
  1440. struct hwi_controller *phwi_ctrlr;
  1441. struct hwi_async_pdu_context *pasync_ctx;
  1442. struct async_pdu_handle *pasync_handle = NULL;
  1443. unsigned int cq_index = -1;
  1444. phwi_ctrlr = phba->phwi_ctrlr;
  1445. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1446. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1447. pdpdu_cqe, &cq_index);
  1448. BUG_ON(pasync_handle->is_header != 0);
  1449. if (pasync_handle->consumed == 0)
  1450. hwi_update_async_writables(pasync_ctx, pasync_handle->is_header,
  1451. cq_index);
  1452. hwi_free_async_msg(phba, pasync_handle->cri);
  1453. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1454. }
  1455. static unsigned int
  1456. hwi_fwd_async_msg(struct beiscsi_conn *beiscsi_conn,
  1457. struct beiscsi_hba *phba,
  1458. struct hwi_async_pdu_context *pasync_ctx, unsigned short cri)
  1459. {
  1460. struct list_head *plist;
  1461. struct async_pdu_handle *pasync_handle;
  1462. void *phdr = NULL;
  1463. unsigned int hdr_len = 0, buf_len = 0;
  1464. unsigned int status, index = 0, offset = 0;
  1465. void *pfirst_buffer = NULL;
  1466. unsigned int num_buf = 0;
  1467. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1468. list_for_each_entry(pasync_handle, plist, link) {
  1469. if (index == 0) {
  1470. phdr = pasync_handle->pbuffer;
  1471. hdr_len = pasync_handle->buffer_len;
  1472. } else {
  1473. buf_len = pasync_handle->buffer_len;
  1474. if (!num_buf) {
  1475. pfirst_buffer = pasync_handle->pbuffer;
  1476. num_buf++;
  1477. }
  1478. memcpy(pfirst_buffer + offset,
  1479. pasync_handle->pbuffer, buf_len);
  1480. offset += buf_len;
  1481. }
  1482. index++;
  1483. }
  1484. status = beiscsi_process_async_pdu(beiscsi_conn, phba,
  1485. (beiscsi_conn->beiscsi_conn_cid -
  1486. phba->fw_config.iscsi_cid_start),
  1487. phdr, hdr_len, pfirst_buffer,
  1488. offset);
  1489. hwi_free_async_msg(phba, cri);
  1490. return 0;
  1491. }
  1492. static unsigned int
  1493. hwi_gather_async_pdu(struct beiscsi_conn *beiscsi_conn,
  1494. struct beiscsi_hba *phba,
  1495. struct async_pdu_handle *pasync_handle)
  1496. {
  1497. struct hwi_async_pdu_context *pasync_ctx;
  1498. struct hwi_controller *phwi_ctrlr;
  1499. unsigned int bytes_needed = 0, status = 0;
  1500. unsigned short cri = pasync_handle->cri;
  1501. struct pdu_base *ppdu;
  1502. phwi_ctrlr = phba->phwi_ctrlr;
  1503. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1504. list_del(&pasync_handle->link);
  1505. if (pasync_handle->is_header) {
  1506. pasync_ctx->async_header.busy_entries--;
  1507. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1508. hwi_free_async_msg(phba, cri);
  1509. BUG();
  1510. }
  1511. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1512. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 1;
  1513. pasync_ctx->async_entry[cri].wait_queue.hdr_len =
  1514. (unsigned short)pasync_handle->buffer_len;
  1515. list_add_tail(&pasync_handle->link,
  1516. &pasync_ctx->async_entry[cri].wait_queue.list);
  1517. ppdu = pasync_handle->pbuffer;
  1518. bytes_needed = ((((ppdu->dw[offsetof(struct amap_pdu_base,
  1519. data_len_hi) / 32] & PDUBASE_DATALENHI_MASK) << 8) &
  1520. 0xFFFF0000) | ((be16_to_cpu((ppdu->
  1521. dw[offsetof(struct amap_pdu_base, data_len_lo) / 32]
  1522. & PDUBASE_DATALENLO_MASK) >> 16)) & 0x0000FFFF));
  1523. if (status == 0) {
  1524. pasync_ctx->async_entry[cri].wait_queue.bytes_needed =
  1525. bytes_needed;
  1526. if (bytes_needed == 0)
  1527. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1528. pasync_ctx, cri);
  1529. }
  1530. } else {
  1531. pasync_ctx->async_data.busy_entries--;
  1532. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1533. list_add_tail(&pasync_handle->link,
  1534. &pasync_ctx->async_entry[cri].wait_queue.
  1535. list);
  1536. pasync_ctx->async_entry[cri].wait_queue.
  1537. bytes_received +=
  1538. (unsigned short)pasync_handle->buffer_len;
  1539. if (pasync_ctx->async_entry[cri].wait_queue.
  1540. bytes_received >=
  1541. pasync_ctx->async_entry[cri].wait_queue.
  1542. bytes_needed)
  1543. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1544. pasync_ctx, cri);
  1545. }
  1546. }
  1547. return status;
  1548. }
  1549. static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn,
  1550. struct beiscsi_hba *phba,
  1551. struct i_t_dpdu_cqe *pdpdu_cqe)
  1552. {
  1553. struct hwi_controller *phwi_ctrlr;
  1554. struct hwi_async_pdu_context *pasync_ctx;
  1555. struct async_pdu_handle *pasync_handle = NULL;
  1556. unsigned int cq_index = -1;
  1557. phwi_ctrlr = phba->phwi_ctrlr;
  1558. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1559. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1560. pdpdu_cqe, &cq_index);
  1561. if (pasync_handle->consumed == 0)
  1562. hwi_update_async_writables(pasync_ctx, pasync_handle->is_header,
  1563. cq_index);
  1564. hwi_gather_async_pdu(beiscsi_conn, phba, pasync_handle);
  1565. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1566. }
  1567. static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba)
  1568. {
  1569. struct be_queue_info *mcc_cq;
  1570. struct be_mcc_compl *mcc_compl;
  1571. unsigned int num_processed = 0;
  1572. mcc_cq = &phba->ctrl.mcc_obj.cq;
  1573. mcc_compl = queue_tail_node(mcc_cq);
  1574. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1575. while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) {
  1576. if (num_processed >= 32) {
  1577. hwi_ring_cq_db(phba, mcc_cq->id,
  1578. num_processed, 0, 0);
  1579. num_processed = 0;
  1580. }
  1581. if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) {
  1582. /* Interpret flags as an async trailer */
  1583. if (is_link_state_evt(mcc_compl->flags))
  1584. /* Interpret compl as a async link evt */
  1585. beiscsi_async_link_state_process(phba,
  1586. (struct be_async_event_link_state *) mcc_compl);
  1587. else
  1588. SE_DEBUG(DBG_LVL_1,
  1589. " Unsupported Async Event, flags"
  1590. " = 0x%08x\n", mcc_compl->flags);
  1591. } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) {
  1592. be_mcc_compl_process_isr(&phba->ctrl, mcc_compl);
  1593. atomic_dec(&phba->ctrl.mcc_obj.q.used);
  1594. }
  1595. mcc_compl->flags = 0;
  1596. queue_tail_inc(mcc_cq);
  1597. mcc_compl = queue_tail_node(mcc_cq);
  1598. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1599. num_processed++;
  1600. }
  1601. if (num_processed > 0)
  1602. hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1, 0);
  1603. }
  1604. static unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq)
  1605. {
  1606. struct be_queue_info *cq;
  1607. struct sol_cqe *sol;
  1608. struct dmsg_cqe *dmsg;
  1609. unsigned int num_processed = 0;
  1610. unsigned int tot_nump = 0;
  1611. struct beiscsi_conn *beiscsi_conn;
  1612. struct beiscsi_endpoint *beiscsi_ep;
  1613. struct iscsi_endpoint *ep;
  1614. struct beiscsi_hba *phba;
  1615. cq = pbe_eq->cq;
  1616. sol = queue_tail_node(cq);
  1617. phba = pbe_eq->phba;
  1618. while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] &
  1619. CQE_VALID_MASK) {
  1620. be_dws_le_to_cpu(sol, sizeof(struct sol_cqe));
  1621. ep = phba->ep_array[(u32) ((sol->
  1622. dw[offsetof(struct amap_sol_cqe, cid) / 32] &
  1623. SOL_CID_MASK) >> 6) -
  1624. phba->fw_config.iscsi_cid_start];
  1625. beiscsi_ep = ep->dd_data;
  1626. beiscsi_conn = beiscsi_ep->conn;
  1627. if (num_processed >= 32) {
  1628. hwi_ring_cq_db(phba, cq->id,
  1629. num_processed, 0, 0);
  1630. tot_nump += num_processed;
  1631. num_processed = 0;
  1632. }
  1633. switch ((u32) sol->dw[offsetof(struct amap_sol_cqe, code) /
  1634. 32] & CQE_CODE_MASK) {
  1635. case SOL_CMD_COMPLETE:
  1636. hwi_complete_cmd(beiscsi_conn, phba, sol);
  1637. break;
  1638. case DRIVERMSG_NOTIFY:
  1639. SE_DEBUG(DBG_LVL_8, "Received DRIVERMSG_NOTIFY\n");
  1640. dmsg = (struct dmsg_cqe *)sol;
  1641. hwi_complete_drvr_msgs(beiscsi_conn, phba, sol);
  1642. break;
  1643. case UNSOL_HDR_NOTIFY:
  1644. SE_DEBUG(DBG_LVL_8, "Received UNSOL_HDR_ NOTIFY\n");
  1645. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1646. (struct i_t_dpdu_cqe *)sol);
  1647. break;
  1648. case UNSOL_DATA_NOTIFY:
  1649. SE_DEBUG(DBG_LVL_8, "Received UNSOL_DATA_NOTIFY\n");
  1650. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1651. (struct i_t_dpdu_cqe *)sol);
  1652. break;
  1653. case CXN_INVALIDATE_INDEX_NOTIFY:
  1654. case CMD_INVALIDATED_NOTIFY:
  1655. case CXN_INVALIDATE_NOTIFY:
  1656. SE_DEBUG(DBG_LVL_1,
  1657. "Ignoring CQ Error notification for cmd/cxn"
  1658. "invalidate\n");
  1659. break;
  1660. case SOL_CMD_KILLED_DATA_DIGEST_ERR:
  1661. case CMD_KILLED_INVALID_STATSN_RCVD:
  1662. case CMD_KILLED_INVALID_R2T_RCVD:
  1663. case CMD_CXN_KILLED_LUN_INVALID:
  1664. case CMD_CXN_KILLED_ICD_INVALID:
  1665. case CMD_CXN_KILLED_ITT_INVALID:
  1666. case CMD_CXN_KILLED_SEQ_OUTOFORDER:
  1667. case CMD_CXN_KILLED_INVALID_DATASN_RCVD:
  1668. SE_DEBUG(DBG_LVL_1,
  1669. "CQ Error notification for cmd.. "
  1670. "code %d cid 0x%x\n",
  1671. sol->dw[offsetof(struct amap_sol_cqe, code) /
  1672. 32] & CQE_CODE_MASK,
  1673. (sol->dw[offsetof(struct amap_sol_cqe, cid) /
  1674. 32] & SOL_CID_MASK));
  1675. break;
  1676. case UNSOL_DATA_DIGEST_ERROR_NOTIFY:
  1677. SE_DEBUG(DBG_LVL_1,
  1678. "Digest error on def pdu ring, dropping..\n");
  1679. hwi_flush_default_pdu_buffer(phba, beiscsi_conn,
  1680. (struct i_t_dpdu_cqe *) sol);
  1681. break;
  1682. case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL:
  1683. case CXN_KILLED_BURST_LEN_MISMATCH:
  1684. case CXN_KILLED_AHS_RCVD:
  1685. case CXN_KILLED_HDR_DIGEST_ERR:
  1686. case CXN_KILLED_UNKNOWN_HDR:
  1687. case CXN_KILLED_STALE_ITT_TTT_RCVD:
  1688. case CXN_KILLED_INVALID_ITT_TTT_RCVD:
  1689. case CXN_KILLED_TIMED_OUT:
  1690. case CXN_KILLED_FIN_RCVD:
  1691. case CXN_KILLED_BAD_UNSOL_PDU_RCVD:
  1692. case CXN_KILLED_BAD_WRB_INDEX_ERROR:
  1693. case CXN_KILLED_OVER_RUN_RESIDUAL:
  1694. case CXN_KILLED_UNDER_RUN_RESIDUAL:
  1695. case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN:
  1696. SE_DEBUG(DBG_LVL_1, "CQ Error %d, reset CID "
  1697. "0x%x...\n",
  1698. sol->dw[offsetof(struct amap_sol_cqe, code) /
  1699. 32] & CQE_CODE_MASK,
  1700. (sol->dw[offsetof(struct amap_sol_cqe, cid) /
  1701. 32] & CQE_CID_MASK));
  1702. iscsi_conn_failure(beiscsi_conn->conn,
  1703. ISCSI_ERR_CONN_FAILED);
  1704. break;
  1705. case CXN_KILLED_RST_SENT:
  1706. case CXN_KILLED_RST_RCVD:
  1707. SE_DEBUG(DBG_LVL_1, "CQ Error %d, reset"
  1708. "received/sent on CID 0x%x...\n",
  1709. sol->dw[offsetof(struct amap_sol_cqe, code) /
  1710. 32] & CQE_CODE_MASK,
  1711. (sol->dw[offsetof(struct amap_sol_cqe, cid) /
  1712. 32] & CQE_CID_MASK));
  1713. iscsi_conn_failure(beiscsi_conn->conn,
  1714. ISCSI_ERR_CONN_FAILED);
  1715. break;
  1716. default:
  1717. SE_DEBUG(DBG_LVL_1, "CQ Error Invalid code= %d "
  1718. "received on CID 0x%x...\n",
  1719. sol->dw[offsetof(struct amap_sol_cqe, code) /
  1720. 32] & CQE_CODE_MASK,
  1721. (sol->dw[offsetof(struct amap_sol_cqe, cid) /
  1722. 32] & CQE_CID_MASK));
  1723. break;
  1724. }
  1725. AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0);
  1726. queue_tail_inc(cq);
  1727. sol = queue_tail_node(cq);
  1728. num_processed++;
  1729. }
  1730. if (num_processed > 0) {
  1731. tot_nump += num_processed;
  1732. hwi_ring_cq_db(phba, cq->id, num_processed, 1, 0);
  1733. }
  1734. return tot_nump;
  1735. }
  1736. void beiscsi_process_all_cqs(struct work_struct *work)
  1737. {
  1738. unsigned long flags;
  1739. struct hwi_controller *phwi_ctrlr;
  1740. struct hwi_context_memory *phwi_context;
  1741. struct be_eq_obj *pbe_eq;
  1742. struct beiscsi_hba *phba =
  1743. container_of(work, struct beiscsi_hba, work_cqs);
  1744. phwi_ctrlr = phba->phwi_ctrlr;
  1745. phwi_context = phwi_ctrlr->phwi_ctxt;
  1746. if (phba->msix_enabled)
  1747. pbe_eq = &phwi_context->be_eq[phba->num_cpus];
  1748. else
  1749. pbe_eq = &phwi_context->be_eq[0];
  1750. if (phba->todo_mcc_cq) {
  1751. spin_lock_irqsave(&phba->isr_lock, flags);
  1752. phba->todo_mcc_cq = 0;
  1753. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1754. beiscsi_process_mcc_isr(phba);
  1755. }
  1756. if (phba->todo_cq) {
  1757. spin_lock_irqsave(&phba->isr_lock, flags);
  1758. phba->todo_cq = 0;
  1759. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1760. beiscsi_process_cq(pbe_eq);
  1761. }
  1762. }
  1763. static int be_iopoll(struct blk_iopoll *iop, int budget)
  1764. {
  1765. static unsigned int ret;
  1766. struct beiscsi_hba *phba;
  1767. struct be_eq_obj *pbe_eq;
  1768. pbe_eq = container_of(iop, struct be_eq_obj, iopoll);
  1769. ret = beiscsi_process_cq(pbe_eq);
  1770. if (ret < budget) {
  1771. phba = pbe_eq->phba;
  1772. blk_iopoll_complete(iop);
  1773. SE_DEBUG(DBG_LVL_8, "rearm pbe_eq->q.id =%d\n", pbe_eq->q.id);
  1774. hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
  1775. }
  1776. return ret;
  1777. }
  1778. static void
  1779. hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg,
  1780. unsigned int num_sg, struct beiscsi_io_task *io_task)
  1781. {
  1782. struct iscsi_sge *psgl;
  1783. unsigned int sg_len, index;
  1784. unsigned int sge_len = 0;
  1785. unsigned long long addr;
  1786. struct scatterlist *l_sg;
  1787. unsigned int offset;
  1788. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  1789. io_task->bhs_pa.u.a32.address_lo);
  1790. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  1791. io_task->bhs_pa.u.a32.address_hi);
  1792. l_sg = sg;
  1793. for (index = 0; (index < num_sg) && (index < 2); index++,
  1794. sg = sg_next(sg)) {
  1795. if (index == 0) {
  1796. sg_len = sg_dma_len(sg);
  1797. addr = (u64) sg_dma_address(sg);
  1798. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  1799. ((u32)(addr & 0xFFFFFFFF)));
  1800. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  1801. ((u32)(addr >> 32)));
  1802. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  1803. sg_len);
  1804. sge_len = sg_len;
  1805. } else {
  1806. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset,
  1807. pwrb, sge_len);
  1808. sg_len = sg_dma_len(sg);
  1809. addr = (u64) sg_dma_address(sg);
  1810. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb,
  1811. ((u32)(addr & 0xFFFFFFFF)));
  1812. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb,
  1813. ((u32)(addr >> 32)));
  1814. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb,
  1815. sg_len);
  1816. }
  1817. }
  1818. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  1819. memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
  1820. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
  1821. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  1822. io_task->bhs_pa.u.a32.address_hi);
  1823. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  1824. io_task->bhs_pa.u.a32.address_lo);
  1825. if (num_sg == 1) {
  1826. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  1827. 1);
  1828. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  1829. 0);
  1830. } else if (num_sg == 2) {
  1831. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  1832. 0);
  1833. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  1834. 1);
  1835. } else {
  1836. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  1837. 0);
  1838. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  1839. 0);
  1840. }
  1841. sg = l_sg;
  1842. psgl++;
  1843. psgl++;
  1844. offset = 0;
  1845. for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
  1846. sg_len = sg_dma_len(sg);
  1847. addr = (u64) sg_dma_address(sg);
  1848. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  1849. (addr & 0xFFFFFFFF));
  1850. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  1851. (addr >> 32));
  1852. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
  1853. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
  1854. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  1855. offset += sg_len;
  1856. }
  1857. psgl--;
  1858. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  1859. }
  1860. static void hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task)
  1861. {
  1862. struct iscsi_sge *psgl;
  1863. unsigned long long addr;
  1864. struct beiscsi_io_task *io_task = task->dd_data;
  1865. struct beiscsi_conn *beiscsi_conn = io_task->conn;
  1866. struct beiscsi_hba *phba = beiscsi_conn->phba;
  1867. io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2;
  1868. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  1869. io_task->bhs_pa.u.a32.address_lo);
  1870. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  1871. io_task->bhs_pa.u.a32.address_hi);
  1872. if (task->data) {
  1873. if (task->data_count) {
  1874. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
  1875. addr = (u64) pci_map_single(phba->pcidev,
  1876. task->data,
  1877. task->data_count, 1);
  1878. } else {
  1879. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  1880. addr = 0;
  1881. }
  1882. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  1883. ((u32)(addr & 0xFFFFFFFF)));
  1884. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  1885. ((u32)(addr >> 32)));
  1886. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  1887. task->data_count);
  1888. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1);
  1889. } else {
  1890. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  1891. addr = 0;
  1892. }
  1893. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  1894. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len);
  1895. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  1896. io_task->bhs_pa.u.a32.address_hi);
  1897. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  1898. io_task->bhs_pa.u.a32.address_lo);
  1899. if (task->data) {
  1900. psgl++;
  1901. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0);
  1902. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0);
  1903. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0);
  1904. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0);
  1905. AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0);
  1906. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  1907. psgl++;
  1908. if (task->data) {
  1909. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  1910. ((u32)(addr & 0xFFFFFFFF)));
  1911. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  1912. ((u32)(addr >> 32)));
  1913. }
  1914. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106);
  1915. }
  1916. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  1917. }
  1918. static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
  1919. {
  1920. unsigned int num_cq_pages, num_async_pdu_buf_pages;
  1921. unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn;
  1922. unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages;
  1923. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  1924. sizeof(struct sol_cqe));
  1925. num_async_pdu_buf_pages =
  1926. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  1927. phba->params.defpdu_hdr_sz);
  1928. num_async_pdu_buf_sgl_pages =
  1929. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  1930. sizeof(struct phys_addr));
  1931. num_async_pdu_data_pages =
  1932. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  1933. phba->params.defpdu_data_sz);
  1934. num_async_pdu_data_sgl_pages =
  1935. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  1936. sizeof(struct phys_addr));
  1937. phba->params.hwi_ws_sz = sizeof(struct hwi_controller);
  1938. phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 *
  1939. BE_ISCSI_PDU_HEADER_SIZE;
  1940. phba->mem_req[HWI_MEM_ADDN_CONTEXT] =
  1941. sizeof(struct hwi_context_memory);
  1942. phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb)
  1943. * (phba->params.wrbs_per_cxn)
  1944. * phba->params.cxns_per_ctrl;
  1945. wrb_sz_per_cxn = sizeof(struct wrb_handle) *
  1946. (phba->params.wrbs_per_cxn);
  1947. phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) *
  1948. phba->params.cxns_per_ctrl);
  1949. phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) *
  1950. phba->params.icds_per_ctrl;
  1951. phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
  1952. phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
  1953. phba->mem_req[HWI_MEM_ASYNC_HEADER_BUF] =
  1954. num_async_pdu_buf_pages * PAGE_SIZE;
  1955. phba->mem_req[HWI_MEM_ASYNC_DATA_BUF] =
  1956. num_async_pdu_data_pages * PAGE_SIZE;
  1957. phba->mem_req[HWI_MEM_ASYNC_HEADER_RING] =
  1958. num_async_pdu_buf_sgl_pages * PAGE_SIZE;
  1959. phba->mem_req[HWI_MEM_ASYNC_DATA_RING] =
  1960. num_async_pdu_data_sgl_pages * PAGE_SIZE;
  1961. phba->mem_req[HWI_MEM_ASYNC_HEADER_HANDLE] =
  1962. phba->params.asyncpdus_per_ctrl *
  1963. sizeof(struct async_pdu_handle);
  1964. phba->mem_req[HWI_MEM_ASYNC_DATA_HANDLE] =
  1965. phba->params.asyncpdus_per_ctrl *
  1966. sizeof(struct async_pdu_handle);
  1967. phba->mem_req[HWI_MEM_ASYNC_PDU_CONTEXT] =
  1968. sizeof(struct hwi_async_pdu_context) +
  1969. (phba->params.cxns_per_ctrl * sizeof(struct hwi_async_entry));
  1970. }
  1971. static int beiscsi_alloc_mem(struct beiscsi_hba *phba)
  1972. {
  1973. struct be_mem_descriptor *mem_descr;
  1974. dma_addr_t bus_add;
  1975. struct mem_array *mem_arr, *mem_arr_orig;
  1976. unsigned int i, j, alloc_size, curr_alloc_size;
  1977. phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL);
  1978. if (!phba->phwi_ctrlr)
  1979. return -ENOMEM;
  1980. phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr),
  1981. GFP_KERNEL);
  1982. if (!phba->init_mem) {
  1983. kfree(phba->phwi_ctrlr);
  1984. return -ENOMEM;
  1985. }
  1986. mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT,
  1987. GFP_KERNEL);
  1988. if (!mem_arr_orig) {
  1989. kfree(phba->init_mem);
  1990. kfree(phba->phwi_ctrlr);
  1991. return -ENOMEM;
  1992. }
  1993. mem_descr = phba->init_mem;
  1994. for (i = 0; i < SE_MEM_MAX; i++) {
  1995. j = 0;
  1996. mem_arr = mem_arr_orig;
  1997. alloc_size = phba->mem_req[i];
  1998. memset(mem_arr, 0, sizeof(struct mem_array) *
  1999. BEISCSI_MAX_FRAGS_INIT);
  2000. curr_alloc_size = min(be_max_phys_size * 1024, alloc_size);
  2001. do {
  2002. mem_arr->virtual_address = pci_alloc_consistent(
  2003. phba->pcidev,
  2004. curr_alloc_size,
  2005. &bus_add);
  2006. if (!mem_arr->virtual_address) {
  2007. if (curr_alloc_size <= BE_MIN_MEM_SIZE)
  2008. goto free_mem;
  2009. if (curr_alloc_size -
  2010. rounddown_pow_of_two(curr_alloc_size))
  2011. curr_alloc_size = rounddown_pow_of_two
  2012. (curr_alloc_size);
  2013. else
  2014. curr_alloc_size = curr_alloc_size / 2;
  2015. } else {
  2016. mem_arr->bus_address.u.
  2017. a64.address = (__u64) bus_add;
  2018. mem_arr->size = curr_alloc_size;
  2019. alloc_size -= curr_alloc_size;
  2020. curr_alloc_size = min(be_max_phys_size *
  2021. 1024, alloc_size);
  2022. j++;
  2023. mem_arr++;
  2024. }
  2025. } while (alloc_size);
  2026. mem_descr->num_elements = j;
  2027. mem_descr->size_in_bytes = phba->mem_req[i];
  2028. mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j,
  2029. GFP_KERNEL);
  2030. if (!mem_descr->mem_array)
  2031. goto free_mem;
  2032. memcpy(mem_descr->mem_array, mem_arr_orig,
  2033. sizeof(struct mem_array) * j);
  2034. mem_descr++;
  2035. }
  2036. kfree(mem_arr_orig);
  2037. return 0;
  2038. free_mem:
  2039. mem_descr->num_elements = j;
  2040. while ((i) || (j)) {
  2041. for (j = mem_descr->num_elements; j > 0; j--) {
  2042. pci_free_consistent(phba->pcidev,
  2043. mem_descr->mem_array[j - 1].size,
  2044. mem_descr->mem_array[j - 1].
  2045. virtual_address,
  2046. (unsigned long)mem_descr->
  2047. mem_array[j - 1].
  2048. bus_address.u.a64.address);
  2049. }
  2050. if (i) {
  2051. i--;
  2052. kfree(mem_descr->mem_array);
  2053. mem_descr--;
  2054. }
  2055. }
  2056. kfree(mem_arr_orig);
  2057. kfree(phba->init_mem);
  2058. kfree(phba->phwi_ctrlr);
  2059. return -ENOMEM;
  2060. }
  2061. static int beiscsi_get_memory(struct beiscsi_hba *phba)
  2062. {
  2063. beiscsi_find_mem_req(phba);
  2064. return beiscsi_alloc_mem(phba);
  2065. }
  2066. static void iscsi_init_global_templates(struct beiscsi_hba *phba)
  2067. {
  2068. struct pdu_data_out *pdata_out;
  2069. struct pdu_nop_out *pnop_out;
  2070. struct be_mem_descriptor *mem_descr;
  2071. mem_descr = phba->init_mem;
  2072. mem_descr += ISCSI_MEM_GLOBAL_HEADER;
  2073. pdata_out =
  2074. (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address;
  2075. memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2076. AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out,
  2077. IIOC_SCSI_DATA);
  2078. pnop_out =
  2079. (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0].
  2080. virtual_address + BE_ISCSI_PDU_HEADER_SIZE);
  2081. memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2082. AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF);
  2083. AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1);
  2084. AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0);
  2085. }
  2086. static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba)
  2087. {
  2088. struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb;
  2089. struct wrb_handle *pwrb_handle = NULL;
  2090. struct hwi_controller *phwi_ctrlr;
  2091. struct hwi_wrb_context *pwrb_context;
  2092. struct iscsi_wrb *pwrb = NULL;
  2093. unsigned int num_cxn_wrbh = 0;
  2094. unsigned int num_cxn_wrb = 0, j, idx = 0, index;
  2095. mem_descr_wrbh = phba->init_mem;
  2096. mem_descr_wrbh += HWI_MEM_WRBH;
  2097. mem_descr_wrb = phba->init_mem;
  2098. mem_descr_wrb += HWI_MEM_WRB;
  2099. phwi_ctrlr = phba->phwi_ctrlr;
  2100. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2101. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2102. pwrb_context->pwrb_handle_base =
  2103. kzalloc(sizeof(struct wrb_handle *) *
  2104. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2105. if (!pwrb_context->pwrb_handle_base) {
  2106. shost_printk(KERN_ERR, phba->shost,
  2107. "Mem Alloc Failed. Failing to load\n");
  2108. goto init_wrb_hndl_failed;
  2109. }
  2110. pwrb_context->pwrb_handle_basestd =
  2111. kzalloc(sizeof(struct wrb_handle *) *
  2112. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2113. if (!pwrb_context->pwrb_handle_basestd) {
  2114. shost_printk(KERN_ERR, phba->shost,
  2115. "Mem Alloc Failed. Failing to load\n");
  2116. goto init_wrb_hndl_failed;
  2117. }
  2118. if (!num_cxn_wrbh) {
  2119. pwrb_handle =
  2120. mem_descr_wrbh->mem_array[idx].virtual_address;
  2121. num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) /
  2122. ((sizeof(struct wrb_handle)) *
  2123. phba->params.wrbs_per_cxn));
  2124. idx++;
  2125. }
  2126. pwrb_context->alloc_index = 0;
  2127. pwrb_context->wrb_handles_available = 0;
  2128. pwrb_context->free_index = 0;
  2129. if (num_cxn_wrbh) {
  2130. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2131. pwrb_context->pwrb_handle_base[j] = pwrb_handle;
  2132. pwrb_context->pwrb_handle_basestd[j] =
  2133. pwrb_handle;
  2134. pwrb_context->wrb_handles_available++;
  2135. pwrb_handle->wrb_index = j;
  2136. pwrb_handle++;
  2137. }
  2138. num_cxn_wrbh--;
  2139. }
  2140. }
  2141. idx = 0;
  2142. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2143. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2144. if (!num_cxn_wrb) {
  2145. pwrb = mem_descr_wrb->mem_array[idx].virtual_address;
  2146. num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) /
  2147. ((sizeof(struct iscsi_wrb) *
  2148. phba->params.wrbs_per_cxn));
  2149. idx++;
  2150. }
  2151. if (num_cxn_wrb) {
  2152. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2153. pwrb_handle = pwrb_context->pwrb_handle_base[j];
  2154. pwrb_handle->pwrb = pwrb;
  2155. pwrb++;
  2156. }
  2157. num_cxn_wrb--;
  2158. }
  2159. }
  2160. return 0;
  2161. init_wrb_hndl_failed:
  2162. for (j = index; j > 0; j--) {
  2163. pwrb_context = &phwi_ctrlr->wrb_context[j];
  2164. kfree(pwrb_context->pwrb_handle_base);
  2165. kfree(pwrb_context->pwrb_handle_basestd);
  2166. }
  2167. return -ENOMEM;
  2168. }
  2169. static void hwi_init_async_pdu_ctx(struct beiscsi_hba *phba)
  2170. {
  2171. struct hwi_controller *phwi_ctrlr;
  2172. struct hba_parameters *p = &phba->params;
  2173. struct hwi_async_pdu_context *pasync_ctx;
  2174. struct async_pdu_handle *pasync_header_h, *pasync_data_h;
  2175. unsigned int index, idx, num_per_mem, num_async_data;
  2176. struct be_mem_descriptor *mem_descr;
  2177. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2178. mem_descr += HWI_MEM_ASYNC_PDU_CONTEXT;
  2179. phwi_ctrlr = phba->phwi_ctrlr;
  2180. phwi_ctrlr->phwi_ctxt->pasync_ctx = (struct hwi_async_pdu_context *)
  2181. mem_descr->mem_array[0].virtual_address;
  2182. pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx;
  2183. memset(pasync_ctx, 0, sizeof(*pasync_ctx));
  2184. pasync_ctx->num_entries = p->asyncpdus_per_ctrl;
  2185. pasync_ctx->buffer_size = p->defpdu_hdr_sz;
  2186. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2187. mem_descr += HWI_MEM_ASYNC_HEADER_BUF;
  2188. if (mem_descr->mem_array[0].virtual_address) {
  2189. SE_DEBUG(DBG_LVL_8,
  2190. "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_HEADER_BUF"
  2191. "va=%p\n", mem_descr->mem_array[0].virtual_address);
  2192. } else
  2193. shost_printk(KERN_WARNING, phba->shost,
  2194. "No Virtual address\n");
  2195. pasync_ctx->async_header.va_base =
  2196. mem_descr->mem_array[0].virtual_address;
  2197. pasync_ctx->async_header.pa_base.u.a64.address =
  2198. mem_descr->mem_array[0].bus_address.u.a64.address;
  2199. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2200. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2201. if (mem_descr->mem_array[0].virtual_address) {
  2202. SE_DEBUG(DBG_LVL_8,
  2203. "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_HEADER_RING"
  2204. "va=%p\n", mem_descr->mem_array[0].virtual_address);
  2205. } else
  2206. shost_printk(KERN_WARNING, phba->shost,
  2207. "No Virtual address\n");
  2208. pasync_ctx->async_header.ring_base =
  2209. mem_descr->mem_array[0].virtual_address;
  2210. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2211. mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE;
  2212. if (mem_descr->mem_array[0].virtual_address) {
  2213. SE_DEBUG(DBG_LVL_8,
  2214. "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_HEADER_HANDLE"
  2215. "va=%p\n", mem_descr->mem_array[0].virtual_address);
  2216. } else
  2217. shost_printk(KERN_WARNING, phba->shost,
  2218. "No Virtual address\n");
  2219. pasync_ctx->async_header.handle_base =
  2220. mem_descr->mem_array[0].virtual_address;
  2221. pasync_ctx->async_header.writables = 0;
  2222. INIT_LIST_HEAD(&pasync_ctx->async_header.free_list);
  2223. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2224. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2225. if (mem_descr->mem_array[0].virtual_address) {
  2226. SE_DEBUG(DBG_LVL_8,
  2227. "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_DATA_RING"
  2228. "va=%p\n", mem_descr->mem_array[0].virtual_address);
  2229. } else
  2230. shost_printk(KERN_WARNING, phba->shost,
  2231. "No Virtual address\n");
  2232. pasync_ctx->async_data.ring_base =
  2233. mem_descr->mem_array[0].virtual_address;
  2234. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2235. mem_descr += HWI_MEM_ASYNC_DATA_HANDLE;
  2236. if (!mem_descr->mem_array[0].virtual_address)
  2237. shost_printk(KERN_WARNING, phba->shost,
  2238. "No Virtual address\n");
  2239. pasync_ctx->async_data.handle_base =
  2240. mem_descr->mem_array[0].virtual_address;
  2241. pasync_ctx->async_data.writables = 0;
  2242. INIT_LIST_HEAD(&pasync_ctx->async_data.free_list);
  2243. pasync_header_h =
  2244. (struct async_pdu_handle *)pasync_ctx->async_header.handle_base;
  2245. pasync_data_h =
  2246. (struct async_pdu_handle *)pasync_ctx->async_data.handle_base;
  2247. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2248. mem_descr += HWI_MEM_ASYNC_DATA_BUF;
  2249. if (mem_descr->mem_array[0].virtual_address) {
  2250. SE_DEBUG(DBG_LVL_8,
  2251. "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_DATA_BUF"
  2252. "va=%p\n", mem_descr->mem_array[0].virtual_address);
  2253. } else
  2254. shost_printk(KERN_WARNING, phba->shost,
  2255. "No Virtual address\n");
  2256. idx = 0;
  2257. pasync_ctx->async_data.va_base =
  2258. mem_descr->mem_array[idx].virtual_address;
  2259. pasync_ctx->async_data.pa_base.u.a64.address =
  2260. mem_descr->mem_array[idx].bus_address.u.a64.address;
  2261. num_async_data = ((mem_descr->mem_array[idx].size) /
  2262. phba->params.defpdu_data_sz);
  2263. num_per_mem = 0;
  2264. for (index = 0; index < p->asyncpdus_per_ctrl; index++) {
  2265. pasync_header_h->cri = -1;
  2266. pasync_header_h->index = (char)index;
  2267. INIT_LIST_HEAD(&pasync_header_h->link);
  2268. pasync_header_h->pbuffer =
  2269. (void *)((unsigned long)
  2270. (pasync_ctx->async_header.va_base) +
  2271. (p->defpdu_hdr_sz * index));
  2272. pasync_header_h->pa.u.a64.address =
  2273. pasync_ctx->async_header.pa_base.u.a64.address +
  2274. (p->defpdu_hdr_sz * index);
  2275. list_add_tail(&pasync_header_h->link,
  2276. &pasync_ctx->async_header.free_list);
  2277. pasync_header_h++;
  2278. pasync_ctx->async_header.free_entries++;
  2279. pasync_ctx->async_header.writables++;
  2280. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].wait_queue.list);
  2281. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
  2282. header_busy_list);
  2283. pasync_data_h->cri = -1;
  2284. pasync_data_h->index = (char)index;
  2285. INIT_LIST_HEAD(&pasync_data_h->link);
  2286. if (!num_async_data) {
  2287. num_per_mem = 0;
  2288. idx++;
  2289. pasync_ctx->async_data.va_base =
  2290. mem_descr->mem_array[idx].virtual_address;
  2291. pasync_ctx->async_data.pa_base.u.a64.address =
  2292. mem_descr->mem_array[idx].
  2293. bus_address.u.a64.address;
  2294. num_async_data = ((mem_descr->mem_array[idx].size) /
  2295. phba->params.defpdu_data_sz);
  2296. }
  2297. pasync_data_h->pbuffer =
  2298. (void *)((unsigned long)
  2299. (pasync_ctx->async_data.va_base) +
  2300. (p->defpdu_data_sz * num_per_mem));
  2301. pasync_data_h->pa.u.a64.address =
  2302. pasync_ctx->async_data.pa_base.u.a64.address +
  2303. (p->defpdu_data_sz * num_per_mem);
  2304. num_per_mem++;
  2305. num_async_data--;
  2306. list_add_tail(&pasync_data_h->link,
  2307. &pasync_ctx->async_data.free_list);
  2308. pasync_data_h++;
  2309. pasync_ctx->async_data.free_entries++;
  2310. pasync_ctx->async_data.writables++;
  2311. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].data_busy_list);
  2312. }
  2313. pasync_ctx->async_header.host_write_ptr = 0;
  2314. pasync_ctx->async_header.ep_read_ptr = -1;
  2315. pasync_ctx->async_data.host_write_ptr = 0;
  2316. pasync_ctx->async_data.ep_read_ptr = -1;
  2317. }
  2318. static int
  2319. be_sgl_create_contiguous(void *virtual_address,
  2320. u64 physical_address, u32 length,
  2321. struct be_dma_mem *sgl)
  2322. {
  2323. WARN_ON(!virtual_address);
  2324. WARN_ON(!physical_address);
  2325. WARN_ON(!length > 0);
  2326. WARN_ON(!sgl);
  2327. sgl->va = virtual_address;
  2328. sgl->dma = (unsigned long)physical_address;
  2329. sgl->size = length;
  2330. return 0;
  2331. }
  2332. static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl)
  2333. {
  2334. memset(sgl, 0, sizeof(*sgl));
  2335. }
  2336. static void
  2337. hwi_build_be_sgl_arr(struct beiscsi_hba *phba,
  2338. struct mem_array *pmem, struct be_dma_mem *sgl)
  2339. {
  2340. if (sgl->va)
  2341. be_sgl_destroy_contiguous(sgl);
  2342. be_sgl_create_contiguous(pmem->virtual_address,
  2343. pmem->bus_address.u.a64.address,
  2344. pmem->size, sgl);
  2345. }
  2346. static void
  2347. hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba,
  2348. struct mem_array *pmem, struct be_dma_mem *sgl)
  2349. {
  2350. if (sgl->va)
  2351. be_sgl_destroy_contiguous(sgl);
  2352. be_sgl_create_contiguous((unsigned char *)pmem->virtual_address,
  2353. pmem->bus_address.u.a64.address,
  2354. pmem->size, sgl);
  2355. }
  2356. static int be_fill_queue(struct be_queue_info *q,
  2357. u16 len, u16 entry_size, void *vaddress)
  2358. {
  2359. struct be_dma_mem *mem = &q->dma_mem;
  2360. memset(q, 0, sizeof(*q));
  2361. q->len = len;
  2362. q->entry_size = entry_size;
  2363. mem->size = len * entry_size;
  2364. mem->va = vaddress;
  2365. if (!mem->va)
  2366. return -ENOMEM;
  2367. memset(mem->va, 0, mem->size);
  2368. return 0;
  2369. }
  2370. static int beiscsi_create_eqs(struct beiscsi_hba *phba,
  2371. struct hwi_context_memory *phwi_context)
  2372. {
  2373. unsigned int i, num_eq_pages;
  2374. int ret, eq_for_mcc;
  2375. struct be_queue_info *eq;
  2376. struct be_dma_mem *mem;
  2377. void *eq_vaddress;
  2378. dma_addr_t paddr;
  2379. num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \
  2380. sizeof(struct be_eq_entry));
  2381. if (phba->msix_enabled)
  2382. eq_for_mcc = 1;
  2383. else
  2384. eq_for_mcc = 0;
  2385. for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
  2386. eq = &phwi_context->be_eq[i].q;
  2387. mem = &eq->dma_mem;
  2388. phwi_context->be_eq[i].phba = phba;
  2389. eq_vaddress = pci_alloc_consistent(phba->pcidev,
  2390. num_eq_pages * PAGE_SIZE,
  2391. &paddr);
  2392. if (!eq_vaddress)
  2393. goto create_eq_error;
  2394. mem->va = eq_vaddress;
  2395. ret = be_fill_queue(eq, phba->params.num_eq_entries,
  2396. sizeof(struct be_eq_entry), eq_vaddress);
  2397. if (ret) {
  2398. shost_printk(KERN_ERR, phba->shost,
  2399. "be_fill_queue Failed for EQ\n");
  2400. goto create_eq_error;
  2401. }
  2402. mem->dma = paddr;
  2403. ret = beiscsi_cmd_eq_create(&phba->ctrl, eq,
  2404. phwi_context->cur_eqd);
  2405. if (ret) {
  2406. shost_printk(KERN_ERR, phba->shost,
  2407. "beiscsi_cmd_eq_create"
  2408. "Failedfor EQ\n");
  2409. goto create_eq_error;
  2410. }
  2411. SE_DEBUG(DBG_LVL_8, "eqid = %d\n", phwi_context->be_eq[i].q.id);
  2412. }
  2413. return 0;
  2414. create_eq_error:
  2415. for (i = 0; i < (phba->num_cpus + 1); i++) {
  2416. eq = &phwi_context->be_eq[i].q;
  2417. mem = &eq->dma_mem;
  2418. if (mem->va)
  2419. pci_free_consistent(phba->pcidev, num_eq_pages
  2420. * PAGE_SIZE,
  2421. mem->va, mem->dma);
  2422. }
  2423. return ret;
  2424. }
  2425. static int beiscsi_create_cqs(struct beiscsi_hba *phba,
  2426. struct hwi_context_memory *phwi_context)
  2427. {
  2428. unsigned int i, num_cq_pages;
  2429. int ret;
  2430. struct be_queue_info *cq, *eq;
  2431. struct be_dma_mem *mem;
  2432. struct be_eq_obj *pbe_eq;
  2433. void *cq_vaddress;
  2434. dma_addr_t paddr;
  2435. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2436. sizeof(struct sol_cqe));
  2437. for (i = 0; i < phba->num_cpus; i++) {
  2438. cq = &phwi_context->be_cq[i];
  2439. eq = &phwi_context->be_eq[i].q;
  2440. pbe_eq = &phwi_context->be_eq[i];
  2441. pbe_eq->cq = cq;
  2442. pbe_eq->phba = phba;
  2443. mem = &cq->dma_mem;
  2444. cq_vaddress = pci_alloc_consistent(phba->pcidev,
  2445. num_cq_pages * PAGE_SIZE,
  2446. &paddr);
  2447. if (!cq_vaddress)
  2448. goto create_cq_error;
  2449. ret = be_fill_queue(cq, phba->params.num_cq_entries,
  2450. sizeof(struct sol_cqe), cq_vaddress);
  2451. if (ret) {
  2452. shost_printk(KERN_ERR, phba->shost,
  2453. "be_fill_queue Failed for ISCSI CQ\n");
  2454. goto create_cq_error;
  2455. }
  2456. mem->dma = paddr;
  2457. ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false,
  2458. false, 0);
  2459. if (ret) {
  2460. shost_printk(KERN_ERR, phba->shost,
  2461. "beiscsi_cmd_eq_create"
  2462. "Failed for ISCSI CQ\n");
  2463. goto create_cq_error;
  2464. }
  2465. SE_DEBUG(DBG_LVL_8, "iscsi cq_id is %d for eq_id %d\n",
  2466. cq->id, eq->id);
  2467. SE_DEBUG(DBG_LVL_8, "ISCSI CQ CREATED\n");
  2468. }
  2469. return 0;
  2470. create_cq_error:
  2471. for (i = 0; i < phba->num_cpus; i++) {
  2472. cq = &phwi_context->be_cq[i];
  2473. mem = &cq->dma_mem;
  2474. if (mem->va)
  2475. pci_free_consistent(phba->pcidev, num_cq_pages
  2476. * PAGE_SIZE,
  2477. mem->va, mem->dma);
  2478. }
  2479. return ret;
  2480. }
  2481. static int
  2482. beiscsi_create_def_hdr(struct beiscsi_hba *phba,
  2483. struct hwi_context_memory *phwi_context,
  2484. struct hwi_controller *phwi_ctrlr,
  2485. unsigned int def_pdu_ring_sz)
  2486. {
  2487. unsigned int idx;
  2488. int ret;
  2489. struct be_queue_info *dq, *cq;
  2490. struct be_dma_mem *mem;
  2491. struct be_mem_descriptor *mem_descr;
  2492. void *dq_vaddress;
  2493. idx = 0;
  2494. dq = &phwi_context->be_def_hdrq;
  2495. cq = &phwi_context->be_cq[0];
  2496. mem = &dq->dma_mem;
  2497. mem_descr = phba->init_mem;
  2498. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2499. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2500. ret = be_fill_queue(dq, mem_descr->mem_array[0].size /
  2501. sizeof(struct phys_addr),
  2502. sizeof(struct phys_addr), dq_vaddress);
  2503. if (ret) {
  2504. shost_printk(KERN_ERR, phba->shost,
  2505. "be_fill_queue Failed for DEF PDU HDR\n");
  2506. return ret;
  2507. }
  2508. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2509. bus_address.u.a64.address;
  2510. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq,
  2511. def_pdu_ring_sz,
  2512. phba->params.defpdu_hdr_sz);
  2513. if (ret) {
  2514. shost_printk(KERN_ERR, phba->shost,
  2515. "be_cmd_create_default_pdu_queue Failed DEFHDR\n");
  2516. return ret;
  2517. }
  2518. phwi_ctrlr->default_pdu_hdr.id = phwi_context->be_def_hdrq.id;
  2519. SE_DEBUG(DBG_LVL_8, "iscsi def pdu id is %d\n",
  2520. phwi_context->be_def_hdrq.id);
  2521. hwi_post_async_buffers(phba, 1);
  2522. return 0;
  2523. }
  2524. static int
  2525. beiscsi_create_def_data(struct beiscsi_hba *phba,
  2526. struct hwi_context_memory *phwi_context,
  2527. struct hwi_controller *phwi_ctrlr,
  2528. unsigned int def_pdu_ring_sz)
  2529. {
  2530. unsigned int idx;
  2531. int ret;
  2532. struct be_queue_info *dataq, *cq;
  2533. struct be_dma_mem *mem;
  2534. struct be_mem_descriptor *mem_descr;
  2535. void *dq_vaddress;
  2536. idx = 0;
  2537. dataq = &phwi_context->be_def_dataq;
  2538. cq = &phwi_context->be_cq[0];
  2539. mem = &dataq->dma_mem;
  2540. mem_descr = phba->init_mem;
  2541. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2542. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2543. ret = be_fill_queue(dataq, mem_descr->mem_array[0].size /
  2544. sizeof(struct phys_addr),
  2545. sizeof(struct phys_addr), dq_vaddress);
  2546. if (ret) {
  2547. shost_printk(KERN_ERR, phba->shost,
  2548. "be_fill_queue Failed for DEF PDU DATA\n");
  2549. return ret;
  2550. }
  2551. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2552. bus_address.u.a64.address;
  2553. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq,
  2554. def_pdu_ring_sz,
  2555. phba->params.defpdu_data_sz);
  2556. if (ret) {
  2557. shost_printk(KERN_ERR, phba->shost,
  2558. "be_cmd_create_default_pdu_queue Failed"
  2559. " for DEF PDU DATA\n");
  2560. return ret;
  2561. }
  2562. phwi_ctrlr->default_pdu_data.id = phwi_context->be_def_dataq.id;
  2563. SE_DEBUG(DBG_LVL_8, "iscsi def data id is %d\n",
  2564. phwi_context->be_def_dataq.id);
  2565. hwi_post_async_buffers(phba, 0);
  2566. SE_DEBUG(DBG_LVL_8, "DEFAULT PDU DATA RING CREATED\n");
  2567. return 0;
  2568. }
  2569. static int
  2570. beiscsi_post_pages(struct beiscsi_hba *phba)
  2571. {
  2572. struct be_mem_descriptor *mem_descr;
  2573. struct mem_array *pm_arr;
  2574. unsigned int page_offset, i;
  2575. struct be_dma_mem sgl;
  2576. int status;
  2577. mem_descr = phba->init_mem;
  2578. mem_descr += HWI_MEM_SGE;
  2579. pm_arr = mem_descr->mem_array;
  2580. page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io *
  2581. phba->fw_config.iscsi_icd_start) / PAGE_SIZE;
  2582. for (i = 0; i < mem_descr->num_elements; i++) {
  2583. hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
  2584. status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl,
  2585. page_offset,
  2586. (pm_arr->size / PAGE_SIZE));
  2587. page_offset += pm_arr->size / PAGE_SIZE;
  2588. if (status != 0) {
  2589. shost_printk(KERN_ERR, phba->shost,
  2590. "post sgl failed.\n");
  2591. return status;
  2592. }
  2593. pm_arr++;
  2594. }
  2595. SE_DEBUG(DBG_LVL_8, "POSTED PAGES\n");
  2596. return 0;
  2597. }
  2598. static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q)
  2599. {
  2600. struct be_dma_mem *mem = &q->dma_mem;
  2601. if (mem->va) {
  2602. pci_free_consistent(phba->pcidev, mem->size,
  2603. mem->va, mem->dma);
  2604. mem->va = NULL;
  2605. }
  2606. }
  2607. static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q,
  2608. u16 len, u16 entry_size)
  2609. {
  2610. struct be_dma_mem *mem = &q->dma_mem;
  2611. memset(q, 0, sizeof(*q));
  2612. q->len = len;
  2613. q->entry_size = entry_size;
  2614. mem->size = len * entry_size;
  2615. mem->va = pci_alloc_consistent(phba->pcidev, mem->size, &mem->dma);
  2616. if (!mem->va)
  2617. return -ENOMEM;
  2618. memset(mem->va, 0, mem->size);
  2619. return 0;
  2620. }
  2621. static int
  2622. beiscsi_create_wrb_rings(struct beiscsi_hba *phba,
  2623. struct hwi_context_memory *phwi_context,
  2624. struct hwi_controller *phwi_ctrlr)
  2625. {
  2626. unsigned int wrb_mem_index, offset, size, num_wrb_rings;
  2627. u64 pa_addr_lo;
  2628. unsigned int idx, num, i;
  2629. struct mem_array *pwrb_arr;
  2630. void *wrb_vaddr;
  2631. struct be_dma_mem sgl;
  2632. struct be_mem_descriptor *mem_descr;
  2633. int status;
  2634. idx = 0;
  2635. mem_descr = phba->init_mem;
  2636. mem_descr += HWI_MEM_WRB;
  2637. pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl,
  2638. GFP_KERNEL);
  2639. if (!pwrb_arr) {
  2640. shost_printk(KERN_ERR, phba->shost,
  2641. "Memory alloc failed in create wrb ring.\n");
  2642. return -ENOMEM;
  2643. }
  2644. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  2645. pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address;
  2646. num_wrb_rings = mem_descr->mem_array[idx].size /
  2647. (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb));
  2648. for (num = 0; num < phba->params.cxns_per_ctrl; num++) {
  2649. if (num_wrb_rings) {
  2650. pwrb_arr[num].virtual_address = wrb_vaddr;
  2651. pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo;
  2652. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  2653. sizeof(struct iscsi_wrb);
  2654. wrb_vaddr += pwrb_arr[num].size;
  2655. pa_addr_lo += pwrb_arr[num].size;
  2656. num_wrb_rings--;
  2657. } else {
  2658. idx++;
  2659. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  2660. pa_addr_lo = mem_descr->mem_array[idx].\
  2661. bus_address.u.a64.address;
  2662. num_wrb_rings = mem_descr->mem_array[idx].size /
  2663. (phba->params.wrbs_per_cxn *
  2664. sizeof(struct iscsi_wrb));
  2665. pwrb_arr[num].virtual_address = wrb_vaddr;
  2666. pwrb_arr[num].bus_address.u.a64.address\
  2667. = pa_addr_lo;
  2668. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  2669. sizeof(struct iscsi_wrb);
  2670. wrb_vaddr += pwrb_arr[num].size;
  2671. pa_addr_lo += pwrb_arr[num].size;
  2672. num_wrb_rings--;
  2673. }
  2674. }
  2675. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  2676. wrb_mem_index = 0;
  2677. offset = 0;
  2678. size = 0;
  2679. hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl);
  2680. status = be_cmd_wrbq_create(&phba->ctrl, &sgl,
  2681. &phwi_context->be_wrbq[i]);
  2682. if (status != 0) {
  2683. shost_printk(KERN_ERR, phba->shost,
  2684. "wrbq create failed.");
  2685. kfree(pwrb_arr);
  2686. return status;
  2687. }
  2688. phwi_ctrlr->wrb_context[i * 2].cid = phwi_context->be_wrbq[i].
  2689. id;
  2690. }
  2691. kfree(pwrb_arr);
  2692. return 0;
  2693. }
  2694. static void free_wrb_handles(struct beiscsi_hba *phba)
  2695. {
  2696. unsigned int index;
  2697. struct hwi_controller *phwi_ctrlr;
  2698. struct hwi_wrb_context *pwrb_context;
  2699. phwi_ctrlr = phba->phwi_ctrlr;
  2700. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2701. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2702. kfree(pwrb_context->pwrb_handle_base);
  2703. kfree(pwrb_context->pwrb_handle_basestd);
  2704. }
  2705. }
  2706. static void be_mcc_queues_destroy(struct beiscsi_hba *phba)
  2707. {
  2708. struct be_queue_info *q;
  2709. struct be_ctrl_info *ctrl = &phba->ctrl;
  2710. q = &phba->ctrl.mcc_obj.q;
  2711. if (q->created)
  2712. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ);
  2713. be_queue_free(phba, q);
  2714. q = &phba->ctrl.mcc_obj.cq;
  2715. if (q->created)
  2716. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  2717. be_queue_free(phba, q);
  2718. }
  2719. static void hwi_cleanup(struct beiscsi_hba *phba)
  2720. {
  2721. struct be_queue_info *q;
  2722. struct be_ctrl_info *ctrl = &phba->ctrl;
  2723. struct hwi_controller *phwi_ctrlr;
  2724. struct hwi_context_memory *phwi_context;
  2725. int i, eq_num;
  2726. phwi_ctrlr = phba->phwi_ctrlr;
  2727. phwi_context = phwi_ctrlr->phwi_ctxt;
  2728. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  2729. q = &phwi_context->be_wrbq[i];
  2730. if (q->created)
  2731. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ);
  2732. }
  2733. free_wrb_handles(phba);
  2734. q = &phwi_context->be_def_hdrq;
  2735. if (q->created)
  2736. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  2737. q = &phwi_context->be_def_dataq;
  2738. if (q->created)
  2739. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  2740. beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
  2741. for (i = 0; i < (phba->num_cpus); i++) {
  2742. q = &phwi_context->be_cq[i];
  2743. if (q->created)
  2744. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  2745. }
  2746. if (phba->msix_enabled)
  2747. eq_num = 1;
  2748. else
  2749. eq_num = 0;
  2750. for (i = 0; i < (phba->num_cpus + eq_num); i++) {
  2751. q = &phwi_context->be_eq[i].q;
  2752. if (q->created)
  2753. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ);
  2754. }
  2755. be_mcc_queues_destroy(phba);
  2756. }
  2757. static int be_mcc_queues_create(struct beiscsi_hba *phba,
  2758. struct hwi_context_memory *phwi_context)
  2759. {
  2760. struct be_queue_info *q, *cq;
  2761. struct be_ctrl_info *ctrl = &phba->ctrl;
  2762. /* Alloc MCC compl queue */
  2763. cq = &phba->ctrl.mcc_obj.cq;
  2764. if (be_queue_alloc(phba, cq, MCC_CQ_LEN,
  2765. sizeof(struct be_mcc_compl)))
  2766. goto err;
  2767. /* Ask BE to create MCC compl queue; */
  2768. if (phba->msix_enabled) {
  2769. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq
  2770. [phba->num_cpus].q, false, true, 0))
  2771. goto mcc_cq_free;
  2772. } else {
  2773. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q,
  2774. false, true, 0))
  2775. goto mcc_cq_free;
  2776. }
  2777. /* Alloc MCC queue */
  2778. q = &phba->ctrl.mcc_obj.q;
  2779. if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
  2780. goto mcc_cq_destroy;
  2781. /* Ask BE to create MCC queue */
  2782. if (beiscsi_cmd_mccq_create(phba, q, cq))
  2783. goto mcc_q_free;
  2784. return 0;
  2785. mcc_q_free:
  2786. be_queue_free(phba, q);
  2787. mcc_cq_destroy:
  2788. beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ);
  2789. mcc_cq_free:
  2790. be_queue_free(phba, cq);
  2791. err:
  2792. return -ENOMEM;
  2793. }
  2794. static int find_num_cpus(void)
  2795. {
  2796. int num_cpus = 0;
  2797. num_cpus = num_online_cpus();
  2798. if (num_cpus >= MAX_CPUS)
  2799. num_cpus = MAX_CPUS - 1;
  2800. SE_DEBUG(DBG_LVL_8, "num_cpus = %d\n", num_cpus);
  2801. return num_cpus;
  2802. }
  2803. static int hwi_init_port(struct beiscsi_hba *phba)
  2804. {
  2805. struct hwi_controller *phwi_ctrlr;
  2806. struct hwi_context_memory *phwi_context;
  2807. unsigned int def_pdu_ring_sz;
  2808. struct be_ctrl_info *ctrl = &phba->ctrl;
  2809. int status;
  2810. def_pdu_ring_sz =
  2811. phba->params.asyncpdus_per_ctrl * sizeof(struct phys_addr);
  2812. phwi_ctrlr = phba->phwi_ctrlr;
  2813. phwi_context = phwi_ctrlr->phwi_ctxt;
  2814. phwi_context->max_eqd = 0;
  2815. phwi_context->min_eqd = 0;
  2816. phwi_context->cur_eqd = 64;
  2817. be_cmd_fw_initialize(&phba->ctrl);
  2818. status = beiscsi_create_eqs(phba, phwi_context);
  2819. if (status != 0) {
  2820. shost_printk(KERN_ERR, phba->shost, "EQ not created\n");
  2821. goto error;
  2822. }
  2823. status = be_mcc_queues_create(phba, phwi_context);
  2824. if (status != 0)
  2825. goto error;
  2826. status = mgmt_check_supported_fw(ctrl, phba);
  2827. if (status != 0) {
  2828. shost_printk(KERN_ERR, phba->shost,
  2829. "Unsupported fw version\n");
  2830. goto error;
  2831. }
  2832. status = beiscsi_create_cqs(phba, phwi_context);
  2833. if (status != 0) {
  2834. shost_printk(KERN_ERR, phba->shost, "CQ not created\n");
  2835. goto error;
  2836. }
  2837. status = beiscsi_create_def_hdr(phba, phwi_context, phwi_ctrlr,
  2838. def_pdu_ring_sz);
  2839. if (status != 0) {
  2840. shost_printk(KERN_ERR, phba->shost,
  2841. "Default Header not created\n");
  2842. goto error;
  2843. }
  2844. status = beiscsi_create_def_data(phba, phwi_context,
  2845. phwi_ctrlr, def_pdu_ring_sz);
  2846. if (status != 0) {
  2847. shost_printk(KERN_ERR, phba->shost,
  2848. "Default Data not created\n");
  2849. goto error;
  2850. }
  2851. status = beiscsi_post_pages(phba);
  2852. if (status != 0) {
  2853. shost_printk(KERN_ERR, phba->shost, "Post SGL Pages Failed\n");
  2854. goto error;
  2855. }
  2856. status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr);
  2857. if (status != 0) {
  2858. shost_printk(KERN_ERR, phba->shost,
  2859. "WRB Rings not created\n");
  2860. goto error;
  2861. }
  2862. SE_DEBUG(DBG_LVL_8, "hwi_init_port success\n");
  2863. return 0;
  2864. error:
  2865. shost_printk(KERN_ERR, phba->shost, "hwi_init_port failed");
  2866. hwi_cleanup(phba);
  2867. return status;
  2868. }
  2869. static int hwi_init_controller(struct beiscsi_hba *phba)
  2870. {
  2871. struct hwi_controller *phwi_ctrlr;
  2872. phwi_ctrlr = phba->phwi_ctrlr;
  2873. if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) {
  2874. phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba->
  2875. init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address;
  2876. SE_DEBUG(DBG_LVL_8, " phwi_ctrlr->phwi_ctxt=%p\n",
  2877. phwi_ctrlr->phwi_ctxt);
  2878. } else {
  2879. shost_printk(KERN_ERR, phba->shost,
  2880. "HWI_MEM_ADDN_CONTEXT is more than one element."
  2881. "Failing to load\n");
  2882. return -ENOMEM;
  2883. }
  2884. iscsi_init_global_templates(phba);
  2885. if (beiscsi_init_wrb_handle(phba))
  2886. return -ENOMEM;
  2887. hwi_init_async_pdu_ctx(phba);
  2888. if (hwi_init_port(phba) != 0) {
  2889. shost_printk(KERN_ERR, phba->shost,
  2890. "hwi_init_controller failed\n");
  2891. return -ENOMEM;
  2892. }
  2893. return 0;
  2894. }
  2895. static void beiscsi_free_mem(struct beiscsi_hba *phba)
  2896. {
  2897. struct be_mem_descriptor *mem_descr;
  2898. int i, j;
  2899. mem_descr = phba->init_mem;
  2900. i = 0;
  2901. j = 0;
  2902. for (i = 0; i < SE_MEM_MAX; i++) {
  2903. for (j = mem_descr->num_elements; j > 0; j--) {
  2904. pci_free_consistent(phba->pcidev,
  2905. mem_descr->mem_array[j - 1].size,
  2906. mem_descr->mem_array[j - 1].virtual_address,
  2907. (unsigned long)mem_descr->mem_array[j - 1].
  2908. bus_address.u.a64.address);
  2909. }
  2910. kfree(mem_descr->mem_array);
  2911. mem_descr++;
  2912. }
  2913. kfree(phba->init_mem);
  2914. kfree(phba->phwi_ctrlr);
  2915. }
  2916. static int beiscsi_init_controller(struct beiscsi_hba *phba)
  2917. {
  2918. int ret = -ENOMEM;
  2919. ret = beiscsi_get_memory(phba);
  2920. if (ret < 0) {
  2921. shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe -"
  2922. "Failed in beiscsi_alloc_memory\n");
  2923. return ret;
  2924. }
  2925. ret = hwi_init_controller(phba);
  2926. if (ret)
  2927. goto free_init;
  2928. SE_DEBUG(DBG_LVL_8, "Return success from beiscsi_init_controller");
  2929. return 0;
  2930. free_init:
  2931. beiscsi_free_mem(phba);
  2932. return ret;
  2933. }
  2934. static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba)
  2935. {
  2936. struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg;
  2937. struct sgl_handle *psgl_handle;
  2938. struct iscsi_sge *pfrag;
  2939. unsigned int arr_index, i, idx;
  2940. phba->io_sgl_hndl_avbl = 0;
  2941. phba->eh_sgl_hndl_avbl = 0;
  2942. mem_descr_sglh = phba->init_mem;
  2943. mem_descr_sglh += HWI_MEM_SGLH;
  2944. if (1 == mem_descr_sglh->num_elements) {
  2945. phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  2946. phba->params.ios_per_ctrl,
  2947. GFP_KERNEL);
  2948. if (!phba->io_sgl_hndl_base) {
  2949. shost_printk(KERN_ERR, phba->shost,
  2950. "Mem Alloc Failed. Failing to load\n");
  2951. return -ENOMEM;
  2952. }
  2953. phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  2954. (phba->params.icds_per_ctrl -
  2955. phba->params.ios_per_ctrl),
  2956. GFP_KERNEL);
  2957. if (!phba->eh_sgl_hndl_base) {
  2958. kfree(phba->io_sgl_hndl_base);
  2959. shost_printk(KERN_ERR, phba->shost,
  2960. "Mem Alloc Failed. Failing to load\n");
  2961. return -ENOMEM;
  2962. }
  2963. } else {
  2964. shost_printk(KERN_ERR, phba->shost,
  2965. "HWI_MEM_SGLH is more than one element."
  2966. "Failing to load\n");
  2967. return -ENOMEM;
  2968. }
  2969. arr_index = 0;
  2970. idx = 0;
  2971. while (idx < mem_descr_sglh->num_elements) {
  2972. psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address;
  2973. for (i = 0; i < (mem_descr_sglh->mem_array[idx].size /
  2974. sizeof(struct sgl_handle)); i++) {
  2975. if (arr_index < phba->params.ios_per_ctrl) {
  2976. phba->io_sgl_hndl_base[arr_index] = psgl_handle;
  2977. phba->io_sgl_hndl_avbl++;
  2978. arr_index++;
  2979. } else {
  2980. phba->eh_sgl_hndl_base[arr_index -
  2981. phba->params.ios_per_ctrl] =
  2982. psgl_handle;
  2983. arr_index++;
  2984. phba->eh_sgl_hndl_avbl++;
  2985. }
  2986. psgl_handle++;
  2987. }
  2988. idx++;
  2989. }
  2990. SE_DEBUG(DBG_LVL_8,
  2991. "phba->io_sgl_hndl_avbl=%d"
  2992. "phba->eh_sgl_hndl_avbl=%d\n",
  2993. phba->io_sgl_hndl_avbl,
  2994. phba->eh_sgl_hndl_avbl);
  2995. mem_descr_sg = phba->init_mem;
  2996. mem_descr_sg += HWI_MEM_SGE;
  2997. SE_DEBUG(DBG_LVL_8, "\n mem_descr_sg->num_elements=%d\n",
  2998. mem_descr_sg->num_elements);
  2999. arr_index = 0;
  3000. idx = 0;
  3001. while (idx < mem_descr_sg->num_elements) {
  3002. pfrag = mem_descr_sg->mem_array[idx].virtual_address;
  3003. for (i = 0;
  3004. i < (mem_descr_sg->mem_array[idx].size) /
  3005. (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io);
  3006. i++) {
  3007. if (arr_index < phba->params.ios_per_ctrl)
  3008. psgl_handle = phba->io_sgl_hndl_base[arr_index];
  3009. else
  3010. psgl_handle = phba->eh_sgl_hndl_base[arr_index -
  3011. phba->params.ios_per_ctrl];
  3012. psgl_handle->pfrag = pfrag;
  3013. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0);
  3014. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0);
  3015. pfrag += phba->params.num_sge_per_io;
  3016. psgl_handle->sgl_index =
  3017. phba->fw_config.iscsi_icd_start + arr_index++;
  3018. }
  3019. idx++;
  3020. }
  3021. phba->io_sgl_free_index = 0;
  3022. phba->io_sgl_alloc_index = 0;
  3023. phba->eh_sgl_free_index = 0;
  3024. phba->eh_sgl_alloc_index = 0;
  3025. return 0;
  3026. }
  3027. static int hba_setup_cid_tbls(struct beiscsi_hba *phba)
  3028. {
  3029. int i, new_cid;
  3030. phba->cid_array = kzalloc(sizeof(void *) * phba->params.cxns_per_ctrl,
  3031. GFP_KERNEL);
  3032. if (!phba->cid_array) {
  3033. shost_printk(KERN_ERR, phba->shost,
  3034. "Failed to allocate memory in "
  3035. "hba_setup_cid_tbls\n");
  3036. return -ENOMEM;
  3037. }
  3038. phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) *
  3039. phba->params.cxns_per_ctrl * 2, GFP_KERNEL);
  3040. if (!phba->ep_array) {
  3041. shost_printk(KERN_ERR, phba->shost,
  3042. "Failed to allocate memory in "
  3043. "hba_setup_cid_tbls\n");
  3044. kfree(phba->cid_array);
  3045. return -ENOMEM;
  3046. }
  3047. new_cid = phba->fw_config.iscsi_cid_start;
  3048. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  3049. phba->cid_array[i] = new_cid;
  3050. new_cid += 2;
  3051. }
  3052. phba->avlbl_cids = phba->params.cxns_per_ctrl;
  3053. return 0;
  3054. }
  3055. static void hwi_enable_intr(struct beiscsi_hba *phba)
  3056. {
  3057. struct be_ctrl_info *ctrl = &phba->ctrl;
  3058. struct hwi_controller *phwi_ctrlr;
  3059. struct hwi_context_memory *phwi_context;
  3060. struct be_queue_info *eq;
  3061. u8 __iomem *addr;
  3062. u32 reg, i;
  3063. u32 enabled;
  3064. phwi_ctrlr = phba->phwi_ctrlr;
  3065. phwi_context = phwi_ctrlr->phwi_ctxt;
  3066. addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
  3067. PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
  3068. reg = ioread32(addr);
  3069. enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3070. if (!enabled) {
  3071. reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3072. SE_DEBUG(DBG_LVL_8, "reg =x%08x addr=%p\n", reg, addr);
  3073. iowrite32(reg, addr);
  3074. }
  3075. if (!phba->msix_enabled) {
  3076. eq = &phwi_context->be_eq[0].q;
  3077. SE_DEBUG(DBG_LVL_8, "eq->id=%d\n", eq->id);
  3078. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3079. } else {
  3080. for (i = 0; i <= phba->num_cpus; i++) {
  3081. eq = &phwi_context->be_eq[i].q;
  3082. SE_DEBUG(DBG_LVL_8, "eq->id=%d\n", eq->id);
  3083. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3084. }
  3085. }
  3086. }
  3087. static void hwi_disable_intr(struct beiscsi_hba *phba)
  3088. {
  3089. struct be_ctrl_info *ctrl = &phba->ctrl;
  3090. u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
  3091. u32 reg = ioread32(addr);
  3092. u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3093. if (enabled) {
  3094. reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3095. iowrite32(reg, addr);
  3096. } else
  3097. shost_printk(KERN_WARNING, phba->shost,
  3098. "In hwi_disable_intr, Already Disabled\n");
  3099. }
  3100. static int beiscsi_get_boot_info(struct beiscsi_hba *phba)
  3101. {
  3102. struct be_cmd_resp_get_boot_target *boot_resp;
  3103. struct be_cmd_resp_get_session *session_resp;
  3104. struct be_mcc_wrb *wrb;
  3105. struct be_dma_mem nonemb_cmd;
  3106. unsigned int tag, wrb_num;
  3107. unsigned short status, extd_status;
  3108. struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
  3109. int ret = -ENOMEM;
  3110. tag = beiscsi_get_boot_target(phba);
  3111. if (!tag) {
  3112. SE_DEBUG(DBG_LVL_1, "be_cmd_get_mac_addr Failed\n");
  3113. return -EAGAIN;
  3114. } else
  3115. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  3116. phba->ctrl.mcc_numtag[tag]);
  3117. wrb_num = (phba->ctrl.mcc_numtag[tag] & 0x00FF0000) >> 16;
  3118. extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
  3119. status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
  3120. if (status || extd_status) {
  3121. SE_DEBUG(DBG_LVL_1, "be_cmd_get_mac_addr Failed"
  3122. " status = %d extd_status = %d\n",
  3123. status, extd_status);
  3124. free_mcc_tag(&phba->ctrl, tag);
  3125. return -EBUSY;
  3126. }
  3127. wrb = queue_get_wrb(mccq, wrb_num);
  3128. free_mcc_tag(&phba->ctrl, tag);
  3129. boot_resp = embedded_payload(wrb);
  3130. if (boot_resp->boot_session_handle < 0) {
  3131. shost_printk(KERN_INFO, phba->shost, "No Boot Session.\n");
  3132. return -ENXIO;
  3133. }
  3134. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  3135. sizeof(*session_resp),
  3136. &nonemb_cmd.dma);
  3137. if (nonemb_cmd.va == NULL) {
  3138. SE_DEBUG(DBG_LVL_1,
  3139. "Failed to allocate memory for"
  3140. "beiscsi_get_session_info\n");
  3141. return -ENOMEM;
  3142. }
  3143. memset(nonemb_cmd.va, 0, sizeof(*session_resp));
  3144. tag = beiscsi_get_session_info(phba,
  3145. boot_resp->boot_session_handle, &nonemb_cmd);
  3146. if (!tag) {
  3147. SE_DEBUG(DBG_LVL_1, "beiscsi_get_session_info"
  3148. " Failed\n");
  3149. goto boot_freemem;
  3150. } else
  3151. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  3152. phba->ctrl.mcc_numtag[tag]);
  3153. wrb_num = (phba->ctrl.mcc_numtag[tag] & 0x00FF0000) >> 16;
  3154. extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
  3155. status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
  3156. if (status || extd_status) {
  3157. SE_DEBUG(DBG_LVL_1, "beiscsi_get_session_info Failed"
  3158. " status = %d extd_status = %d\n",
  3159. status, extd_status);
  3160. free_mcc_tag(&phba->ctrl, tag);
  3161. goto boot_freemem;
  3162. }
  3163. wrb = queue_get_wrb(mccq, wrb_num);
  3164. free_mcc_tag(&phba->ctrl, tag);
  3165. session_resp = nonemb_cmd.va ;
  3166. memcpy(&phba->boot_sess, &session_resp->session_info,
  3167. sizeof(struct mgmt_session_info));
  3168. ret = 0;
  3169. boot_freemem:
  3170. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  3171. nonemb_cmd.va, nonemb_cmd.dma);
  3172. return ret;
  3173. }
  3174. static void beiscsi_boot_release(void *data)
  3175. {
  3176. struct beiscsi_hba *phba = data;
  3177. scsi_host_put(phba->shost);
  3178. }
  3179. static int beiscsi_setup_boot_info(struct beiscsi_hba *phba)
  3180. {
  3181. struct iscsi_boot_kobj *boot_kobj;
  3182. /* get boot info using mgmt cmd */
  3183. if (beiscsi_get_boot_info(phba))
  3184. /* Try to see if we can carry on without this */
  3185. return 0;
  3186. phba->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no);
  3187. if (!phba->boot_kset)
  3188. return -ENOMEM;
  3189. /* get a ref because the show function will ref the phba */
  3190. if (!scsi_host_get(phba->shost))
  3191. goto free_kset;
  3192. boot_kobj = iscsi_boot_create_target(phba->boot_kset, 0, phba,
  3193. beiscsi_show_boot_tgt_info,
  3194. beiscsi_tgt_get_attr_visibility,
  3195. beiscsi_boot_release);
  3196. if (!boot_kobj)
  3197. goto put_shost;
  3198. if (!scsi_host_get(phba->shost))
  3199. goto free_kset;
  3200. boot_kobj = iscsi_boot_create_initiator(phba->boot_kset, 0, phba,
  3201. beiscsi_show_boot_ini_info,
  3202. beiscsi_ini_get_attr_visibility,
  3203. beiscsi_boot_release);
  3204. if (!boot_kobj)
  3205. goto put_shost;
  3206. if (!scsi_host_get(phba->shost))
  3207. goto free_kset;
  3208. boot_kobj = iscsi_boot_create_ethernet(phba->boot_kset, 0, phba,
  3209. beiscsi_show_boot_eth_info,
  3210. beiscsi_eth_get_attr_visibility,
  3211. beiscsi_boot_release);
  3212. if (!boot_kobj)
  3213. goto put_shost;
  3214. return 0;
  3215. put_shost:
  3216. scsi_host_put(phba->shost);
  3217. free_kset:
  3218. iscsi_boot_destroy_kset(phba->boot_kset);
  3219. return -ENOMEM;
  3220. }
  3221. static int beiscsi_init_port(struct beiscsi_hba *phba)
  3222. {
  3223. int ret;
  3224. ret = beiscsi_init_controller(phba);
  3225. if (ret < 0) {
  3226. shost_printk(KERN_ERR, phba->shost,
  3227. "beiscsi_dev_probe - Failed in"
  3228. "beiscsi_init_controller\n");
  3229. return ret;
  3230. }
  3231. ret = beiscsi_init_sgl_handle(phba);
  3232. if (ret < 0) {
  3233. shost_printk(KERN_ERR, phba->shost,
  3234. "beiscsi_dev_probe - Failed in"
  3235. "beiscsi_init_sgl_handle\n");
  3236. goto do_cleanup_ctrlr;
  3237. }
  3238. if (hba_setup_cid_tbls(phba)) {
  3239. shost_printk(KERN_ERR, phba->shost,
  3240. "Failed in hba_setup_cid_tbls\n");
  3241. kfree(phba->io_sgl_hndl_base);
  3242. kfree(phba->eh_sgl_hndl_base);
  3243. goto do_cleanup_ctrlr;
  3244. }
  3245. return ret;
  3246. do_cleanup_ctrlr:
  3247. hwi_cleanup(phba);
  3248. return ret;
  3249. }
  3250. static void hwi_purge_eq(struct beiscsi_hba *phba)
  3251. {
  3252. struct hwi_controller *phwi_ctrlr;
  3253. struct hwi_context_memory *phwi_context;
  3254. struct be_queue_info *eq;
  3255. struct be_eq_entry *eqe = NULL;
  3256. int i, eq_msix;
  3257. unsigned int num_processed;
  3258. phwi_ctrlr = phba->phwi_ctrlr;
  3259. phwi_context = phwi_ctrlr->phwi_ctxt;
  3260. if (phba->msix_enabled)
  3261. eq_msix = 1;
  3262. else
  3263. eq_msix = 0;
  3264. for (i = 0; i < (phba->num_cpus + eq_msix); i++) {
  3265. eq = &phwi_context->be_eq[i].q;
  3266. eqe = queue_tail_node(eq);
  3267. num_processed = 0;
  3268. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  3269. & EQE_VALID_MASK) {
  3270. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  3271. queue_tail_inc(eq);
  3272. eqe = queue_tail_node(eq);
  3273. num_processed++;
  3274. }
  3275. if (num_processed)
  3276. hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1);
  3277. }
  3278. }
  3279. static void beiscsi_clean_port(struct beiscsi_hba *phba)
  3280. {
  3281. int mgmt_status;
  3282. mgmt_status = mgmt_epfw_cleanup(phba, CMD_CONNECTION_CHUTE_0);
  3283. if (mgmt_status)
  3284. shost_printk(KERN_WARNING, phba->shost,
  3285. "mgmt_epfw_cleanup FAILED\n");
  3286. hwi_purge_eq(phba);
  3287. hwi_cleanup(phba);
  3288. kfree(phba->io_sgl_hndl_base);
  3289. kfree(phba->eh_sgl_hndl_base);
  3290. kfree(phba->cid_array);
  3291. kfree(phba->ep_array);
  3292. }
  3293. static void beiscsi_cleanup_task(struct iscsi_task *task)
  3294. {
  3295. struct beiscsi_io_task *io_task = task->dd_data;
  3296. struct iscsi_conn *conn = task->conn;
  3297. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3298. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3299. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3300. struct hwi_wrb_context *pwrb_context;
  3301. struct hwi_controller *phwi_ctrlr;
  3302. phwi_ctrlr = phba->phwi_ctrlr;
  3303. pwrb_context = &phwi_ctrlr->wrb_context[beiscsi_conn->beiscsi_conn_cid
  3304. - phba->fw_config.iscsi_cid_start];
  3305. if (io_task->cmd_bhs) {
  3306. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3307. io_task->bhs_pa.u.a64.address);
  3308. io_task->cmd_bhs = NULL;
  3309. }
  3310. if (task->sc) {
  3311. if (io_task->pwrb_handle) {
  3312. free_wrb_handle(phba, pwrb_context,
  3313. io_task->pwrb_handle);
  3314. io_task->pwrb_handle = NULL;
  3315. }
  3316. if (io_task->psgl_handle) {
  3317. spin_lock(&phba->io_sgl_lock);
  3318. free_io_sgl_handle(phba, io_task->psgl_handle);
  3319. spin_unlock(&phba->io_sgl_lock);
  3320. io_task->psgl_handle = NULL;
  3321. }
  3322. } else {
  3323. if (!beiscsi_conn->login_in_progress) {
  3324. if (io_task->pwrb_handle) {
  3325. free_wrb_handle(phba, pwrb_context,
  3326. io_task->pwrb_handle);
  3327. io_task->pwrb_handle = NULL;
  3328. }
  3329. if (io_task->psgl_handle) {
  3330. spin_lock(&phba->mgmt_sgl_lock);
  3331. free_mgmt_sgl_handle(phba,
  3332. io_task->psgl_handle);
  3333. spin_unlock(&phba->mgmt_sgl_lock);
  3334. io_task->psgl_handle = NULL;
  3335. }
  3336. }
  3337. }
  3338. }
  3339. void
  3340. beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn,
  3341. struct beiscsi_offload_params *params)
  3342. {
  3343. struct wrb_handle *pwrb_handle;
  3344. struct iscsi_target_context_update_wrb *pwrb = NULL;
  3345. struct be_mem_descriptor *mem_descr;
  3346. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3347. struct iscsi_task *task = beiscsi_conn->task;
  3348. struct iscsi_session *session = task->conn->session;
  3349. u32 doorbell = 0;
  3350. /*
  3351. * We can always use 0 here because it is reserved by libiscsi for
  3352. * login/startup related tasks.
  3353. */
  3354. beiscsi_conn->login_in_progress = 0;
  3355. spin_lock_bh(&session->lock);
  3356. beiscsi_cleanup_task(task);
  3357. spin_unlock_bh(&session->lock);
  3358. pwrb_handle = alloc_wrb_handle(phba, (beiscsi_conn->beiscsi_conn_cid -
  3359. phba->fw_config.iscsi_cid_start));
  3360. pwrb = (struct iscsi_target_context_update_wrb *)pwrb_handle->pwrb;
  3361. memset(pwrb, 0, sizeof(*pwrb));
  3362. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3363. max_burst_length, pwrb, params->dw[offsetof
  3364. (struct amap_beiscsi_offload_params,
  3365. max_burst_length) / 32]);
  3366. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3367. max_send_data_segment_length, pwrb,
  3368. params->dw[offsetof(struct amap_beiscsi_offload_params,
  3369. max_send_data_segment_length) / 32]);
  3370. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3371. first_burst_length,
  3372. pwrb,
  3373. params->dw[offsetof(struct amap_beiscsi_offload_params,
  3374. first_burst_length) / 32]);
  3375. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, erl, pwrb,
  3376. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3377. erl) / 32] & OFFLD_PARAMS_ERL));
  3378. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, dde, pwrb,
  3379. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3380. dde) / 32] & OFFLD_PARAMS_DDE) >> 2);
  3381. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, hde, pwrb,
  3382. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3383. hde) / 32] & OFFLD_PARAMS_HDE) >> 3);
  3384. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, ir2t, pwrb,
  3385. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3386. ir2t) / 32] & OFFLD_PARAMS_IR2T) >> 4);
  3387. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, imd, pwrb,
  3388. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3389. imd) / 32] & OFFLD_PARAMS_IMD) >> 5);
  3390. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, stat_sn,
  3391. pwrb,
  3392. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3393. exp_statsn) / 32] + 1));
  3394. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, type, pwrb,
  3395. 0x7);
  3396. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, wrb_idx,
  3397. pwrb, pwrb_handle->wrb_index);
  3398. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, ptr2nextwrb,
  3399. pwrb, pwrb_handle->nxt_wrb_index);
  3400. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3401. session_state, pwrb, 0);
  3402. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, compltonack,
  3403. pwrb, 1);
  3404. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, notpredblq,
  3405. pwrb, 0);
  3406. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, mode, pwrb,
  3407. 0);
  3408. mem_descr = phba->init_mem;
  3409. mem_descr += ISCSI_MEM_GLOBAL_HEADER;
  3410. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3411. pad_buffer_addr_hi, pwrb,
  3412. mem_descr->mem_array[0].bus_address.u.a32.address_hi);
  3413. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3414. pad_buffer_addr_lo, pwrb,
  3415. mem_descr->mem_array[0].bus_address.u.a32.address_lo);
  3416. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_target_context_update_wrb));
  3417. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3418. doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK)
  3419. << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3420. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3421. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3422. }
  3423. static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt,
  3424. int *index, int *age)
  3425. {
  3426. *index = (int)itt;
  3427. if (age)
  3428. *age = conn->session->age;
  3429. }
  3430. /**
  3431. * beiscsi_alloc_pdu - allocates pdu and related resources
  3432. * @task: libiscsi task
  3433. * @opcode: opcode of pdu for task
  3434. *
  3435. * This is called with the session lock held. It will allocate
  3436. * the wrb and sgl if needed for the command. And it will prep
  3437. * the pdu's itt. beiscsi_parse_pdu will later translate
  3438. * the pdu itt to the libiscsi task itt.
  3439. */
  3440. static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode)
  3441. {
  3442. struct beiscsi_io_task *io_task = task->dd_data;
  3443. struct iscsi_conn *conn = task->conn;
  3444. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3445. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3446. struct hwi_wrb_context *pwrb_context;
  3447. struct hwi_controller *phwi_ctrlr;
  3448. itt_t itt;
  3449. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3450. dma_addr_t paddr;
  3451. io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool,
  3452. GFP_ATOMIC, &paddr);
  3453. if (!io_task->cmd_bhs)
  3454. return -ENOMEM;
  3455. io_task->bhs_pa.u.a64.address = paddr;
  3456. io_task->libiscsi_itt = (itt_t)task->itt;
  3457. io_task->conn = beiscsi_conn;
  3458. task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr;
  3459. task->hdr_max = sizeof(struct be_cmd_bhs);
  3460. io_task->psgl_handle = NULL;
  3461. io_task->pwrb_handle = NULL;
  3462. if (task->sc) {
  3463. spin_lock(&phba->io_sgl_lock);
  3464. io_task->psgl_handle = alloc_io_sgl_handle(phba);
  3465. spin_unlock(&phba->io_sgl_lock);
  3466. if (!io_task->psgl_handle)
  3467. goto free_hndls;
  3468. io_task->pwrb_handle = alloc_wrb_handle(phba,
  3469. beiscsi_conn->beiscsi_conn_cid -
  3470. phba->fw_config.iscsi_cid_start);
  3471. if (!io_task->pwrb_handle)
  3472. goto free_io_hndls;
  3473. } else {
  3474. io_task->scsi_cmnd = NULL;
  3475. if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) {
  3476. if (!beiscsi_conn->login_in_progress) {
  3477. spin_lock(&phba->mgmt_sgl_lock);
  3478. io_task->psgl_handle = (struct sgl_handle *)
  3479. alloc_mgmt_sgl_handle(phba);
  3480. spin_unlock(&phba->mgmt_sgl_lock);
  3481. if (!io_task->psgl_handle)
  3482. goto free_hndls;
  3483. beiscsi_conn->login_in_progress = 1;
  3484. beiscsi_conn->plogin_sgl_handle =
  3485. io_task->psgl_handle;
  3486. io_task->pwrb_handle =
  3487. alloc_wrb_handle(phba,
  3488. beiscsi_conn->beiscsi_conn_cid -
  3489. phba->fw_config.iscsi_cid_start);
  3490. if (!io_task->pwrb_handle)
  3491. goto free_io_hndls;
  3492. beiscsi_conn->plogin_wrb_handle =
  3493. io_task->pwrb_handle;
  3494. } else {
  3495. io_task->psgl_handle =
  3496. beiscsi_conn->plogin_sgl_handle;
  3497. io_task->pwrb_handle =
  3498. beiscsi_conn->plogin_wrb_handle;
  3499. }
  3500. beiscsi_conn->task = task;
  3501. } else {
  3502. spin_lock(&phba->mgmt_sgl_lock);
  3503. io_task->psgl_handle = alloc_mgmt_sgl_handle(phba);
  3504. spin_unlock(&phba->mgmt_sgl_lock);
  3505. if (!io_task->psgl_handle)
  3506. goto free_hndls;
  3507. io_task->pwrb_handle =
  3508. alloc_wrb_handle(phba,
  3509. beiscsi_conn->beiscsi_conn_cid -
  3510. phba->fw_config.iscsi_cid_start);
  3511. if (!io_task->pwrb_handle)
  3512. goto free_mgmt_hndls;
  3513. }
  3514. }
  3515. itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle->
  3516. wrb_index << 16) | (unsigned int)
  3517. (io_task->psgl_handle->sgl_index));
  3518. io_task->pwrb_handle->pio_handle = task;
  3519. io_task->cmd_bhs->iscsi_hdr.itt = itt;
  3520. return 0;
  3521. free_io_hndls:
  3522. spin_lock(&phba->io_sgl_lock);
  3523. free_io_sgl_handle(phba, io_task->psgl_handle);
  3524. spin_unlock(&phba->io_sgl_lock);
  3525. goto free_hndls;
  3526. free_mgmt_hndls:
  3527. spin_lock(&phba->mgmt_sgl_lock);
  3528. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  3529. spin_unlock(&phba->mgmt_sgl_lock);
  3530. free_hndls:
  3531. phwi_ctrlr = phba->phwi_ctrlr;
  3532. pwrb_context = &phwi_ctrlr->wrb_context[
  3533. beiscsi_conn->beiscsi_conn_cid -
  3534. phba->fw_config.iscsi_cid_start];
  3535. if (io_task->pwrb_handle)
  3536. free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
  3537. io_task->pwrb_handle = NULL;
  3538. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3539. io_task->bhs_pa.u.a64.address);
  3540. io_task->cmd_bhs = NULL;
  3541. SE_DEBUG(DBG_LVL_1, "Alloc of SGL_ICD Failed\n");
  3542. return -ENOMEM;
  3543. }
  3544. static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg,
  3545. unsigned int num_sg, unsigned int xferlen,
  3546. unsigned int writedir)
  3547. {
  3548. struct beiscsi_io_task *io_task = task->dd_data;
  3549. struct iscsi_conn *conn = task->conn;
  3550. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3551. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3552. struct iscsi_wrb *pwrb = NULL;
  3553. unsigned int doorbell = 0;
  3554. pwrb = io_task->pwrb_handle->pwrb;
  3555. io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
  3556. io_task->bhs_len = sizeof(struct be_cmd_bhs);
  3557. if (writedir) {
  3558. memset(&io_task->cmd_bhs->iscsi_data_pdu, 0, 48);
  3559. AMAP_SET_BITS(struct amap_pdu_data_out, itt,
  3560. &io_task->cmd_bhs->iscsi_data_pdu,
  3561. (unsigned int)io_task->cmd_bhs->iscsi_hdr.itt);
  3562. AMAP_SET_BITS(struct amap_pdu_data_out, opcode,
  3563. &io_task->cmd_bhs->iscsi_data_pdu,
  3564. ISCSI_OPCODE_SCSI_DATA_OUT);
  3565. AMAP_SET_BITS(struct amap_pdu_data_out, final_bit,
  3566. &io_task->cmd_bhs->iscsi_data_pdu, 1);
  3567. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3568. INI_WR_CMD);
  3569. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
  3570. } else {
  3571. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3572. INI_RD_CMD);
  3573. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  3574. }
  3575. memcpy(&io_task->cmd_bhs->iscsi_data_pdu.
  3576. dw[offsetof(struct amap_pdu_data_out, lun) / 32],
  3577. &io_task->cmd_bhs->iscsi_hdr.lun, sizeof(struct scsi_lun));
  3578. AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb,
  3579. cpu_to_be16(*(unsigned short *)
  3580. &io_task->cmd_bhs->iscsi_hdr.lun));
  3581. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen);
  3582. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  3583. io_task->pwrb_handle->wrb_index);
  3584. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  3585. be32_to_cpu(task->cmdsn));
  3586. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  3587. io_task->psgl_handle->sgl_index);
  3588. hwi_write_sgl(pwrb, sg, num_sg, io_task);
  3589. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  3590. io_task->pwrb_handle->nxt_wrb_index);
  3591. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  3592. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3593. doorbell |= (io_task->pwrb_handle->wrb_index &
  3594. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3595. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3596. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3597. return 0;
  3598. }
  3599. static int beiscsi_mtask(struct iscsi_task *task)
  3600. {
  3601. struct beiscsi_io_task *io_task = task->dd_data;
  3602. struct iscsi_conn *conn = task->conn;
  3603. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3604. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3605. struct iscsi_wrb *pwrb = NULL;
  3606. unsigned int doorbell = 0;
  3607. unsigned int cid;
  3608. cid = beiscsi_conn->beiscsi_conn_cid;
  3609. pwrb = io_task->pwrb_handle->pwrb;
  3610. memset(pwrb, 0, sizeof(*pwrb));
  3611. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  3612. be32_to_cpu(task->cmdsn));
  3613. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  3614. io_task->pwrb_handle->wrb_index);
  3615. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  3616. io_task->psgl_handle->sgl_index);
  3617. switch (task->hdr->opcode & ISCSI_OPCODE_MASK) {
  3618. case ISCSI_OP_LOGIN:
  3619. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3620. TGT_DM_CMD);
  3621. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3622. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1);
  3623. hwi_write_buffer(pwrb, task);
  3624. break;
  3625. case ISCSI_OP_NOOP_OUT:
  3626. if (task->hdr->ttt != ISCSI_RESERVED_TAG) {
  3627. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3628. TGT_DM_CMD);
  3629. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt,
  3630. pwrb, 0);
  3631. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 1);
  3632. } else {
  3633. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3634. INI_RD_CMD);
  3635. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3636. }
  3637. hwi_write_buffer(pwrb, task);
  3638. break;
  3639. case ISCSI_OP_TEXT:
  3640. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3641. TGT_DM_CMD);
  3642. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3643. hwi_write_buffer(pwrb, task);
  3644. break;
  3645. case ISCSI_OP_SCSI_TMFUNC:
  3646. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3647. INI_TMF_CMD);
  3648. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3649. hwi_write_buffer(pwrb, task);
  3650. break;
  3651. case ISCSI_OP_LOGOUT:
  3652. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3653. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3654. HWH_TYPE_LOGOUT);
  3655. hwi_write_buffer(pwrb, task);
  3656. break;
  3657. default:
  3658. SE_DEBUG(DBG_LVL_1, "opcode =%d Not supported\n",
  3659. task->hdr->opcode & ISCSI_OPCODE_MASK);
  3660. return -EINVAL;
  3661. }
  3662. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb,
  3663. task->data_count);
  3664. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  3665. io_task->pwrb_handle->nxt_wrb_index);
  3666. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  3667. doorbell |= cid & DB_WRB_POST_CID_MASK;
  3668. doorbell |= (io_task->pwrb_handle->wrb_index &
  3669. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3670. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3671. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3672. return 0;
  3673. }
  3674. static int beiscsi_task_xmit(struct iscsi_task *task)
  3675. {
  3676. struct beiscsi_io_task *io_task = task->dd_data;
  3677. struct scsi_cmnd *sc = task->sc;
  3678. struct scatterlist *sg;
  3679. int num_sg;
  3680. unsigned int writedir = 0, xferlen = 0;
  3681. if (!sc)
  3682. return beiscsi_mtask(task);
  3683. io_task->scsi_cmnd = sc;
  3684. num_sg = scsi_dma_map(sc);
  3685. if (num_sg < 0) {
  3686. SE_DEBUG(DBG_LVL_1, " scsi_dma_map Failed\n")
  3687. return num_sg;
  3688. }
  3689. xferlen = scsi_bufflen(sc);
  3690. sg = scsi_sglist(sc);
  3691. if (sc->sc_data_direction == DMA_TO_DEVICE) {
  3692. writedir = 1;
  3693. SE_DEBUG(DBG_LVL_4, "task->imm_count=0x%08x\n",
  3694. task->imm_count);
  3695. } else
  3696. writedir = 0;
  3697. return beiscsi_iotask(task, sg, num_sg, xferlen, writedir);
  3698. }
  3699. static void beiscsi_quiesce(struct beiscsi_hba *phba)
  3700. {
  3701. struct hwi_controller *phwi_ctrlr;
  3702. struct hwi_context_memory *phwi_context;
  3703. struct be_eq_obj *pbe_eq;
  3704. unsigned int i, msix_vec;
  3705. u8 *real_offset = 0;
  3706. u32 value = 0;
  3707. phwi_ctrlr = phba->phwi_ctrlr;
  3708. phwi_context = phwi_ctrlr->phwi_ctxt;
  3709. hwi_disable_intr(phba);
  3710. if (phba->msix_enabled) {
  3711. for (i = 0; i <= phba->num_cpus; i++) {
  3712. msix_vec = phba->msix_entries[i].vector;
  3713. free_irq(msix_vec, &phwi_context->be_eq[i]);
  3714. kfree(phba->msi_name[i]);
  3715. }
  3716. } else
  3717. if (phba->pcidev->irq)
  3718. free_irq(phba->pcidev->irq, phba);
  3719. pci_disable_msix(phba->pcidev);
  3720. destroy_workqueue(phba->wq);
  3721. if (blk_iopoll_enabled)
  3722. for (i = 0; i < phba->num_cpus; i++) {
  3723. pbe_eq = &phwi_context->be_eq[i];
  3724. blk_iopoll_disable(&pbe_eq->iopoll);
  3725. }
  3726. beiscsi_clean_port(phba);
  3727. beiscsi_free_mem(phba);
  3728. real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
  3729. value = readl((void *)real_offset);
  3730. if (value & 0x00010000) {
  3731. value &= 0xfffeffff;
  3732. writel(value, (void *)real_offset);
  3733. }
  3734. beiscsi_unmap_pci_function(phba);
  3735. pci_free_consistent(phba->pcidev,
  3736. phba->ctrl.mbox_mem_alloced.size,
  3737. phba->ctrl.mbox_mem_alloced.va,
  3738. phba->ctrl.mbox_mem_alloced.dma);
  3739. }
  3740. static void beiscsi_remove(struct pci_dev *pcidev)
  3741. {
  3742. struct beiscsi_hba *phba = NULL;
  3743. phba = pci_get_drvdata(pcidev);
  3744. if (!phba) {
  3745. dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n");
  3746. return;
  3747. }
  3748. beiscsi_quiesce(phba);
  3749. iscsi_boot_destroy_kset(phba->boot_kset);
  3750. iscsi_host_remove(phba->shost);
  3751. pci_dev_put(phba->pcidev);
  3752. iscsi_host_free(phba->shost);
  3753. pci_disable_device(pcidev);
  3754. }
  3755. static void beiscsi_shutdown(struct pci_dev *pcidev)
  3756. {
  3757. struct beiscsi_hba *phba = NULL;
  3758. phba = (struct beiscsi_hba *)pci_get_drvdata(pcidev);
  3759. if (!phba) {
  3760. dev_err(&pcidev->dev, "beiscsi_shutdown called with no phba\n");
  3761. return;
  3762. }
  3763. beiscsi_quiesce(phba);
  3764. pci_disable_device(pcidev);
  3765. }
  3766. static void beiscsi_msix_enable(struct beiscsi_hba *phba)
  3767. {
  3768. int i, status;
  3769. for (i = 0; i <= phba->num_cpus; i++)
  3770. phba->msix_entries[i].entry = i;
  3771. status = pci_enable_msix(phba->pcidev, phba->msix_entries,
  3772. (phba->num_cpus + 1));
  3773. if (!status)
  3774. phba->msix_enabled = true;
  3775. return;
  3776. }
  3777. static int __devinit beiscsi_dev_probe(struct pci_dev *pcidev,
  3778. const struct pci_device_id *id)
  3779. {
  3780. struct beiscsi_hba *phba = NULL;
  3781. struct hwi_controller *phwi_ctrlr;
  3782. struct hwi_context_memory *phwi_context;
  3783. struct be_eq_obj *pbe_eq;
  3784. int ret, num_cpus, i;
  3785. u8 *real_offset = 0;
  3786. u32 value = 0;
  3787. ret = beiscsi_enable_pci(pcidev);
  3788. if (ret < 0) {
  3789. dev_err(&pcidev->dev, "beiscsi_dev_probe-"
  3790. " Failed to enable pci device\n");
  3791. return ret;
  3792. }
  3793. phba = beiscsi_hba_alloc(pcidev);
  3794. if (!phba) {
  3795. dev_err(&pcidev->dev, "beiscsi_dev_probe-"
  3796. " Failed in beiscsi_hba_alloc\n");
  3797. goto disable_pci;
  3798. }
  3799. switch (pcidev->device) {
  3800. case BE_DEVICE_ID1:
  3801. case OC_DEVICE_ID1:
  3802. case OC_DEVICE_ID2:
  3803. phba->generation = BE_GEN2;
  3804. break;
  3805. case BE_DEVICE_ID2:
  3806. case OC_DEVICE_ID3:
  3807. phba->generation = BE_GEN3;
  3808. break;
  3809. default:
  3810. phba->generation = 0;
  3811. }
  3812. if (enable_msix)
  3813. num_cpus = find_num_cpus();
  3814. else
  3815. num_cpus = 1;
  3816. phba->num_cpus = num_cpus;
  3817. SE_DEBUG(DBG_LVL_8, "num_cpus = %d\n", phba->num_cpus);
  3818. if (enable_msix) {
  3819. beiscsi_msix_enable(phba);
  3820. if (!phba->msix_enabled)
  3821. phba->num_cpus = 1;
  3822. }
  3823. ret = be_ctrl_init(phba, pcidev);
  3824. if (ret) {
  3825. shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe-"
  3826. "Failed in be_ctrl_init\n");
  3827. goto hba_free;
  3828. }
  3829. if (!num_hba) {
  3830. real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
  3831. value = readl((void *)real_offset);
  3832. if (value & 0x00010000) {
  3833. gcrashmode++;
  3834. shost_printk(KERN_ERR, phba->shost,
  3835. "Loading Driver in crashdump mode\n");
  3836. ret = beiscsi_cmd_reset_function(phba);
  3837. if (ret) {
  3838. shost_printk(KERN_ERR, phba->shost,
  3839. "Reset Failed. Aborting Crashdump\n");
  3840. goto hba_free;
  3841. }
  3842. ret = be_chk_reset_complete(phba);
  3843. if (ret) {
  3844. shost_printk(KERN_ERR, phba->shost,
  3845. "Failed to get out of reset."
  3846. "Aborting Crashdump\n");
  3847. goto hba_free;
  3848. }
  3849. } else {
  3850. value |= 0x00010000;
  3851. writel(value, (void *)real_offset);
  3852. num_hba++;
  3853. }
  3854. }
  3855. spin_lock_init(&phba->io_sgl_lock);
  3856. spin_lock_init(&phba->mgmt_sgl_lock);
  3857. spin_lock_init(&phba->isr_lock);
  3858. ret = mgmt_get_fw_config(&phba->ctrl, phba);
  3859. if (ret != 0) {
  3860. shost_printk(KERN_ERR, phba->shost,
  3861. "Error getting fw config\n");
  3862. goto free_port;
  3863. }
  3864. phba->shost->max_id = phba->fw_config.iscsi_cid_count;
  3865. beiscsi_get_params(phba);
  3866. phba->shost->can_queue = phba->params.ios_per_ctrl;
  3867. ret = beiscsi_init_port(phba);
  3868. if (ret < 0) {
  3869. shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe-"
  3870. "Failed in beiscsi_init_port\n");
  3871. goto free_port;
  3872. }
  3873. for (i = 0; i < MAX_MCC_CMD ; i++) {
  3874. init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
  3875. phba->ctrl.mcc_tag[i] = i + 1;
  3876. phba->ctrl.mcc_numtag[i + 1] = 0;
  3877. phba->ctrl.mcc_tag_available++;
  3878. }
  3879. phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0;
  3880. snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_q_irq%u",
  3881. phba->shost->host_no);
  3882. phba->wq = alloc_workqueue(phba->wq_name, WQ_MEM_RECLAIM, 1);
  3883. if (!phba->wq) {
  3884. shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe-"
  3885. "Failed to allocate work queue\n");
  3886. goto free_twq;
  3887. }
  3888. INIT_WORK(&phba->work_cqs, beiscsi_process_all_cqs);
  3889. phwi_ctrlr = phba->phwi_ctrlr;
  3890. phwi_context = phwi_ctrlr->phwi_ctxt;
  3891. if (blk_iopoll_enabled) {
  3892. for (i = 0; i < phba->num_cpus; i++) {
  3893. pbe_eq = &phwi_context->be_eq[i];
  3894. blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget,
  3895. be_iopoll);
  3896. blk_iopoll_enable(&pbe_eq->iopoll);
  3897. }
  3898. }
  3899. ret = beiscsi_init_irqs(phba);
  3900. if (ret < 0) {
  3901. shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe-"
  3902. "Failed to beiscsi_init_irqs\n");
  3903. goto free_blkenbld;
  3904. }
  3905. hwi_enable_intr(phba);
  3906. if (beiscsi_setup_boot_info(phba))
  3907. /*
  3908. * log error but continue, because we may not be using
  3909. * iscsi boot.
  3910. */
  3911. shost_printk(KERN_ERR, phba->shost, "Could not set up "
  3912. "iSCSI boot info.");
  3913. SE_DEBUG(DBG_LVL_8, "\n\n\n SUCCESS - DRIVER LOADED\n\n\n");
  3914. return 0;
  3915. free_blkenbld:
  3916. destroy_workqueue(phba->wq);
  3917. if (blk_iopoll_enabled)
  3918. for (i = 0; i < phba->num_cpus; i++) {
  3919. pbe_eq = &phwi_context->be_eq[i];
  3920. blk_iopoll_disable(&pbe_eq->iopoll);
  3921. }
  3922. free_twq:
  3923. beiscsi_clean_port(phba);
  3924. beiscsi_free_mem(phba);
  3925. free_port:
  3926. real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
  3927. value = readl((void *)real_offset);
  3928. if (value & 0x00010000) {
  3929. value &= 0xfffeffff;
  3930. writel(value, (void *)real_offset);
  3931. }
  3932. pci_free_consistent(phba->pcidev,
  3933. phba->ctrl.mbox_mem_alloced.size,
  3934. phba->ctrl.mbox_mem_alloced.va,
  3935. phba->ctrl.mbox_mem_alloced.dma);
  3936. beiscsi_unmap_pci_function(phba);
  3937. hba_free:
  3938. if (phba->msix_enabled)
  3939. pci_disable_msix(phba->pcidev);
  3940. iscsi_host_remove(phba->shost);
  3941. pci_dev_put(phba->pcidev);
  3942. iscsi_host_free(phba->shost);
  3943. disable_pci:
  3944. pci_disable_device(pcidev);
  3945. return ret;
  3946. }
  3947. struct iscsi_transport beiscsi_iscsi_transport = {
  3948. .owner = THIS_MODULE,
  3949. .name = DRV_NAME,
  3950. .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO |
  3951. CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD,
  3952. .create_session = beiscsi_session_create,
  3953. .destroy_session = beiscsi_session_destroy,
  3954. .create_conn = beiscsi_conn_create,
  3955. .bind_conn = beiscsi_conn_bind,
  3956. .destroy_conn = iscsi_conn_teardown,
  3957. .attr_is_visible = be2iscsi_attr_is_visible,
  3958. .set_param = beiscsi_set_param,
  3959. .get_conn_param = iscsi_conn_get_param,
  3960. .get_session_param = iscsi_session_get_param,
  3961. .get_host_param = beiscsi_get_host_param,
  3962. .start_conn = beiscsi_conn_start,
  3963. .stop_conn = iscsi_conn_stop,
  3964. .send_pdu = iscsi_conn_send_pdu,
  3965. .xmit_task = beiscsi_task_xmit,
  3966. .cleanup_task = beiscsi_cleanup_task,
  3967. .alloc_pdu = beiscsi_alloc_pdu,
  3968. .parse_pdu_itt = beiscsi_parse_pdu,
  3969. .get_stats = beiscsi_conn_get_stats,
  3970. .get_ep_param = beiscsi_ep_get_param,
  3971. .ep_connect = beiscsi_ep_connect,
  3972. .ep_poll = beiscsi_ep_poll,
  3973. .ep_disconnect = beiscsi_ep_disconnect,
  3974. .session_recovery_timedout = iscsi_session_recovery_timedout,
  3975. };
  3976. static struct pci_driver beiscsi_pci_driver = {
  3977. .name = DRV_NAME,
  3978. .probe = beiscsi_dev_probe,
  3979. .remove = beiscsi_remove,
  3980. .shutdown = beiscsi_shutdown,
  3981. .id_table = beiscsi_pci_id_table
  3982. };
  3983. static int __init beiscsi_module_init(void)
  3984. {
  3985. int ret;
  3986. beiscsi_scsi_transport =
  3987. iscsi_register_transport(&beiscsi_iscsi_transport);
  3988. if (!beiscsi_scsi_transport) {
  3989. SE_DEBUG(DBG_LVL_1,
  3990. "beiscsi_module_init - Unable to register beiscsi"
  3991. "transport.\n");
  3992. return -ENOMEM;
  3993. }
  3994. SE_DEBUG(DBG_LVL_8, "In beiscsi_module_init, tt=%p\n",
  3995. &beiscsi_iscsi_transport);
  3996. ret = pci_register_driver(&beiscsi_pci_driver);
  3997. if (ret) {
  3998. SE_DEBUG(DBG_LVL_1,
  3999. "beiscsi_module_init - Unable to register"
  4000. "beiscsi pci driver.\n");
  4001. goto unregister_iscsi_transport;
  4002. }
  4003. return 0;
  4004. unregister_iscsi_transport:
  4005. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4006. return ret;
  4007. }
  4008. static void __exit beiscsi_module_exit(void)
  4009. {
  4010. pci_unregister_driver(&beiscsi_pci_driver);
  4011. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4012. }
  4013. module_init(beiscsi_module_init);
  4014. module_exit(beiscsi_module_exit);