fimc-core.c 36 KB

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  1. /*
  2. * S5P camera interface (video postprocessor) driver
  3. *
  4. * Copyright (c) 2010 Samsung Electronics
  5. *
  6. * Sylwester Nawrocki, <s.nawrocki@samsung.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published
  10. * by the Free Software Foundation, either version 2 of the License,
  11. * or (at your option) any later version.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/version.h>
  16. #include <linux/types.h>
  17. #include <linux/errno.h>
  18. #include <linux/bug.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/device.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/list.h>
  23. #include <linux/io.h>
  24. #include <linux/slab.h>
  25. #include <linux/clk.h>
  26. #include <media/v4l2-ioctl.h>
  27. #include <media/videobuf-dma-contig.h>
  28. #include "fimc-core.h"
  29. static char *fimc_clock_name[NUM_FIMC_CLOCKS] = { "sclk_fimc", "fimc" };
  30. static struct fimc_fmt fimc_formats[] = {
  31. {
  32. .name = "RGB565",
  33. .fourcc = V4L2_PIX_FMT_RGB565X,
  34. .depth = 16,
  35. .color = S5P_FIMC_RGB565,
  36. .buff_cnt = 1,
  37. .planes_cnt = 1
  38. }, {
  39. .name = "BGR666",
  40. .fourcc = V4L2_PIX_FMT_BGR666,
  41. .depth = 32,
  42. .color = S5P_FIMC_RGB666,
  43. .buff_cnt = 1,
  44. .planes_cnt = 1
  45. }, {
  46. .name = "XRGB-8-8-8-8, 24 bpp",
  47. .fourcc = V4L2_PIX_FMT_RGB24,
  48. .depth = 32,
  49. .color = S5P_FIMC_RGB888,
  50. .buff_cnt = 1,
  51. .planes_cnt = 1
  52. }, {
  53. .name = "YUV 4:2:2 packed, YCbYCr",
  54. .fourcc = V4L2_PIX_FMT_YUYV,
  55. .depth = 16,
  56. .color = S5P_FIMC_YCBYCR422,
  57. .buff_cnt = 1,
  58. .planes_cnt = 1
  59. }, {
  60. .name = "YUV 4:2:2 packed, CbYCrY",
  61. .fourcc = V4L2_PIX_FMT_UYVY,
  62. .depth = 16,
  63. .color = S5P_FIMC_CBYCRY422,
  64. .buff_cnt = 1,
  65. .planes_cnt = 1
  66. }, {
  67. .name = "YUV 4:2:2 packed, CrYCbY",
  68. .fourcc = V4L2_PIX_FMT_VYUY,
  69. .depth = 16,
  70. .color = S5P_FIMC_CRYCBY422,
  71. .buff_cnt = 1,
  72. .planes_cnt = 1
  73. }, {
  74. .name = "YUV 4:2:2 packed, YCrYCb",
  75. .fourcc = V4L2_PIX_FMT_YVYU,
  76. .depth = 16,
  77. .color = S5P_FIMC_YCRYCB422,
  78. .buff_cnt = 1,
  79. .planes_cnt = 1
  80. }, {
  81. .name = "YUV 4:2:2 planar, Y/Cb/Cr",
  82. .fourcc = V4L2_PIX_FMT_YUV422P,
  83. .depth = 12,
  84. .color = S5P_FIMC_YCBCR422,
  85. .buff_cnt = 1,
  86. .planes_cnt = 3
  87. }, {
  88. .name = "YUV 4:2:2 planar, Y/CbCr",
  89. .fourcc = V4L2_PIX_FMT_NV16,
  90. .depth = 16,
  91. .color = S5P_FIMC_YCBCR422,
  92. .buff_cnt = 1,
  93. .planes_cnt = 2
  94. }, {
  95. .name = "YUV 4:2:2 planar, Y/CrCb",
  96. .fourcc = V4L2_PIX_FMT_NV61,
  97. .depth = 16,
  98. .color = S5P_FIMC_RGB565,
  99. .buff_cnt = 1,
  100. .planes_cnt = 2
  101. }, {
  102. .name = "YUV 4:2:0 planar, YCbCr",
  103. .fourcc = V4L2_PIX_FMT_YUV420,
  104. .depth = 12,
  105. .color = S5P_FIMC_YCBCR420,
  106. .buff_cnt = 1,
  107. .planes_cnt = 3
  108. }, {
  109. .name = "YUV 4:2:0 planar, Y/CbCr",
  110. .fourcc = V4L2_PIX_FMT_NV12,
  111. .depth = 12,
  112. .color = S5P_FIMC_YCBCR420,
  113. .buff_cnt = 1,
  114. .planes_cnt = 2
  115. }
  116. };
  117. static struct v4l2_queryctrl fimc_ctrls[] = {
  118. {
  119. .id = V4L2_CID_HFLIP,
  120. .type = V4L2_CTRL_TYPE_BOOLEAN,
  121. .name = "Horizontal flip",
  122. .minimum = 0,
  123. .maximum = 1,
  124. .default_value = 0,
  125. },
  126. {
  127. .id = V4L2_CID_VFLIP,
  128. .type = V4L2_CTRL_TYPE_BOOLEAN,
  129. .name = "Vertical flip",
  130. .minimum = 0,
  131. .maximum = 1,
  132. .default_value = 0,
  133. },
  134. {
  135. .id = V4L2_CID_ROTATE,
  136. .type = V4L2_CTRL_TYPE_INTEGER,
  137. .name = "Rotation (CCW)",
  138. .minimum = 0,
  139. .maximum = 270,
  140. .step = 90,
  141. .default_value = 0,
  142. },
  143. };
  144. static struct v4l2_queryctrl *get_ctrl(int id)
  145. {
  146. int i;
  147. for (i = 0; i < ARRAY_SIZE(fimc_ctrls); ++i)
  148. if (id == fimc_ctrls[i].id)
  149. return &fimc_ctrls[i];
  150. return NULL;
  151. }
  152. static int fimc_check_scaler_ratio(struct v4l2_rect *r, struct fimc_frame *f)
  153. {
  154. if (r->width > f->width) {
  155. if (f->width > (r->width * SCALER_MAX_HRATIO))
  156. return -EINVAL;
  157. } else {
  158. if ((f->width * SCALER_MAX_HRATIO) < r->width)
  159. return -EINVAL;
  160. }
  161. if (r->height > f->height) {
  162. if (f->height > (r->height * SCALER_MAX_VRATIO))
  163. return -EINVAL;
  164. } else {
  165. if ((f->height * SCALER_MAX_VRATIO) < r->height)
  166. return -EINVAL;
  167. }
  168. return 0;
  169. }
  170. static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
  171. {
  172. if (src >= tar * 64) {
  173. return -EINVAL;
  174. } else if (src >= tar * 32) {
  175. *ratio = 32;
  176. *shift = 5;
  177. } else if (src >= tar * 16) {
  178. *ratio = 16;
  179. *shift = 4;
  180. } else if (src >= tar * 8) {
  181. *ratio = 8;
  182. *shift = 3;
  183. } else if (src >= tar * 4) {
  184. *ratio = 4;
  185. *shift = 2;
  186. } else if (src >= tar * 2) {
  187. *ratio = 2;
  188. *shift = 1;
  189. } else {
  190. *ratio = 1;
  191. *shift = 0;
  192. }
  193. return 0;
  194. }
  195. static int fimc_set_scaler_info(struct fimc_ctx *ctx)
  196. {
  197. struct fimc_scaler *sc = &ctx->scaler;
  198. struct fimc_frame *s_frame = &ctx->s_frame;
  199. struct fimc_frame *d_frame = &ctx->d_frame;
  200. int tx, ty, sx, sy;
  201. int ret;
  202. tx = d_frame->width;
  203. ty = d_frame->height;
  204. if (tx <= 0 || ty <= 0) {
  205. v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
  206. "invalid target size: %d x %d", tx, ty);
  207. return -EINVAL;
  208. }
  209. sx = s_frame->width;
  210. sy = s_frame->height;
  211. if (sx <= 0 || sy <= 0) {
  212. err("invalid source size: %d x %d", sx, sy);
  213. return -EINVAL;
  214. }
  215. sc->real_width = sx;
  216. sc->real_height = sy;
  217. dbg("sx= %d, sy= %d, tx= %d, ty= %d", sx, sy, tx, ty);
  218. ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
  219. if (ret)
  220. return ret;
  221. ret = fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor);
  222. if (ret)
  223. return ret;
  224. sc->pre_dst_width = sx / sc->pre_hratio;
  225. sc->pre_dst_height = sy / sc->pre_vratio;
  226. sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
  227. sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
  228. sc->scaleup_h = (tx >= sx) ? 1 : 0;
  229. sc->scaleup_v = (ty >= sy) ? 1 : 0;
  230. /* check to see if input and output size/format differ */
  231. if (s_frame->fmt->color == d_frame->fmt->color
  232. && s_frame->width == d_frame->width
  233. && s_frame->height == d_frame->height)
  234. sc->copy_mode = 1;
  235. else
  236. sc->copy_mode = 0;
  237. return 0;
  238. }
  239. static irqreturn_t fimc_isr(int irq, void *priv)
  240. {
  241. struct fimc_vid_buffer *src_buf, *dst_buf;
  242. struct fimc_dev *fimc = (struct fimc_dev *)priv;
  243. struct fimc_ctx *ctx;
  244. BUG_ON(!fimc);
  245. fimc_hw_clear_irq(fimc);
  246. spin_lock(&fimc->slock);
  247. if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
  248. ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
  249. if (!ctx || !ctx->m2m_ctx)
  250. goto isr_unlock;
  251. src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
  252. dst_buf = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
  253. if (src_buf && dst_buf) {
  254. spin_lock(&fimc->irqlock);
  255. src_buf->vb.state = dst_buf->vb.state = VIDEOBUF_DONE;
  256. wake_up(&src_buf->vb.done);
  257. wake_up(&dst_buf->vb.done);
  258. spin_unlock(&fimc->irqlock);
  259. v4l2_m2m_job_finish(fimc->m2m.m2m_dev, ctx->m2m_ctx);
  260. }
  261. }
  262. isr_unlock:
  263. spin_unlock(&fimc->slock);
  264. return IRQ_HANDLED;
  265. }
  266. /* The color format (planes_cnt, buff_cnt) must be already configured. */
  267. static int fimc_prepare_addr(struct fimc_ctx *ctx,
  268. struct fimc_vid_buffer *buf, enum v4l2_buf_type type)
  269. {
  270. struct fimc_frame *frame;
  271. struct fimc_addr *paddr;
  272. u32 pix_size;
  273. int ret = 0;
  274. ctx_m2m_get_frame(frame, ctx, type);
  275. paddr = &frame->paddr;
  276. if (!buf)
  277. return -EINVAL;
  278. pix_size = frame->width * frame->height;
  279. dbg("buff_cnt= %d, planes_cnt= %d, frame->size= %d, pix_size= %d",
  280. frame->fmt->buff_cnt, frame->fmt->planes_cnt,
  281. frame->size, pix_size);
  282. if (frame->fmt->buff_cnt == 1) {
  283. paddr->y = videobuf_to_dma_contig(&buf->vb);
  284. switch (frame->fmt->planes_cnt) {
  285. case 1:
  286. paddr->cb = 0;
  287. paddr->cr = 0;
  288. break;
  289. case 2:
  290. /* decompose Y into Y/Cb */
  291. paddr->cb = (u32)(paddr->y + pix_size);
  292. paddr->cr = 0;
  293. break;
  294. case 3:
  295. paddr->cb = (u32)(paddr->y + pix_size);
  296. /* decompose Y into Y/Cb/Cr */
  297. if (S5P_FIMC_YCBCR420 == frame->fmt->color)
  298. paddr->cr = (u32)(paddr->cb
  299. + (pix_size >> 2));
  300. else /* 422 */
  301. paddr->cr = (u32)(paddr->cb
  302. + (pix_size >> 1));
  303. break;
  304. default:
  305. return -EINVAL;
  306. }
  307. }
  308. dbg("PHYS_ADDR: type= %d, y= 0x%X cb= 0x%X cr= 0x%X ret= %d",
  309. type, paddr->y, paddr->cb, paddr->cr, ret);
  310. return ret;
  311. }
  312. /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
  313. static void fimc_set_yuv_order(struct fimc_ctx *ctx)
  314. {
  315. /* The one only mode supported in SoC. */
  316. ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
  317. ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
  318. /* Set order for 1 plane input formats. */
  319. switch (ctx->s_frame.fmt->color) {
  320. case S5P_FIMC_YCRYCB422:
  321. ctx->in_order_1p = S5P_FIMC_IN_YCRYCB;
  322. break;
  323. case S5P_FIMC_CBYCRY422:
  324. ctx->in_order_1p = S5P_FIMC_IN_CBYCRY;
  325. break;
  326. case S5P_FIMC_CRYCBY422:
  327. ctx->in_order_1p = S5P_FIMC_IN_CRYCBY;
  328. break;
  329. case S5P_FIMC_YCBYCR422:
  330. default:
  331. ctx->in_order_1p = S5P_FIMC_IN_YCBYCR;
  332. break;
  333. }
  334. dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
  335. switch (ctx->d_frame.fmt->color) {
  336. case S5P_FIMC_YCRYCB422:
  337. ctx->out_order_1p = S5P_FIMC_OUT_YCRYCB;
  338. break;
  339. case S5P_FIMC_CBYCRY422:
  340. ctx->out_order_1p = S5P_FIMC_OUT_CBYCRY;
  341. break;
  342. case S5P_FIMC_CRYCBY422:
  343. ctx->out_order_1p = S5P_FIMC_OUT_CRYCBY;
  344. break;
  345. case S5P_FIMC_YCBYCR422:
  346. default:
  347. ctx->out_order_1p = S5P_FIMC_OUT_YCBYCR;
  348. break;
  349. }
  350. dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
  351. }
  352. /**
  353. * fimc_prepare_config - check dimensions, operation and color mode
  354. * and pre-calculate offset and the scaling coefficients.
  355. *
  356. * @ctx: hardware context information
  357. * @flags: flags indicating which parameters to check/update
  358. *
  359. * Return: 0 if dimensions are valid or non zero otherwise.
  360. */
  361. static int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags)
  362. {
  363. struct fimc_frame *s_frame, *d_frame;
  364. struct fimc_vid_buffer *buf = NULL;
  365. struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
  366. int ret = 0;
  367. s_frame = &ctx->s_frame;
  368. d_frame = &ctx->d_frame;
  369. if (flags & FIMC_PARAMS) {
  370. if ((ctx->out_path == FIMC_DMA) &&
  371. (ctx->rotation == 90 || ctx->rotation == 270)) {
  372. swap(d_frame->f_width, d_frame->f_height);
  373. swap(d_frame->width, d_frame->height);
  374. }
  375. /* Prepare the output offset ratios for scaler. */
  376. d_frame->dma_offset.y_h = d_frame->offs_h;
  377. if (!variant->pix_hoff)
  378. d_frame->dma_offset.y_h *= (d_frame->fmt->depth >> 3);
  379. d_frame->dma_offset.y_v = d_frame->offs_v;
  380. d_frame->dma_offset.cb_h = d_frame->offs_h;
  381. d_frame->dma_offset.cb_v = d_frame->offs_v;
  382. d_frame->dma_offset.cr_h = d_frame->offs_h;
  383. d_frame->dma_offset.cr_v = d_frame->offs_v;
  384. if (!variant->pix_hoff && d_frame->fmt->planes_cnt == 3) {
  385. d_frame->dma_offset.cb_h >>= 1;
  386. d_frame->dma_offset.cb_v >>= 1;
  387. d_frame->dma_offset.cr_h >>= 1;
  388. d_frame->dma_offset.cr_v >>= 1;
  389. }
  390. dbg("out offset: color= %d, y_h= %d, y_v= %d",
  391. d_frame->fmt->color,
  392. d_frame->dma_offset.y_h, d_frame->dma_offset.y_v);
  393. /* Prepare the input offset ratios for scaler. */
  394. s_frame->dma_offset.y_h = s_frame->offs_h;
  395. if (!variant->pix_hoff)
  396. s_frame->dma_offset.y_h *= (s_frame->fmt->depth >> 3);
  397. s_frame->dma_offset.y_v = s_frame->offs_v;
  398. s_frame->dma_offset.cb_h = s_frame->offs_h;
  399. s_frame->dma_offset.cb_v = s_frame->offs_v;
  400. s_frame->dma_offset.cr_h = s_frame->offs_h;
  401. s_frame->dma_offset.cr_v = s_frame->offs_v;
  402. if (!variant->pix_hoff && s_frame->fmt->planes_cnt == 3) {
  403. s_frame->dma_offset.cb_h >>= 1;
  404. s_frame->dma_offset.cb_v >>= 1;
  405. s_frame->dma_offset.cr_h >>= 1;
  406. s_frame->dma_offset.cr_v >>= 1;
  407. }
  408. dbg("in offset: color= %d, y_h= %d, y_v= %d",
  409. s_frame->fmt->color, s_frame->dma_offset.y_h,
  410. s_frame->dma_offset.y_v);
  411. fimc_set_yuv_order(ctx);
  412. /* Check against the scaler ratio. */
  413. if (s_frame->height > (SCALER_MAX_VRATIO * d_frame->height) ||
  414. s_frame->width > (SCALER_MAX_HRATIO * d_frame->width)) {
  415. err("out of scaler range");
  416. return -EINVAL;
  417. }
  418. }
  419. /* Input DMA mode is not allowed when the scaler is disabled. */
  420. ctx->scaler.enabled = 1;
  421. if (flags & FIMC_SRC_ADDR) {
  422. buf = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
  423. ret = fimc_prepare_addr(ctx, buf,
  424. V4L2_BUF_TYPE_VIDEO_OUTPUT);
  425. if (ret)
  426. return ret;
  427. }
  428. if (flags & FIMC_DST_ADDR) {
  429. buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
  430. ret = fimc_prepare_addr(ctx, buf,
  431. V4L2_BUF_TYPE_VIDEO_CAPTURE);
  432. }
  433. return ret;
  434. }
  435. static void fimc_dma_run(void *priv)
  436. {
  437. struct fimc_ctx *ctx = priv;
  438. struct fimc_dev *fimc;
  439. unsigned long flags;
  440. u32 ret;
  441. if (WARN(!ctx, "null hardware context"))
  442. return;
  443. fimc = ctx->fimc_dev;
  444. spin_lock_irqsave(&ctx->slock, flags);
  445. set_bit(ST_M2M_PEND, &fimc->state);
  446. ctx->state |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
  447. ret = fimc_prepare_config(ctx, ctx->state);
  448. if (ret) {
  449. err("general configuration error");
  450. goto dma_unlock;
  451. }
  452. if (fimc->m2m.ctx != ctx)
  453. ctx->state |= FIMC_PARAMS;
  454. fimc_hw_set_input_addr(fimc, &ctx->s_frame.paddr);
  455. if (ctx->state & FIMC_PARAMS) {
  456. fimc_hw_set_input_path(ctx);
  457. fimc_hw_set_in_dma(ctx);
  458. if (fimc_set_scaler_info(ctx)) {
  459. err("scaler configuration error");
  460. goto dma_unlock;
  461. }
  462. fimc_hw_set_prescaler(ctx);
  463. fimc_hw_set_scaler(ctx);
  464. fimc_hw_set_target_format(ctx);
  465. fimc_hw_set_rotation(ctx);
  466. fimc_hw_set_effect(ctx);
  467. }
  468. fimc_hw_set_output_path(ctx);
  469. if (ctx->state & (FIMC_DST_ADDR | FIMC_PARAMS))
  470. fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr);
  471. if (ctx->state & FIMC_PARAMS)
  472. fimc_hw_set_out_dma(ctx);
  473. if (ctx->scaler.enabled)
  474. fimc_hw_start_scaler(fimc);
  475. fimc_hw_en_capture(ctx);
  476. ctx->state = 0;
  477. fimc_hw_start_in_dma(fimc);
  478. fimc->m2m.ctx = ctx;
  479. dma_unlock:
  480. spin_unlock_irqrestore(&ctx->slock, flags);
  481. }
  482. /* Nothing done in job_abort. */
  483. static void fimc_job_abort(void *priv) {}
  484. static void fimc_buf_release(struct videobuf_queue *vq,
  485. struct videobuf_buffer *vb)
  486. {
  487. videobuf_dma_contig_free(vq, vb);
  488. vb->state = VIDEOBUF_NEEDS_INIT;
  489. }
  490. static int fimc_buf_setup(struct videobuf_queue *vq, unsigned int *count,
  491. unsigned int *size)
  492. {
  493. struct fimc_ctx *ctx = vq->priv_data;
  494. struct fimc_frame *frame;
  495. ctx_m2m_get_frame(frame, ctx, vq->type);
  496. *size = (frame->width * frame->height * frame->fmt->depth) >> 3;
  497. if (0 == *count)
  498. *count = 1;
  499. return 0;
  500. }
  501. static int fimc_buf_prepare(struct videobuf_queue *vq,
  502. struct videobuf_buffer *vb, enum v4l2_field field)
  503. {
  504. struct fimc_ctx *ctx = vq->priv_data;
  505. struct v4l2_device *v4l2_dev = &ctx->fimc_dev->m2m.v4l2_dev;
  506. struct fimc_frame *frame;
  507. int ret;
  508. ctx_m2m_get_frame(frame, ctx, vq->type);
  509. if (vb->baddr) {
  510. if (vb->bsize < frame->size) {
  511. v4l2_err(v4l2_dev,
  512. "User-provided buffer too small (%d < %d)\n",
  513. vb->bsize, frame->size);
  514. WARN_ON(1);
  515. return -EINVAL;
  516. }
  517. } else if (vb->state != VIDEOBUF_NEEDS_INIT
  518. && vb->bsize < frame->size) {
  519. return -EINVAL;
  520. }
  521. vb->width = frame->width;
  522. vb->height = frame->height;
  523. vb->bytesperline = (frame->width * frame->fmt->depth) >> 3;
  524. vb->size = frame->size;
  525. vb->field = field;
  526. if (VIDEOBUF_NEEDS_INIT == vb->state) {
  527. ret = videobuf_iolock(vq, vb, NULL);
  528. if (ret) {
  529. v4l2_err(v4l2_dev, "Iolock failed\n");
  530. fimc_buf_release(vq, vb);
  531. return ret;
  532. }
  533. }
  534. vb->state = VIDEOBUF_PREPARED;
  535. return 0;
  536. }
  537. static void fimc_buf_queue(struct videobuf_queue *vq,
  538. struct videobuf_buffer *vb)
  539. {
  540. struct fimc_ctx *ctx = vq->priv_data;
  541. v4l2_m2m_buf_queue(ctx->m2m_ctx, vq, vb);
  542. }
  543. struct videobuf_queue_ops fimc_qops = {
  544. .buf_setup = fimc_buf_setup,
  545. .buf_prepare = fimc_buf_prepare,
  546. .buf_queue = fimc_buf_queue,
  547. .buf_release = fimc_buf_release,
  548. };
  549. static int fimc_m2m_querycap(struct file *file, void *priv,
  550. struct v4l2_capability *cap)
  551. {
  552. struct fimc_ctx *ctx = file->private_data;
  553. struct fimc_dev *fimc = ctx->fimc_dev;
  554. strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
  555. strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
  556. cap->bus_info[0] = 0;
  557. cap->version = KERNEL_VERSION(1, 0, 0);
  558. cap->capabilities = V4L2_CAP_STREAMING |
  559. V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT;
  560. return 0;
  561. }
  562. static int fimc_m2m_enum_fmt(struct file *file, void *priv,
  563. struct v4l2_fmtdesc *f)
  564. {
  565. struct fimc_fmt *fmt;
  566. if (f->index >= ARRAY_SIZE(fimc_formats))
  567. return -EINVAL;
  568. fmt = &fimc_formats[f->index];
  569. strncpy(f->description, fmt->name, sizeof(f->description) - 1);
  570. f->pixelformat = fmt->fourcc;
  571. return 0;
  572. }
  573. static int fimc_m2m_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
  574. {
  575. struct fimc_ctx *ctx = priv;
  576. struct fimc_frame *frame;
  577. ctx_m2m_get_frame(frame, ctx, f->type);
  578. f->fmt.pix.width = frame->width;
  579. f->fmt.pix.height = frame->height;
  580. f->fmt.pix.field = V4L2_FIELD_NONE;
  581. f->fmt.pix.pixelformat = frame->fmt->fourcc;
  582. return 0;
  583. }
  584. static struct fimc_fmt *find_format(struct v4l2_format *f)
  585. {
  586. struct fimc_fmt *fmt;
  587. unsigned int i;
  588. for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
  589. fmt = &fimc_formats[i];
  590. if (fmt->fourcc == f->fmt.pix.pixelformat)
  591. break;
  592. }
  593. if (i == ARRAY_SIZE(fimc_formats))
  594. return NULL;
  595. return fmt;
  596. }
  597. static int fimc_m2m_try_fmt(struct file *file, void *priv,
  598. struct v4l2_format *f)
  599. {
  600. struct fimc_fmt *fmt;
  601. u32 max_width, max_height, mod_x, mod_y;
  602. struct fimc_ctx *ctx = priv;
  603. struct fimc_dev *fimc = ctx->fimc_dev;
  604. struct v4l2_pix_format *pix = &f->fmt.pix;
  605. struct samsung_fimc_variant *variant = fimc->variant;
  606. fmt = find_format(f);
  607. if (!fmt) {
  608. v4l2_err(&fimc->m2m.v4l2_dev,
  609. "Fourcc format (0x%X) invalid.\n", pix->pixelformat);
  610. return -EINVAL;
  611. }
  612. if (pix->field == V4L2_FIELD_ANY)
  613. pix->field = V4L2_FIELD_NONE;
  614. else if (V4L2_FIELD_NONE != pix->field)
  615. return -EINVAL;
  616. if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
  617. max_width = variant->scaler_dis_w;
  618. max_height = variant->scaler_dis_w;
  619. mod_x = variant->min_inp_pixsize;
  620. mod_y = variant->min_inp_pixsize;
  621. } else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
  622. max_width = variant->out_rot_dis_w;
  623. max_height = variant->out_rot_dis_w;
  624. mod_x = variant->min_out_pixsize;
  625. mod_y = variant->min_out_pixsize;
  626. } else {
  627. err("Wrong stream type (%d)", f->type);
  628. return -EINVAL;
  629. }
  630. dbg("max_w= %d, max_h= %d", max_width, max_height);
  631. if (pix->height > max_height)
  632. pix->height = max_height;
  633. if (pix->width > max_width)
  634. pix->width = max_width;
  635. if (tiled_fmt(fmt)) {
  636. mod_x = 64; /* 64x32 tile */
  637. mod_y = 32;
  638. }
  639. dbg("mod_x= 0x%X, mod_y= 0x%X", mod_x, mod_y);
  640. pix->width = (pix->width == 0) ? mod_x : ALIGN(pix->width, mod_x);
  641. pix->height = (pix->height == 0) ? mod_y : ALIGN(pix->height, mod_y);
  642. if (pix->bytesperline == 0 ||
  643. pix->bytesperline * 8 / fmt->depth > pix->width)
  644. pix->bytesperline = (pix->width * fmt->depth) >> 3;
  645. if (pix->sizeimage == 0)
  646. pix->sizeimage = pix->height * pix->bytesperline;
  647. dbg("pix->bytesperline= %d, fmt->depth= %d",
  648. pix->bytesperline, fmt->depth);
  649. return 0;
  650. }
  651. static int fimc_m2m_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
  652. {
  653. struct fimc_ctx *ctx = priv;
  654. struct v4l2_device *v4l2_dev = &ctx->fimc_dev->m2m.v4l2_dev;
  655. struct videobuf_queue *src_vq, *dst_vq;
  656. struct fimc_frame *frame;
  657. struct v4l2_pix_format *pix;
  658. unsigned long flags;
  659. int ret = 0;
  660. BUG_ON(!ctx);
  661. ret = fimc_m2m_try_fmt(file, priv, f);
  662. if (ret)
  663. return ret;
  664. mutex_lock(&ctx->fimc_dev->lock);
  665. src_vq = v4l2_m2m_get_src_vq(ctx->m2m_ctx);
  666. dst_vq = v4l2_m2m_get_dst_vq(ctx->m2m_ctx);
  667. mutex_lock(&src_vq->vb_lock);
  668. mutex_lock(&dst_vq->vb_lock);
  669. if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
  670. if (videobuf_queue_is_busy(src_vq)) {
  671. v4l2_err(v4l2_dev, "%s queue busy\n", __func__);
  672. ret = -EBUSY;
  673. goto s_fmt_out;
  674. }
  675. frame = &ctx->s_frame;
  676. spin_lock_irqsave(&ctx->slock, flags);
  677. ctx->state |= FIMC_SRC_FMT;
  678. spin_unlock_irqrestore(&ctx->slock, flags);
  679. } else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
  680. if (videobuf_queue_is_busy(dst_vq)) {
  681. v4l2_err(v4l2_dev, "%s queue busy\n", __func__);
  682. ret = -EBUSY;
  683. goto s_fmt_out;
  684. }
  685. frame = &ctx->d_frame;
  686. spin_lock_irqsave(&ctx->slock, flags);
  687. ctx->state |= FIMC_DST_FMT;
  688. spin_unlock_irqrestore(&ctx->slock, flags);
  689. } else {
  690. v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
  691. "Wrong buffer/video queue type (%d)\n", f->type);
  692. return -EINVAL;
  693. }
  694. pix = &f->fmt.pix;
  695. frame->fmt = find_format(f);
  696. if (!frame->fmt) {
  697. ret = -EINVAL;
  698. goto s_fmt_out;
  699. }
  700. frame->f_width = pix->bytesperline * 8 / frame->fmt->depth;
  701. frame->f_height = pix->sizeimage/pix->bytesperline;
  702. frame->width = pix->width;
  703. frame->height = pix->height;
  704. frame->o_width = pix->width;
  705. frame->o_height = pix->height;
  706. frame->offs_h = 0;
  707. frame->offs_v = 0;
  708. frame->size = (pix->width * pix->height * frame->fmt->depth) >> 3;
  709. src_vq->field = dst_vq->field = pix->field;
  710. spin_lock_irqsave(&ctx->slock, flags);
  711. ctx->state |= FIMC_PARAMS;
  712. spin_unlock_irqrestore(&ctx->slock, flags);
  713. dbg("f_width= %d, f_height= %d", frame->f_width, frame->f_height);
  714. s_fmt_out:
  715. mutex_unlock(&dst_vq->vb_lock);
  716. mutex_unlock(&src_vq->vb_lock);
  717. mutex_unlock(&ctx->fimc_dev->lock);
  718. return ret;
  719. }
  720. static int fimc_m2m_reqbufs(struct file *file, void *priv,
  721. struct v4l2_requestbuffers *reqbufs)
  722. {
  723. struct fimc_ctx *ctx = priv;
  724. return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
  725. }
  726. static int fimc_m2m_querybuf(struct file *file, void *priv,
  727. struct v4l2_buffer *buf)
  728. {
  729. struct fimc_ctx *ctx = priv;
  730. return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
  731. }
  732. static int fimc_m2m_qbuf(struct file *file, void *priv,
  733. struct v4l2_buffer *buf)
  734. {
  735. struct fimc_ctx *ctx = priv;
  736. return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
  737. }
  738. static int fimc_m2m_dqbuf(struct file *file, void *priv,
  739. struct v4l2_buffer *buf)
  740. {
  741. struct fimc_ctx *ctx = priv;
  742. return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
  743. }
  744. static int fimc_m2m_streamon(struct file *file, void *priv,
  745. enum v4l2_buf_type type)
  746. {
  747. struct fimc_ctx *ctx = priv;
  748. return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
  749. }
  750. static int fimc_m2m_streamoff(struct file *file, void *priv,
  751. enum v4l2_buf_type type)
  752. {
  753. struct fimc_ctx *ctx = priv;
  754. return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
  755. }
  756. int fimc_m2m_queryctrl(struct file *file, void *priv,
  757. struct v4l2_queryctrl *qc)
  758. {
  759. struct v4l2_queryctrl *c;
  760. c = get_ctrl(qc->id);
  761. if (!c)
  762. return -EINVAL;
  763. *qc = *c;
  764. return 0;
  765. }
  766. int fimc_m2m_g_ctrl(struct file *file, void *priv,
  767. struct v4l2_control *ctrl)
  768. {
  769. struct fimc_ctx *ctx = priv;
  770. switch (ctrl->id) {
  771. case V4L2_CID_HFLIP:
  772. ctrl->value = (FLIP_X_AXIS & ctx->flip) ? 1 : 0;
  773. break;
  774. case V4L2_CID_VFLIP:
  775. ctrl->value = (FLIP_Y_AXIS & ctx->flip) ? 1 : 0;
  776. break;
  777. case V4L2_CID_ROTATE:
  778. ctrl->value = ctx->rotation;
  779. break;
  780. default:
  781. v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev, "Invalid control\n");
  782. return -EINVAL;
  783. }
  784. dbg("ctrl->value= %d", ctrl->value);
  785. return 0;
  786. }
  787. static int check_ctrl_val(struct fimc_ctx *ctx,
  788. struct v4l2_control *ctrl)
  789. {
  790. struct v4l2_queryctrl *c;
  791. c = get_ctrl(ctrl->id);
  792. if (!c)
  793. return -EINVAL;
  794. if (ctrl->value < c->minimum || ctrl->value > c->maximum
  795. || (c->step != 0 && ctrl->value % c->step != 0)) {
  796. v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
  797. "Invalid control value\n");
  798. return -ERANGE;
  799. }
  800. return 0;
  801. }
  802. int fimc_m2m_s_ctrl(struct file *file, void *priv,
  803. struct v4l2_control *ctrl)
  804. {
  805. struct fimc_ctx *ctx = priv;
  806. struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
  807. unsigned long flags;
  808. int ret = 0;
  809. ret = check_ctrl_val(ctx, ctrl);
  810. if (ret)
  811. return ret;
  812. switch (ctrl->id) {
  813. case V4L2_CID_HFLIP:
  814. if (ctx->rotation != 0)
  815. return 0;
  816. if (ctrl->value)
  817. ctx->flip |= FLIP_X_AXIS;
  818. else
  819. ctx->flip &= ~FLIP_X_AXIS;
  820. break;
  821. case V4L2_CID_VFLIP:
  822. if (ctx->rotation != 0)
  823. return 0;
  824. if (ctrl->value)
  825. ctx->flip |= FLIP_Y_AXIS;
  826. else
  827. ctx->flip &= ~FLIP_Y_AXIS;
  828. break;
  829. case V4L2_CID_ROTATE:
  830. if (ctrl->value == 90 || ctrl->value == 270) {
  831. if (ctx->out_path == FIMC_LCDFIFO &&
  832. !variant->has_inp_rot) {
  833. return -EINVAL;
  834. } else if (ctx->in_path == FIMC_DMA &&
  835. !variant->has_out_rot) {
  836. return -EINVAL;
  837. }
  838. }
  839. ctx->rotation = ctrl->value;
  840. if (ctrl->value == 180)
  841. ctx->flip = FLIP_XY_AXIS;
  842. break;
  843. default:
  844. v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev, "Invalid control\n");
  845. return -EINVAL;
  846. }
  847. spin_lock_irqsave(&ctx->slock, flags);
  848. ctx->state |= FIMC_PARAMS;
  849. spin_unlock_irqrestore(&ctx->slock, flags);
  850. return 0;
  851. }
  852. static int fimc_m2m_cropcap(struct file *file, void *fh,
  853. struct v4l2_cropcap *cr)
  854. {
  855. struct fimc_frame *frame;
  856. struct fimc_ctx *ctx = fh;
  857. ctx_m2m_get_frame(frame, ctx, cr->type);
  858. cr->bounds.left = 0;
  859. cr->bounds.top = 0;
  860. cr->bounds.width = frame->f_width;
  861. cr->bounds.height = frame->f_height;
  862. cr->defrect.left = frame->offs_h;
  863. cr->defrect.top = frame->offs_v;
  864. cr->defrect.width = frame->o_width;
  865. cr->defrect.height = frame->o_height;
  866. return 0;
  867. }
  868. static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
  869. {
  870. struct fimc_frame *frame;
  871. struct fimc_ctx *ctx = file->private_data;
  872. ctx_m2m_get_frame(frame, ctx, cr->type);
  873. cr->c.left = frame->offs_h;
  874. cr->c.top = frame->offs_v;
  875. cr->c.width = frame->width;
  876. cr->c.height = frame->height;
  877. return 0;
  878. }
  879. static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
  880. {
  881. struct fimc_ctx *ctx = file->private_data;
  882. struct fimc_dev *fimc = ctx->fimc_dev;
  883. unsigned long flags;
  884. struct fimc_frame *f;
  885. u32 min_size;
  886. int ret = 0;
  887. if (cr->c.top < 0 || cr->c.left < 0) {
  888. v4l2_err(&fimc->m2m.v4l2_dev,
  889. "doesn't support negative values for top & left\n");
  890. return -EINVAL;
  891. }
  892. if (cr->c.width <= 0 || cr->c.height <= 0) {
  893. v4l2_err(&fimc->m2m.v4l2_dev,
  894. "crop width and height must be greater than 0\n");
  895. return -EINVAL;
  896. }
  897. ctx_m2m_get_frame(f, ctx, cr->type);
  898. /* Adjust to required pixel boundary. */
  899. min_size = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) ?
  900. fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize;
  901. cr->c.width = round_down(cr->c.width, min_size);
  902. cr->c.height = round_down(cr->c.height, min_size);
  903. cr->c.left = round_down(cr->c.left + 1, min_size);
  904. cr->c.top = round_down(cr->c.top + 1, min_size);
  905. if ((cr->c.left + cr->c.width > f->o_width)
  906. || (cr->c.top + cr->c.height > f->o_height)) {
  907. v4l2_err(&fimc->m2m.v4l2_dev, "Error in S_CROP params\n");
  908. return -EINVAL;
  909. }
  910. spin_lock_irqsave(&ctx->slock, flags);
  911. if ((ctx->state & FIMC_SRC_FMT) && (ctx->state & FIMC_DST_FMT)) {
  912. /* Check for the pixel scaling ratio when cropping input img. */
  913. if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
  914. ret = fimc_check_scaler_ratio(&cr->c, &ctx->d_frame);
  915. else if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
  916. ret = fimc_check_scaler_ratio(&cr->c, &ctx->s_frame);
  917. if (ret) {
  918. spin_unlock_irqrestore(&ctx->slock, flags);
  919. v4l2_err(&fimc->m2m.v4l2_dev, "Out of scaler range");
  920. return -EINVAL;
  921. }
  922. }
  923. ctx->state |= FIMC_PARAMS;
  924. spin_unlock_irqrestore(&ctx->slock, flags);
  925. f->offs_h = cr->c.left;
  926. f->offs_v = cr->c.top;
  927. f->width = cr->c.width;
  928. f->height = cr->c.height;
  929. return 0;
  930. }
  931. static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = {
  932. .vidioc_querycap = fimc_m2m_querycap,
  933. .vidioc_enum_fmt_vid_cap = fimc_m2m_enum_fmt,
  934. .vidioc_enum_fmt_vid_out = fimc_m2m_enum_fmt,
  935. .vidioc_g_fmt_vid_cap = fimc_m2m_g_fmt,
  936. .vidioc_g_fmt_vid_out = fimc_m2m_g_fmt,
  937. .vidioc_try_fmt_vid_cap = fimc_m2m_try_fmt,
  938. .vidioc_try_fmt_vid_out = fimc_m2m_try_fmt,
  939. .vidioc_s_fmt_vid_cap = fimc_m2m_s_fmt,
  940. .vidioc_s_fmt_vid_out = fimc_m2m_s_fmt,
  941. .vidioc_reqbufs = fimc_m2m_reqbufs,
  942. .vidioc_querybuf = fimc_m2m_querybuf,
  943. .vidioc_qbuf = fimc_m2m_qbuf,
  944. .vidioc_dqbuf = fimc_m2m_dqbuf,
  945. .vidioc_streamon = fimc_m2m_streamon,
  946. .vidioc_streamoff = fimc_m2m_streamoff,
  947. .vidioc_queryctrl = fimc_m2m_queryctrl,
  948. .vidioc_g_ctrl = fimc_m2m_g_ctrl,
  949. .vidioc_s_ctrl = fimc_m2m_s_ctrl,
  950. .vidioc_g_crop = fimc_m2m_g_crop,
  951. .vidioc_s_crop = fimc_m2m_s_crop,
  952. .vidioc_cropcap = fimc_m2m_cropcap
  953. };
  954. static void queue_init(void *priv, struct videobuf_queue *vq,
  955. enum v4l2_buf_type type)
  956. {
  957. struct fimc_ctx *ctx = priv;
  958. struct fimc_dev *fimc = ctx->fimc_dev;
  959. videobuf_queue_dma_contig_init(vq, &fimc_qops,
  960. fimc->m2m.v4l2_dev.dev,
  961. &fimc->irqlock, type, V4L2_FIELD_NONE,
  962. sizeof(struct fimc_vid_buffer), priv);
  963. }
  964. static int fimc_m2m_open(struct file *file)
  965. {
  966. struct fimc_dev *fimc = video_drvdata(file);
  967. struct fimc_ctx *ctx = NULL;
  968. int err = 0;
  969. mutex_lock(&fimc->lock);
  970. fimc->m2m.refcnt++;
  971. set_bit(ST_OUTDMA_RUN, &fimc->state);
  972. mutex_unlock(&fimc->lock);
  973. ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
  974. if (!ctx)
  975. return -ENOMEM;
  976. file->private_data = ctx;
  977. ctx->fimc_dev = fimc;
  978. /* default format */
  979. ctx->s_frame.fmt = &fimc_formats[0];
  980. ctx->d_frame.fmt = &fimc_formats[0];
  981. /* per user process device context initialization */
  982. ctx->state = 0;
  983. ctx->flags = 0;
  984. ctx->effect.type = S5P_FIMC_EFFECT_ORIGINAL;
  985. ctx->in_path = FIMC_DMA;
  986. ctx->out_path = FIMC_DMA;
  987. spin_lock_init(&ctx->slock);
  988. ctx->m2m_ctx = v4l2_m2m_ctx_init(ctx, fimc->m2m.m2m_dev, queue_init);
  989. if (IS_ERR(ctx->m2m_ctx)) {
  990. err = PTR_ERR(ctx->m2m_ctx);
  991. kfree(ctx);
  992. }
  993. return err;
  994. }
  995. static int fimc_m2m_release(struct file *file)
  996. {
  997. struct fimc_ctx *ctx = file->private_data;
  998. struct fimc_dev *fimc = ctx->fimc_dev;
  999. v4l2_m2m_ctx_release(ctx->m2m_ctx);
  1000. kfree(ctx);
  1001. mutex_lock(&fimc->lock);
  1002. if (--fimc->m2m.refcnt <= 0)
  1003. clear_bit(ST_OUTDMA_RUN, &fimc->state);
  1004. mutex_unlock(&fimc->lock);
  1005. return 0;
  1006. }
  1007. static unsigned int fimc_m2m_poll(struct file *file,
  1008. struct poll_table_struct *wait)
  1009. {
  1010. struct fimc_ctx *ctx = file->private_data;
  1011. return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
  1012. }
  1013. static int fimc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
  1014. {
  1015. struct fimc_ctx *ctx = file->private_data;
  1016. return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
  1017. }
  1018. static const struct v4l2_file_operations fimc_m2m_fops = {
  1019. .owner = THIS_MODULE,
  1020. .open = fimc_m2m_open,
  1021. .release = fimc_m2m_release,
  1022. .poll = fimc_m2m_poll,
  1023. .ioctl = video_ioctl2,
  1024. .mmap = fimc_m2m_mmap,
  1025. };
  1026. static struct v4l2_m2m_ops m2m_ops = {
  1027. .device_run = fimc_dma_run,
  1028. .job_abort = fimc_job_abort,
  1029. };
  1030. static int fimc_register_m2m_device(struct fimc_dev *fimc)
  1031. {
  1032. struct video_device *vfd;
  1033. struct platform_device *pdev;
  1034. struct v4l2_device *v4l2_dev;
  1035. int ret = 0;
  1036. if (!fimc)
  1037. return -ENODEV;
  1038. pdev = fimc->pdev;
  1039. v4l2_dev = &fimc->m2m.v4l2_dev;
  1040. /* set name if it is empty */
  1041. if (!v4l2_dev->name[0])
  1042. snprintf(v4l2_dev->name, sizeof(v4l2_dev->name),
  1043. "%s.m2m", dev_name(&pdev->dev));
  1044. ret = v4l2_device_register(&pdev->dev, v4l2_dev);
  1045. if (ret)
  1046. return ret;;
  1047. vfd = video_device_alloc();
  1048. if (!vfd) {
  1049. v4l2_err(v4l2_dev, "Failed to allocate video device\n");
  1050. goto err_m2m_r1;
  1051. }
  1052. vfd->fops = &fimc_m2m_fops;
  1053. vfd->ioctl_ops = &fimc_m2m_ioctl_ops;
  1054. vfd->minor = -1;
  1055. vfd->release = video_device_release;
  1056. snprintf(vfd->name, sizeof(vfd->name), "%s:m2m", dev_name(&pdev->dev));
  1057. video_set_drvdata(vfd, fimc);
  1058. platform_set_drvdata(pdev, fimc);
  1059. fimc->m2m.vfd = vfd;
  1060. fimc->m2m.m2m_dev = v4l2_m2m_init(&m2m_ops);
  1061. if (IS_ERR(fimc->m2m.m2m_dev)) {
  1062. v4l2_err(v4l2_dev, "failed to initialize v4l2-m2m device\n");
  1063. ret = PTR_ERR(fimc->m2m.m2m_dev);
  1064. goto err_m2m_r2;
  1065. }
  1066. ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
  1067. if (ret) {
  1068. v4l2_err(v4l2_dev,
  1069. "%s(): failed to register video device\n", __func__);
  1070. goto err_m2m_r3;
  1071. }
  1072. v4l2_info(v4l2_dev,
  1073. "FIMC m2m driver registered as /dev/video%d\n", vfd->num);
  1074. return 0;
  1075. err_m2m_r3:
  1076. v4l2_m2m_release(fimc->m2m.m2m_dev);
  1077. err_m2m_r2:
  1078. video_device_release(fimc->m2m.vfd);
  1079. err_m2m_r1:
  1080. v4l2_device_unregister(v4l2_dev);
  1081. return ret;
  1082. }
  1083. static void fimc_unregister_m2m_device(struct fimc_dev *fimc)
  1084. {
  1085. if (fimc) {
  1086. v4l2_m2m_release(fimc->m2m.m2m_dev);
  1087. video_unregister_device(fimc->m2m.vfd);
  1088. video_device_release(fimc->m2m.vfd);
  1089. v4l2_device_unregister(&fimc->m2m.v4l2_dev);
  1090. }
  1091. }
  1092. static void fimc_clk_release(struct fimc_dev *fimc)
  1093. {
  1094. int i;
  1095. for (i = 0; i < NUM_FIMC_CLOCKS; i++) {
  1096. if (fimc->clock[i]) {
  1097. clk_disable(fimc->clock[i]);
  1098. clk_put(fimc->clock[i]);
  1099. }
  1100. }
  1101. }
  1102. static int fimc_clk_get(struct fimc_dev *fimc)
  1103. {
  1104. int i;
  1105. for (i = 0; i < NUM_FIMC_CLOCKS; i++) {
  1106. fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clock_name[i]);
  1107. if (IS_ERR(fimc->clock[i])) {
  1108. dev_err(&fimc->pdev->dev,
  1109. "failed to get fimc clock: %s\n",
  1110. fimc_clock_name[i]);
  1111. return -ENXIO;
  1112. }
  1113. clk_enable(fimc->clock[i]);
  1114. }
  1115. return 0;
  1116. }
  1117. static int fimc_probe(struct platform_device *pdev)
  1118. {
  1119. struct fimc_dev *fimc;
  1120. struct resource *res;
  1121. struct samsung_fimc_driverdata *drv_data;
  1122. int ret = 0;
  1123. dev_dbg(&pdev->dev, "%s():\n", __func__);
  1124. drv_data = (struct samsung_fimc_driverdata *)
  1125. platform_get_device_id(pdev)->driver_data;
  1126. if (pdev->id >= drv_data->devs_cnt) {
  1127. dev_err(&pdev->dev, "Invalid platform device id: %d\n",
  1128. pdev->id);
  1129. return -EINVAL;
  1130. }
  1131. fimc = kzalloc(sizeof(struct fimc_dev), GFP_KERNEL);
  1132. if (!fimc)
  1133. return -ENOMEM;
  1134. fimc->id = pdev->id;
  1135. fimc->variant = drv_data->variant[fimc->id];
  1136. fimc->pdev = pdev;
  1137. fimc->state = ST_IDLE;
  1138. spin_lock_init(&fimc->irqlock);
  1139. spin_lock_init(&fimc->slock);
  1140. mutex_init(&fimc->lock);
  1141. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1142. if (!res) {
  1143. dev_err(&pdev->dev, "failed to find the registers\n");
  1144. ret = -ENOENT;
  1145. goto err_info;
  1146. }
  1147. fimc->regs_res = request_mem_region(res->start, resource_size(res),
  1148. dev_name(&pdev->dev));
  1149. if (!fimc->regs_res) {
  1150. dev_err(&pdev->dev, "failed to obtain register region\n");
  1151. ret = -ENOENT;
  1152. goto err_info;
  1153. }
  1154. fimc->regs = ioremap(res->start, resource_size(res));
  1155. if (!fimc->regs) {
  1156. dev_err(&pdev->dev, "failed to map registers\n");
  1157. ret = -ENXIO;
  1158. goto err_req_region;
  1159. }
  1160. ret = fimc_clk_get(fimc);
  1161. if (ret)
  1162. goto err_regs_unmap;
  1163. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1164. if (!res) {
  1165. dev_err(&pdev->dev, "failed to get IRQ resource\n");
  1166. ret = -ENXIO;
  1167. goto err_clk;
  1168. }
  1169. fimc->irq = res->start;
  1170. fimc_hw_reset(fimc);
  1171. ret = request_irq(fimc->irq, fimc_isr, 0, pdev->name, fimc);
  1172. if (ret) {
  1173. dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
  1174. goto err_clk;
  1175. }
  1176. fimc->work_queue = create_workqueue(dev_name(&fimc->pdev->dev));
  1177. if (!fimc->work_queue)
  1178. goto err_irq;
  1179. ret = fimc_register_m2m_device(fimc);
  1180. if (ret)
  1181. goto err_wq;
  1182. fimc_hw_en_lastirq(fimc, true);
  1183. dev_dbg(&pdev->dev, "%s(): fimc-%d registered successfully\n",
  1184. __func__, fimc->id);
  1185. return 0;
  1186. err_wq:
  1187. destroy_workqueue(fimc->work_queue);
  1188. err_irq:
  1189. free_irq(fimc->irq, fimc);
  1190. err_clk:
  1191. fimc_clk_release(fimc);
  1192. err_regs_unmap:
  1193. iounmap(fimc->regs);
  1194. err_req_region:
  1195. release_resource(fimc->regs_res);
  1196. kfree(fimc->regs_res);
  1197. err_info:
  1198. kfree(fimc);
  1199. dev_err(&pdev->dev, "failed to install\n");
  1200. return ret;
  1201. }
  1202. static int __devexit fimc_remove(struct platform_device *pdev)
  1203. {
  1204. struct fimc_dev *fimc =
  1205. (struct fimc_dev *)platform_get_drvdata(pdev);
  1206. v4l2_info(&fimc->m2m.v4l2_dev, "Removing %s\n", pdev->name);
  1207. free_irq(fimc->irq, fimc);
  1208. fimc_hw_reset(fimc);
  1209. fimc_unregister_m2m_device(fimc);
  1210. fimc_clk_release(fimc);
  1211. iounmap(fimc->regs);
  1212. release_resource(fimc->regs_res);
  1213. kfree(fimc->regs_res);
  1214. kfree(fimc);
  1215. return 0;
  1216. }
  1217. static struct samsung_fimc_variant fimc01_variant_s5p = {
  1218. .has_inp_rot = 1,
  1219. .has_out_rot = 1,
  1220. .min_inp_pixsize = 16,
  1221. .min_out_pixsize = 16,
  1222. .scaler_en_w = 3264,
  1223. .scaler_dis_w = 8192,
  1224. .in_rot_en_h = 1920,
  1225. .in_rot_dis_w = 8192,
  1226. .out_rot_en_w = 1920,
  1227. .out_rot_dis_w = 4224,
  1228. };
  1229. static struct samsung_fimc_variant fimc2_variant_s5p = {
  1230. .min_inp_pixsize = 16,
  1231. .min_out_pixsize = 16,
  1232. .scaler_en_w = 4224,
  1233. .scaler_dis_w = 8192,
  1234. .in_rot_en_h = 1920,
  1235. .in_rot_dis_w = 8192,
  1236. .out_rot_en_w = 1920,
  1237. .out_rot_dis_w = 4224,
  1238. };
  1239. static struct samsung_fimc_variant fimc01_variant_s5pv210 = {
  1240. .has_inp_rot = 1,
  1241. .has_out_rot = 1,
  1242. .min_inp_pixsize = 16,
  1243. .min_out_pixsize = 32,
  1244. .scaler_en_w = 4224,
  1245. .scaler_dis_w = 8192,
  1246. .in_rot_en_h = 1920,
  1247. .in_rot_dis_w = 8192,
  1248. .out_rot_en_w = 1920,
  1249. .out_rot_dis_w = 4224,
  1250. };
  1251. static struct samsung_fimc_variant fimc2_variant_s5pv210 = {
  1252. .min_inp_pixsize = 16,
  1253. .min_out_pixsize = 32,
  1254. .scaler_en_w = 1920,
  1255. .scaler_dis_w = 8192,
  1256. .in_rot_en_h = 1280,
  1257. .in_rot_dis_w = 8192,
  1258. .out_rot_en_w = 1280,
  1259. .out_rot_dis_w = 1920,
  1260. };
  1261. static struct samsung_fimc_driverdata fimc_drvdata_s5p = {
  1262. .variant = {
  1263. [0] = &fimc01_variant_s5p,
  1264. [1] = &fimc01_variant_s5p,
  1265. [2] = &fimc2_variant_s5p,
  1266. },
  1267. .devs_cnt = 3
  1268. };
  1269. static struct samsung_fimc_driverdata fimc_drvdata_s5pv210 = {
  1270. .variant = {
  1271. [0] = &fimc01_variant_s5pv210,
  1272. [1] = &fimc01_variant_s5pv210,
  1273. [2] = &fimc2_variant_s5pv210,
  1274. },
  1275. .devs_cnt = 3
  1276. };
  1277. static struct platform_device_id fimc_driver_ids[] = {
  1278. {
  1279. .name = "s5p-fimc",
  1280. .driver_data = (unsigned long)&fimc_drvdata_s5p,
  1281. }, {
  1282. .name = "s5pv210-fimc",
  1283. .driver_data = (unsigned long)&fimc_drvdata_s5pv210,
  1284. },
  1285. {},
  1286. };
  1287. MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
  1288. static struct platform_driver fimc_driver = {
  1289. .probe = fimc_probe,
  1290. .remove = __devexit_p(fimc_remove),
  1291. .id_table = fimc_driver_ids,
  1292. .driver = {
  1293. .name = MODULE_NAME,
  1294. .owner = THIS_MODULE,
  1295. }
  1296. };
  1297. static char banner[] __initdata = KERN_INFO
  1298. "S5PC Camera Interface V4L2 Driver, (c) 2010 Samsung Electronics\n";
  1299. static int __init fimc_init(void)
  1300. {
  1301. u32 ret;
  1302. printk(banner);
  1303. ret = platform_driver_register(&fimc_driver);
  1304. if (ret) {
  1305. printk(KERN_ERR "FIMC platform driver register failed\n");
  1306. return -1;
  1307. }
  1308. return 0;
  1309. }
  1310. static void __exit fimc_exit(void)
  1311. {
  1312. platform_driver_unregister(&fimc_driver);
  1313. }
  1314. module_init(fimc_init);
  1315. module_exit(fimc_exit);
  1316. MODULE_AUTHOR("Sylwester Nawrocki, s.nawrocki@samsung.com");
  1317. MODULE_DESCRIPTION("S3C/S5P FIMC (video postprocessor) driver");
  1318. MODULE_LICENSE("GPL");